Method for manufacturing semiconductor device and method for managing product history of semiconductor device

Abstract

To satisfy the demand for a technique capable of suppressing an increase in cost while accurately performing traceability of a semiconductor device.SOLUTION: By mapping positions of crystal defects 10, position information of the crystal defects 10 on a wafer map WFM is stored in a storage device. In each of a plurality of chip regions (CHPa), a metal film MF is formed in a wiring layer located above a semiconductor element 1Q. In each of the plurality of chip regions (CHPa), a surface morphology image 1AI of a specific area 1A in the metal film MF is acquired. The position information of the crystal defects 10 on the wafer map WFM, a wafer identification number ID, position information of the plurality of chip regions (CHPa), position information of the specific area 1A within each chip region (CHPa), and the surface morphology images 1AI for the respective chip regions (CHPa) are associated with one another and stored in the storage device.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a method for managing the product history of a semiconductor device. [Background technology]

[0002] When a defect is discovered after the manufacturing of a semiconductor device, it is necessary to identify the cause of the defect early and provide feedback to the manufacturing process of the semiconductor device. To achieve this, traceability of semiconductor devices determined to be defective is effective. In other words, it is effective to clarify which wafer, which lot number and which wafer identification number the semiconductor device determined to be defective was manufactured on, and at what position within the wafer it was manufactured.

[0003] For example, in Patent Document 1, images of dicing marks on the side of the wafer and images of contact marks on the surface of the pad electrodes formed during probe testing are stored in a storage device at the four corners of the semiconductor chip. Similar images are also acquired for semiconductor chips that have been determined to be defective, and by comparing these images with the images stored in the storage device, the wafer identification number and position within the wafer on which the semiconductor chip determined to be defective was manufactured are identified. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-165389 Summary of the Invention [Problem to be solved by the invention]

[0005] Generally, in the semiconductor front-end process, an identification code is attached to the wafer. However, the semiconductor chips separated from the wafer do not have an identification code. While attaching an identification code to every semiconductor chip would enable traceability, such an approach would increase costs.

[0006] Semiconductor chips separated from a wafer are packaged through post-processing to manufacture semiconductor devices. During this process, external connection members such as bonding wires or bump electrodes are formed on the surfaces of pad electrodes. The semiconductor chips are also covered with a sealing resin. To ensure traceability of semiconductor devices determined to be defective, it is necessary to accurately obtain information that can identify the semiconductor chips even after the sealing resin is opened and the external connection members are removed.

[0007] In other words, there is a need for a technology that can suppress cost increases and perform semiconductor device traceability with high accuracy. There is also a need for a technology that can identify the cause of semiconductor device defects early and provide feedback to the semiconductor device manufacturing method early. These technologies will enable the supply of highly reliable semiconductor devices after feedback, improve yield, and prevent defective products from being released into the market.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A brief summary of a representative embodiment of the present invention will be given below.

[0010] (b) dividing the wafer into a plurality of chip regions arranged in a matrix and generating a wafer map; (c) inspecting the wafer for crystal defects; (d) storing position information of the crystal defects on the wafer map in a storage device by mapping the positions of the crystal defects; (e) forming semiconductor elements in each of the plurality of chip regions; (f) forming a metal film in a wiring layer located above the semiconductor elements in each of the plurality of chip regions; (g) acquiring a first surface morphology image of a specific area of ​​the metal film in each of the plurality of chip regions; and (h) linking the position information of the crystal defects on the wafer map, the wafer identification number, the position information of the plurality of chip regions, the position information of the specific area within the chip region, and the first surface morphology image for each of the plurality of chip regions, and storing them in the storage device.

[0011] A method for managing product history of a semiconductor device according to one embodiment includes: (a) assigning a wafer identification number to a wafer made of silicon carbide; (b) dividing the wafer into a plurality of chip regions arranged in a matrix and generating a wafer map; (c) inspecting the wafer for crystal defects present in the wafer; (d) storing position information of the crystal defects on the wafer map in a storage device by mapping the positions of the crystal defects; (e) forming semiconductor elements in each of the plurality of chip regions; (f) forming a metal film in a wiring layer located above the semiconductor elements in each of the plurality of chip regions; (g) acquiring a first surface morphology image of a specific area of ​​the metal film in each of the plurality of chip regions; (h) storing the wafer identification number, the position information of the crystal defects on the wafer map, the position information of the plurality of chip regions, and the position information of the crystal defects in each of the chip regions. (i) obtaining a plurality of semiconductor chips by singulating the plurality of chip regions of the wafer; (j) forming a plurality of first semiconductor devices by encapsulating the plurality of semiconductor chips with encapsulation resin; (k) obtaining a second semiconductor device determined to be defective; (l) removing the encapsulation resin from the second semiconductor device and obtaining a second surface morphology image of a portion of the metal film provided on the second semiconductor device that corresponds to the specific area; and (m) identifying the wafer identification number of the wafer on which the second semiconductor device was manufactured and the position of the chip region on which the second semiconductor device was manufactured by comparing the second surface morphology image with the first surface morphology image for each of the plurality of chip regions stored in the storage device. The position of the chip area identified in step (m) is compared with the position information of the crystal defect on the wafer map, and if the crystal defect is present in the chip area identified in step (m), it can be estimated that the defect in the second semiconductor device is caused by the crystal defect. [Effects of the Invention]

[0012] According to one embodiment, it is possible to suppress an increase in costs and to perform traceability of semiconductor devices with high accuracy. Furthermore, it is possible to identify the cause of a defect in a semiconductor device early and provide feedback to a manufacturing method of the semiconductor device early. [Brief explanation of the drawings]

[0013] [Figure 1] 3 is a flowchart showing a method for manufacturing a semiconductor device and a method for managing product history of the semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a plan view showing a wafer map in the first embodiment. [Figure 3] FIG. 2 is a plan view showing a chip region in the first embodiment. [Figure 4] FIG. 2 is a schematic diagram showing how data is stored in a storage device according to the first embodiment. [Figure 5] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing a manufacturing process following FIG. 5. [Figure 7] 7A to 7C are cross-sectional views showing a manufacturing process following FIG. 6. [Figure 8] 8 is a cross-sectional view showing a manufacturing process following FIG. 7. [Figure 9] 9 is a cross-sectional view showing a manufacturing process following FIG. 8. [Figure 10] 10 is a cross-sectional view showing a manufacturing process following FIG. 9. [Figure 11] 11 is a cross-sectional view showing a manufacturing process following FIG. 10. [Figure 12] 12 is a schematic diagram showing the manufacturing process following FIG. 11 and the subsequent product history management process for the semiconductor device. [Figure 13] FIG. 13 is a plan view showing the product history management process following FIG. [Figure 14] FIG. 10 is a plan view showing position information of crystal defects in the second embodiment. [Figure 15] FIG. 11 is a schematic diagram showing a method for matching surface morphology images in the third embodiment. [Figure 16]FIG. 10 is a plan view showing a shape pattern of a metal film in the fourth embodiment. [Figure 17] FIG. 13 is a plan view showing a chip region in a fifth embodiment. [Figure 18] 13 is a flowchart showing a method for manufacturing a semiconductor device and a method for managing the product history of a semiconductor device according to a sixth embodiment. [Figure 19] FIG. 20 is a schematic diagram showing how data is stored in a storage device according to the sixth embodiment. [Figure 20] FIG. 20 is a plan view showing a method for managing the product history of a semiconductor device in a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0015] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, height, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that the surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0016] (Embodiment 1) <Method for manufacturing semiconductor device and method for managing product history of semiconductor device> A method for manufacturing the semiconductor device 100 and a method for managing the product history of the semiconductor device 100 according to the first embodiment will be described below with reference to Fig. 1. The method for managing the product history of the semiconductor device 100 includes steps S1 to S13 shown in Fig. 1. The method for manufacturing the semiconductor device 100 is part of the method for managing the product history of the semiconductor device 100, and includes steps S1 to S8.

[0017] In addition, in the description of steps S1 to S13, FIGS. 2 to 13 will be used as necessary.

[0018] In step S1, first, a wafer WF is prepared, and a wafer identification number ID is assigned to a portion of the wafer WF as shown in FIG. 4. Next, as shown in FIG. 2, the wafer WF is partitioned into a plurality of chip areas CHPa arranged in a matrix, and a wafer map WFM is generated. Each of the plurality of chip areas CHPa is partitioned by a dicing line DL. The plurality of chip areas CHPa are singulated along the dicing lines DL to obtain a plurality of semiconductor chips CHP.

[0019] 3 is a plan view showing details of the chip region CHPa (semiconductor chip CHP). The chip region CHPa has a cell region CR in which a semiconductor element 1Q is formed and an outer periphery region OR that surrounds the cell region CR in a plan view. The semiconductor element 1Q is a power device such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). In the first embodiment, the semiconductor element 1Q is illustrated as an n-type power MOSFET with a trench gate structure.

[0020] The source wiring SW is formed in most of the cell region CR. The gate wiring GW is formed in the outer peripheral region OR so as to surround the source wiring SW in a plan view. The field limiting wiring FLW is formed in the outer peripheral region OR so as to surround the gate wiring GW in a plan view. The source wiring SW and the gate wiring GW are formed of the same metal film MF and are electrically connected to the semiconductor element 1Q.

[0021] In addition, in the outer periphery region OR, a dummy pattern DP is formed between the field limiting wiring FLW and the dicing line DL (the side surface of the semiconductor chip CHP). The dummy pattern DP is formed of a metal film MF and is electrically insulated from the semiconductor element 1Q.

[0022] Although not shown here, the source wiring SW, gate wiring GW, field limiting wiring FLW, and dummy pattern DP are covered with a protective film PIQ such as a polyimide film. Openings are provided in parts of the protective film PIQ. The portions of the source wiring SW and gate wiring GW exposed by the openings become the source pad SP and gate pad GP. The portions surrounded by dashed lines in FIG. 3 are the source pad SP and gate pad GP. By connecting external connection members such as bonding wires, bump electrodes, or clips (copper plates) to the source pad SP and gate pad GP, the semiconductor chip CHP can be electrically connected to another semiconductor chip, a wiring substrate, or the like.

[0023] The wafer WF is made of silicon carbide (SiC) and has n-type conductivity. As shown in FIG. 5, the wafer WF has a support substrate SS made of silicon carbide and a semiconductor layer NEP made of silicon carbide. The semiconductor layer NEP is formed on the support substrate SS by epitaxial growth. The support substrate SS and the semiconductor layer NEP have n-type conductivity. The semiconductor layer NEP has an impurity concentration lower than the impurity concentration of the support substrate SS and functions as a drift layer.

[0024] It is known that various crystal defects are inherent in the support substrate SS made of silicon carbide. Furthermore, since crystalline defects propagate during epitaxial growth, it is highly likely that various crystal defects are also inherent in the semiconductor layer NEP. Therefore, wafers WF made of silicon carbide tend to have a higher frequency of defects caused by crystal defects compared to wafers made of silicon.

[0025] 4, first, the crystal defects 10 present in the wafer WF are inspected. Next, the positions of the crystal defects 10 are mapped, and the position information of the crystal defects 10 on the wafer map WFM is stored in the memory device MD.

[0026] Types of crystal defects 10 include, for example, basal plane defects, stacking faults, spiral defects, and micropipes. Semiconductor elements 1Q and the like are formed in subsequent processes, but the semiconductor device 100 may later be determined to be defective. At this point, it is difficult to determine which type of crystal defect 10 is directly linked to the defect. Depending on the type of semiconductor element 1Q, the manufacturing conditions in each manufacturing process for manufacturing the semiconductor element 1Q, or the usage conditions of the semiconductor device 100, any of the crystal defects 10 may be the cause of the defect. Therefore, in order to identify or estimate which type of crystal defect 10 caused the defect, position information of the crystal defect 10 on the wafer map WFM is acquired.

[0027] In step S3, semiconductor elements 1Q are formed in each of the chip areas CHPa. Each manufacturing process for forming the semiconductor elements 1Q will be described below with reference to FIGS.

[0028] A wafer WF is prepared as shown in Fig. 5. As described above, the wafer WF has a support substrate SS and a semiconductor layer NEP formed on the support substrate SS by epitaxial growth.

[0029] As shown in FIG. 6, an n-type drain region ND, a p-type body region PB, and an n-type source region NS are formed in a wafer WF.

[0030] First, a drain region ND is formed in the support substrate SS using photolithography and ion implantation to a predetermined depth from the bottom surface of the wafer WF. Next, a body region PB is formed in the semiconductor layer NEP using photolithography and ion implantation to a predetermined depth from the top surface of the wafer WF. Next, a source region NS is formed in the body region PB using photolithography and ion implantation to a predetermined depth from the top surface of the wafer WF. The drain region ND and the source region NS each have an impurity concentration higher than the impurity concentration of the semiconductor layer NEP.

[0031] As shown in FIG. 7, a trench TR is formed in the semiconductor layer NEP so as to reach a predetermined depth from the upper surface of the wafer WF.

[0032] First, a silicon oxide film, for example, is formed on the wafer WF by a film formation process using, for example, a CVD (Chemical Vapor Deposition) method. Next, a hard mask is formed by patterning the silicon oxide film using photolithography and an anisotropic etching process. Next, an anisotropic etching process is performed using the hard mask as a mask to form trenches TR that penetrate the source region NS and the body region PB and reach the semiconductor layer NEP. Thereafter, the hard mask is removed by an isotropic etching process using, for example, a solution containing hydrofluoric acid.

[0033] As shown in FIG. 8, a trench GR is formed in the semiconductor layer NEP so as to reach a predetermined depth from the upper surface of the wafer WF, and a high concentration diffusion region PR is formed at the bottom of the trench GR.

[0034] First, a trench GR is selectively formed in the semiconductor layer NEP using photolithography and anisotropic etching. The trench GR penetrates the source region NS and reaches into the body region PB. Next, a p-type heavily doped diffusion region PR is formed in the body region PB at the bottom of the trench GR using photolithography and ion implantation. The heavily doped diffusion region PR has an impurity concentration higher than that of the body region PB.

[0035] Thereafter, the wafer WF is subjected to a heat treatment in order to activate the impurities contained in the body region PB, the source region NS, and the high-concentration diffusion region PR.

[0036] As shown in FIG. 9, a gate insulating film GI and a gate electrode GE are formed inside the trench TR.

[0037] First, a gate insulating film GI is formed inside the trench TR and on the upper surface of the wafer WF by thermal oxidation. The gate insulating film GI is, for example, a silicon oxide film. Next, a conductive film is formed on the gate insulating film GI by, for example, a film formation process using a CVD method. The conductive film is, for example, an n-type polycrystalline silicon film.

[0038] Next, the gate insulating film GI and the gate electrode GE are patterned by photolithography and anisotropic etching. At this time, the inside of the trench TR is filled with the gate electrode GE via the gate insulating film GI. Furthermore, on the upper surface of the wafer WF, the source region NS and the high-concentration diffusion region PR are exposed from the gate insulating film GI and the gate electrode GE.

[0039] As described above, the semiconductor elements 1Q are formed in each of the plurality of chip areas CHPa.

[0040] In step S4, a metal film MF is formed in the wiring layer located above the semiconductor element 1Q in each of the chip areas CHPa. Each manufacturing process for forming the wiring layer will be described below with reference to FIGS.

[0041] As shown in FIG. 10, first, an interlayer insulating film IL is formed on the upper surface of the wafer WF by, for example, CVD so as to cover the gate electrode GE. Next, the interlayer insulating film IL is patterned by photolithography and anisotropic etching to form through-holes TH. At this time, the gate electrode GE is covered by the interlayer insulating film IL. Furthermore, on the upper surface of the wafer WF, the source region NS and the high-concentration diffusion region PR are exposed in the through-holes TH.

[0042] 11, a metal film MF is formed on the interlayer insulating film IL and on the upper surface of the wafer WF by a film formation process using a sputtering method or a CVD method so as to fill the through holes TH and the trenches GR. The metal film MF is a film mainly made of aluminum. Specifically, the metal film MF is a laminated film of a barrier metal film made of, for example, a titanium tungsten film and an aluminum alloy film, for example, doped with copper or silicon, formed on the barrier metal film.

[0043] Next, the metal film MF is patterned by photolithography and anisotropic etching. As a result, the source wiring SW, gate wiring GW, field limiting wiring FLW, and dummy pattern DP are formed from the metal film MF in the first wiring layer, as shown in Figure 3. In the first embodiment, the first wiring layer is the only wiring layer located above the semiconductor element 1Q.

[0044] The source wiring SW is electrically connected to the source region NS, the heavily doped diffusion region PR, and the body region PB, and supplies a source potential to these regions. Although not shown here, a through hole TH is also formed on the gate wiring GW. Therefore, the gate wiring GW is electrically connected to the gate electrode GE, and supplies a gate potential to the gate electrode GE.

[0045] Alternatively, a plug layer, mainly made of, for example, a tungsten film, may be formed in the through hole TH and the trench GR, and then a metal film MF may be formed on the interlayer insulating film IL. In this case, the source wiring SW is electrically connected to the source region NS, the heavily doped diffusion region PR, and the body region PB via the plug layer. The gate wiring GW is also electrically connected to the gate electrode GE via the plug layer.

[0046] Next, a protective film PIQ made of, for example, a polyimide film is formed on the source wiring SW, gate wiring GW, field limiting wiring FLW, and dummy pattern DP by, for example, a coating method. Next, a portion of the protective film PIQ is exposed to light to form openings, exposing the source electrode SE and the gate wiring GW in areas that will become the source pad SP and gate pad GP. Next, a drain electrode DE is formed on the underside of the wafer WF by a film formation process using a sputtering method.

[0047] The processing history included in the manufacturing process of the semiconductor element 1Q in step S3 and the manufacturing process of the metal film MF in step S4 is stored in the memory device MD.

[0048] In step S5, a surface morphology image 1AI of a specific area 1A of the metal film MF is acquired in each of the plurality of chip regions CHPa.

[0049] As shown in FIG. 3, a portion of the metal film MF present in the chip area CHPa is provided as a specific area 1A. The position of the specific area 1A is the same for each of the multiple chip areas CHPa. In the first embodiment, the metal film MF is formed to occupy the specific area 1A. In the example of FIG. 3, for example, a portion of the source wiring SW or a portion of the dummy pattern DP is used as the specific area 1A. For example, a portion of the gate wiring GW may also be used as the specific area 1A. The planar size of the specific area 1A is, for example, 50 μm×50 μm or more and 200 μm×200 μm or less.

[0050] As shown in FIG. 12, a surface morphology image 1AI of a specific area 1A is acquired for each of a plurality of chip regions CHPa, and the surface morphology images 1AI are stored in the memory device MD.

[0051] In step S5, it is desirable to acquire a surface morphology image 1AI through the protective film PIQ while the specific area 1A is covered with the protective film PIQ. The surface morphology image 1AI is later used for comparison with a surface morphology image 2AI of the semiconductor device 200 determined to be defective. For example, if the specific area 1A is set within the source pad SP, there is a risk that a bonding wire or the like will be provided in the specific area 1A. In this case, it will be impossible to acquire a surface morphology image 2AI of the semiconductor device 200.

[0052] Furthermore, if the specific area 1A is not covered with the protective film PIQ when acquiring the surface morphology image 2AI, there is a risk that the surface condition of the specific area 1A of the semiconductor device 200 will change, which makes it difficult to acquire an accurate surface morphology image 2AI.

[0053] 4, in step S6, the wafer identification number ID, position information of the crystal defect 10 on the wafer map WFM, position information of the plurality of chip regions CHPa, position information of the specific area 1A within the chip region CHPa, and the surface morphology image 1AI for each of the plurality of chip regions CHPa are linked and stored in the memory device MD. The surface morphology image 1AI linked with each piece of information in this way can be effectively used for traceability of the semiconductor device 200 determined to be defective.

[0054] In step S7, a plurality of chip areas CHPa of the wafer WF are diced along the dicing lines DL to obtain a plurality of semiconductor chips CHP.

[0055] In step S8, a plurality of semiconductor devices 100 are formed by sealing the plurality of semiconductor chips CHP with sealing resin SR.

[0056] For example, first, the semiconductor chip CHP is mounted on a lead frame, and the source pad SP, gate pad GP, and drain electrode DE are electrically connected to the lead terminals using external connection members such as bonding wires, clips, or paste. Next, the semiconductor chip CHP and each lead terminal are encapsulated with a sealing resin SR such as epoxy resin. By cutting each lead terminal from the lead frame, the semiconductor device 100 shown in FIG. 12 is formed.

[0057] As described above, a plurality of semiconductor devices 100 can be obtained from the wafer WF.

[0058] In step S9, as shown in Fig. 12, a semiconductor device 200 determined to be defective is acquired. A semiconductor device 200 determined to be defective is, for example, a semiconductor device that has been shipped to a customer and then returned because the customer pointed out a defect. In order to perform traceability on such a semiconductor device 200, the sealing resin SR of the semiconductor device 200 is opened. Furthermore, external connection members of the semiconductor device 200 are removed as necessary.

[0059] In step S10, a surface morphology image 2AI is acquired for a portion of the metal film MF provided on the semiconductor device 200 that corresponds to the specific area 1A. At this time, if the portion corresponding to the specific area 1A is covered with a protective film PIQ, the surface morphology image 2AI may be acquired with the protective film PIQ remaining, or the surface morphology image 2AI may be acquired after the protective film PIQ is removed. Because the specific area 1A is protected by the protective film PIQ, the surface of the specific area 1A remains in good condition even after the sealing resin SR is removed. Therefore, a highly accurate surface morphology image 2AI can be acquired.

[0060] In step S11, the surface morphology image 2AI is compared with the surface morphology images 1AI for each of the multiple chip areas CHPa stored in the memory device MD, thereby identifying the wafer identification number ID of the wafer WF on which the semiconductor device 200 is manufactured and the position of the chip area CHPa1 on which the semiconductor device 200 is manufactured.

[0061] If the surface morphology image 2AI does not match any of the surface morphology images 1AI for the plurality of chip areas CHPa stored in the memory device MD, the semiconductor device 200 can be identified as a counterfeit product.

[0062] In step S12, as shown in FIG. 13, the position of the identified chip area CHPa1 is compared with the position information of the crystal defect 10 on the wafer map WFM, and if the crystal defect 10 exists in the identified chip area CHPa1, it can be estimated that the defect in the semiconductor device 200 is caused by the crystal defect 10.

[0063] Furthermore, the type of crystal defect 10 present in the identified chip area CHPa1 has been determined in advance by the inspection in step S2. Therefore, by comparing other chip areas CHPa on the wafer map WFM in which the same type of crystal defect 10 exists, it can be estimated that there is a high possibility that the same defect as that in the semiconductor device 200 will occur in semiconductor devices 100 manufactured from the other chip areas CHPa.

[0064] In step S13, the result of step S12 is fed back to the manufacturing method of the semiconductor device 100. For example, the result of step S12 can be fed back to steps S3 and S4 to review the manufacturing conditions or take measures such as not commercializing the chip region CHPa1. Similar measures may also be taken for chip regions CHPa that have the same type of crystal defects 10 as the chip region CHPa1.

[0065] As described above, according to the first embodiment, traceability can be achieved without the need to attach an identification mark to every semiconductor chip CHP or to perform special processing within the wafer WF, thereby suppressing increases in costs associated with traceability.

[0066] Furthermore, an accurate surface morphology image 2AI can be acquired even after the sealing resin SR is opened and the external connection member is removed. That is, information that leads to the identification of the semiconductor chip CHP can be acquired with high accuracy. Furthermore, the cause of the defect in the semiconductor device 200 can be identified early, and feedback can be provided to the manufacturing method of the semiconductor device 100 early. As a result, after feedback, highly reliable semiconductor devices 100 can be supplied, the yield can be improved, and the release of defective products into the market can be suppressed.

[0067] Although the first embodiment illustrates a power MOSFET as the semiconductor element 1Q, the semiconductor element 1Q may be an IGBT. In this case, the source region NS, the source wiring SW, the body region PB, the drain region NS, and the drain electrode DE function as an emitter region, an emitter wiring, a base region, a collector region, and a collector electrode.

[0068] Although the first embodiment employs a trench gate structure for the semiconductor element 1Q, the semiconductor element 1Q may have a planar structure. In this case, the trench TR is not formed inside the wafer WF, and the gate insulating film GI and the gate electrode GE are formed on the upper surface of the wafer WF.

[0069] (Embodiment 2) 14, a method for manufacturing the semiconductor device 100 and a method for managing the product history of the semiconductor device 100 according to the second embodiment will be described below. Note that in the following description, differences from the first embodiment will be mainly described, and explanations of points that overlap with the first embodiment will be omitted.

[0070] In the second embodiment, in addition to the position information (first position information) of the crystal defects 10 stored in the memory device MD in step S2, position information (second position information) of the crystal defects 10 after the heat treatment is also acquired.

[0071] That is, after the wafer WF is subjected to heat treatment, the crystal defects 10 present in the wafer WF are re-inspected. Then, as shown in Fig. 14, the positions of the crystal defects 10 are mapped again, and the position information (second position information) of the crystal defects 10 on the wafer map WFM is stored in the memory device MD.

[0072] It is known that a high temperature for heat treatment is likely to increase the number of crystal defects 10. Therefore, as shown in Fig. 14, the number of crystal defects 10 after heat treatment changes from the number of crystal defects 10 before heat treatment.

[0073] The position of the chip area CHPa1 identified in step S11 is compared with both the first position information and the second position information. If the crystal defect 10 of the first position information does not exist in the identified chip area CHPa1 and the crystal defect 10 of the second position information exists, it can be assumed that the defect of the semiconductor device 200 is caused by the heat treatment.

[0074] In step S12, the result that the defects are caused by the heat treatment is fed back to the manufacturing method of the semiconductor device 100. For example, the conditions (temperature, time, etc.) of the heat treatment can be changed so that the number of crystal defects 10 does not increase.

[0075] Ideally, the method of the second embodiment would be applied after all of the heat treatments performed in steps S3 and S4. However, in order to reduce the number of steps, the heat treatments to be performed in the second embodiment may be limited to only those that are expected to increase the number of crystal defects 10, such as heat treatments at relatively high temperatures. For example, the heat treatment to be performed in the second embodiment may be the heat treatment for activating impurities in FIG. 8 or the thermal oxidation treatment for forming the gate insulating film GI in FIG. 9.

[0076] (Embodiment 3) 15, a method for manufacturing the semiconductor device 100 and a method for managing the product history of the semiconductor device 100 according to the third embodiment will be described below. In the following description, differences from the first embodiment will be mainly described, and explanations of points that overlap with the first embodiment will be omitted.

[0077] In the third embodiment, as shown in FIG. 15, a surface morphology image 1AI and a surface morphology image 2AI are collated using a plurality of feature amounts extracted from each image.

[0078] In step S5, the surface morphology image 1AI is acquired and multiple feature amounts are extracted from the surface morphology image 1AI. For example, an intersection of multiple line segments or the center of an area surrounded by line segments is defined as a feature point in the surface morphology image 1AI, and feature amounts at the feature point are extracted.

[0079] In step S6, the plurality of feature amounts are stored in the storage device MD as information related to the surface morphology image 1AI.

[0080] In step S10, a surface morphology image 2AI is acquired, and a plurality of feature amounts of the surface morphology image 2AI are extracted.

[0081] In step S11, the surface morphology image 2AI is matched with the surface morphology image 1AI for each of the multiple chip areas CHPa stored in the memory device MD by comparing multiple feature amounts of the surface morphology image 2AI with multiple feature amounts of the surface morphology image 1AI.

[0082] In the third embodiment, since a plurality of feature amounts are compared with each other, even if the coordinates of the surface morphology image 1AI and the surface morphology image 2AI do not completely match, it is possible to determine whether the images are within the specific area 1A.

[0083] For example, there may be cases where the coordinates at which the surface morphology image 2AI was captured are slightly different from the coordinates at which the surface morphology image 1AI was captured, or where the surface morphology image 2AI was captured in a rotated state relative to the surface morphology image 1AI. Even in such cases, if multiple feature amounts match, these images can be determined to be images within the specific area 1A. Therefore, by using multiple feature amounts from each other, the accuracy of matching between the surface morphology image 1AI and the surface morphology image 2AI can be improved.

[0084] The technology disclosed in the third embodiment can be applied in combination with the technology disclosed in the second embodiment.

[0085] (Fourth embodiment) 16, a method for manufacturing the semiconductor device 100 and a method for managing the product history of the semiconductor device 100 according to the fourth embodiment will be described below. In the following description, differences from the first embodiment will be mainly described, and explanations of points that overlap with the first embodiment will be omitted.

[0086] In the fourth embodiment, as shown in Fig. 16, a geometric pattern 20 is provided on a metal film MF located within a specific area 1A, around the specific area 1A, or both. In Fig. 16, the region of the metal film MF surrounded by a dashed line is shown as the specific area 1A. Fig. 16 also illustrates a case where a rectangular dummy pattern DP is used as the metal film MF including the specific area 1A.

[0087] By providing the geometric pattern 20, it becomes easier to find the specific area 1A when acquiring the surface morphology image 1AI or the surface morphology image 2AI. This makes it easier to align the exact coordinates of the specific area 1A, improving the accuracy of matching the surface morphology image 1AI with the surface morphology image 2AI. The shape data of the geometric pattern 20 is stored in the memory device MD as information related to the position information of the specific area 1A within the chip area CHPa.

[0088] As examples of the geometric pattern 20, "Pattern 1" to "Pattern 4" shown in FIG. 16 are shown. In "Pattern 1," a plurality of concave and convex portions are provided as the geometric pattern 20 on at least one of the four sides of the metal film MF in a planar view. In "Pattern 2," three two-dimensional code patterns are provided on the metal film MF as the geometric pattern 20. In the case of "Pattern 2," the area surrounded by the three geometric pattern patterns 20 can be recognized as the specific area 1A. In "Pattern 3" and "Pattern 4," slits are provided on the metal film MF as the geometric pattern 20.

[0089] The geometric design pattern 20 is not limited to the shapes of "Pattern 1" to "Pattern 4", and may be any other pattern as long as it has a shape that makes it easy to find the specific area 1A.

[0090] The technique disclosed in the fourth embodiment can be applied in combination with the techniques disclosed in the second and third embodiments.

[0091] (Embodiment 5) 17, a method for manufacturing the semiconductor device 100 and a method for managing the product history of the semiconductor device 100 according to the fifth embodiment will be described below. In the following description, differences from the first embodiment will be mainly described, and explanations of points that overlap with the first embodiment will be omitted.

[0092] In the fifth embodiment, a plurality of specific areas 1A are provided in the chip area CHPa as shown in Fig. 17. In step S5, a surface morphology image 1AI is acquired for each of the plurality of specific areas 1A.

[0093] In step S10, a plurality of surface morphology images 2AI of locations corresponding to a plurality of specific areas 1A are obtained.

[0094] In step S11, the plurality of surface morphology images 2AI are collated with the plurality of surface morphology images 1AI for each of the plurality of chip areas CHPa stored in the memory device MD.

[0095] When a surface morphology image 1AI of only one specific area 1A is acquired for one chip region CHPa, and the portion of the semiconductor device 200 determined to be defective that corresponds to the specific area 1A is damaged or deformed, it becomes difficult to acquire a surface morphology image 2AI. For example, when the semiconductor device 100 is in use, a high electric field may be concentrated in a part of the source wiring SW, causing the part of the source wiring SW to be damaged or deformed.

[0096] If multiple surface morphology images 1AI of multiple specific areas 1A are acquired for one chip region CHPa, even if it is difficult to acquire a surface morphology image 2AI at a certain location, it is possible to acquire a surface morphology image 2AI at another location. Therefore, according to the fifth embodiment, it is easy to eliminate the risk that the surface morphology image 1AI and the surface morphology image 2AI cannot be matched.

[0097] The technique disclosed in the fifth embodiment can be applied in combination with the techniques disclosed in the second to fourth embodiments.

[0098] (Embodiment 6) 18, a method for manufacturing the semiconductor device 100 and a method for managing the product history of the semiconductor device 100 according to the sixth embodiment will be described below. In the following description, differences from the first embodiment will be mainly described, and explanations of points that overlap with the first embodiment will be omitted.

[0099] In the first embodiment, the relationship between the crystal defect 10 and defects in the semiconductor device 200 has been described, but the identification or estimation of defects in the semiconductor device 200 is not limited to the relationship with the crystal defect 10. In the sixth embodiment, in the process of manufacturing the semiconductor device 100 from the wafer WF, an in-line inspection, an electrical characteristic test, and a screening test are performed, and the acquired inspection data or test data is used to identify defects in the semiconductor device 200.

[0100] The method for managing the product history of the semiconductor device 100 includes steps S14 to S20 shown in Fig. 18. The method for manufacturing the semiconductor device 100 includes steps S14 to S17 shown in Fig. 18 in the method for managing the product history of the semiconductor device 100.

[0101] As shown in FIG. 18, while steps S3 and S4 are being performed, an in-line inspection is appropriately performed (step S14). The in-line inspection includes, for example, one or more of foreign matter inspection, defect inspection, dimensional inspection, overlay inspection, and appearance inspection. Furthermore, before performing step S7, an electrical characteristic test is performed on the semiconductor element 1Q for each of the plurality of chip areas CHPa (step S15). Furthermore, before performing step S9, a screening test is performed to screen the reliability of each of the plurality of semiconductor devices 100 (step S16). The screening test is, for example, a burn-in test.

[0102] As described above, the processing history included in the manufacturing process of the semiconductor element 1Q in step S3 and the manufacturing process of the metal film MF in step S4 is stored in the storage device MD.

[0103] In step S17, as shown in FIG. 19, the processing history, the inspection data from the in-line inspection, the test data from the electrical characteristic test, the test data from the sorting test, and the surface morphology image 1AI for each of the multiple chip areas CHPa are linked and stored in the memory device MD.

[0104] For example, suppose a foreign particle is detected in a chip area CHPa during in-line foreign particle inspection. At this point, the process history can be referenced to review the manufacturing conditions of the manufacturing process in which the foreign particle occurred. However, not all foreign particles directly lead to defects, and some foreign particles will not lead to defects even if left unattended. Therefore, if the foreign particle does not affect the electrical characteristics of the semiconductor element 1Q or the reliability of the semiconductor device 100, it may be determined that the foreign particle can be left unattended.

[0105] However, there is a possibility that the semiconductor device 100 may become defective for some reason during use, and a failure analysis may reveal that the neglected foreign matter was the cause of the defect. In this way, in order to quickly perform traceability on the semiconductor device 100 having a potential defect factor and identify the cause of the defect, the processing history, each inspection data, and each test data are linked to the surface morphology image 1AI.

[0106] Thereafter, steps S9 and S10 are performed, and step S11 identifies the position of the chip area CHPa1 in which the semiconductor device 200 is manufactured. In step S18, because step S17 has been performed, it is possible to identify the processing history corresponding to the semiconductor device 200, and it is possible to identify one or more of the inspection data of the in-line inspection, the test data of the electrical characteristic test, and the test data of the screening test corresponding to the semiconductor device 200.

[0107] For example, if the chip area CHPa1 in which the semiconductor device 200 was manufactured was the chip area CHPa in which a foreign substance that would not cause any problems if left alone was detected during a foreign substance inspection, it can be inferred that the foreign substance may have been the cause of the defect.

[0108] In step S19, a failure analysis is performed on the semiconductor device 200. The failure analysis includes one or more of an optical emission analysis, an OBIRCH analysis, a DLS analysis, an IDDQ analysis, a heat generation analysis, a nanoprober analysis, and an EBAC analysis.

[0109] In step S20, the cause of defects in the semiconductor device 200 can be identified from the relationship between the analysis data of the failure analysis and one or more of the inspection data of the in-line inspection corresponding to the semiconductor device 200, the test data of the electrical characteristic test, and the test data of the screening test.

[0110] If the inspection data from the in-line inspection, the test data from the electrical characteristic test, and the test data from the screening test corresponding to the semiconductor device 200 are identified in step S18, the appropriate failure analysis can be performed preferentially in step S19. For example, in the case of a semiconductor device 200 that has a history of detecting a foreign particle in a foreign particle inspection and a history of not detecting an abnormality in a dimensional inspection, it can be predicted that the detected foreign particle is highly likely to have caused the defect. Therefore, a failure analysis suitable for detecting the predicted defect can be performed preferentially.

[0111] In this way, also in the sixth embodiment, the cause of defects in the semiconductor device 200 can be identified early, and in step S12, feedback can be performed early on to the manufacturing method of the semiconductor device 100. As a result, after feedback, highly reliable semiconductor devices 100 can be supplied, the yield can be improved, and the release of defective products into the market can be suppressed.

[0112] For example, if a foreign particle detected during foreign particle inspection is identified as the cause of the defect, the process history can be referenced to review the manufacturing process immediately before the foreign particle was generated, or measures such as not commercializing the chip area CHPa1 can be taken.

[0113] 20, in step S18, there may be another chip area CHPa having similar data to the inspection data of the in-line inspection, the test data of the electrical characteristic test, and the test data of the screening test corresponding to the semiconductor device 200 (chip area CHPa1). In this case, it can be estimated that the semiconductor device 100 manufactured from the corresponding chip area CHPa is likely to have the same defects as the semiconductor device 200. Therefore, the corresponding chip area CHPa may be collated on the wafer map WFM, and the same feedback as in step S12 may be performed for the corresponding chip area CHPa.

[0114] Furthermore, the technology of the sixth embodiment can be used particularly effectively when the cause of the defect in the first embodiment is not the crystal defect 10. For example, by comparing the position of the chip area CHPa1 identified in step S11 with the position information of the crystal defect 10 on the wafer map WFM, if no crystal defect 10 exists in the chip area CHPa1, it can be determined that the defect has occurred due to a cause other than the crystal defect 10. In such a case, the technology of the sixth embodiment can be used to identify the cause of the defect.

[0115] The technique disclosed in the sixth embodiment can be applied in combination with the techniques disclosed in the second to fifth embodiments.

[0116] Although the present invention has been specifically described above based on the above embodiment, the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0117] 100 Semiconductor device 200 Semiconductor device judged to be defective 10 Crystal defects 20 Geometric Patterns 1A Specific Area 1AI, 2AI surface morphology images 1Q semiconductor element CHP semiconductor chip CHPa chip area CHPa1 identified chip region CR Cell Area DE drain electrode DL dicing line DP Dummy Pattern FLW Field Limiting Wiring GE gate electrode GI gate insulating film GP Gate Pad GR Groove GW Gate wiring ID Wafer identification number IL Interlayer insulating film MD storage device MF metal film ND drain region NEP semiconductor layer NS Source Region OR outer area PB body region PIQ protective film PR high concentration diffusion region SP sauce pad SR sealing resin SS support board SW source wiring TH through hole TR Trench WF wafer WFM Wafer Map

Claims

1. (a) assigning a wafer identification number to a wafer comprised of silicon carbide; (b) partitioning the wafer into a plurality of chip regions arranged in a matrix to generate a wafer map; (c) inspecting the wafer for inherent crystal defects; (d) mapping the positions of the crystal defects to store position information of the crystal defects on the wafer map in a storage device; (e) forming a semiconductor element in each of the plurality of chip regions; (f) forming a metal film in a wiring layer located above the semiconductor element in each of the plurality of chip regions; (g) acquiring a first surface morphology image of a specific area of ​​the metal film in each of the plurality of chip regions; (h) linking the position information of the crystal defect on the wafer map, the wafer identification number, the position information of the plurality of chip regions, the position information of the specific area within the chip region, and the first surface morphology image for each of the plurality of chip regions, and storing them in the storage device; A method for manufacturing a semiconductor device, comprising:

2. 2. The method for manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the metal film is a film containing aluminum as a main component.

3. 2. The method for manufacturing a semiconductor device according to claim 1, (i) forming a protective film on a portion of the metal film so as to cover the specific area; Further provided with In the step (g), the first surface morphology image is acquired through the protective film.

4. 2. The method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein the specific area has a planar size of 50 μm×50 μm or more and 200 μm×200 μm or less.

5. 2. The method for manufacturing a semiconductor device according to claim 1, the position information of the crystal defect stored in the storage device in the step (d) is set as first position information of the crystal defect; The step (e) is (e1) performing a heat treatment on the wafer; (e2) after the step (e1), re-inspecting the wafer for crystal defects inherent therein; (e3) after the step (e2), a step of storing second position information of the crystal defect on the wafer map in the storage device by mapping the positions of the crystal defect again; The method for manufacturing a semiconductor device includes the steps of:

6. 2. The method for manufacturing a semiconductor device according to claim 1, In the step (g), a plurality of first feature amounts are extracted from the first surface morphology image; In the step (h), the plurality of first feature amounts are stored in the storage device as information related to the first surface morphology image.

7. 2. The method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein a geometric pattern is provided on the metal film located within the specific area, around the specific area, or both.

8. 2. The method for manufacturing a semiconductor device according to claim 1, A plurality of the specific areas are provided in each of the plurality of chip regions, In the step (g), the first surface morphology image is acquired for each of the plurality of specific areas.

9. 2. The method for manufacturing a semiconductor device according to claim 1, Each of the plurality of chip areas includes: a cell region in which the semiconductor device is formed; a peripheral region surrounding the cell region in a plan view; and The method for manufacturing a semiconductor device, wherein the metal film is formed in the cell region and is electrically connected to the semiconductor element.

10. 2. The method for manufacturing a semiconductor device according to claim 1, Each of the plurality of chip areas includes: a cell region in which the semiconductor device is formed; a peripheral region surrounding the cell region in a plan view; and The method for manufacturing a semiconductor device, wherein the metal film is formed in the peripheral region and is electrically insulated from the semiconductor element.

11. 2. The method for manufacturing a semiconductor device according to claim 1, (j) storing in the storage device a processing history included in the manufacturing process of the semiconductor element in the step (e) and the manufacturing process of the metal film in the step (f); (k) performing in-line inspection during the steps (e) and (f); (l) storing the processing history, the inspection data of the in-line inspection, and the first surface morphology image for each of the plurality of chip regions in the storage device in association with each other; The method for manufacturing a semiconductor device further comprises:

12. 12. The method for manufacturing a semiconductor device according to claim 11, The method for manufacturing a semiconductor device, wherein the in-line inspection includes any one or more of a foreign substance inspection, a defect inspection, a dimension inspection, an overlay inspection, and a visual inspection.

13. 2. The method for manufacturing a semiconductor device according to claim 1, (m) performing an electrical characteristic test on the semiconductor elements in each of the plurality of chip regions; (n) linking test data of the electrical characteristic test with the first surface morphology image for each of the plurality of chip regions and storing the linked test data in the storage device; The method for manufacturing a semiconductor device further comprises:

14. 2. The method for manufacturing a semiconductor device according to claim 1, (o) obtaining a plurality of semiconductor chips by singulating the plurality of chip regions of the wafer; (p) forming a plurality of first semiconductor devices by sealing the plurality of semiconductor chips with a sealing resin; (q) performing a screening test to screen the reliability of each of the plurality of first semiconductor devices; (r) linking the test data of the screening test with the first surface morphology image for each of the plurality of chip regions and storing the linked test data in the storage device; The method for manufacturing a semiconductor device further comprises:

15. (a) assigning a wafer identification number to a wafer comprised of silicon carbide; (b) partitioning the wafer into a plurality of chip regions arranged in a matrix to generate a wafer map; (c) inspecting the wafer for inherent crystal defects; (d) mapping the positions of the crystal defects to store position information of the crystal defects on the wafer map in a storage device; (e) forming a semiconductor element in each of the plurality of chip regions; (f) forming a metal film in a wiring layer located above the semiconductor element in each of the plurality of chip regions; (g) acquiring a first surface morphology image of a specific area of ​​the metal film in each of the plurality of chip regions; (h) linking the wafer identification number, position information of the crystal defects on the wafer map, position information of the plurality of chip regions, position information of the specific area within the chip region, and the first surface morphology image for each of the plurality of chip regions, and storing them in the storage device; (i) obtaining a plurality of semiconductor chips by singulating the plurality of chip regions of the wafer; (j) forming a plurality of first semiconductor devices by sealing the plurality of semiconductor chips with sealing resin; (k) acquiring the second semiconductor device determined to be defective; (l) removing the sealing resin from the second semiconductor device and acquiring a second surface morphology image of a portion of the metal film provided on the second semiconductor device that corresponds to the specific area; (m) a step of identifying the wafer identification number of the wafer on which the second semiconductor device is manufactured and the position of the chip area on which the second semiconductor device is manufactured by collating the second surface morphology image with the first surface morphology image for each of the plurality of chip areas stored in the storage device; Equipped with A product history management method for semiconductor devices, which compares the position of the chip area identified in step (m) with position information of the crystal defect on the wafer map, and if the crystal defect is present in the chip area identified in step (m), it can be assumed that the defect in the second semiconductor device is caused by the crystal defect.

16. 16. The semiconductor device product history management method according to claim 15, (n) storing in the storage device a processing history included in the manufacturing process of the semiconductor element in the step (e) and the manufacturing process of the metal film in the step (f); (o) performing in-line inspection during the steps (e) and (f); (p) performing an electrical characteristic test on the semiconductor element; (q) after the step (j), performing a screening test to screen the reliability of each of the plurality of first semiconductor devices; (r) linking the processing history, the inspection data of the in-line inspection, the test data of the electrical characteristic test, the test data of the screening test, and the first surface morphology image for each of the plurality of chip regions, and storing them in the storage device; Further provided with A product history management method for semiconductor devices, wherein by identifying the position of the chip area in which the second semiconductor device is manufactured in the (m) step, the processing history corresponding to the second semiconductor device can be identified, and any one or more of the inspection data of the in-line inspection, the test data of the electrical characteristic test, and the test data of the sorting test corresponding to the second semiconductor device can be identified.

17. 17. The semiconductor device product history management method according to claim 16, (s) performing a failure analysis on the second semiconductor device; Further provided with A product history management method for semiconductor devices, which can identify the cause of defects in the second semiconductor device from the relationship between the analysis data of the failure analysis and one or more of the inspection data of the in-line inspection corresponding to the second semiconductor device, the test data of the electrical characteristic test, and the test data of the screening test.

18. 18. The semiconductor device product history management method according to claim 17, The failure analysis includes at least one of an optical emission analysis, an OBIRCH analysis, a DLS analysis, an IDDQ analysis, a heat generation analysis, a nanoprober analysis, and an EBAC analysis.

19. 18. The semiconductor device product history management method according to claim 17, The identified cause of the defect in the second semiconductor device is fed back to the steps (e) and (f).

20. 16. The semiconductor device product history management method according to claim 15, A product history management method for semiconductor devices, wherein the second semiconductor device can be identified as a counterfeit product if the second surface morphology image does not match any of the first surface morphology images for each of the plurality of chip areas stored in the storage device.

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