Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device that can stabilize its operation, and a method for manufacturing the same.SOLUTION: A semiconductor device 1 has a silicon substrate, a BOX film, a shallow trench isolation (STI) 13, a silicon portion 20, a gate electrode 30, and contacts 41-44. In the silicon portion 20, impurities are introduced to respective parts to provide a semiconductor of a p-type or n-type conductivity, and channel regions of the p--type conductivity (portions 21a, 21b), Halo regions of the p-type conductivity (portions 22a-22c), a body contact region 23 of a p+-type conductivity, a source region 24 of the n-type conductivity, and a drain region 25 of the n-type conductivity are provided. In the gate electrode 30, a first electrode portion 31, a second electrode portion 32, a pad portion 33, and a side wall 35 are provided. The pad portion 33 is arranged outside an opening 13e of the STI 13 in a +Y direction side of the silicon portion 20.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In semiconductor devices that constitute logic circuits, a technique for forming MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) on SOI (Silicon On Insulator) substrates is known to improve the operating speed, but MOSFETs formed on SOI substrates have the problem of being less stable in operation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-69913 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments is to provide a semiconductor device capable of stabilizing its operation and a method for manufacturing the same. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor device according to an embodiment includes the steps of: forming an electrode on a structure including a first insulating film, a second insulating film disposed on the first insulating film, and a semiconductor portion disposed on the first insulating film and surrounded by the second insulating film; the electrode including a first electrode portion extending in a first direction and crossing a region directly above the semiconductor portion, and a second electrode portion extending from the first electrode portion in a second direction intersecting with the first direction; and implanting impurities into a portion of the semiconductor portion not covered by the electrode using the electrode as a mask in a direction inclined with respect to a third direction orthogonal to the first direction and the second direction. and forming a first semiconductor portion of a first conductivity type in a portion of the semiconductor portion covered by the electrode that is in contact with a portion not covered by the electrode; forming a first mask on the structure to cover a portion of the semiconductor portion not covered by the electrode that is in contact with a portion covered by the second electrode; forming a second semiconductor portion of a second conductivity type in a portion of the first semiconductor portion by ion-implanting impurities using the first mask and the electrode as masks; removing the first mask; and forming a contact connected to the portion.

[0006] a second semiconductor portion disposed on the first insulating film, the second semiconductor portion being of a second conductivity type, in contact with the first semiconductor portion, and partitioned into two regions by the first semiconductor portion; a third semiconductor portion disposed on the first insulating film, the second semiconductor portion being of the first conductivity type, and having an effective impurity concentration higher than the effective impurity concentration of the first semiconductor portion, in contact with the second portion of the first semiconductor portion and spaced apart from the first portion; a second insulating film disposed on the first insulating film, surrounding a semiconductor portion including the first semiconductor portion, the second semiconductor portion, and the third semiconductor portion when viewed from above; an electrode having a first electrode portion disposed in a region directly above the first portion and a second electrode portion disposed in a region directly above the second portion; and a contact connected to the third semiconductor portion. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a plan view showing a silicon portion and an STI of the semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line AA' shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line BB' shown in FIG. [Figure 5] FIG. 5 is a plan view showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along line AA' shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line BB' shown in FIG. [Figure 8] FIG. 8 is a plan view showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a cross-sectional view taken along line AA' shown in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along line BB' shown in FIG. [Figure 11] FIG. 11 is a plan view showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 12] FIG. 12 is a cross-sectional view taken along line AA' shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along line BB' shown in FIG. [Figure 14] FIG. 14 is a plan view showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 15] FIG. 15 is a cross-sectional view taken along line AA' shown in FIG. [Figure 16] FIG. 16 is a cross-sectional view taken along line BB' shown in FIG. [Figure 17] FIG. 17 is a plan view showing a method for manufacturing a semiconductor device according to a comparative example. [Figure 18]FIG. 18 is a cross-sectional view taken along line AA' shown in FIG. [Figure 19] FIG. 19 is a cross-sectional view taken along line BB' shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] <Embodiment> FIG. 1 is a plan view showing a semiconductor device according to this embodiment. FIG. 2 is a plan view showing the silicon portion and STI of the semiconductor device according to this embodiment. FIG. 3 is a cross-sectional view taken along line AA' shown in FIG. FIG. 4 is a cross-sectional view taken along line BB' shown in FIG.

[0009] As shown in Figures 1 to 4, the semiconductor device 1 according to this embodiment includes a silicon substrate 11, a BOX film 12, an STI (Shallow Trench Isolation: element isolation insulating film) 13, a silicon portion 20, a gate electrode 30, and contacts 41 to 44.

[0010] The silicon substrate 11 is made of, for example, a semiconductor material, such as single-crystal silicon (Si). The BOX film 12 and the STI 13 are made of an insulating material, such as silicon oxide (SiO2). The silicon portion 20 is made of, for example, a semiconductor material, such as silicon. The BOX film 12 is disposed on the silicon substrate 11. The STI 13 and the silicon portion 20 are disposed on the BOX film 12. The gate electrode 30 and contacts 41 to 44 are disposed on the STI 13 and the silicon portion 20.

[0011] An opening 13e is formed in the STI 13, and the silicon portion 20 is disposed within the opening 13e. Therefore, when viewed from above, the silicon portion 20 is surrounded by the STI 13 and is separated from the surroundings by the BOX film 12 and the STI 13. Note that although the semiconductor device 1 may be provided with a plurality of silicon portions 20, only one silicon portion 20 will be described in this embodiment.

[0012] For ease of explanation, this specification employs an XYZ Cartesian coordinate system. The direction from the silicon substrate 11 toward the BOX film 12 is defined as the "Z direction," and two directions that are perpendicular to the Z direction and perpendicular to each other are defined as the "X direction" and the "Y direction." The X direction is divided into the "+X direction" and the "-X direction" as necessary. The same applies to the Y direction and the Z direction. The +Z direction is also referred to as "up" and the -Z direction as "down," but these expressions are also for convenience and are unrelated to the direction of gravity. In this specification, "connection" means electrical connection.

[0013] When viewed from the Z direction, the shape of the opening 13e of the STI 13 is, for example, rectangular. Therefore, when viewed from the Z direction, the shape of the silicon portion 20 is also, for example, rectangular. The inner edge of the opening 13e is made up of a pair of sides 13a and 13b extending in the X direction and a pair of sides 13c and 13d extending in the Y direction.

[0014] In the silicon portion 20, impurities are introduced into each portion to make the conductivity type a p-type or n-type semiconductor. - A channel region 21 of p-type, a halo region 22 of p-type, and a + The semiconductor device includes a body contact region 23 having an n-type conductivity, a source region 24 having an n-type conductivity, and a drain region 25 having an n-type conductivity. The effective impurity concentration of the body contact region 23 is higher than the effective impurity concentration of the halo region 22. The effective impurity concentration of the halo region 22 is higher than the effective impurity concentration of the channel region 21.

[0015] The term "effective impurity concentration" refers to the concentration of impurities that contribute to the conductivity of a semiconductor, and when a certain portion contains both impurities that act as acceptors and impurities that act as donors, the term refers to the net impurity concentration excluding the offset amounts.

[0016] The channel region 21 includes a portion 21a that extends in the Y direction and reaches from the X-direction center of the side 13a of the STI 13 to the X-direction center of the side 13b, and a portion 21b that extends from the portion 21a to one side in the X direction (the -X direction side), extends along the side 13b of the STI 13, and reaches the side 13c.

[0017] The halo region 22 includes a portion 22a disposed on the +X side of the portion 21a of the channel region 21 and in contact with the portion 21a, a portion 22b disposed on the −X side of the portion 21a and in contact with the portion 21a, and a portion 22c disposed on the +Y side of the portion 21b of the channel region 21 and in contact with the portion 21b. The portions 22a and 22b extend in the Y direction. The portion 22c extends in the −X direction from the −Y side end of the portion 22b, extends in the −X direction along the portion 21b of the channel region 21, and reaches the side 13c of the STI 13. The portions 22b and 22c of the halo region 22 are formed continuously. The portion 22a is separated from the portions 22b and 22c via the portion 21a of the channel region 21.

[0018] The body contact region 23 is in contact with the portion 22c of the halo region 22 and the side 13c of the STI 13, and is separated from the entire channel region 21 and the portions 22a and 22b of the halo region 22. When viewed from above, the shape of the body contact region 23 is, for example, rectangular. As described above, the body contact region 23 is in contact with the portion 22c of the halo region 22, and the portion 22b of the halo region 22 is in contact with the channel region 21, and therefore the body contact region 23 is connected to the channel region 21 via the halo region 22.

[0019] The source region 24 is located on the −X direction side of the portion 22a of the halo region 22, and is in contact with the portions 22b and 22c of the halo region 22, the body contact region 23, and the sides 13a and 13c of the STI 13. The drain region 25 is located on the +X direction side of the portion 22a of the halo region 22, and is in contact with the portion 22a of the halo region 22, and the sides 13a, 13b, and 13d of the STI 13.

[0020] A portion 21a of the channel region 21 is disposed between the source region 24 and the drain region 25. A portion 22b of the halo region 22 is disposed between the source region 24 and the portion 21a. A portion 22a of the halo region 22 is disposed between the drain region 25 and the portion 21a. The source region 24 and the drain region 25 are partitioned by the portion 21a of the channel region 21 and the portions 22a and 22b of the halo region 22.

[0021] In the center of the silicon portion 20 in the Y direction, the source region 24, the portion 22b of the halo region 22, the portion 21a of the channel region 21, the portion 22a of the halo region 22, and the drain region 25 are arranged in this order from the side 13c toward the side 13d of the STI 13. The portion 21b of the channel region 21, the portion 22c of the halo region 22, and the body contact region 23 are arranged on the source electrode 24 side and the -Y direction side as viewed from the portion 21a of the channel region 21.

[0022] The gate electrode 30 includes a first electrode portion 31, a second electrode portion 32, a pad portion 33, and a sidewall 35. As viewed from the Z direction, the pad portion 33 is located on the +Y direction side of the silicon portion 20 and outside the opening 13e of the STI 13. The first electrode portion 31 extends from the pad portion 33 in the −Y direction and crosses the area directly above the silicon portion 20. The second electrode portion 32 extends from the end of the first electrode portion 31 on the −Y direction side in the −X direction and extends along the area directly above the side 13b of the STI 13. The pad portion 33, the first electrode portion 31, and the second electrode portion 32 are integrally formed of a conductive material, such as polysilicon containing impurities. The sidewall 35 is insulating and is located around the conductive portion, including the first electrode portion 31, the second electrode portion 32, and the pad portion 33, as viewed from the Z direction.

[0023] A gate insulating film 26 is disposed between the silicon portion 20 and the gate electrode 30. Therefore, the gate electrode 30 is insulated from the silicon portion 20. The gate insulating film 26 is formed of, for example, silicon oxide. Note that the gate insulating film 26 is omitted in Figures 1 and 2. The same applies to other plan views described later.

[0024] A portion 21a of the channel region 21 and portions 22a and 22b of the halo region 22 are disposed directly below the first electrode portion 31 of the gate electrode 30. A portion 21b of the channel region 21 and a portion 22c of the halo region 22 are disposed directly below the second electrode portion 32. The body contact region 23, the source region 24, and the drain region 25 are not disposed directly below the gate electrode 30.

[0025] An interlayer insulating film (not shown) is provided above the STI 13, the gate insulating film 26, the gate electrode 30, and the sidewall 35, and the contacts 41 to 44 are disposed in the interlayer insulating film. The lower end of the contact 41 is connected to the body contact region 23 of the silicon portion 20. The lower end of the contact 42 is connected to the pad portion 33 of the gate electrode 30. The lower end of the contact 43 is connected to the source region 24. The lower end of the contact 44 is connected to the drain region 25. The contacts 43 and 44 in the source region 24 and the drain region 25 are connected to each other at their contact points. + A mold contact layer may be formed on each of the electrodes.

[0026] Next, a method for manufacturing the semiconductor device according to this embodiment will be described. FIG. 5 is a plan view showing the method for manufacturing a semiconductor device according to this embodiment. FIG. 6 is a cross-sectional view taken along line AA' shown in FIG. FIG. 7 is a cross-sectional view taken along line BB' shown in FIG. FIG. 8 is a plan view showing the method for manufacturing a semiconductor device according to this embodiment. FIG. 9 is a cross-sectional view taken along line AA' shown in FIG. FIG. 10 is a cross-sectional view taken along line BB' shown in FIG. FIG. 11 is a plan view showing the method for manufacturing a semiconductor device according to this embodiment. FIG. 12 is a cross-sectional view taken along line AA' shown in FIG. FIG. 13 is a cross-sectional view taken along line BB' shown in FIG. FIG. 14 is a plan view showing the method for manufacturing a semiconductor device according to this embodiment. FIG. 15 is a cross-sectional view taken along line AA' shown in FIG. FIG. 16 is a cross-sectional view taken along line BB' shown in FIG.

[0027] First, as shown in FIGS. 5 to 7, an SOI substrate 10 is prepared. In the SOI substrate 10, a silicon substrate 11, a BOX film 12, and a silicon layer 20a are stacked in this order. The conductivity type of the silicon layer 20a is p - It is a type.

[0028] Next, the silicon layer 20a is selectively thermally oxidized to form the STI 13. At this time, the lower surface of the STI 13 is brought into contact with the upper surface of the BOX film 12. The unoxidized portion of the silicon layer 20a becomes the silicon portion 20, which is disposed in the opening 13e of the STI 13. In this manner, the structure 100 is formed.

[0029] Next, a gate insulating film 26 is formed on the upper surface of the silicon portion 20. Next, a pad portion 33, a first electrode portion 31 extending in the Y direction, and a second electrode portion 32 extending from the first electrode portion 31 in the -X direction are integrally formed on the gate insulating film 26. Next, insulating sidewalls 35 are formed on the side surfaces of the pad portion 33, the first electrode portion 31, and the second electrode portion 32. In this manner, a gate electrode 30 is formed on the structure 100. In the following description, the "structure 100" includes the gate insulating film 26 and the gate electrode 30. Furthermore, the "gate electrode 30" includes the sidewalls 35.

[0030] Next, as shown in FIGS. 8 to 10, a mask 101 (third mask) is formed on the structure 100. The mask 101 is formed, for example, by exposing and developing a resist. An opening 101a is formed in the mask 101. The silicon portion 20 and a portion of the STI 13 located around the opening 13e are exposed in the opening 101a. Of the silicon portion 20, a portion located directly under the gate electrode 30 is covered with the gate electrode 30, and the other portion is not covered with either the gate electrode 30 or the mask 101.

[0031] Next, using the mask 101 and the gate electrode 30 as a mask, impurities are implanted from directions tilted with respect to the Z direction. For example, impurities to be acceptors, such as boron (B), are ion-implanted four times from a total of four directions: a direction tilted 30° in the -X direction, a direction tilted 30° in the +X direction, a direction tilted 30° in the -Y direction, and a direction tilted 30° in the +Y direction with respect to the Z direction. The dose at this time is, for example, 10 12 cm -2 By implanting the impurity from a direction tilted with respect to the Z direction, the impurity is implanted not only into the portion of the silicon portion 20 that is not covered with the gate electrode 30 but also into a part of the portion that is covered with the gate electrode 30.

[0032] As a result, p-type halo regions 22 are formed in the portions of silicon portion 20 that are not covered with gate electrode 30 and in the portions of silicon portion 20 that are covered with gate electrode 30 and that are in contact with the portions that are not covered with gate electrode 30. Thereafter, mask 101 is removed.

[0033] Next, as shown in FIGS. 11 to 13, a mask 102 (first mask) is formed on the structure 100. The mask 102 is formed, for example, by exposing and developing a resist. An opening 102a is formed in the mask 102. The mask 102 covers portions 20h arranged at corners on the −X direction side and the −Y direction side of the silicon portion 20, and exposes portions of the silicon portion 20 other than the portion 20h. The portion 20h is part of the halo region 22 in this step, and is a portion where the body contact region 23 will be formed in a later step. In the silicon portion 20, the portion 20h is not covered by the gate electrode 30, and is in contact with a portion covered by the gate electrode 30.

[0034] Next, impurities are implanted using the mask 102 and the gate electrode 30 as a mask. For example, impurities that become donors, such as phosphorus (P), are ion-implanted from the Z direction. The dose at this time is, for example, 10 13 ~10 14 cm -2 As a result, the regions of the halo region 22 that are not covered by either the mask 102 or the gate electrode 30 become the n-type source region 24 and the n-type drain region 25. Of the remaining halo region 22, the portions covered by the first electrode portion 31 become portions 22a and 22b, and the portions covered by the second electrode portion 32 become portion 22c. In this process, the donor impurity is not implanted into portion 20h. Thereafter, the mask 102 is removed.

[0035] Next, as shown in FIGS. 14 to 16, a mask 103 (second mask) is formed on the structure 100. The mask 103 is formed, for example, by exposing and developing a resist. An opening 103a is formed in the mask 103. A portion 20h of the silicon portion 20 is exposed in the opening 103a. The mask 103 and the gate electrode 30 cover the silicon portion 20 except for the portion 20h.

[0036] Next, impurities are implanted using the mask 103 and the gate electrode 30 as a mask. For example, impurities to be acceptors, such as boron, are ion-implanted from the Z direction. The dose at this time is, for example, 10 15 cm -2 As a result, the portion 20h is changed from the p-type halo region 22 to the p + The body contact region 23 changes to a shaped body contact region 23. As a result, the body contact region 23 comes into contact with the portion 22c of the halo region 22 located directly below the second electrode portion 32.

[0037] Thereafter, the mask 103 is removed. The region of the silicon portion 20 where the halo region 22, the source region 24, the drain region 25 and the body contact region 23 are not formed is p - This forms a channel region 21.

[0038] 1 to 4, for example, a heat treatment is performed to activate the impurities implanted in each portion. Furthermore, an interlayer insulating film (not shown) is formed on the structure 100, and contacts 41 to 44 are formed in the interlayer insulating film. The lower end of the contact 41 is connected to the body contact region 23, the lower end of the contact 42 is connected to the pad portion 33 of the gate electrode 30, the lower end of the contact 43 is connected to the source region 24, and the lower end of the contact 44 is connected to the drain region 25. In this manner, the semiconductor device 1 is manufactured.

[0039] In semiconductor device 1, a ground potential is applied to halo region 22 and channel region 21 via contact 41 and body contact region 23, a ground potential is applied to source region 24 via contact 43, and a positive power supply potential is applied to drain region 25 via contact 44. In this state, when a potential equal to or greater than the threshold is applied to gate electrode 30 via contact 42, source region 24 and drain region 25 become conductive, and when a potential less than the threshold is applied to gate electrode 30, source region 24 and drain region 25 become non-conductive. At this time, the potentials of halo region 22 and channel region 21 are fixed to the ground potential, thereby stabilizing the operation of semiconductor device 1.

[0040] Next, the effects of this embodiment will be described. 8 to 10, when forming the halo region 22, the mask 101 does not cover the portion 20h that will become the body contact region 23. Furthermore, the impurity that will become the acceptor is ion-implanted from a direction tilted with respect to the Z direction. As a result, the halo region 22 is also formed in the portion that is covered with the gate electrode 30 and that contacts the portion 20h.

[0041] 11 to 13, when the source region 24 and the drain region 25 are formed, the portion 20h is covered with a mask 102. Also, donor impurities are ion-implanted from the Z direction. This prevents the donor impurities from being implanted into the portion 20h. Next, as shown in FIGS. 14 to 16, the body contact region 23 is formed using a mask 103 that exposes the portion 20h.

[0042] As a result, the body contact region 23 contacts the portion 22c of the halo region 22, thereby forming a continuous current path from the body contact region 23 to the channel region 21. As described above, according to this embodiment, the halo region 22 is formed in the portion of the silicon portion 20 that is covered with the gate electrode 30, and the body contact region 23 can be connected to the channel region 21 via this portion. This stabilizes the potential of the channel region 21, thereby stabilizing the operation of the semiconductor device 1.

[0043] Furthermore, by separating the body contact region 23 from the portion 22b of the halo region 22, the gate width on the source region 24 side and the gate width on the drain region 25 side become equal, ensuring source-drain symmetry.

[0044] Furthermore, by selectively using the mask 101 and the mask 102, the body contact region 23 can be separated from the portion 22b of the halo region 22 while suppressing shadowing of the mask 101 and the electrode 30, thereby shortening the distance between the body contact region 23 and the portion 22b. As a result, the semiconductor device 1 can be miniaturized.

[0045] <Comparative Example> In this comparative example, a common mask 110 is used instead of the masks 101 and 102 in the above-described embodiment. FIG. 17 is a plan view showing a method for manufacturing a semiconductor device according to this comparative example. FIG. 18 is a cross-sectional view taken along line AA' shown in FIG. FIG. 19 is a cross-sectional view taken along line BB' shown in FIG.

[0046] First, the steps shown in FIGS. 5 to 7 are carried out. 17 to 19, a mask 110 is formed on the structure 100. The shape of the mask 110 is the same as the mask 102 shown in FIGS. 11 to 13. Then, using the mask 110 and the gate electrode 30 as a mask, impurity ions are implanted from a direction tilted with respect to the Z direction.

[0047] At this time, because the portion 20h of the silicon portion 20 is covered with the mask 110, the periphery of the portion 20h is shaded by the mask 110 during the implantation of the impurities, preventing the implantation of the impurities. In other words, shadowing due to the mask 110 occurs. As a result, the halo region 22 is not formed in the portion of the silicon portion 20 that contacts the portion 20h of the portion 20 covered with the gate electrode 30.

[0048] 11 to 13 are then performed. However, the mask 110 continues to be used instead of the mask 102. That is, impurities are implanted using the mask 110 and the gate electrode 30 as a mask to form the source region 24 and the drain region 25. At this time, the impurities are not implanted into the portion 20h.

[0049] 14 to 16 are then performed. That is, impurities are implanted using the mask 103 and the gate electrode 30 as a mask to form the body contact region 23 in the portion 20h. The subsequent steps are the same as those in the above-described embodiment.

[0050] 17 to 19, halo region 22 is not formed in the portion of silicon portion 20 that contacts portion 20h. Therefore, after body contact region 23 is formed in portion 20h, body contact region 23 is not substantially in contact with halo region 22, and therefore a current path from contact 41 to channel region 21 is not stably formed. As a result, the operation of the semiconductor device is unstable.

[0051] According to the embodiment described above, a semiconductor device capable of stabilizing operation and a method for manufacturing the same can be realized.

[0052] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0053] For example, the second electrode portion 32 of the gate electrode 30 may be disposed in a region directly above the side 13a of the STI 13. That is, in the Y direction, the second electrode portion 32 may be disposed between the pad portion 33 and the first electrode portion 31. In this case, too, the portion 21b of the channel region 21 and the portion 22c of the halo region 22 are disposed directly below the second electrode portion 32, and the body contact region 23 is disposed in a position contacting the portion 22c. Furthermore, the conductivity types of the above-mentioned portions may be reversed.

[0054] The present invention includes the following aspects.

[0055] (Appendix 1) forming an electrode on a structure including a first insulating film, a second insulating film disposed on the first insulating film, and a semiconductor portion disposed on the first insulating film and surrounded by the second insulating film, the electrode including a first electrode portion extending in a first direction and crossing a region directly above the semiconductor portion, and a second electrode portion extending from the first electrode portion in a second direction intersecting the first direction; a step of forming a first conductivity type first semiconductor portion in a portion of the semiconductor portion that is not covered with the electrode and in a portion of the semiconductor portion that is covered with the electrode and that is in contact with the portion that is not covered with the electrode, by ion-implanting impurities from a direction that is inclined with respect to a third direction that is orthogonal to the first direction and the second direction, using the electrode as a mask; forming a first mask on the structure to cover a part of the semiconductor portion that is not covered by the electrode and that is in contact with the part that is covered by the second electrode portion; forming a second semiconductor portion of a second conductivity type in a part of the first semiconductor portion by ion-implanting an impurity using the first mask and the electrode as a mask; removing the first mask; forming a contact connected to the portion; A method for manufacturing a semiconductor device comprising:

[0056] (Appendix 2) After the step of removing the first mask and before the step of forming the contact, forming a second mask over the structure covering the second semiconductor portion and exposing the portion; forming a third semiconductor portion of the first conductivity type in the portion by ion-implanting an impurity using the second mask and the electrode as a mask, the third semiconductor portion having an effective impurity concentration higher than the effective impurity concentration of the first semiconductor portion; 2. The method for manufacturing a semiconductor device according to claim 1, further comprising:

[0057] (Appendix 3) 3. The method for manufacturing a semiconductor device according to claim 2, wherein the third semiconductor portion is in contact with a portion of the first semiconductor portion located directly below the second electrode portion and is spaced apart from a portion of the first semiconductor portion located directly below the first electrode portion.

[0058] (Appendix 4) further comprising, after the step of forming the electrode and before the step of forming the first semiconductor portion, forming a third mask on the structure to expose the semiconductor portion; further comprising removing the third mask after the step of forming the first semiconductor portion and before the step of forming the first mask; 4. The method for manufacturing a semiconductor device according to claim 1, wherein the third mask is also used as a mask in the step of forming the first semiconductor portion.

[0059] (Appendix 5) 5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein in the step of forming the electrode, the semiconductor portion is of a first conductivity type.

[0060] (Appendix 6) 6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the second semiconductor portion is divided into two regions by a portion of the first semiconductor portion located directly below the first electrode portion.

[0061] (Appendix 7) 7. The method for manufacturing a semiconductor device according to claim 6, wherein the electrode is a gate electrode, the two regions are a source region and a drain region, and the second electrode portion is disposed on the source region side.

[0062] (Appendix 8) A first insulating film; a first semiconductor portion disposed on the first insulating film, the first semiconductor portion being of a first conductivity type and having a first portion extending in a first direction and a second portion extending from the first portion in a second direction intersecting the first direction; a second semiconductor portion that is disposed on the first insulating film, has a second conductivity type, contacts the first semiconductor portion, and is partitioned into two regions by the first semiconductor portion; a third semiconductor portion disposed on the first insulating film, of a first conductivity type, having an effective impurity concentration higher than an effective impurity concentration of the first semiconductor portion, contacting the second portion of the first semiconductor portion and spaced apart from the first portion; a second insulating film disposed on the first insulating film and surrounding a semiconductor portion including the first semiconductor portion, the second semiconductor portion, and the third semiconductor portion when viewed from above; an electrode having a first electrode portion disposed in a region directly above the first portion and a second electrode portion disposed in a region directly above the second portion; a contact connected to the third semiconductor portion; A semiconductor device comprising:

[0063] (Appendix 9) 9. The semiconductor device of claim 8, wherein the electrode is a gate electrode, the two regions are a source region and a drain region, and the third semiconductor portion is arranged on the source region side and in contact with the source region.

[0064] (Appendix 10) 10. The semiconductor device according to claim 8, wherein the first conductivity type is p-type and the second conductivity type is n-type.

[0065] (Appendix 11) Further comprising a semiconductor substrate; 11. The semiconductor device according to claim 8, wherein the first insulating film is disposed on the semiconductor substrate. [Explanation of symbols]

[0066] 1. Semiconductor device 10 SOI substrate 11 Silicon substrate 12 BOX membrane 13 STI Sides 13a, 13b, 13c, and 13d 13e opening 20 Silicone part 20a Silicon layer 20h portion 21 Channel Region 21a, 21b parts 22 Halo area 22a, 22b, 22c parts 23 Body Contact Area 24 Source Region 25 Drain region 26 Gate insulating film 30 gate electrode 31 1st electrode part 32 2nd electrode part 33 Pad part 35 side wall 41, 42, 43, 44 Contact 100 structures 101 Mask (3rd Mask) 101a opening 102 Mask (1st Mask) 102a opening 103 Mask (Second Mask) 103a opening 110 Mask

Claims

1. forming an electrode on a structure including a first insulating film, a second insulating film disposed on the first insulating film, and a semiconductor portion disposed on the first insulating film and surrounded by the second insulating film, the electrode including a first electrode portion extending in a first direction and crossing a region directly above the semiconductor portion, and a second electrode portion extending from the first electrode portion in a second direction intersecting the first direction; a step of forming a first conductivity type first semiconductor portion in a portion of the semiconductor portion that is not covered with the electrode and in a portion of the semiconductor portion that is covered with the electrode and that is in contact with the portion that is not covered with the electrode, by ion-implanting impurities from a direction inclined with respect to a third direction that is orthogonal to the first direction and the second direction, using the electrode as a mask; forming a first mask on the structure to cover a portion of the semiconductor portion that is not covered by the electrode and that is in contact with the portion that is covered by the second electrode portion; forming a second semiconductor portion of a second conductivity type in a part of the first semiconductor portion by ion-implanting an impurity using the first mask and the electrode as a mask; removing the first mask; forming a contact connected to the portion; A method for manufacturing a semiconductor device comprising:

2. After the step of removing the first mask and before the step of forming the contact, forming a second mask over the structure covering the second semiconductor portion and exposing the portion; forming a third semiconductor portion of the first conductivity type in the portion by ion-implanting an impurity using the second mask and the electrode as a mask, the third semiconductor portion having an effective impurity concentration higher than the effective impurity concentration of the first semiconductor portion; The method for manufacturing a semiconductor device according to claim 1 , further comprising:

3. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the third semiconductor portion is in contact with a portion of the first semiconductor portion located directly below the second electrode portion and is spaced apart from a portion of the first semiconductor portion located directly below the first electrode portion.

4. After the step of forming the electrode and before the step of forming the first semiconductor portion, a third mask is formed on the structure to expose the semiconductor portion; further comprising the step of removing the third mask after the step of forming the first semiconductor portion and before the step of forming the first mask; 2. The method for manufacturing a semiconductor device according to claim 1, wherein the third mask is also used as a mask in the step of forming the first semiconductor portion.

5. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the electrode, the semiconductor portion is of a first conductivity type.

6. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the second semiconductor portion is divided into two regions by a portion of the first semiconductor portion located directly below the first electrode portion.

7. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the electrode is a gate electrode, the two regions are a source region and a drain region, and the second electrode portion is disposed on the source region side.

8. a first insulating film; a first semiconductor portion disposed on the first insulating film, the first semiconductor portion being of a first conductivity type and having a first portion extending in a first direction and a second portion extending from the first portion in a second direction intersecting the first direction; a second semiconductor portion disposed on the first insulating film, having a second conductivity type, in contact with the first semiconductor portion, and partitioned into two regions by the first semiconductor portion; a third semiconductor portion disposed on the first insulating film, of a first conductivity type, having an effective impurity concentration higher than an effective impurity concentration of the first semiconductor portion, contacting the second portion of the first semiconductor portion and spaced apart from the first portion; a second insulating film disposed on the first insulating film and surrounding a semiconductor portion including the first semiconductor portion, the second semiconductor portion, and the third semiconductor portion when viewed from above; an electrode having a first electrode portion disposed in a region directly above the first portion and a second electrode portion disposed in a region directly above the second portion; a contact connected to the third semiconductor portion; A semiconductor device comprising:

9. 9. The semiconductor device according to claim 8, wherein the electrode is a gate electrode, the two regions are a source region and a drain region, and the third semiconductor portion is disposed on the source region side and in contact with the source region.

10. 9. The semiconductor device according to claim 8, wherein the first conductivity type is p-type and the second conductivity type is n-type.

11. Further comprising a semiconductor substrate; 11. The semiconductor device according to claim 8, wherein the first insulating film is disposed on the semiconductor substrate.

Images