Semiconductor module

Abstract

To prevent outflow of solder for soldering a terminal made of a lead frame.SOLUTION: In a semiconductor device 1, a conductive pattern 7b and a terminal 9 made of a lead frame are connected via a conductive plate 11a. The conductive plate 11a and the terminal 9 are soldered using solder 10d, and a solder dam 11b is formed enclosing the solder region of the terminal 9 on the conductive plate 11a.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module.

[0002] In a semiconductor module, a solder dam made of resin and wire is formed on a lead frame to surround the solder joint surface area, and a lead frame for internal wiring is soldered inside the solder dam (see, for example, Patent Documents 1 and 2).

[0003] In semiconductor devices, solder flow is prevented by providing wires or metal members on the side of the area where a semiconductor element is bonded on a circuit board (see, for example, Patent Documents 3 and 4).

[0004] In addition, solder flow is prevented by wires or metal components surrounding the solder joint surface area, and the semiconductor device is mounted and joined to a semiconductor chip with a U-shaped upper electrode, and a groove into which a connection terminal fits is formed on the upper surface of the upper electrode, and the connection terminal is solder-joined (see, for example, Patent Document 5). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-363216 [Patent Document 2] Japanese Patent Application Publication No. 2018-207002 [Patent Document 3] Patent Publication No. 2021-044452 [Patent Document 4] Japanese Patent Application Laid-Open No. 2017-117813 [Patent Document 5] Japanese Patent Application Publication No. 4-253349 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to prevent the outflow of solder used to join terminals made of lead frames. [Means for solving the problem]

[0007] In order to solve the above problem, in one aspect of the present invention, in a semiconductor device in which a conductive pattern and a lead frame are joined via a conductive plate, the conductive plate and the lead frame are joined with solder, and a solder dam is formed on the conductive plate surrounding the joining area of ​​the lead frame.

[0008] The height of the solder dam from the conductive plate is preferably equal to or greater than the thickness of the solder joint.

[0009] A semiconductor element may be bonded to the conductive pattern.

[0010] The conductive pattern and the conductive plate may be joined by solder.

[0011] The solder dam may be integrally formed with the conductive plate. The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Effects of the Invention]

[0012] According to the disclosed technology, it is possible to prevent the solder from flowing out while suppressing an increase in area, and to obtain a good solder joint between the conductive plate and the terminal. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to an embodiment; [Figure 2] 1 is a plan view of a main part of a semiconductor device according to an embodiment; [Figure 3] 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment; [Figure 4] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a modified example. [Figure 5] 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0015] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "top surface" refer to the XY plane facing upward (+Z direction) in the semiconductor device 1 shown in the drawings. Similarly, "top" refers to the upward direction (+Z direction) in the semiconductor device 1 shown in the drawings. The terms "back surface" and "bottom surface" refer to the XY plane facing downward (-Z direction) in the semiconductor device 1 shown in the drawings.

[0016] Similarly, "bottom" refers to the downward direction (-Z direction) in the semiconductor device 1 in the figure. The same directionality as above will be used in other figures as needed. "Higher" and "upper" refer to the upper position (+Z direction) in the semiconductor device 1 in the figure.

[0017] Similarly, "lower" and "lower" refer to the position on the lower side (-Z direction) in the semiconductor device 1 shown in the figure. "Front surface," "top surface," "top" and "back surface," "bottom surface," "bottom" and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "top" and "bottom" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "top" and "bottom" are not limited to the direction of gravity.

[0018] In the following description, "main component" refers to a component that contains 80% by volume or more (a proportion excluding the filler if a filler is included). Furthermore, "substantially the same" means that the difference is within a range of ±10%.

[0019] The semiconductor module will be described with reference to FIGS. 1 and 2. FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. FIG. 2 is a plan view of a main part of the semiconductor device according to the first embodiment. Note that FIG. 2 shows an enlarged view of the region including the semiconductor chip and terminals, with the sealing member, case, and wires removed from the semiconductor module of FIG. 1. FIG. 1 is a cross-sectional view taken along dashed line II in FIG. 2, including such a case.

[0020] 1, the semiconductor module 1 includes a semiconductor unit 2, a base plate 3 on the surface of which the semiconductor unit is disposed, a case 4 provided on the upper outer edge of the base plate to house the semiconductor unit, and a lid 5 covering the top surface of the case. The interior of the case 4 of the semiconductor device 1 is sealed with a sealing member 6.

[0021] The sealing member 6 may be, for example, a silicone gel. Alternatively, the sealing member 6 may be a thermosetting resin mixed with a filler. In this case, the thermosetting resin may be, for example, an epoxy resin, a phenolic resin, a maleimide resin, or a polyester resin. The filler is an insulating ceramic having high thermal conductivity. Such a filler may be, for example, silicon oxide, aluminum oxide, boron nitride, or aluminum nitride. The filler content is 10% by volume or more and 80% by volume or less of the entire sealing member 6.

[0022] The semiconductor unit 2 includes an insulating circuit board 7 consisting of an insulating plate 7a, a plurality of conductive patterns 7b provided on the front surface of the insulating plate 7a, and a metal plate 7c provided on the back surface of the insulating plate 7a, a semiconductor chip 8 arranged on the surface of the conductive pattern 7b via solder 10a, a terminal 9a consisting of a lead frame arranged on the surface of the conductive pattern 7b via solder 10b, a conductive block 11 arranged on the surface of the conductive pattern 7b via solder 10c, and a terminal 9b consisting of a lead frame arranged on the conductive block 11 via solder 10d.

[0023] The insulating plate 7a and the metal plate 7c are rectangular in plan view. The corners of the insulating plate 7a and the metal plate 7c may be rounded or chamfered. The size of the metal plate 7c is smaller than the size of the insulating plate 7a in plan view, and is formed inside the insulating plate 7a.

[0024] The insulating plate 7a may be, for example, a ceramic substrate. The ceramic substrate is made of ceramics with good thermal conductivity. The ceramics is made of a material containing aluminum oxide, aluminum nitride, or silicon nitride as its main component, for example.

[0025] The semiconductor chip 8 is disposed on the upper surface of the conductive pattern 7b. The conductive pattern 7b is formed over the entire surface of the insulating plate 7a except for the edges. Preferably, in a plan view, the end of the conductive pattern 7b facing the outer periphery of the insulating plate 7a overlaps the end of the outer periphery of the metal plate 7c. This maintains a stress balance between the insulating circuit board 7 and the metal plate 7c on the back surface of the insulating plate 7a, suppressing damage to the insulating plate 7a such as excessive warping and cracking.

[0026] The conductive pattern 7b is made of a material with excellent conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. The conductive pattern 7a can also be plated with a material with excellent corrosion resistance. Examples of such materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The thickness of the plating film is 10 μm or less.

[0027] The conductive pattern 7b is obtained by forming a metal plate on the front surface of the insulating plate 7a and then performing a process such as etching on the metal plate. Alternatively, the conductive pattern 7b may be cut out from a metal plate in advance and bonded to the front surface of the insulating plate 7a. Note that the conductive pattern 7b included in the semiconductor module 1 of this embodiment is merely an example. The number, shape, size, etc. of the conductive patterns may be selected appropriately as needed.

[0028] The underside of the metal plate 7c is placed on the base plate. The metal plate 7c is made of a metal with excellent thermal conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. To improve corrosion resistance, the surface of the metal plate 23 may be plated. In this case, the plating material contains nickel. Examples of such plating materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The thickness of the plating film is 3 μm or more and 7 μm or less.

[0029] For example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate may be used as the insulating circuit board 7 having such a configuration. Alternatively, a resin insulating substrate using an insulating plate 7a made of resin may be used. The insulating circuit board 7 dissipates heat generated by the semiconductor chip 8 (described later) by conducting it to the back side of the insulating circuit board 7 via the conductive pattern 7b, insulating plate 7a, and metal plate 7c.

[0030] The semiconductor chip 8 includes a switching element made primarily of silicon, for example. The switching element is, for example, an RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor). The RC-IGBT is a circuit in which an IGBT and an FWD (Free Wheeling Diode) are connected in anti-parallel and configured within a single chip.

[0031] The semiconductor chip 8 has a collector electrode as an input electrode on the back surface, and a gate electrode as a control electrode and an emitter electrode as an output electrode on the front surface. The control electrode may be provided at the center of one side of the front surface of the semiconductor chip 8. Alternatively, the control electrode does not necessarily have to be provided at the center of one side of the front surface of the semiconductor chip 8, and may be shifted laterally from the center.

[0032] Another switching element may be a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) mainly composed of silicon carbide. In the power MOSFET, the body diode may function as the FWD. Such a semiconductor chip 8 has, for example, an input electrode (drain electrode) as a main electrode on the back surface, and an output electrode (source electrode) and a control electrode (gate electrode) as main electrodes on the front surface.

[0033] Moreover, instead of the semiconductor chip 8, a semiconductor chip mainly composed of silicon or silicon carbide and including a pair of switching elements and a pair of diode elements may be used.

[0034] The switching element is, for example, a power MOSFET or an IGBT. A semiconductor chip including the switching element has, for example, an input electrode (a drain electrode in a power MOSFET, and a collector electrode in an IGBT) as a main electrode on the back surface, and a gate electrode (a source electrode in a power MOSFET, and an emitter electrode in an IGBT) as a control electrode and an output electrode (a source electrode in a power MOSFET, and an emitter electrode in an IGBT) as a main electrode on the front surface. The diode element uses, for example, an SBD (Schottky Barrier Diode) or a PiN (P-intrinsic-N) diode as an FWD. A semiconductor chip including the diode element has, for example, an output electrode (cathode electrode) as a main electrode on the back surface, and an input electrode (anode electrode) as a main electrode on the front surface.

[0035] The back side of the semiconductor chip 8 is bonded to the conductive pattern 7b with solder 10a. The solder is made of lead-free solder containing a predetermined alloy as a main component. The predetermined alloy contains tin. Such an alloy is, for example, at least one of an alloy consisting of tin-silver, an alloy consisting of tin-silver-copper, an alloy consisting of tin-zinc-bismuth, an alloy consisting of tin-copper, an alloy consisting of tin-silver-indium-bismuth, and an alloy consisting of tin-antimony. The solder may contain an additive. Examples of the additive include nickel, germanium, cobalt, and silicon. These solders are preferably bonded using plate-shaped solder.

[0036] Also, a sintered body may be used instead of solder. When joining using a sintered body, the sintered material is, for example, a powder of silver, iron, copper, aluminum, titanium, nickel, tungsten, or molybdenum. Note that here, the solder 10a is made of the same solder as the solder 10c described below.

[0037] The upper surface of the semiconductor chip 8 is connected to the wiring member 12. In this example, the wiring member is a wire. The wire is a member made of a metal material such as copper or aluminum.

[0038] The wires connect the semiconductor chip 8 and the conductive pattern 7b.

[0039] The case 4 is made up of a frame portion 41. The frame portion 41 has a rectangular shape in a plan view and forms a frame shape surrounding a storage area 42. The storage area 42 is an open area extending from an upper opening 42a on the front surface of the case 4 to a lower opening 42b on the back surface. The frame 41 is formed by injection molding using a thermoplastic resin containing a filler. Examples of such a resin include polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, and polyamide (PA) resin. The filler may be, for example, glass fiber, glass beads, calcium carbide, talc, magnesium oxide, or aluminum hydroxide.

[0040] The outer periphery of the front surface of the base plate 3, to which the semiconductor unit 2 is bonded, is bonded with an adhesive (not shown) to the back surface of the frame 41 of the case 4 on the side of the lower opening 42b. This allows the semiconductor unit 2 to be stored in the storage area 42 of the frame 41. A lid 5 may also be bonded with an adhesive to the front surface of the frame 41 on the side of the upper opening 42a. The adhesive may be, for example, a thermosetting resin adhesive or an elastomer adhesive. The thermosetting resin adhesive is primarily composed of, for example, epoxy resin or phenolic resin. The elastomer adhesive is primarily composed of, for example, silicone rubber or chloroprene rubber.

[0041] The base plate 3 is mainly composed of copper. The thickness of the base plate 3 depends on the size of the semiconductor device 1, but may be, for example, 2.5 mm or more and 3.5 mm or less. The base plate 3 is also provided with a plating layer to improve corrosion resistance. The plating layer contains nickel. Examples of such plating layers include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0042] The solder 10e is provided on the base plate to join the insulating circuit board to the surface of the base plate, and has a thickness of 100 μm or more and 500 μm or less.

[0043] Terminal 9a is not adjacent to the semiconductor chip, but has one end joined to the surface of the conductive pattern by solder 10b, while terminal 9b is adjacent to semiconductor chip 8, and has one end joined to the surface of the conductive pattern via solder 10c, conductive block 11, and solder 10d.

[0044] The terminals 9a and 9b are made of lead frames formed of a metal material such as copper or aluminum, and at least a portion of the surface may be plated with nickel or the like. The terminals 9a and 9b may have a plate-like portion. The plate-like shape refers to a shape in which the area of ​​two opposing main surfaces is larger than the area of ​​the other surfaces. At least the portions of the terminals 9a and 9b that connect to the conductive pattern 7b or the conductive block 11, and the leg portions 9c, may be plate-like. The terminals 9a and 9b may be formed by bending a single metal plate.

[0045] Terminals 9a and 9b extend upward and protrude from openings in the top cover of the case. In this example, the lead frame is a copper plate 10 to 15 mm wide and 1 mm thick, with its tip bent so that the length of the part facing the metal plate is 4 mm.

[0046] The terminals may extend laterally and be joined to terminals provided on the frame portion 41 of the case 4, or may be formed integrally with the frame portion.

[0047] FIG. 2 shows a plan view of a portion where terminal 9b is bonded onto conductive pattern 7b via conductive block 11. Conductive block 11 consists of conductive plate 11a and solder dam 11b provided at the edge of the surface of conductive plate 11a. Conductive plate 11a is preferably rectangular. Leg 9c of terminal 9b is rectangular and is bonded to approximately the center of the area surrounded by solder dam 11b on the surface of conductive plate 11a. Conductive block 11 is adjacent to semiconductor chip 8 and is bonded to conductive pattern 7b between adjacent semiconductor chips 8.

[0048] 3 shows a cross-sectional view of a portion where leg portion 9c of terminal 9b is joined onto conductive pattern 7b via conductive block 11. Only the portion of terminal 9b close to conductive block 11 is shown. FIG. 3 is an enlarged view of cross section II of FIG. 2.

[0049] The height of solder dam 11b from the top surface of conductive plate 11a is designated as Hd. Hd is set to a dimension greater than the required solder thickness determined in consideration of the thermal resistance and fatigue life of the solder layer, preventing solder from overflowing and causing poor chip bonding even if sufficient solder is supplied. Specifically, the solder thickness should be 0.1 mm to 0.3 mm, and the solder dam height Hd should be approximately 0.5 mm to 1.5 mm.

[0050] The distance from the inside of the solder dam 11b to the end of the terminal leg is preferably about 0.2 mm to 1.0 mm, more preferably about 0.3 mm to 0.8 mm, and is set to 0.5 mm in this embodiment.

[0051] The conductive plate 11a may be made of copper, aluminum, iron, or an alloy containing these as its main components. The conductive plate 11a may also be plated. Examples of the plated layer include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The thickness of the conductive plate is preferably about 0.15 mm to 0.3 mm.

[0052] The solder dam 11b may be integral with the conductive plate 11a, in which case the conductive plate 11a may be formed by drawing a flat plate.

[0053] 3(a) shows a state in which the solder 10d spreads to form a good fillet 13, and the solder is stopped by the solder dam 11b. By supplying a sufficient amount of solder 10d, a good bond can be obtained between the terminal and the conductive plate 11a, and a good bond can be obtained between the terminal 9b and the conductive pattern 7b.

[0054] 3(b) shows a state in which the amount of solder 10d has increased and the solder 10d has risen to the solder dam 11b at the end of the fillet 13. This makes it possible to suppress the concentration of stress at the end of the solder 10d and improve reliability.

[0055] 3(c) shows a state in which the amount of solder 10d is further increased, and the solder 10d is bonded not only to the bottom surface of the leg 9c of the terminal but also to the side surface, thereby further suppressing the concentration of stress at the end of the solder 10d and improving reliability.

[0056] The solder 10c between the conductive block and the conductive pattern can be made of plate-shaped solder to prevent the solder from spreading and prevent poor chip bonding. As with the bonding between the chip and the conductive pattern, a sintered material may be used instead of solder.

[0057] Furthermore, by using the same material for the solder 10c as that for the solder 10a that joins the semiconductor chip to the conductive pattern, the semiconductor chip and the conductive block can be joined together, thereby suppressing an increase in the number of processes.

[0058] In addition, by using cream solder for the solder 10d used to join the terminals and the conductive block, sufficient solder can be supplied and a strong bond can be obtained as shown in Figures 3(b) and 3(c). Furthermore, by using the same material as the solder 10b used to directly join the terminals to the conductive pattern, the number of processes can be reduced. Furthermore, compared to the conventional case where a resin or wire dam is provided on a conductive pattern, the process of providing the dam is easier and the space can be reduced. [Variations] A modified example of the semiconductor module of the embodiment will be described with reference to FIG.

[0059] The conductive block 11 of the modified example also comprises a conductive plate 11a and a solder dam 11c, and differs from the embodiment in that the solder dam 11c is made of resin.

[0060] In this case, insulation failure due to contact between the semiconductor chip and the conductive block can be prevented. Furthermore, compared to providing a resin dam on the conductive pattern, the process of providing the dam is easier and space can be reduced.

[0061] The resin material used should be a highly heat-resistant resin. Specific examples include thermosetting or photosetting polyimide resin, silicone resin, epoxy resin, urethane resin, phenolic resin, and maleimide resin. These liquid resins can be applied to the conductive plate 11a and then cured to form the dam 11c. A dispenser can be used as the application method.

[0062] Alternatively, a cured resin in the shape of a dam may be formed in advance using a mold, and then adhered to the conductive plate 11a with an adhesive to form the dam 11c. Thermosetting or photocurable polyimide resin, silicone resin, epoxy resin, urethane resin, phenolic resin, or maleimide resin may be used for the resin or adhesive in the shape of the dam. Alternatively, the cured resin in the shape of the dam may be injection molded using a thermoplastic resin. Examples of such resins include polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, and polyamide (PA) resin.

[0063] It is advisable to prepare the conductive plate 11a by forming a solder dam 11c on the conductive plate 11a, and then bond the conductive block onto the conductive pattern.

[0064] In this case, when joining the terminals with solder 10d, it is necessary to prevent deterioration of solder dam 11c and a decrease in the adhesive strength between solder dam 11c and conductive plate 11a. To this end, it is preferable to set the solidus or melting point of solder 10d lower than the glass transition point or thermal decomposition temperature of the resin or adhesive, and to set the joining temperature of solder 10d lower than the glass transition point or thermal decomposition temperature of the resin or adhesive. [Manufacturing method] Next, a method for manufacturing the semiconductor device 1 will be described with reference to Fig. 5. Fig. 5 is a flowchart showing the manufacturing method. Note that the flowchart showing the manufacturing method in Fig. 5 is merely an example. The semiconductor device 1 can be manufactured by methods other than the flowchart in Fig. 5 as long as it includes a base plate 3 to which a semiconductor unit 2 is bonded.

[0065] First, a preparation step is performed to prepare the components of the semiconductor device 1 (step S1 in FIG. 5). The components prepared at this time include, for example, the insulating circuit board 7, the semiconductor chip 8, the conductive block 11, the case 4, and the base plate 3. In addition to these, other components necessary for the semiconductor device 1 may also be prepared. In addition, manufacturing equipment used to manufacture the semiconductor device 1 may also be prepared.

[0066] The metal plate constituting the conductive block is drawn after cutting, and when a resin dam is used, the resin dam may be formed either before or after cutting the metal plate.

[0067] Next, the insulating circuit board 7 is placed on the base plate 3 via the solder 10e, and the semiconductor chip and conductive block are placed on the insulating circuit board 7 via the solders 10a and 10c (step S2 in FIG. 5). The solders 10a, 10c, and 10e are plate solders made of the same material.

[0068] Thereafter, bonding (reflow) is performed using a hydrogen reduction furnace (step S3 in FIG. 5). When a resin material is used for the solder dam, it is advisable to set the bonding temperature lower than the glass transition point or decomposition temperature of the resin material to prevent deterioration of the resin material and a decrease in adhesive strength between the resin material and the conductive plate 11a.

[0069] Subsequently, the conductive pattern 7b on the insulating circuit board 7 and the bonding wires of the semiconductor chip 8 are ultrasonically bonded (step S4 in FIG. 5), thereby forming the semiconductor unit 2 arranged on the base plate 3.

[0070] Solder 10b and 10d are applied to the conductive pattern 7b and the conductive block of the insulating circuit board 7. The solder 10b and 10d are preferably applied using a dispenser. Then, terminals 9a and 9b are placed on the solder of the conductive pattern and the conductive block (step S5 in FIG. 5). The solder 10b and 10d are then melted and joined using a hydrogen reduction furnace (step S6 in FIG. 5).

[0071] Next, an adhesive is applied to the outer periphery of the base plate 3, and then the case 3 is placed thereon and heated to bond and harden (step S7 in FIG. 5). After that, a sealing member 6 made of silicone gel is introduced into the case so as to cover the semiconductor unit 2 and the leg portions 9c of the terminals, and is heated and hardened (step S8 in FIG. 5).

[0072] Then, the lid 5 is attached to the case. The lid may be attached by fitting or by adhesion (step S9 in FIG. 5).

[0073] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. Modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included in the technical scope of the present invention. [Explanation of symbols]

[0074] 1. Semiconductor module 2 Semiconductor Unit 3 Base Plate 4 cases 41 Frame 42 Storage Area 42a Top opening 42b Bottom opening 5 Lid 6 Sealing member 7. Insulated circuit board 7a Insulating plate 7b Conductive pattern 7c metal plate 8. Semiconductor Chips 9, 9a, 9b terminals 9c Terminal leg 10, 10a, 10b, 10c, 10d, 10e solder 11 Conductive Block 11a Conductive plate 11b, 11c Solder dam 12 Wiring materials 13 Fillet

Claims

1. In a semiconductor device in which a conductive pattern and a lead frame are joined via a conductive plate, the conductive plate and the lead frame are joined by soldering; A semiconductor device comprising: a solder dam formed on the conductive plate to surround the bonding area of ​​the lead frame.

2. The height of the solder dam from the conductive plate is equal to or greater than the solder joint thickness. The semiconductor device according to claim 1 .

3. A semiconductor element is bonded to the conductive pattern. The semiconductor device according to claim 1 .

4. The conductive pattern and the conductive plate are joined by solder. The semiconductor device according to claim 1 .

5. The solder dam is integrally formed with the conductive plate.

5. The semiconductor device according to claim 1.

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