Semiconductor devices and electrical equipment

Abstract

To obtain a highly reliable semiconductor device with improved heat dissipation characteristics.SOLUTION: A power semiconductor chip 10 and a control chip 20 are stacked in this order and mounted. The power semiconductor chip 10 is bonded via a conductive metal bonding layer. At this time, a large metal pad 11 connected to a drain (D) electrode is formed on the back surface of the power semiconductor chip 10. The control chip 20 and the power semiconductor chip 10 are bonded via an insulating bonding layer. Electrodes (terminals) other than the drain (D) electrode and a gate (G) electrode are taken out as pins (lead terminals) protruding from negative and positive sides of the semiconductor device 1 in a y direction.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] An embodiment of the present disclosure relates to a semiconductor device and an electrical device in which the semiconductor device is used. [Background technology]

[0002] There is known an IPD (Intelligent Power Device) in which power semiconductor elements (rectifier diodes, power MOSFETs, IGBTs, etc.) that perform switching and rectification of large currents and a control IC for controlling them are mounted in a common module. In this case, the power semiconductor elements and the control IC are formed on different semiconductor substrates, and it is desirable that the semiconductor substrate on which the power semiconductor elements, which generate a large amount of heat during operation, are formed has high heat dissipation efficiency.

[0003] Furthermore, one of the functions of the control IC is to forcibly stop the operation of a power semiconductor element and issue an alarm to the outside if an excessive temperature rise occurs in the element, for example.

[0004] The structure of such an IPD is described, for example, in Patent Document 1. In this IPD (semiconductor device), a semiconductor substrate (power semiconductor chip) on which a power semiconductor element is formed is mounted on a large heat sink, a semiconductor substrate (control chip) on which a control IC is formed is mounted on a small heat sink separate from the large heat sink, and a temperature sensor is mounted on the latter heat sink. The entire structure is sealed in a common package (sealing resin layer).

[0005] This structure makes it possible to control the power semiconductor elements while suppressing excessive temperature rise during operation. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 4985809 Summary of the Invention [Problem to be solved by the invention]

[0007] In order to achieve low on-resistance and low switching loss in power semiconductor elements, it is effective to increase the element size, i.e., the size of the power semiconductor chip. In this case, the size of the entire semiconductor device increases. In this case, the size of a semiconductor device that includes both a control chip and a power semiconductor chip becomes particularly large. Alternatively, when the size of the entire semiconductor device is limited, it is difficult to improve the on-resistance and switching loss in the power semiconductor element.

[0008] Therefore, an IPD that allows a larger area for the power semiconductor chip is desired.

[0009] The present disclosure has been made in consideration of the above problems, and aims to provide a semiconductor device and an electrical device that solve the above problems. [Means for solving the problem]

[0010] In order to solve the above problems, the present disclosure has the following configuration. The semiconductor device of the present disclosure is a semiconductor device in which a power semiconductor chip, on which a power semiconductor element in which a current between a first main electrode and a second main electrode is controlled by a control electrode, and a control chip, on which a control element that controls the power semiconductor element, are mounted, are provided in an encapsulating resin layer made of an insulating resin material, the structure of which is mounted on a metal lead frame, the power semiconductor chip having a pad connected to the first main electrode formed on its underside, a pad connected to the second main electrode, and a pad connected to the control electrode formed on its upper side, the power semiconductor chip and the lead frame being joined by a conductive metal bonding layer, the control chip being bonded on top of the power semiconductor chip via an insulating insulating bonding layer and connected to the pad connected to the control electrode in the power semiconductor chip, the lead frame being exposed on the underside of the encapsulating resin layer, and a pin connected to the second main electrode of the power semiconductor element on one side in one direction along the horizontal direction and a pin connected to an electrode used to control the control element on the other side in the one direction each protrude from the encapsulating resin layer. [Effects of the Invention]

[0011] Since the present disclosure is configured as described above, an IPD that allows a large area for the power semiconductor chip can be obtained. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a diagram illustrating an example of a circuit configuration of a semiconductor device according to an embodiment of the present disclosure. [Figure 2] 1A and 1B are a top view and a bottom view, respectively, of a semiconductor device according to an embodiment of the present disclosure. [Figure 3] 1A to 1C are side perspective views of a semiconductor device according to an embodiment of the present disclosure as viewed from two different directions. [Figure 4] 1 is a plan view illustrating a configuration of a metal frame used when manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 5]1 is a diagram illustrating an example of a configuration of an electrical device in which a semiconductor device according to an embodiment of the present disclosure is used; DETAILED DESCRIPTION OF THE INVENTION

[0013] A semiconductor device according to an embodiment of the present disclosure will be described below. This semiconductor device is a semiconductor module including a power semiconductor chip, which is a semiconductor substrate on which power semiconductor elements are formed, and a control chip on which a control IC for controlling the power semiconductor chip is formed. FIG. 1 is a simplified diagram showing two examples of the circuit configuration of this semiconductor device. In the example of FIG. 1(a), a power semiconductor chip 10 is equipped with one power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and a drain (D) electrode (first main electrode), a source (S) electrode (second main electrode), and a gate (G) electrode (control electrode) are provided as input / output terminals to the outside. The potential of the gate (G) electrode of the MOSFET is controlled by a control chip (control IC) 20. Terminals for input / output between this semiconductor device and the outside are provided on the left side of the control chip 20 in the figure. Three terminals are provided in the figure, but the number can be set appropriately depending on the purpose, function, etc. of the semiconductor device. Furthermore, as described in Patent Document 1, for example, the control chip 20 is equipped with a temperature sensor, and if the temperature rises excessively, the gate potential of the MOSFET can be controlled to forcibly turn it off.

[0014] The gate potential of the MOSFET is at most about 10 V, and the potential applied to or output from other terminals of the control chip 20 is also at a similar level. On the other hand, a voltage of up to about 1000 V is applied between the source and drain of the power MOSFET, and the current that flows is also large. For this reason, the terminals provided on the control chip 20 side are compatible with the above-mentioned low voltages and low currents, and the terminals provided on the power semiconductor chip 10 are compatible with the above-mentioned high voltages and large currents.

[0015] In the circuit configuration of Figure 1(b), two MOSFETs are mounted on the power semiconductor chip 10, and each has a source (S) and drain (D) terminal as an input / output terminal to the outside. The potential of each gate (G) electrode is controlled by the control IC 20, as described above. The terminals used for input / output between the control chip 20 and the outside are set appropriately, as in the case of Figure 1(a), and both terminals are also compatible with low voltages and low currents.

[0016] The configuration of the semiconductor device 1 described below corresponds to FIG. 1(a). FIGS. 2(a) and 2(b) show top and bottom perspective views of the semiconductor device 1, respectively, and FIG. 3 shows side perspective views from two different horizontal directions. Here, the up-down direction is defined as the direction (z direction) perpendicular to the surface of the semiconductor substrate (power semiconductor chip 10, control chip 20) on which the semiconductor device is mounted. The semiconductor device 1 is a small outline package (SOP), and multiple pins are arranged for input and output on both the negative side (one side) and the positive side (the other side) of one horizontal direction (y direction). Each pin is used for input and output between the semiconductor device 1 and the outside. FIGS. 3(a) and 3(b) show side views along the x and y directions, respectively. For ease of explanation, the scale in the z direction in FIG. 3 is enlarged compared to the x and y directions.

[0017] In this power semiconductor device 1, a power semiconductor chip 10 and a control chip 20 are sequentially stacked and mounted on a single lead frame 31 made of copper or a copper alloy. Lead frame 31 has lead frame connecting portions 311 at the ends on the positive and negative sides in the x direction, which locally protrude and extend toward the positive and negative sides in the x direction, respectively.

[0018] At this time, as shown in FIG. 3, the power semiconductor chip 10 is bonded via a conductive metal bonding layer 41. At this time, as shown in FIG. 2(b), a large metal pad 11 connected to the drain (D) electrode in FIG. 1 is formed on the back surface (surface on the lead frame 31 side) of the power semiconductor chip 10. Therefore, the entire lead frame 31 serves as the drain terminal (high-side terminal) of the MOSFET. Furthermore, because heat dissipation from the power semiconductor chip 10 during operation also occurs via the metal bonding layer 41, it is preferable to use a material with high electrical conductivity and thermal conductivity for the metal bonding layer 41. For this reason, it is preferable to use, for example, solder or a bonding material containing silver particles (nanosilver particles) that can be bonded at about 300°C for the metal bonding layer 41.

[0019] The control chip 20 and the power semiconductor chip 10 are bonded together by an insulating bonding layer 42. An insulating adhesive, an insulating film for bonding (DAF: Die Attach Film), or the like can be used as the insulating bonding layer 42. When these materials are used, the thermal conductivity of the insulating bonding layer 42 is lower than that of the metal bonding layer 41.

[0020] 1, electrodes (terminals) other than the drain (D) electrode and gate (G) electrode are taken out as pins (lead terminals) that protrude respectively on the negative and positive sides in the y direction in this semiconductor device 1. In Fig. 2, on the negative side in the y direction, a lead 51 formed from the same metal plate as the lead frame 31 is installed adjacent to the lead frame 31. The lead 51 has 12 pins (lead terminals) arranged along the x direction, each protruding toward the negative side in the y direction, but as shown in Fig. 2, these are actually integrated to form the lead 51.

[0021] Similarly, leads are provided on the positive side in the y direction, but on this side, pins (lead terminals) 52A to 52L are formed separated from one another in the x direction, unlike lead 51. Therefore, each pin can be used as an individual functional terminal.

[0022] The source (S) electrode of the power semiconductor chip 10 is connected to a pad 12 on the surface of the power semiconductor chip 10 (the surface opposite to the lead frame 31). Because a large current flows through this terminal when the power semiconductor chip 10 is turned on, the pad 12 is formed, for example, from an Al-Si alloy with a thickness of 4 μm, and is long in the x direction and has a large area. Here, the pad 12 may not have a simple rectangular shape, but may be patterned to correspond to copper rewiring. The pad 12 is also connected to the lead 51 by 15 bonding wires 61. Here, in order to accommodate a large current, the bonding wires 61 are made of, for example, copper wires with a diameter of 50 μm, and by using a plurality of these in parallel, it is possible to accommodate a large current when the power semiconductor chip 10 is turned on. Instead of the 15 bonding wires 61, clip leads made of a metal plate similar to the lead frame 31 may be connected.

[0023] Furthermore, a plurality of pads 21 (seven in FIG. 2) are formed on the surface of the control chip 20, and these are connected to the respective terminals extending from the control chip 20 on the left side in FIG. 1(a). The pads 21 are formed, for example, of a 3 μm thick AlCu / Ti laminated structure. Each pad 21 is connected to the lead terminals 52B to 52H by a bonding wire 62. Since the bonding wire 62 does not carry the large current described above, it is made of, for example, a 25 μm diameter copper wire, and the signals flowing through each bonding wire 62 are independent.

[0024] Also, a plurality of pads 13 (five in FIG. 2) connected to the gate (G) electrodes of the MOSFET are formed on the upper surface of the power semiconductor chip 10, and each is connected to a pad 22 for gate voltage control formed on the upper surface of the control chip 20 by a bonding wire 63. The pad 22 and the bonding wire 63 are the same as the pad 21 and the bonding wire 62 described above, respectively.

[0025] 2 and 3, the above structure is sealed in a sealing resin layer 100 made of an insulating resin material (such as an epoxy resin). At this time, each pin of the lead 51 protrudes from the sealing resin layer 100 on the negative side in the y direction, and pins (lead terminals) 52A to 52L protrude from the sealing resin layer 100 on the positive side in the y direction. Also, as shown in FIG. 3, the lead frame 31 is exposed on the back side (negative side in the z direction) of the sealing resin layer 100.

[0026] 1(a) is connected to the lead frame 31 exposed on the back surface side of the semiconductor device 1, and the other electrodes (terminals) are connected to leads protruding from the sealing resin layer 100 on the negative and positive sides in the y direction. Therefore, when mounting the semiconductor device 1, the semiconductor device 1 can be used by joining the external wiring and each of these leads, as well as a metal plate to which a voltage is applied and on which the semiconductor device 1 is mounted, to the lead frame 31 on the back surface side.

[0027] In the above structure, by stacking the control chip 20 and the power semiconductor chip 10 on the lead frame 31, it is possible to reduce the area of ​​the lead frame 31 or the entire area even when two chips (semiconductor substrates) are used in this way. In this case, the power semiconductor chip 10, which generates a large amount of heat during operation, is joined to the lead frame 31 by the metal bonding layer 41, which has high thermal conductivity, so that heat is efficiently dissipated via the metal bonding layer 41 and the lead frame 31 to the substrate on which the semiconductor device 1 is mounted.

[0028] On the other hand, since an insulating bonding layer 42 with low thermal conductivity is provided between the control chip 20 and the power semiconductor chip 10, the heat generated by the power semiconductor chip 10 is not easily transmitted to the control chip 20. Therefore, the adverse effect of this heat on the operation of the control chip 20 is suppressed.

[0029] In the semiconductor device 1, the highest voltage is applied between the drain (D) electrode and the source (S) electrode in Fig. 1(a). In Figs. 2 and 3, a thick resin material constituting the sealing resin layer 100 is formed between these electrodes, ensuring insulation therebetween.

[0030] To manufacture this semiconductor device 1, a metal frame as shown in FIG. 4 is used, in which the lead frames 31 are connected in the x and y directions and arranged two-dimensionally. In this metal frame, the lead frame connecting portions 311 are connected to beam portions 35 extending in the y direction, and the leads are connected to beam portions 36 extending in the x direction, forming a two-dimensional array of the lead frames 31 and the leads shown in FIG. 2. The power semiconductor chip 10 and the control chip 20 are mounted on the metal frame in the portions corresponding to the lead frames 31, as described above, and bonding wires are connected to form the encapsulating resin layer 100. The semiconductor device 1 can then be obtained by cutting along the cutting line C in FIG. 4. This manufacturing method is similar to that used to manufacture conventional semiconductor modules (semiconductor devices), except for the use of a metal frame with the above structure. Therefore, the semiconductor device 1 can be easily manufactured.

[0031] In the above example, the drain (D) electrode (main electrode on the high potential side) of the power MOSFET is connected to the lead frame 31 side, and the source (S) electrode (main electrode on the low potential side) is connected to the pin on the upper surface side, but this setting can be changed as appropriate depending on the manner of use of this semiconductor device, etc. In other words, the main electrode on the low potential side may be connected to the lead frame side, and the main electrode on the high potential side may be connected to the pin on the upper surface side.

[0032] Although the semiconductor device 1 described above has the circuit configuration shown in FIG. 1(a), a semiconductor device having the circuit configuration shown in FIG. 1(b) can also be realized in the same way. In this case, one of the main electrodes (drain or source) of the two MOSFETs can be connected to the lead frame in a common manner as described above. In this case, the other main electrode can be connected to each of the two leads, for example, by dividing the lead 51 in FIG. 2 into two. Each control electrode can be individually connected to a control chip in the same manner as in FIG. 2.

[0033] In the above example, the power semiconductor element formed on the power semiconductor chip 10 is a power MOSFET, but other types of elements may be used. An example of such an element is an IGBT (Insulated Gate Bipolar Transistor). In this case, a collector electrode and an emitter electrode are used instead of the drain electrode and source electrode (first electrode and second electrode), and the operation thereof is similarly performed by controlling the potential of the gate electrode.

[0034] The semiconductor device 1 having the above configuration can control a large current with a small configuration, and therefore is particularly easy to install for each load in an electrical device that simultaneously uses multiple loads that consume power, such as those installed in automobiles.

[0035] In an automobile, such loads include small motors for driving wipers, windows, etc., air conditioner motors, various actuators, various sensors, etc., and the ECU (Engine Control Unit) is also included in this load. To prevent a malfunction (such as a short circuit) in any of these loads from significantly affecting the overall functionality of the automobile, a fuse is provided for each of these loads. If a short circuit occurs in one load, the power supply to that load is cut off, making it impossible to use, while power is normally supplied to other loads. For this reason, in the past, a large number of fuses were provided in a fuse box, or a large number of fuse boxes were provided.

[0036] 5 schematically shows the configuration of an electrical device (electrical control system of an automobile) 400 using the semiconductor device 1. Here, a battery 410 is used as a power source, and output from the battery 410 is supplied to various loads 430 throughout the vehicle via a wire harness 420 that can pass a large current. Here, an IPD 440, which is the semiconductor device 1, is provided between the load 430 and the wire harness 420, and each load 430 is controlled by the IPD 440. In other words, the semiconductor device 1 can be used instead of a fuse.

[0037] In the above-mentioned semiconductor device 1, the power semiconductor chip 10 that can handle large power (large current) and the control chip 20 can be combined while miniaturizing the entire device, so that a function similar to that of a fuse in the event of an abnormality can be realized in the small semiconductor device 1 (IPD440).

[0038] In this case, while a fuse only functions to cut off the current in the event of an overcurrent, the configuration of the control chip (control IC) allows it to cut off the power supply to the corresponding load 430 in response to other conditions, for example, the occurrence of an abnormality other than an overcurrent in the corresponding load 430. In other words, the vehicle can be operated more safely. Furthermore, because safety against overcurrent is thus improved, a wire harness 420 with a smaller diameter can be used, making it lighter and easier to handle.

[0039] 5, depending on the configuration of the control chip used, it is also possible to link, for example, IPDs 440 corresponding to different loads 430. In other words, if an abnormality is detected in one load 430, it is possible to easily perform an operation such as restricting the power supply not only to this load 430 but also to other loads 430.

[0040] Furthermore, when a fuse is used, electrical and mechanical contacts are provided when the fuse is installed, whereas when the semiconductor device 1 (IPD440) described above is used, it is mounted using, for example, solder, and no such electrical or mechanical contacts exist. Therefore, problems caused by, for example, wear of such contacts do not occur, and higher reliability is achieved than when a fuse is simply used. It is clear that such applications can be realized in applications other than automobiles as well. [Explanation of symbols]

[0041] 1. Semiconductor device (semiconductor module: IPD) 10 Power semiconductor chips 11, 12, 13, 21, 22 pads 20 Control chip (control IC) 31 Lead frame 35, 36 Beam section 41 Metal bonding layer 42 Insulating bonding layer 51 leads 52A~52L pins (lead terminals) 61, 62, 63 Bonding wire 100 Sealing resin layer 311 Lead frame connection part 400 Electrical Equipment (Automotive Electrical Control Systems) 410 Battery 420 Wire Harness 430 load 440 IPD

Claims

1. A semiconductor device in which a power semiconductor chip, in which a power semiconductor element in which a current between a first main electrode and a second main electrode is controlled by a control electrode, is formed on a metal lead frame, and a control chip, in which a control element for controlling the power semiconductor element is formed, are mounted on the power semiconductor chip, and the structure is provided in a sealing resin layer made of an insulating resin material, In the power semiconductor chip, a pad connected to the first main electrode is formed on a lower surface, and a pad connected to the second main electrode and a pad connected to the control electrode are formed on an upper surface, The power semiconductor chip and the lead frame are joined by a conductive metal joining layer, the control chip is bonded onto the power semiconductor chip via an insulating bonding layer and is connected to a pad on the power semiconductor chip that is connected to the control electrode, the lead frame is exposed on the lower surface of the sealing resin layer, A semiconductor device characterized in that a pin connected to the second main electrode of the power semiconductor element on one side in one direction along the horizontal direction, and a pin connected to an electrode used to control the control element on the other side in the one direction, are configured to protrude from the sealing resin layer.

2. 2. The semiconductor device according to claim 1, wherein in the power semiconductor chip, the first main electrode is an electrode to which a high potential is applied, and the second main electrode is an electrode to which a low potential is applied.

3. 2. The semiconductor device according to claim 1, wherein the metal bonding layer contains solder or silver particles.

4. 4. The semiconductor device according to claim 3, wherein the insulating bonding layer is an adhesive material or an insulating film.

5. 3. An electrical device comprising the semiconductor device according to claim 1.

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