Semiconductor device

Abstract

To provide a semiconductor device that suppresses thermal interference between adjacent semiconductor elements.SOLUTION: A semiconductor device 10 includes a component-embedded substrate 20, which includes a substrate 25, a first semiconductor element 31, a second semiconductor element 32 arranged next to the first semiconductor element 31 at a distance in a direction perpendicular to the thickness direction DT of the substrate 25, a first heat dissipation member 61 connected to the first semiconductor element 31 in the thickness direction DT, a second heat dissipation member 62 connected to the second semiconductor element 32 in the thickness direction DT, and a thermal interference suppression member 65 arranged between the first heat dissipation member 61 and the second heat dissipation member 62 and configured to dissipate heat to the outside of the component-embedded substrate 20.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] As described in Patent Document 1, there has been known an electronic device including a component-embedded substrate, a capacitor, and a first heat dissipation member. The capacitor is provided on a first surface, which is one of the two surfaces in the thickness direction of the component-embedded substrate. The first heat dissipation member is provided on a second surface, which is one of the two surfaces in the thickness direction of the component-embedded substrate and is the surface opposite to the first surface. The component-embedded substrate also includes a semiconductor element and a second heat dissipation member. The semiconductor elements are embedded in the component-embedded substrate, and multiple semiconductor elements are arranged at intervals in a direction perpendicular to the thickness direction of the component-embedded substrate. The second heat dissipation members are embedded in the component-embedded substrate, and are provided between the capacitor and the first heat dissipation member, and multiple second heat dissipation members are arranged at intervals in a direction perpendicular to the thickness direction of the component-embedded substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-97157 Summary of the Invention [Problem to be solved by the invention]

[0004] In the electronic device described in Patent Document 1, when a capacitor generates heat, the heat is conducted to the first heat dissipation member via the second heat dissipation member. The second heat dissipation member promotes heat conduction to the first heat dissipation member, thereby promoting heat dissipation from the capacitor. However, not only the capacitor but also the semiconductor element generates heat. Because multiple second heat dissipation members connected to the semiconductor element are arranged at intervals in a direction perpendicular to the thickness direction of the component-embedded substrate, the heat from the semiconductor element is easily conducted to adjacent semiconductor elements. This makes it easy for thermal interference to occur between adjacent semiconductor elements. This makes the semiconductor elements more susceptible to damage.

[0005] An object of the present disclosure is to provide a semiconductor device that suppresses mutual thermal interference between adjacent semiconductor elements. [Means for solving the problem]

[0006] The invention described in claim 1 is a semiconductor device comprising a component-embedded substrate (20), the component-embedded substrate having a substrate (25), a first semiconductor element (31) embedded in the substrate, a second semiconductor element (32) embedded in the substrate and aligned with the first semiconductor element at an interval in a direction perpendicular to the thickness direction (DT) of the substrate, a first heat dissipation member (61) embedded in the substrate and connected to the first semiconductor element in the thickness direction and through which heat from the first semiconductor element is conducted, a second heat dissipation member (62) embedded in the substrate and connected to the second semiconductor element in the thickness direction and through which heat from the second semiconductor element is conducted, and a thermal interference suppression member (65) embedded in the substrate and arranged between the first heat dissipation member and the second heat dissipation member and dissipating heat to the outside of the component-embedded substrate.

[0007] As a result, heat conducted from the first semiconductor element to the first heat dissipation member is conducted to the thermal interference suppression member. Furthermore, the heat conducted to the thermal interference suppression member is dissipated to the outside of the component-embedded substrate. Therefore, heat conducted from the first semiconductor element to the first heat dissipation member is less likely to be conducted to the second heat dissipation member and the second semiconductor element. Furthermore, heat conducted from the second semiconductor element to the second heat dissipation member is conducted to the thermal interference suppression member. Furthermore, heat conducted to the thermal interference suppression member is dissipated to the outside of the component-embedded substrate. Therefore, heat conducted from the second semiconductor element to the second heat dissipation member is less likely to be conducted to the first heat dissipation member and the first semiconductor element. Therefore, mutual thermal interference between the first semiconductor element and the second semiconductor element is suppressed.

[0008] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 10 is a cross-sectional view of a semiconductor device according to a comparative example. [Figure 3] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 4] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 5] FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 6] FIG. 10 is a cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 7] FIG. 10 is a cross-sectional view of a semiconductor device according to a sixth embodiment. [Figure 8] FIG. 13 is a cross-sectional view of a semiconductor device according to a seventh embodiment. [Figure 9] FIG. 13 is a cross-sectional view of a semiconductor device according to an eighth embodiment. [Figure 10] FIG. 13 is a cross-sectional view of a semiconductor device according to a ninth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals, and description thereof will be omitted.

[0011] (First embodiment) The semiconductor device of this embodiment suppresses the mutual thermal interference between adjacent semiconductor elements. Specifically, as shown in FIG.

[0012] The component-embedded substrate 20 has a substrate 25, a first semiconductor element 31, a second semiconductor element 32, a first via 41, a first wiring layer 51, a second via 42, a third via 43, a second wiring layer 52, a fourth via 44, a first heat dissipation member 61, a second heat dissipation member 62, and a thermal interference suppression member 65.

[0013] The substrate 25 is a printed circuit board and is made of glass epoxy resin such as FR4. FR4 stands for Flame Retardant Type 4. In the following description, the thickness direction of the substrate 25 will be simply referred to as the thickness direction DT.

[0014] Furthermore, the substrate 25 includes a substrate front surface 252 and a substrate back surface 254. The substrate front surface 252 is a surface that intersects with the thickness direction DT. The substrate back surface 254 is a surface that intersects with the thickness direction DT and is a surface on the opposite side to the substrate front surface 252. Furthermore, here, the substrate front surface 252 and the substrate back surface 254 are perpendicular to the thickness direction DT.

[0015] The first semiconductor element 31 is a MOSFET or an IGBT, and is built into the substrate 25. The first semiconductor element 31 is disposed on the substrate surface 252 side inside the substrate 25. Note that MOSFET is an abbreviation for Metal-Oxide-Semiconductor Field-Effect Transistor, and IGBT is an abbreviation for Insulated Gate Bipolar Transistor.

[0016] The second semiconductor element 32 is a MOSFET or an IGBT, and is built into the substrate 25. Furthermore, the second semiconductor element 32 is disposed on the substrate surface 252 side within the substrate 25. Furthermore, the second semiconductor element 32 is arranged next to the first semiconductor element 31 with a gap therebetween in a direction perpendicular to the thickness direction DT. Therefore, the first semiconductor element 31 and the second semiconductor element 32 are adjacent to each other in the direction perpendicular to the thickness direction DT.

[0017] The first vias 41 are made of copper or the like and are therefore conductive. Furthermore, the first vias 41 are embedded in the substrate 25 and connected to the substrate surface 252 side of the first semiconductor element 31 in the thickness direction DT. Furthermore, a plurality of the first vias 41 are lined up at intervals in a direction perpendicular to the thickness direction DT.

[0018] The first wiring layer 51 is made of copper or the like and is therefore conductive. Furthermore, the first wiring layer 51 is embedded in the substrate 25 and is connected to the side of the first via 41 opposite to the first semiconductor element 31 in the thickness direction DT. Furthermore, the first wiring layer 51 extends in a direction perpendicular to the thickness direction DT.

[0019] The second vias 42 are made of copper or the like and are therefore conductive. Furthermore, the second vias 42 are embedded in the substrate 25 and connected to the side of the first wiring layer 51 opposite to the first vias 41 in the thickness direction DT. Furthermore, a plurality of the second vias 42 are arranged at intervals in a direction perpendicular to the thickness direction DT. Furthermore, the portion of the second vias 42 opposite to the first wiring layer 51 is exposed from the substrate surface 252 and is connected to an electronic component such as a capacitor or chip resistor (not shown).

[0020] The third via 43 is made of copper or the like and is therefore conductive. Furthermore, the third via 43 is built into the substrate 25 and connected to the substrate surface 252 side of the second semiconductor element 32 in the thickness direction DT. Furthermore, a plurality of the third vias 43 are lined up at intervals in a direction perpendicular to the thickness direction DT.

[0021] The second wiring layer 52 is made of copper or the like and is therefore conductive. Furthermore, the second wiring layer 52 is embedded in the substrate 25 and is connected to the side of the third via 43 opposite to the second semiconductor element 32 in the thickness direction DT. Furthermore, the second wiring layer 52 extends in a direction perpendicular to the thickness direction DT.

[0022] The fourth via 44 is made of copper or the like and is therefore conductive. Furthermore, the fourth via 44 is embedded in the substrate 25 and connected to the second wiring layer 52 on the opposite side to the third via 43. Furthermore, a plurality of the fourth vias 44 are arranged at intervals in a direction perpendicular to the thickness direction DT. Furthermore, the portion of the fourth via 44 on the opposite side to the second wiring layer 52 is exposed from the substrate surface 252 and is connected to an electronic component such as a capacitor or chip resistor (not shown).

[0023] The first heat dissipation member 61 is made of a metal such as copper or aluminum, or graphite. This makes the thermal conductivity of the first heat dissipation member 61 relatively high. The first heat dissipation member 61 is built into the substrate 25 and arranged inside the substrate 25 on the substrate back surface 254 side. The first heat dissipation member 61 is also connected to the side of the first semiconductor element 31 opposite to the first via 41 in the thickness direction DT. This allows the heat from the first semiconductor element 31 to be conducted to the first heat dissipation member 61 and dissipated.

[0024] The second heat dissipation member 62 is made of a metal such as copper or aluminum, or graphite. This makes the thermal conductivity of the second heat dissipation member 62 relatively high. The second heat dissipation member 62 is built into the substrate 25 and disposed inside the substrate 25 on the substrate back surface 254 side. The second heat dissipation member 62 is disposed next to the first heat dissipation member 61 at an interval in a direction perpendicular to the thickness direction DT. The second heat dissipation member 62 is connected to the side of the second semiconductor element 32 opposite to the third via 43 in the thickness direction DT. As a result, when the second semiconductor element 32 generates heat, the heat from the second semiconductor element 32 is conducted to the second heat dissipation member 62 and dissipated.

[0025] The thermal interference suppression member 65 is made of a metal such as copper or aluminum, or graphite. This provides the thermal interference suppression member 65 with a relatively high thermal conductivity, which is higher than that of the substrate 25. The thermal interference suppression member 65 has, for example, a cylindrical shape with a height equal to the length in the thickness direction DT. The thermal interference suppression member 65 is embedded in the substrate 25 and disposed between the first heat dissipation member 61 and the second heat dissipation member 62. This arrangement allows the heat conducted from the first semiconductor element 31 to the first heat dissipation member 61 and the heat conducted from the second semiconductor element 32 to the second heat dissipation member 62 to be conducted to the thermal interference suppression member 65. The heat conducted from the first heat dissipation member 61 and the second heat dissipation member 62 to the thermal interference suppression member 65 is dissipated to the outside of the component-embedded substrate 20.

[0026] Furthermore, the thermal interference suppression member 65 includes an exposed surface 650. The exposed surface 650 is a surface that intersects with the thickness direction DT and is exposed from the substrate 25. In this example, the exposed surface 650 is perpendicular to the thickness direction DT and is exposed from the rear surface 254 of the substrate.

[0027] Furthermore, the thermal interference suppression member 65 is formed by via fill plating, stacked vias, copper inlay, caulking, or the like. Via fill plating is a method of forming a via by plating holes in the substrate 25 formed by drilling or the like. Stacked vias are formed by plating each layer of the substrate 25. Copper inlay is a method of forming a via by press-fitting a copper pin or the like into a hole in the substrate 25 formed by drilling or the like. Caulking is a method of forming a via by inserting a member into a hole in the substrate 25 formed by drilling or the like and deforming the inserted member to fix it to the substrate 25.

[0028] The cooling member 70 is connected to the substrate back surface 254 and the exposed surface 650, and cools the thermal interference suppression member 65. As a result, heat conducted to the thermal interference suppression member 65 is dissipated by being conducted to the cooling member 70. For this reason, heat from the first heat dissipation member 61 and the second heat dissipation member 62 is easily conducted to the thermal interference suppression member 65. The cooling member 70 is, for example, a pipe, and the thermal interference suppression member 65 is cooled by cooling water flowing through the cooling member 70. Alternatively, the cooling member 70 is, for example, a fin formed by arranging multiple flat plates, a corrugated fin, or a pin fin, which is made of a metal such as copper or aluminum, or a material with a relatively high thermal conductivity such as graphite.

[0029] The semiconductor device 10 of the first embodiment is configured as described above. Next, how the semiconductor device 10 suppresses the mutual thermal interference between the first semiconductor element 31 and the second semiconductor element 32 will be described.

[0030] In the semiconductor device 10 of the comparative example shown in FIG. 2 , the first semiconductor element 31 and the second semiconductor element 32 generate heat. At this time, the first heat dissipation member 61 and the second heat dissipation member 62 facilitate conduction of heat from the first semiconductor element 31 to the second semiconductor element 32, and facilitate conduction of heat from the second semiconductor element 32 to the first semiconductor element 31. This facilitates thermal interference between the adjacent first semiconductor element 31 and the second semiconductor element 32. This makes the first semiconductor element 31 and the second semiconductor element 32 more susceptible to damage. Furthermore, the bond between the first semiconductor element 31 and the first heat dissipation member 61 is more likely to deteriorate. Furthermore, the bond between the second semiconductor element 32 and the second heat dissipation member 62 is more likely to deteriorate. Furthermore, in order to suppress thermal interference between the adjacent first semiconductor element 31 and the second semiconductor element 32, the distance between the adjacent first semiconductor element 31 and the second semiconductor element 32 may be increased. If the distance between the first semiconductor element 31 and the second semiconductor element 32 adjacent to each other increases, the component-embedded substrate 20 increases in size.

[0031] In contrast, the component-embedded substrate 20 of the semiconductor device 10 of this embodiment has a thermal interference suppression member 65. The thermal interference suppression member 65 is built into the substrate 25 and is disposed between the first heat dissipation member 61 and the second heat dissipation member 62. As a result, the thermal interference suppression member 65 conducts heat from the first heat dissipation member 61 and the second heat dissipation member 62 and dissipates the heat from the first heat dissipation member 61 and the second heat dissipation member 62 to the outside of the component-embedded substrate 20.

[0032] As a result, heat conducted from the first semiconductor element 31 to the first heat dissipation member 61 is conducted to the thermal interference suppression member 65. Furthermore, the heat conducted to the thermal interference suppression member 65 is dissipated to the outside of the component-embedded substrate 20. Therefore, the heat conducted from the first semiconductor element 31 to the first heat dissipation member 61 is less likely to be conducted to the second heat dissipation member 62 and the second semiconductor element 32. Furthermore, the heat conducted from the second semiconductor element 32 to the second heat dissipation member 62 is conducted to the thermal interference suppression member 65. Furthermore, the heat conducted to the thermal interference suppression member 65 is dissipated to the outside of the component-embedded substrate 20. Therefore, the heat conducted from the second semiconductor element 32 to the second heat dissipation member 62 is less likely to be conducted to the first heat dissipation member 61 and the first semiconductor element 31. Therefore, mutual thermal interference between the first semiconductor element 31 and the second semiconductor element 32 is suppressed.

[0033] Furthermore, since the mutual thermal interference between the first semiconductor element 31 and the second semiconductor element 32 is suppressed, deterioration of the bond between the first semiconductor element 31 and the first heat dissipation member 61 and the bond between the second semiconductor element 32 and the second heat dissipation member 62 is suppressed. Also, the distance between the first semiconductor element 31 and the second semiconductor element 32 in the direction perpendicular to the thickness direction DT can be reduced. This prevents the component-embedded substrate 20 from becoming larger.

[0034] Furthermore, since the wiring inside the semiconductor device 10 can be made smaller, an increase in the inductance of the semiconductor device 10 is suppressed. Furthermore, since an increase in the inductance of the semiconductor device 10 is suppressed, a decrease in the switching speed of the first semiconductor element 31 and the second semiconductor element 32 is suppressed. Therefore, switching loss of the first semiconductor element 31 and the second semiconductor element 32 is suppressed.

[0035] Furthermore, the semiconductor device 10 of the first embodiment also provides the following effects.

[0036] [1-1] The thermal interference suppression member 65 includes an exposed surface 650. The exposed surface 650 intersects with the thickness direction DT and is exposed from the substrate 25. Here, the exposed surface 650 is exposed from the rear surface 254 of the substrate. The semiconductor device 10 also includes a cooling member 70. The cooling member 70 is connected to the exposed surface 650 and cools the thermal interference suppression member 65.

[0037] As a result, the heat conducted to the thermal interference suppression member 65 is dissipated by being conducted to the cooling member 70. Therefore, the heat conducted from the first semiconductor element 31 to the first heat dissipation member 61 and the heat conducted from the second semiconductor element 32 to the second heat dissipation member 62 are more likely to be conducted to the thermal interference suppression member 65, and are therefore more likely to be dissipated to the outside of the component-embedded substrate 20. This increases the thermal interference suppression effect of the thermal interference suppression member 65.

[0038] [1-2] The thermal conductivity of the thermal interference suppression member 65 is higher than the thermal conductivity of the substrate 25.

[0039] As a result, the heat conducted from the first semiconductor element 31 to the first heat dissipation member 61 and the heat conducted from the second semiconductor element 32 to the second heat dissipation member 62 are more likely to be conducted to the thermal interference suppression member 65 than to the substrate 25, and are therefore more likely to be dissipated to the outside of the component-embedded substrate 20. This increases the thermal interference suppression effect of the thermal interference suppression member 65.

[0040] (Second embodiment) 3, the second embodiment differs from the first embodiment in the form of a thermal interference suppression member 65. Other than this, the second embodiment is similar to the first embodiment.

[0041] Specifically, the thermal interference suppression member 65 extends in the thickness direction DT and penetrates the substrate front surface 252 and the substrate back surface 254. Therefore, the thermal interference suppression member 65 includes a first exposed surface 651 and a second exposed surface 652 instead of the exposed surface 650.

[0042] The first exposed surface 651 corresponds to the exposed surface 650, intersects with the thickness direction DT, and is exposed from the substrate back surface 254. Here, the first exposed surface 651 is perpendicular to the thickness direction DT. Furthermore, the first exposed surface 651 is connected to the cooling member 70.

[0043] The second exposed surface 652 is the surface of the thermal interference suppression member 65 opposite to the first exposed surface 651, intersects with the thickness direction DT, and is exposed from the substrate surface 252. Here, the second exposed surface 652 is perpendicular to the thickness direction DT.

[0044] The semiconductor device 10 of the second embodiment is configured as described above. The second embodiment also provides the same effects as the first embodiment.

[0045] (Third embodiment) 4, the third embodiment differs from the second embodiment in the form of the cooling member 70. Other than this, the third embodiment is similar to the second embodiment.

[0046] Specifically, the semiconductor device 10 includes a plurality of cooling members 70. The cooling members 70 are connected to the substrate back surface 254 and the first exposed surface 651, and also to the second exposed surface 652. Furthermore, the cooling members 70 are connected to a portion of the substrate front surface 252 so as not to interfere with electronic components such as capacitors and chip resistors (not shown) connected to the second vias 42 and the fourth vias 44.

[0047] The semiconductor device 10 of the third embodiment is configured as described above. The third embodiment also provides the same effects as the second embodiment.

[0048] (Fourth embodiment) 5, the fourth embodiment differs from the first embodiment in the form of a thermal interference suppression member 65. Other than this, the fourth embodiment is similar to the first embodiment.

[0049] Specifically, instead of being cylindrical, the thermal interference suppression member 65 is shaped like a truncated cone whose height is the length in the thickness direction DT. Moreover, the thermal interference suppression member 65 includes a first surface 661 and a second surface 662 instead of the exposed surface 650.

[0050] The first surface 661 and the second surface 662 are surfaces that intersect with the thickness direction DT. Furthermore, the first surface 661 and the second surface 662 are orthogonal to the thickness direction DT. The area of ​​the second surface 662 is larger than the area of ​​the first surface 661. Furthermore, the second surface 662 is exposed from the substrate back surface 254 and is connected to the cooling member 70.

[0051] The semiconductor device 10 of the fourth embodiment is configured as described above. The fourth embodiment also provides the same effects as the first embodiment. The fourth embodiment also provides the following effects.

[0052] [2] The thermal interference suppression member 65 has a truncated cone shape with a height equal to the length in the thickness direction DT. The thermal interference suppression member 65 includes a first surface 661 and a second surface 662. The area of ​​the second surface 662 is larger than the area of ​​the first surface 661. The second surface 662 is exposed from the substrate rear surface 254 and is connected to the cooling member 70.

[0053] As a result, when the volume is fixed, the size of the surface exposed from the substrate rear surface 254 becomes larger compared to when the thermal interference suppression member 65 is cylindrical. This makes it easier for the cooling member 70 to cool the thermal interference suppression member 65. Therefore, heat from the first heat dissipation member 61 and the second heat dissipation member 62 is more easily conducted to the thermal interference suppression member 65, and is more easily dissipated to the outside of the component-embedded substrate 20. This increases the thermal interference suppression effect of the thermal interference suppression member 65.

[0054] Furthermore, because the thermal interference suppression member 65 has a truncated cone shape, when the radius and height are fixed, the size of the thermal interference suppression member 65 can be made smaller than when the thermal interference suppression member 65 has a cylindrical shape. This makes it possible to reduce the amount of material used to form the thermal interference suppression member 65. This reduces the cost of the thermal interference suppression member 65, and therefore the cost of the semiconductor device 10.

[0055] (Fifth embodiment) 6, the fifth embodiment differs from the first embodiment in the form of a thermal interference suppression member 65. Other than this, the fifth embodiment is similar to the fourth embodiment.

[0056] Specifically, instead of the second surface 662, the first surface 661 is exposed from the substrate rear surface 254 and is connected to the cooling member .

[0057] The semiconductor device 10 of the fifth embodiment is configured as described above. The fifth embodiment also provides the same effects as the fourth embodiment.

[0058] (Sixth embodiment) 7, the sixth embodiment differs from the first embodiment in the form of a thermal interference suppression member 65. Other than this, the sixth embodiment is similar to the first embodiment.

[0059] Specifically, the thermal interference suppression member 65 is hollow instead of being solid. Therefore, a space is formed inside the thermal interference suppression member 65. Furthermore, both ends of the thermal interference suppression member 65 in the thickness direction DT are open. Therefore, here, the thermal interference suppression member 65 is formed in a cylindrical shape.

[0060] The semiconductor device 10 of the sixth embodiment is configured as described above. The sixth embodiment also provides the same effects as the first embodiment. The sixth embodiment also provides the following effects.

[0061] [3] A space is formed inside the thermal interference suppression member 65. Because the thermal conductivity of the space is relatively small, heat conducted from the first semiconductor element 31 to the thermal interference suppression member 65 via the first heat dissipation member 61 is less likely to be conducted to the second heat dissipation member 62 and the second semiconductor element 32. Furthermore, heat conducted from the second semiconductor element 32 to the thermal interference suppression member 65 via the second heat dissipation member 62 is less likely to be conducted to the first heat dissipation member 61 and the first semiconductor element 31. This increases the thermal interference suppression effect of the thermal interference suppression member 65.

[0062] Seventh embodiment 8, the seventh embodiment differs from the sixth embodiment in the form of a thermal interference suppression member 65. Other than this, the seventh embodiment is similar to the sixth embodiment.

[0063] Specifically, both ends of the thermal interference suppression member 65 in the thickness direction DT are closed instead of being open. Therefore, the thermal interference suppression member 65 is formed in a cylindrical shape with a bottom. Note that both ends of the thermal interference suppression member 65 in the thickness direction DT are not limited to being closed, and one end of the thermal interference suppression member 65 in the thickness direction DT may be closed and the other end of the thermal interference suppression member 65 in the thickness direction DT may be open.

[0064] The semiconductor device 10 of the seventh embodiment is configured as described above. The seventh embodiment also provides the same effects as the sixth embodiment.

[0065] (Eighth embodiment) 9, the eighth embodiment differs from the first embodiment in the form of a thermal interference suppression member 65. Other than this, the eighth embodiment is similar to the first embodiment.

[0066] Specifically, the thermal interference suppression member 65 is not exposed from the substrate 25. Therefore, the thermal interference suppression member 65 does not include an exposed surface 650.

[0067] The semiconductor device 10 of the eighth embodiment is configured as described above. The eighth embodiment also provides the same effects as the first embodiment.

[0068] (Ninth embodiment) 10, the ninth embodiment differs from the first embodiment in the form of a thermal interference suppression member 65. Other than this, the ninth embodiment is similar to the first embodiment.

[0069] Specifically, instead of being cylindrical in shape, the thermal interference suppression member 65 has a T-shaped cross section when cut in the thickness direction DT.

[0070] The semiconductor device 10 of the ninth embodiment is configured as described above. The ninth embodiment also provides the same effects as the first embodiment.

[0071] (Other embodiments) The present disclosure is not limited to the above-described embodiments, and appropriate modifications can be made to the above-described embodiments. Furthermore, it goes without saying that the elements constituting the embodiments in the above-described embodiments are not necessarily essential unless they are specifically stated as essential or are considered to be clearly essential in principle.

[0072] The above embodiments may be combined as appropriate.

[0073] (Aspects of the present disclosure) [Point 1] A semiconductor device, A component-embedded substrate (20) is provided, The component-embedded substrate comprises: A substrate (25), a first semiconductor element (31) built into the substrate; a second semiconductor element (32) that is built into the substrate and is arranged next to the first semiconductor element at an interval in a direction perpendicular to the thickness direction (DT) of the substrate; a first heat dissipation member (61) that is built into the substrate and is connected to the first semiconductor element in the thickness direction, and through which heat from the first semiconductor element is conducted; a second heat dissipation member (62) that is built into the substrate and is connected to the second semiconductor element in the thickness direction, and through which heat from the second semiconductor element is conducted; a thermal interference suppression member (65) that is built into the substrate and is disposed between the first heat dissipation member and the second heat dissipation member, and that dissipates heat to the outside of the component-embedded substrate; A semiconductor device having: [Point 2] the thermal interference suppression member includes exposed surfaces (650, 651, 652) that intersect with the thickness direction and are exposed from the substrate, The semiconductor device according to Aspect 1, further comprising a cooling member (70) connected to the exposed surface and configured to cool the thermal interference suppression member. [Point 3] The substrate is a substrate surface (252) that intersects with the thickness direction and is a surface on the first semiconductor element and second semiconductor element sides; a substrate back surface (254) that intersects the thickness direction and is opposite to the substrate front surface; Including, Aspect 3. The semiconductor device according to aspect 2, wherein the exposed surface is exposed from the rear surface of the substrate. [Point 4] The substrate is a substrate surface (252) that intersects with the thickness direction and is a surface on the first semiconductor element and second semiconductor element sides; a substrate back surface (254) that intersects the thickness direction and is opposite to the substrate front surface; Including, 3. The semiconductor device according to aspect 1 or 2, wherein the thermal interference suppression member extends in the thickness direction and penetrates through the front surface and the back surface of the substrate. [Point 5] Aspect 3. The semiconductor device according to aspect 1 or 2, wherein the thermal interference suppression member has a truncated cone shape with a length in the thickness direction being equal to a height. [Point 6] The thermal interference suppression member is a first surface (661) that intersects with the thickness direction; a second surface (662) that intersects with the thickness direction and has an area larger than that of the first surface; Including, The substrate is a substrate surface (252) that intersects with the thickness direction and is a surface on the first semiconductor element and second semiconductor element sides; a substrate back surface (254) that intersects the thickness direction and is opposite to the substrate front surface; Including, the second surface is exposed from the rear surface of the substrate, A semiconductor device according to aspect 5, further comprising a cooling member (70) connected to the second surface and configured to cool the thermal interference suppression member. [Point 7] Aspect 7. The semiconductor device according to any one of Aspects 1 to 6, wherein a space is formed inside the thermal interference suppression member. [Point 8] Aspect 8. The semiconductor device according to any one of Aspects 1 to 7, wherein the thermal conductivity of the thermal interference suppression member is higher than the thermal conductivity of the substrate. [Explanation of symbols]

[0074] 10 Semiconductor device 20. Substrate with embedded components 25 boards 31 First semiconductor element 32 second semiconductor element 61 First heat dissipation member 62 second heat dissipation member 65 Thermal interference suppression material

Claims

1. A semiconductor device, A component-embedded substrate (20) is provided, The component-embedded substrate comprises: A substrate (25); a first semiconductor element (31) embedded in the substrate; a second semiconductor element (32) built into the substrate and arranged next to the first semiconductor element at an interval in a direction perpendicular to the thickness direction (DT) of the substrate; a first heat dissipation member (61) that is built into the substrate and is connected to the first semiconductor element in the thickness direction, and through which heat from the first semiconductor element is conducted; a second heat dissipation member (62) that is built into the substrate and is connected to the second semiconductor element in the thickness direction, and through which heat from the second semiconductor element is conducted; a thermal interference suppression member (65) that is built into the substrate and is disposed between the first heat dissipation member and the second heat dissipation member, and that dissipates heat to the outside of the component-embedded substrate; A semiconductor device having:

2. the thermal interference suppression member includes exposed surfaces (650, 651, 652) that intersect with the thickness direction and are exposed from the substrate, 2. The semiconductor device according to claim 1, further comprising a cooling member (70) connected to the exposed surface and configured to cool the thermal interference suppression member.

3. The substrate is a substrate surface (252) that intersects the thickness direction and is a surface on the first semiconductor element and second semiconductor element side; a substrate back surface (254) that intersects the thickness direction and is opposite to the substrate front surface; Including, The semiconductor device according to claim 2 , wherein the exposed surface is exposed from the rear surface of the substrate.

4. The substrate is a substrate surface (252) that intersects the thickness direction and is a surface on the first semiconductor element and second semiconductor element side; a substrate back surface (254) that intersects the thickness direction and is opposite to the substrate front surface; Including, The semiconductor device according to claim 1 , wherein the thermal interference suppression member extends in the thickness direction and penetrates the front surface and the rear surface of the substrate.

5. The semiconductor device according to claim 1 , wherein the thermal interference suppression member has a truncated cone shape whose height is equal to the length in the thickness direction.

6. The thermal interference suppression member is A first surface (661) that intersects with the thickness direction; a second surface (662) that intersects with the thickness direction and has an area larger than that of the first surface; Including, The substrate is a substrate surface (252) that intersects the thickness direction and is a surface on the first semiconductor element and second semiconductor element side; a substrate back surface (254) that intersects the thickness direction and is opposite to the substrate front surface; Including, the second surface is exposed from the rear surface of the substrate, The semiconductor device according to claim 5, further comprising a cooling member (70) connected to the second surface and configured to cool the thermal interference suppression member.

7. 2. The semiconductor device according to claim 1, wherein a space is formed inside the thermal interference suppression member.

8. 8. The semiconductor device according to claim 1, wherein the thermal conductivity of the thermal interference suppression member is higher than the thermal conductivity of the substrate.

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