Semiconductor device

Abstract

To provide a semiconductor device that optimizes threshold voltages of transistors having different threshold voltages.SOLUTION: A semiconductor device includes a semiconductor substrate 100 including a first region 10 and a second region 20, a first gate structure GS1 disposed on the semiconductor substrate in the first region, and a second gate structure GS2 disposed on the semiconductor substrate in the second region, and the first gate structure includes a first metal pattern WF1, a first high dielectric pattern HK1, and a first work function layer which is a first lower portion of the first metal pattern, and the second gate structure includes a second metal pattern WF2, a second high dielectric pattern HK2, and a second work function layer which is a second upper portion of the second high dielectric pattern. The first work function layer includes a first metal element in the first metal pattern and a dipole material in the first high dielectric pattern, and the second work function layer and the second high dielectric pattern include a metal oxide. An oxygen content in the second work function layer is greater than an oxygen content in the second high dielectric pattern.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices including transistors with different threshold voltages. [Background technology]

[0002] Semiconductor devices include integrated circuits configured with MOS (Metal Oxide Semiconductor) field effect transistors (FETs). As the integration density of such semiconductor devices increases, the size of MOS field effect transistors is being scaled down at an ever-increasing rate, which results in a deterioration in the operating characteristics of the semiconductor devices. Therefore, various methods are being researched to overcome the limitations associated with the increase in integration density of semiconductor devices and to form semiconductor devices with better performance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 1,143,0651 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor device with improved electrical characteristics. [Means for solving the problem]

[0005] In order to achieve the above object, one aspect of the present invention provides a semiconductor device comprising: a semiconductor substrate including a first region and a second region; a first gate structure disposed on the semiconductor substrate in the first region; and a second gate structure disposed on the semiconductor substrate in the second region, wherein the first gate structure comprises a first metal pattern, a first high dielectric pattern between the semiconductor substrate and the first metal pattern, and a first work function layer between the first high dielectric pattern and the first metal pattern; the second gate structure comprises a second metal pattern, a second high dielectric pattern between the semiconductor substrate and the second metal pattern, and a second work function layer between the second high dielectric pattern and the second metal pattern; the first work function layer comprises a first metal element in the first metal pattern and a dipole material in the first high dielectric pattern; the second work function layer and the second high dielectric pattern comprise metal oxides; and an oxygen content in the second work function layer is greater than an oxygen content in the second high dielectric pattern.

[0006] In order to achieve the above object, according to another aspect of the present invention, a semiconductor device includes a semiconductor substrate including a first region and a second region, a first gate structure disposed on the semiconductor substrate in the first region, and a second gate structure disposed on the semiconductor substrate in the second region, wherein the first gate structure includes a first gate electrode, a first interface pattern between the first gate electrode and the semiconductor substrate, a first high dielectric constant pattern between the first interface pattern and the first gate electrode, and a first metal pattern between the first high dielectric constant pattern and the first gate electrode, and the second gate structure includes a second gate electrode, a second interface pattern between the second gate electrode and the semiconductor substrate, a first metal pattern between the second interface pattern and the second gate electrode, and a second high dielectric pattern between the first high dielectric pattern and the second gate electrode, and a second metal pattern between the second high dielectric pattern and the second gate electrode, the first metal pattern and the second metal pattern comprising a metal material having the same work function, the first metal pattern comprising a first lower portion in contact with an upper surface of the first high dielectric pattern and a first upper portion spaced apart from the first high dielectric pattern, the second high dielectric pattern comprising a second lower portion adjacent to the second interface pattern and a second upper portion adjacent to the second metal pattern, the first high dielectric pattern and the first lower portion of the first metal pattern comprising a lanthanide material, and an oxygen content in the second upper portion of the second high dielectric pattern being greater than the oxygen content in the second lower portion.

[0007] In order to achieve the above object, according to still another aspect of the present invention, a semiconductor device includes a semiconductor substrate including a cell array region and a peripheral region including a first region and a second region; an isolation film defining a cell active region in the cell array region, a first active region in the first region, and a second active region in the second region; a bit line structure crossing the cell active region in the cell array region; a first gate structure disposed on the first active region; and a second gate structure disposed on the second active region, wherein the first gate structure includes a first gate electrode, a first interface pattern between the first gate electrode and the semiconductor substrate, a first high dielectric pattern between the first interface pattern and the first gate electrode, and a first metal pattern between the first high dielectric pattern and the first gate electrode; The structure includes a second gate electrode, a second interface pattern between the second gate electrode and the semiconductor substrate, a second high dielectric pattern between the second interface pattern and the second gate electrode, and a second metal pattern between the second high dielectric pattern and the second gate electrode. The bit line structure includes a bit line extending in one direction and a bit line contact pattern between the bit line and the cell active region. The first high dielectric pattern and a lower portion of the first gate electrode contacting the first high dielectric pattern include a dipole material. The second high dielectric pattern includes a lower portion adjacent to the second interface pattern and an upper portion adjacent to the second metal pattern. An oxygen content in the upper portion of the second high dielectric pattern is greater than an oxygen content in the lower portion.

[0008] According to one embodiment, a method for manufacturing a semiconductor device includes providing a semiconductor substrate including first and second regions, forming a high-k dielectric film on the semiconductor substrate, forming a sacrificial metal pattern on the high-k dielectric film in the second region, forming a dipole film on the high-k dielectric film in the first region and on the sacrificial metal pattern in the second region, performing a first heat treatment process to provide a dipole material in the dipole film into the high-k dielectric film in the first region to form a first work function layer between the sacrificial metal pattern and the high-k dielectric film, removing the dipole film and the sacrificial metal pattern, forming a metal film on the high-k dielectric film including the dipole material in the first region, and performing a second heat treatment process to form a second work function layer including the dipole material between the high-k dielectric film and the metal film in the first region.

[0009] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0010] According to the present invention, in first and second transistors having different threshold voltages, the difference in height between the first and second gate structures can be reduced, and the threshold voltages of the first and second transistors can be optimized.

[0011] Furthermore, since the first and second metal patterns of the first and second gate structures are formed of the same metal material, the step between the first and second gate structures can be reduced.

[0012] Furthermore, the dipole layer containing the first adjusting material that adjusts the threshold voltage of the first transistor provided in the first region is removed from the second region, and the first adjusting material in the second region does not penetrate into the high dielectric pattern, thereby preventing a deterioration in the characteristics of the second transistor provided in the second region. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a plan view of a semiconductor device according to an embodiment of the present invention; [Figure 2] 2 is a cross-sectional view of a first example of a semiconductor device according to an embodiment of the present invention, taken along lines AA' and BB' in FIG. 1; FIG. [Figure 3A] FIG. 3 is an enlarged view of a portion P1 in FIG. 2. [Figure 3B] FIG. 3 is an enlarged view of part P2 in FIG. 2. [Figure 4] 1. FIG. 4 is a cross-sectional view of a second example of a semiconductor device according to an embodiment of the present invention, taken along lines AA' and BB' in FIG. [Figure 5] 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13A] 1. FIG. 4 is a cross-sectional view of a third example of a semiconductor device according to an embodiment of the present invention, taken along lines AA' and BB' in FIG. [Figure 13B] 1. FIG. 4 is a cross-sectional view of a third example of a semiconductor device according to an embodiment of the present invention, taken along lines CC' and DD' in FIG. [Figure 14A] 1. FIG. 4 is a cross-sectional view of a fourth example of a semiconductor device according to an embodiment of the present invention, taken along lines AA' and BB' in FIG. [Figure 14B]1. FIG. 4 is a cross-sectional view of a fourth example of a semiconductor device according to an embodiment of the present invention, taken along lines CC' and DD' in FIG. [Figure 15A] FIG. 14B is an enlarged view of the P3 portion of FIG. 14A. [Figure 15B] FIG. 14B is an enlarged view of the P4 portion of FIG. 14A. [Figure 16] 1 is a plan view of a semiconductor device including a cell array region according to an embodiment of the present invention; [Figure 17] 17A and 17B are cross-sectional views of a semiconductor device including a cell array region according to an embodiment of the present invention, taken along lines II', II-II', and III-III' of FIG. 16. DETAILED DESCRIPTION OF THE INVENTION

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of embodiments for carrying out the semiconductor device of the present invention will be described in detail with reference to the drawings.

[0015] Fig. 1 is a plan view of a semiconductor device according to one embodiment of the present invention. Fig. 2 is a cross-sectional view of a first example of a semiconductor device according to one embodiment of the present invention, showing cross sections taken along lines A-A' and B-B' in Fig. 1. Fig. 3A is an enlarged view of part P1 in Fig. 2, and Fig. 3B is an enlarged view of part P2 in Fig. 2.

[0016] 1 and 2, a semiconductor substrate 100 including a first region 10 and a second region 20 is provided.

[0017] The semiconductor substrate 100 may be a single crystal silicon substrate, or alternatively, the semiconductor substrate 100 may be a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial thin film substrate obtained by selective epitaxial growth (SEG). According to one embodiment, the semiconductor substrate 100 includes an n-type or p-type well impurity layer.

[0018] According to this embodiment, a first transistor is provided in the first region 10, and a second transistor is provided in the second region 20. The first and second transistors have different threshold voltages. For example, the threshold voltage of the second transistor is lower than the threshold voltage of the first transistor. For example, an NMOS transistor is provided in the first region, and a PMOS transistor is provided in the second region.

[0019] More specifically, an isolation layer 101 is disposed in the semiconductor substrate 100, and the isolation layer 101 defines a first active region ACT1 in the semiconductor substrate 100 in the first region 10 and a second active region ACT2 in the semiconductor substrate 100 in the second region 20.

[0020] A first gate structure GS1 is disposed on the first active region ACT1, and first source and drain regions SD1 are provided on both sides of the first gate structure GS1 in the semiconductor substrate 100. The first source and drain regions SD1 include impurities of a first conductivity type (e.g., n-type) doped into the semiconductor substrate 100.

[0021] A second gate structure GS2 is disposed on the semiconductor substrate 100 on the second active region ACT2, and second source and drain regions SD2 are provided in the semiconductor substrate 100 on both sides of the second gate structure GS2. The second source and drain regions SD2 include impurities of a second conductivity type (e.g., p-type) doped into the semiconductor substrate 100.

[0022] According to this embodiment, the first gate structure GS1 includes a first interface pattern IL1, a first high dielectric constant pattern HK1, a first metal pattern WF1, a first gate electrode EP1, and a first hard mask pattern HM1.

[0023] In detail, the first interface pattern IL1 is disposed between the first high dielectric constant pattern HK1 and the semiconductor substrate 100. The first interface pattern IL1 includes, for example, silicon oxide, silicon oxide, nitride, silicon nitride, or a combination thereof. Further, referring to FIG. 3A, the first interface pattern IL1 includes a dipole material Da that adjusts the threshold voltage of the first transistor.

[0024] The first high dielectric pattern HK1 is disposed between the first interface pattern IL1 and the first metal pattern WF1. The first high dielectric pattern HK1 is made of a high dielectric material having a dielectric constant greater than that of silicon oxide. The first high dielectric pattern HK1 may include metal oxide, metal silicate, metal silicate nitride, etc.

[0025] The first high dielectric pattern HK1 may include an oxide containing a metal such as hafnium (Hf), aluminum (Al), lanthanum (La), or zirconium (Zr). The first high dielectric pattern HK1 may include hafnium silicate (HfSiO), zirconium silicate (ZrSiO), or a combination thereof. Alternatively, the first high dielectric pattern HK1 may include hafnium silicate nitride (HfSiON), zirconium silicate nitride (ZrSiON), or a combination thereof.

[0026] 3A, the first high-dielectric pattern HK1 includes a dipole material Da that adjusts the threshold voltage of the first transistor. The dipole material Da includes an n-type or p-type dipole material. The dipole material Da includes, for example, hafnium (Hf), aluminum (Al), lanthanum (La), zirconium (Zr), yttrium (Y), magnesium (Mg), or a combination thereof. For example, the dipole material is an n-type dipole material such as lanthanum (La). For example, the first high-dielectric pattern HK1 includes LaHfSiON.

[0027] The first metal pattern WF1 is disposed between the first high dielectric constant pattern HK1 and the first gate electrode EP1. The first metal pattern WF1 is formed of a conductive material having a predetermined work function. The first metal pattern WF1 includes a metal material having a work function of approximately 4.7 eV to approximately 5.2 eV. The first metal pattern WF1 is formed of a metal nitride film such as titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, or zirconium nitride.

[0028] 3A, the first metal pattern WF1 includes a first lower portion WF1a in contact with the top surface of the first high dielectric constant pattern HK1 and a first upper portion WF1b spaced apart from the first high dielectric constant pattern HK1. The first lower portion WF1a of the first metal pattern WF1 includes a dipole material Da that adjusts the threshold voltage of the first transistor. In some embodiments, the first lower portion WF1a of the first metal pattern WF1 is referred to as a "first work function layer."

[0029] For example, the dipole material Da in the first lower portion WF1a of the first metal pattern WF1 is the same as the dipole material Da in the first high-dielectric pattern HK1. That is, the first lower portion WF1a of the first metal pattern HK1 includes an n-type dipole material Da of a lanthanum series, such as lanthanum (La). The first lower portion WF1a of the first metal pattern WF1 has a thickness ranging from approximately 1 Å to 20 Å. The first lower portion WF1a of the first metal pattern WF1 includes La, Hf, Ti, N, O, Si, etc. For example, the first lower portion WF1a of the first metal pattern WF1 includes LaTiN, and the first upper portion WF1b includes TiN.

[0030] The dipole material Da present in the first interface pattern IL1, the first high dielectric pattern HK1, and the lower portion WF1a of the first metal pattern WF1 forms a dipole at the interface between the first high dielectric pattern HK1 and the first interface pattern IL1, thereby changing the effective work function of the first transistor and changing the threshold voltage of the first transistor.

[0031] The first gate electrode EP1 is disposed between the first metal pattern WF1 and the first hard mask pattern HM1. The first gate electrode EP1 is formed of a material having a lower resistivity than the first metal pattern WF1. For example, the first gate electrode EP1 is formed of any one or combination of tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal nitrides.

[0032] The first hard mask pattern HM1 on the first gate electrode EP1 includes silicon nitride.

[0033] According to this embodiment, the second gate structure GS2 includes a second interface pattern IL2, a second high-k dielectric pattern HK2, a second metal pattern WF2, a second gate electrode EP2, and a second hard mask pattern HM2.

[0034] The second interface pattern IL2 is disposed between the semiconductor substrate 100 and the second high dielectric constant pattern HK2. The second interface pattern IL2 includes, for example, silicon oxide, silicon oxide, nitride, silicon nitride, or a combination thereof. The second interface pattern IL2 has substantially the same thickness as the first interface pattern IL1. The second interface pattern IL2 is formed of the same insulating material as the first interface pattern IL1 and does not include the dipole material Da in the first interface pattern IL1.

[0035] The second high dielectric pattern HK2 is disposed between the second interface pattern IL2 and the second metal pattern WF2. The second high dielectric pattern HK2 is made of a high dielectric material having a dielectric constant greater than that of silicon oxide. The second high dielectric pattern HK2 may include, for example, metal oxide, metal silicate, or metal silicate nitride.

[0036] The second high-dielectric pattern HK2 has substantially the same thickness and contains the same metal element as the first high-dielectric pattern HK1. Referring to FIG. 3B , the second high-dielectric pattern HK2 includes a second lower portion HK2a adjacent to the second interface pattern IL2 and a second upper portion HK2b adjacent to the second metal pattern WF2. The second high-dielectric pattern HK2 is formed of a metal oxide, and the oxygen content of the second upper portion HK2b is greater than the oxygen content of the second lower portion HK2a. The oxygen-rich second high-dielectric pattern HK2 can adjust the threshold voltage of the second transistor. In some embodiments, the upper portion HK2b of the second high-dielectric pattern HK2 is referred to as a “second work function layer.” In this embodiment, “oxygen content” refers to the number of oxygen atoms per unit volume.

[0037] The second lower portion HK2a of the second high-k dielectric pattern HK2 includes HfSiON, and the second upper portion HK2b includes oxygen-rich TiHfSiON, and the second upper portion HK2b has a thickness ranging from about 1 Å to 20 Å.

[0038] The second metal pattern WF2 is disposed between the second high-dielectric pattern HK2 and the second gate electrode EP2. The second metal pattern WF2 is formed of a metal material having the same work function as the metal material of the first metal pattern WF1. The second metal pattern WF2 includes a metal material having a work function of, for example, about 4.7 eV to about 5.2 eV. The second metal pattern WF2 is formed of a metal nitride film such as titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, or zirconium nitride. The second metal pattern WF2 has substantially the same thickness as the first metal pattern WF1.

[0039] The second gate electrode EP2 is disposed between the second metal pattern WF2 and the second hard mask pattern HM2. The second gate electrode EP2 is formed of, for example, any one or combination of tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal nitrides. The second gate electrode EP2 includes the same metal material as the first gate electrode EP1 and has substantially the same thickness as the first gate electrode EP1.

[0040] The second hard mask pattern HM2 on the second gate electrode EP2 includes silicon nitride.

[0041] In the first and second gate structures (GS1, GS2), the distance from the upper surface of the semiconductor substrate 100 to the first work function layer WF1a is substantially the same as the distance from the upper surface of the semiconductor substrate 100 to the second work function layer HK2b. Alternatively, the distance from the upper surface of the semiconductor substrate 100 to the first work function layer WF1a may be greater than the distance from the upper surface of the semiconductor substrate 100 to the second work function layer HK2b.

[0042] According to this embodiment, the second interface pattern IL2, the second high dielectric constant pattern HK2, and the second metal pattern WF2 of the second gate structure GS2 do not contain n-type dipole material, which prevents the dipole material from penetrating into the interface between the semiconductor substrate 100 and the second gate structure GS2 in the second region 20 and degrading the characteristics of the second transistor.

[0043] Furthermore, since the first gate structure GS1 and the second gate structure GS2 have substantially the same height and the first and second metal patterns WF1 and WF2 contain the same metal material, the manufacturing process of the semiconductor device is simplified.

[0044] Figure 4 is a cross-sectional view of a second example of a semiconductor device according to an embodiment of the present invention, taken along lines A-A' and B-B' in Figure 1. For simplicity of explanation, explanation of content that overlaps with the previously described embodiment will be omitted, and differences from the previously described content will be mainly explained.

[0045] According to the embodiment shown in FIG. 4, as described above, the first gate structure GS1 includes a first interface pattern IL1, a first high dielectric pattern HK1, a first lower portion (first work function layer) WF1a of the first metal pattern WF1, a first upper portion WF1b of the first metal pattern WF1, a first gate electrode EP1, and a first hard mask pattern HM1, which are stacked in order.

[0046] The second gate structure GS2 includes a second interface pattern IL2, a second lower portion HK2a of the second high dielectric pattern HK2, a second upper portion (second work function layer) HK2b of the second high dielectric pattern HK2, a second metal pattern WF2, a second gate electrode EP2, and a second hard mask pattern HM2, which are stacked in order.

[0047] In the first and second gate structures (GS1, GS2), the first interface pattern IL1 and the first high-dielectric pattern HK1 contain a dipole material Da, while the second interface pattern IL2 and the second high-dielectric pattern HK2 do not. The first gate structure GS1 contains a first work function layer WF1a, and the second gate structure GS2 contains a second work function layer HK2b. The first work function layer WF1a of the first metal pattern WF1 is disposed between the first high-dielectric pattern HK1 and a first upper portion WF1b of the first metal pattern WF1 and contains a dipole material Da. The second work function layer HK2b of the second high-dielectric pattern HK2 is disposed between a second lower portion HK2a of the second high-dielectric pattern HK2 and the second metal pattern WF2 and has an oxygen content greater than that in the second lower portion HK2a of the second high-dielectric pattern HK2.

[0048] The first upper portion WF1b of the first metal pattern WF1 of the first gate structure GS1 is formed of the same metal material as the second metal pattern WF2. The thickness of the first metal pattern WF1 is different from the thickness of the second metal pattern WF2. For example, the top surface of the second metal pattern WF2 is located at a higher level than the top surface of the first metal pattern WF1. That is, the thickness of the first metal pattern WF1 of the first gate structure GS1 is smaller than the thickness of the second metal pattern WF2 of the second gate structure GS2. The height difference h1 between the top surfaces of the first and second metal patterns WF1 and WF2 is approximately 1 Å to 20 Å.

[0049] The first work function layer WF1a includes a first metal element and a lanthanide material, and the second work function layer HK2b includes a second metal element and oxygen, where the second metal element is different from the first metal element.

[0050] The second gate electrode EP2 includes the same metal material as the first gate electrode EP1 and has substantially the same thickness as the first gate electrode EP1.

[0051] Fig. 5 is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention, Fig. 6 to Fig. 12 are diagrams showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0052] 5 and 6, a semiconductor substrate 100 including a first region 10 and a second region 20 is provided.

[0053] The semiconductor substrate 100 may be a single crystal silicon substrate, or alternatively, the semiconductor substrate 100 may be a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial thin film substrate obtained by selective epitaxial growth (SEG). According to one embodiment, the semiconductor substrate 100 includes an n-type or p-type well impurity layer.

[0054] A first transistor having a first threshold voltage is formed in the first region 10, and a second transistor having a second threshold voltage lower than the first threshold voltage is formed in the second region 20.

[0055] An isolation layer 101 is formed in a semiconductor substrate 100 to define a first active region ACT1 and a second active region ACT2.

[0056] The isolation layer 101 is formed by patterning the semiconductor substrate 100 to form trenches, depositing an insulating layer to fill the trenches, and planarizing the insulating layer to expose the top surface of the semiconductor substrate 100.

[0057] As another example, the top surface of the isolation layer 101 may be recessed from the top surface of the semiconductor substrate 100 , and the semiconductor substrate 100 may include pin-shaped active patterns protruding above the top surface of the isolation layer 101 .

[0058] Next, an interface layer 110 and a high dielectric layer 120 are sequentially formed on the semiconductor substrate 100 (step S10).

[0059] The interface film 110 is formed of an insulating material having a dielectric constant of 9 or less. For example, the interface film 110 includes a silicon oxide film and / or a silicon oxynitride film. The interface film is formed using a thermal oxidation method, an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, etc. The interface film 110 improves the interface characteristics between the semiconductor substrate 100 and the high dielectric film 120, thereby improving electron mobility characteristics.

[0060] The high-k dielectric film 120 is made of a high-k material having a dielectric constant greater than that of silicon oxide, and is thicker than the interfacial film 110. For example, the high-k dielectric film 120 includes metal oxide, metal silicate, metal silicate nitride, and the like.

[0061] Metal oxides include oxides containing metals such as hafnium (Hf), aluminum (Al), lanthanum (La), and zirconium (Zr). Metal oxides include hafnium oxide, aluminum oxide, lanthanum oxide, zirconium oxide, or combinations of these materials. For example, metal oxides include HfO2, Al2O3, La2O3, ZrO2, or combinations of these materials.

[0062] Metal silicates include silicates containing metals such as hafnium (Hf), zirconium (Zr), etc. For example, metal silicates include hafnium silicate (HfSiO), zirconium silicate (ZrSiO), or a combination thereof.

[0063] Metal silicate nitrides include silicate nitrides containing metals such as hafnium (Hf), zirconium (Zr), etc. For example, metal silicate nitrides include hafnium silicate nitride (HfSiON), zirconium silicate nitride (ZrSiON), or a combination thereof.

[0064] The high dielectric film 120 can be formed by, for example, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), etc. Atomic layer deposition (ALD) or plasma-enhanced atomic layer deposition (PEALD) can be used to form a uniform film.

[0065] In the first and second regions 10 and 20, a sacrificial metal layer 130 is formed on the high dielectric layer 120 (step S20).

[0066] The sacrificial metal layer 130 is formed of a conductive material having a predetermined work function. According to this embodiment, the sacrificial metal layer 130 determines the work function of an n-type or p-type transistor. For example, the sacrificial metal layer 130 includes a metal material having a work function of about 4.7 eV to about 5.2 eV.

[0067] The sacrificial metal film 130 may include a metal nitride, a metal oxynitride, a metal oxide carbide, or a metal oxycarbide nitride. For example, the sacrificial metal film 130 may include a p-type work function metal. The sacrificial metal film 130 may be formed of a metal nitride film such as titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, or zirconium nitride.

[0068] The sacrificial metal layer 130 may include a first metal nitride layer, a work function adjustment layer, and a second metal nitride layer, which are stacked in order.

[0069] According to this embodiment, the sacrificial metal layer 130 is formed of a conductive material containing aluminum (Al), such as metal aluminide, metal aluminum carbide, metal aluminum nitride, or metal aluminum silicide.

[0070] The sacrificial metal film 130 is a layer containing, for example, TiN, TiN / TaN, Al2O3 / TiN, Al / TiN, TiN / Al / TiN, TiN / TiON, Ta / TiN, or TaN / TiN, where TiN can be replaced with TaN, TaCN, TiCN, CoN, or CoCN. The sacrificial metal film 130 has a thickness of approximately 10 Å to 60 Å.

[0071] 5 and 7, the sacrificial metal layer 130 is removed in the first region 10 (step S30). Thus, the top surface of the high dielectric layer 120 is exposed in the first region 10, and a sacrificial metal pattern 131 is formed on the second region 20.

[0072] In detail, after forming a mask pattern MP on the sacrificial metal film 130 in the second region 20, the mask pattern MP is used as an etching mask to etch the sacrificial metal film 130 in the first region 10, thereby exposing the top surface of the high dielectric film 120 in the first region 10.

[0073] After the high dielectric film 120 is exposed in the first region 10, the mask pattern MP is removed.

[0074] 5 and 8, a dipole film 140 (or a work function control film) is formed on the high dielectric film 120 in the first region 10 and the sacrificial metal pattern 131 in the second region 20 (step S40).

[0075] The dipole film 140 includes an n-type or p-type dipole material. The dipole material is a metal material having a higher electron affinity than the metal material included in the high-k dielectric film 120. For example, the dipole material includes Al, Mg, Ca, Sr, V, Nb, Sc, Y, or a lanthanoid material, or a combination thereof. As an example, the dipole film 140 includes at least one selected from lanthanum (La), lanthanum oxide (LaO), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), and titanium nitride (TiN). When the first region 10 is an NMOS transistor region, the dipole film 140 is a lanthanum oxide film.

[0076] The dipole film 140 is formed using chemical vapor deposition or atomic layer deposition.

[0077] 5 and 9, after the dipole film 140 is formed, a first heat treatment process is performed (step S50).

[0078] The first heat treatment process includes performing an annealing process in a first temperature range, which is determined according to the threshold voltage of the transistor in the first region 10. For example, the first heat treatment process is performed at a temperature of about 50°C to 1400°C using oxygen gas or nitrogen gas.

[0079] By performing the first heat treatment process, the dipole material in the dipole film 140 in the first region 10 is diffused into the interface film 110 and the high-k dielectric film 120. The dipole material diffused into the high-k dielectric film 120 in the first region 10 forms a dipole at the interface between the interface film 110 and the high-k dielectric film 120. The induced dipole can change the threshold voltage of the transistor.

[0080] After the first heat treatment process, the concentration of the dipole material in the interface film 110 and the high-k film 120 is different between the first region 10 and the second region 120. According to this embodiment, the interface film 110 and the high-k film 120 in the first region 10 contain the dipole material, while the interface film 110 and the high-k film 120 in the second region 20 do not contain the dipole material.

[0081] Furthermore, according to this embodiment, during the first heat treatment process, the sacrificial metal pattern 131 in the second region 20 prevents the dipole material in the dipole film 140 from penetrating into the interface film 110 and the high dielectric film 120 in the second region 20.

[0082] In addition, since the first heat treatment process is performed using oxygen gas, oxygen penetrates into the sacrificial metal pattern 131 in the second region 20, and the oxygen concentration in the upper portion 120b of the high dielectric film 120 in contact with the sacrificial metal pattern 131 increases compared to the oxygen concentration in the lower portion 120a. That is, after the first heat treatment process, the high dielectric film 120 in the second region 20 is formed as a metal oxide film having a different oxygen content, and an oxygen-rich second work function layer 120b is formed between the sacrificial metal pattern 131 and the lower portion 120a of the high dielectric film 120 in the second region 20.

[0083] 5 and 10, after the first heat treatment process, the dipole film 140 and the sacrificial metal pattern 131 are sequentially removed (step S60), thereby exposing the top surface of the high dielectric film 120 in the first and second regions 10 and 20.

[0084] Referring to FIGS. 5 and 11, a work function metal layer 150 is formed on the high dielectric layer 120 in the first and second regions 10 and 20 (step S70).

[0085] The work function metal film 150 may include Ti, N, O, Al, W, Mo, La, etc. The work function metal film 150 may be formed of a metal nitride film such as titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, and zirconium nitride. For example, the work function metal film 150 may be formed of titanium nitride (TiN) or tantalum nitride (TaN).

[0086] Subsequently, a gate metal film 160 is formed on the work function metal film 150. The gate metal film 160 is formed of one of materials having a lower resistivity than the work function metal film 150. For example, the gate metal film 160 is formed of any one or combination of materials selected from tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal nitrides.

[0087] Referring to FIGS. 5 and 11, after the gate metal film 160 is formed, a second heat treatment process is performed (step S80).

[0088] The second heat treatment process includes performing an annealing process at a second temperature range, which is higher than the first temperature range of the first heat treatment process. For example, the second heat treatment process is performed at a temperature of about 50°C to 1400°C using nitrogen gas or oxygen gas.

[0089] In this embodiment, the second heat treatment process includes an annealing process for activating the source and drain regions.

[0090] During the second heat treatment process, the dipole material in the high dielectric film 120 in the first region 10 diffuses into the lower portion of the work function metal film 150. Therefore, the work function metal film 150 in the first region 10 includes a first work function layer 150a containing the dipole material.

[0091] Referring to FIGS. 5 and 12, a gate patterning process is performed (step S90).

[0092] In detail, first and second hard mask patterns HM1 and HM2 are formed on the gate metal layer 160.

[0093] By sequentially etching the gate metal film 160, the work function metal film 150, the high dielectric film 120, and the interface film 110 using the first hard mask pattern HM1, a first gate structure GS1 is formed, which includes a first interface pattern IL1, a first high dielectric pattern HK1, a first work function metal pattern WF1, a first gate electrode EP1, and a first hard mask pattern HM1 stacked in sequence in the first region 10.

[0094] By sequentially etching the gate metal film 160, the work function metal film 150, the high dielectric film 120, and the interface film 110 using the second hard mask pattern HM2, a second gate structure GS2 is formed, which includes a second interface pattern IL2, a second high dielectric pattern HK2, a second work function metal pattern WF2, a second gate electrode EP2, and a second hard mask pattern HM2 stacked in sequence in the second region 20.

[0095] Thereafter, gate spacers are formed on both sidewalls of the first and second gate structures GS1 and GS2, and first source and drain regions SD1 are formed in the semiconductor substrate 100 on both sides of the first gate structure GS1 in the first region 10. Second source and drain regions SD2 are formed in the semiconductor substrate 100 on both sides of the second gate structure GS2 in the second region 20.

[0096] Fig. 13A is a cross-sectional view of a third example of a semiconductor device according to an embodiment of the present invention, taken along lines A-A' and B-B' in Fig. 1. Fig. 13B is a cross-sectional view of a third example of a semiconductor device according to an embodiment of the present invention, taken along lines C-C' and D-D' in Fig. 1. For simplicity of explanation, explanation of content that overlaps with the previously described embodiments will be omitted, and differences from the previously described content will be mainly explained.

[0097] 13A and 13B, a semiconductor substrate 100 includes a first pin active pattern AP1 in a first region 10 and a second pin active pattern AP2 in a second region 20. The first and second pin active patterns AP1 and AP2 are parts of the semiconductor substrate 100 and are epitaxial layers grown on the semiconductor substrate 100.

[0098] The first and second gate structures GS1 and GS2 are disposed across the first and second pin active patterns AP1 and AP2, respectively. Although the first and second pin active patterns AP1 and AP2 are illustrated as being one each, the present invention is not limited thereto and may be provided in plural.

[0099] The isolation layer 101 defines first and second pin active patterns AP1 and AP2, and the top surface of the isolation layer 101 is located at a lower level than the top surfaces of the first and second pin active patterns AP1 and AP2.

[0100] The first source and drain regions SD1 are disposed on the first pinned active pattern AP1 on both sides of the first gate structure GS1, and the second source and drain regions SD2 are disposed on the second pinned active pattern AP2 on both sides of the second gate structure GS2.

[0101] The first and second source and drain regions (SD1, SD2) are formed in an epitaxial layer. The first source and drain region SD1 is formed of a material that provides tensile strain to the channel region. For example, the first source and drain region SD1 is formed of silicon carbide (SiC). The second source and drain region SD2 is formed of a material that provides compressive strain to the channel region. For example, the second source and drain region SD2 is formed of silicon germanium (SiGe).

[0102] The first gate structure GS1 includes a first interface pattern IL1, a first high-dielectric pattern HK1, a first metal pattern WF1, and a first gate electrode EP1. The second gate structure GS2 includes a second interface pattern IL2, a second high-dielectric pattern HK2, a second metal pattern WF2, a second gate electrode EP2, and a second hard mask pattern HM2.

[0103] Spacers SS are disposed on both side walls of each of the first and second gate structures (GS1, GS2).

[0104] The first high-dielectric pattern HK1 of the first gate structure GS1 extends between the lower surface of the first gate electrode EP1 and the first interface pattern IL1, between the sidewalls of the first gate electrode EP1 and the spacers SS. The first metal pattern WF1 of the first gate structure GS1 extends between the lower surface of the first gate electrode EP1 and the first high-dielectric pattern HK1, between the sidewalls of the first gate electrode EP1 and the spacers SS. The first interface pattern IL1, the first high-dielectric pattern HK1, and the first metal pattern WF1 have a substantially U-shape, and the first gate electrode EP1 fills the gap region defined by the first metal pattern WF1 between the spacers SS. As described above, in the first gate structure GS1, the lower portions of the first interface pattern IL1, the first high-dielectric pattern HK1, and the first metal pattern WF1 include dipole material.

[0105] Similarly, the second high-dielectric pattern HK2 of the second gate structure GS2 extends between the lower surface of the second gate electrode EP2 and the second interface pattern IL2, between the sidewalls of the second gate electrode EP2 and the spacers SS. The second metal pattern WF2 of the second gate structure GS2 extends between the lower surface of the second gate electrode EP2 and the second high-dielectric pattern HK2, between the sidewalls of the second gate electrode EP2 and the spacers SS. The second interface pattern IL2, the second high-dielectric pattern HK2, and the second metal pattern WF2 have a substantially U-shape, and the second gate electrode EP2 fills the gap region defined by the second metal pattern WF2 between the spacers SS. As described above, in the second gate structure GS2, the second high-dielectric pattern HK2 contains metal elements and oxygen, and the oxygen content of the upper portion adjacent to the second metal pattern WF2 is higher than the oxygen content of the lower portion adjacent to the second interface pattern IL2.

[0106] The interlayer dielectric film ILD is disposed to cover the isolation film 101 and the first and second source and drain regions SD1 and SD2. The interlayer dielectric film ILD is substantially coplanar with upper surfaces of the first and second gate structures GS1 and GS2. The interlayer dielectric film ILD includes a low-k material, for example, at least one of oxide, nitride, and oxynitride.

[0107] 14A is a cross-sectional view of a fourth example of a semiconductor device according to an embodiment of the present invention, taken along lines A-A' and B-B' in FIG. 1. FIG. 14B is a cross-sectional view of a fourth example of a semiconductor device according to an embodiment of the present invention, taken along lines C-C' and D-D' in FIG. 1. FIG. 15A is an enlarged view of part P3 in FIG. 14A, and FIG. 15B is an enlarged view of part P4 in FIG. 14A. For simplicity of explanation, descriptions of content that overlaps with the previously described embodiments will be omitted, and differences from the previously described content will be mainly described.

[0108] Referring to Figures 14A and 14B, the transistors provided in the first and second regions (10, 20) are three-dimensional field effect transistors (e.g., MBCFET (multi-bridge channel field effect transistor) or GAAFET (gate-all-around field effect transistor)) in which a gate electrode three-dimensionally surrounds a nanowire channel or a nanosheet channel.

[0109] Specifically, first and second channel patterns (CH1, CH2) are disposed on first and second active patterns (AP1, AP2), respectively. The first channel pattern CH1 includes first semiconductor patterns SP1 stacked in sequence and spaced apart vertically, and the second channel pattern CH2 includes second semiconductor patterns SP2 stacked in sequence and spaced apart vertically.

[0110] The first channel pattern CH1 is disposed between the first source and drain regions SD1, and the second channel pattern CH2 is disposed between the second source and drain regions SD2.

[0111] The first semiconductor patterns SP1 of the first channel pattern CH1 may have the same thickness or different thicknesses, and the second semiconductor patterns SP2 of the second channel pattern CH2 may have the same thickness or different thicknesses.

[0112] The first source and drain region SD1 is an epitaxial pattern formed using the first semiconductor pattern SP1 as a seed layer, and the second source and drain region SD2 is an epitaxial pattern formed using the second semiconductor pattern SP2 as a seed layer.

[0113] A sidewall insulating pattern IP is interposed between the second source / drain region SD2 and the second gate electrode EP2. The sidewall insulating pattern IP is interposed between the vertically spaced second semiconductor patterns SP2. The sidewall insulating pattern IP electrically insulates the first and second gate electrodes EP1 and EP2 from the first and second source / drain patterns SD1 and SD2. For example, the sidewall insulating pattern IP includes a silicon nitride layer.

[0114] The first and second gate structures (GS1, GS2) extend in one direction across the first and second channel patterns (CH1, CH2). The first and second gate structures (GS1, GS2) vertically overlap the first and second channel patterns (CH1, CH2), respectively. A pair of gate spacers are disposed on both sidewalls of the outer electrodes of each of the first and second gate structures (GS1, GS2).

[0115] Each of the first and second gate structures (GS1, GS2) includes an inner electrode interposed between the corresponding active pattern (AP1, AP2) and the first and second semiconductor patterns (SP1, SP2), and an outer electrode on the first and second semiconductor patterns (SP1, SP2).

[0116] The first gate structure GS1 includes the first interface pattern IL1, the first high dielectric pattern HK1, the first metal pattern WF1, the first gate electrode EP1, and the first hard mask pattern HM1, as previously described.

[0117] The second gate structure GS2 includes the second interface pattern IL2, the second high-k dielectric pattern HK2, the second metal pattern WF2, the second gate electrode EP2, and the second hard mask pattern HM2, as previously described.

[0118] 15A and 15B, the first and second interface patterns (IL1, IL2) are respectively interposed between the first and second gate electrodes (EP1, EP2) and the first and second semiconductor patterns (SP1, SP2). The first and second interface patterns (IL1, IL2) surround the first and second semiconductor patterns (SP1, SP2). That is, the first interface pattern IL1 covers the top, bottom, and both sidewalls of the first semiconductor pattern SP1, and the second interface pattern IL2 covers the top, bottom, and both sidewalls of the second semiconductor pattern SP2. The first and second interface patterns (IL1, IL2) directly cover the first and second semiconductor patterns (SP1, SP2). The first and second interface patterns (IL1, IL2) are interposed between the inner electrodes and the corresponding active patterns (AP1, AP2). For example, the first and second interface patterns (IL1, IL2) include a silicon oxide layer or a silicon oxynitride layer.

[0119] The first and second high dielectric patterns (HK1, HK2) surround the first and second semiconductor patterns (SP1, SP2) on the first and second interface patterns (IL1, IL2), respectively. The first and second high dielectric patterns (HK1, HK2) include a metal oxide. The first and second high dielectric patterns (HK1, HK2) include the same first metal element and oxygen. The first metal element includes at least one of hafnium, zirconium, tantalum, lanthanum, titanium, barium, strontium, lithium, aluminum, lead, scandium, zinc, and niobate.

[0120] As described above, the first high dielectric pattern HK1 includes the dipole material Da. The second high dielectric pattern HK2 does not include the dipole material Da in the first high dielectric pattern HK1, and includes a lower portion HK2a adjacent to the second interface pattern IL2 and an upper portion HK2b adjacent to the second metal pattern WF2, and the oxygen content of the upper portion HK2b is greater than the oxygen content of the lower portion HK2a.

[0121] The first and second metal patterns (WF1, WF2) surround the first and second semiconductor patterns (SP1, SP2) on the first and second high dielectric patterns (HK1, HK2), respectively. The first and second metal patterns (WF1, WF2) contain a work function metal that adjusts the threshold voltage of the transistor. The thickness and composition of the first and second metal patterns (WF1, WF2) can be adjusted to achieve a desired threshold voltage of the transistor.

[0122] The first and second metal patterns (WF1, WF2) include a metal nitride film. For example, the first and second metal patterns (WF1, WF2) include nitrogen (N) and at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). Furthermore, the first and second metal patterns (WF1, WF2) further include carbon (C). The first and second metal patterns (WF1, WF2) include a plurality of stacked work function metal films.

[0123] In this embodiment, the first metal pattern WF1 includes a first lower portion WF1a in contact with the top surface of the first high dielectric pattern HK1 and a first upper portion WF1b spaced apart from the first high dielectric pattern HK1, as described above. The first lower portion WF1a of the first metal pattern WF1 adjusts the threshold voltage of the transistor and includes the same dipole material as the dipole material Da in the first high dielectric pattern HK1.

[0124] The first and second gate electrodes (EP1, EP2) surround the first and second semiconductor patterns (SP1, SP2) on the first and second metal patterns (WF1, WF2), respectively. The first and second gate electrodes (EP1, EP2) include a metal having a lower resistance than the first and second metal patterns (WF1, WF2). For example, the first and second gate electrodes (EP1, EP2) include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0125] 16 is a plan view of a semiconductor device including a cell array region according to an embodiment of the present invention. FIG. 17 is a cross-sectional view of a semiconductor device including a cell array region according to an embodiment of the present invention, taken along lines I-I', II-II', and III-III' in FIG. 16. For simplicity, description of content that overlaps with the previously described embodiment will be omitted, and differences from the previously described content will be mainly described.

[0126] 16 and 17, a semiconductor substrate 100 includes a cell array region CAR and a peripheral circuit region PCR, and the peripheral circuit region PCR includes a first region 10 and a second region 20. As shown in FIG.

[0127] Peripheral circuits for driving word line structures WL and bit lines BL arranged in the cell array region CAR are arranged in the first region 10 and the second region 20. For example, an NMOS transistor is provided in the first region 10, and a PMOS transistor is provided in the second region 20.

[0128] More specifically, an isolation film 101 defining a cell active region ACT is disposed in a semiconductor substrate 100 of the cell array region CAR. The semiconductor substrate 100 may be a silicon substrate, a germanium substrate, and / or a silicon germanium substrate.

[0129] According to one example, the cell active regions ACT have a rectangular (or bar) shape in a plan view and are two-dimensionally arranged along a first direction D1 and a second direction D2 that crosses the first direction D1 (for example, perpendicular to the first direction D1). The cell active regions ACT are arranged in a zigzag shape in a plan view and have their major axes in a diagonal direction relative to the first direction D1 and the second direction D2.

[0130] The word line structures WL extend in a first direction D1 across the cell active regions ACT within the semiconductor substrate 100. Each word line structure includes a word line, a gate insulating pattern between the semiconductor substrate 100 and the word line, and a gate capping pattern on the word line. The word line includes a conductive material. The gate insulating pattern includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material. The gate capping pattern includes, for example, a silicon nitride film or a silicon oxynitride film.

[0131] The word line structures WL are disposed in the semiconductor substrate 100 and extend in a first direction D1 in a plan view, crossing the cell active regions ACT and the device isolation films 101. One cell active region ACT intersects a pair of word line structures WL. The upper surfaces of the word lines of the word line structures are located below the upper surface of the semiconductor substrate 100. The lower surfaces of the word lines vary in height depending on the material underneath.

[0132] First and second impurity regions 1a and 1b are formed in each of the cell active regions ACT on both sides of the word line structure WL. The lower surfaces of the first and second impurity regions 1a and 1b are located at a predetermined depth from the upper surface of the cell active region ACT. The first impurity region 1a is disposed within each of the cell active regions ACT between the word line structures WL, and the second impurity region 1b is disposed in end portions of each of the cell active regions ACT, spaced apart from the first impurity region 1a. The first and second impurity regions 1a and 1b are doped with dopants having a conductivity type opposite to that of the semiconductor substrate 100.

[0133] A buffer insulating film 115 is provided on the semiconductor substrate 100. For example, the buffer insulating film 115 may be formed as a single film or a multi-layer film.

[0134] The bit line structures BLS extend in the second direction D2 across the word line structures WL on the semiconductor substrate 100. Each of the bit line structures BLS is disposed on the first impurity region 1a. According to an example, the bit line structures BLS include a polysilicon pattern 125 extending in the second direction D2, a bit line BL on the polysilicon pattern 125, and a hard mask pattern HM on the bit line BL. A buffer insulating film 115 is interposed between the polysilicon pattern 125 and the semiconductor substrate 100. A bit line contact pattern DC is disposed between the bit line BL and the first impurity region 1a. The bit line contact pattern DC contacts the first impurity region 1a. The bit line contact pattern DC includes polysilicon, and a silicide pattern is interposed between the bit line contact pattern DC and the bit line BL. The silicide pattern includes at least one of titanium silicide, cobalt silicide, and nickel silicide. The bit line contact pattern DC includes a conductive metal nitride (eg, titanium nitride, tantalum nitride, etc.) and a metal (eg, tungsten, titanium, tantalum, etc.).

[0135] The bottom surfaces of the bit line contact patterns DC are located below the top surface of the semiconductor substrate 100 and above the top surfaces of the word lines. In one example, the bit line contact patterns DC are locally disposed within recess regions RS formed in the semiconductor substrate 100 and exposing the first impurity regions 1 a. The recess regions RS have an elliptical shape, and the minimum width of the recess regions RS is greater than the width of each of the bit line structures BLS.

[0136] In the bit line structure BLS, the hard mask pattern HM includes an insulating material such as silicon nitride.

[0137] The bit line contact spacers DCS fill the recess regions RS in which the bit line contact patterns DC are formed. In one example, the bit line contact spacers DCS cover both sidewalls of the bit line contact patterns DC. For example, the bit line contact spacers DCS are formed of a multi-layer film including a silicon oxide film, a silicon nitride film, and / or a silicon oxynitride film.

[0138] According to this embodiment, bit line spacers are disposed on both sidewalls of the bit line structures BLS, extend along one sidewall of the bit line structures BLS in the second direction D2, and are disposed between the sidewall of the bit line structures BLS and the buried contact patterns BC.

[0139] A buried contact pattern BC is disposed between a pair of adjacent bit line structures BLS. The buried contact pattern BC includes polysilicon or a metal material doped with impurities. The buried contact pattern BC is in direct contact with each second impurity region 1b. In a plan view, the buried contact pattern BC is disposed between the word line structures WL and between the bit line structures BLS.

[0140] The buried contact patterns BC are spaced apart from each other in a two-dimensional manner, and the upper surfaces of the buried contact patterns BC are located at a level lower than the upper surfaces of the bit line structures BLS.

[0141] The bottom surface of the buried contact pattern BC is located below the top surface of the semiconductor substrate 100 and above the bottom surface of the bit line contact pattern DC, and is insulated from the bit line contact pattern DC by bit line contact spacers DCS.

[0142] Fence patterns (not shown) are arranged between the bit line structures BLS and spaced apart in the second direction D2. The fence patterns are arranged between the buried contact patterns BC adjacent to each other in the second direction D2. The fence patterns overlap the word lines WL in a plan view. The fence patterns include an insulating material such as silicon nitride.

[0143] The landing pads LP are disposed on the buried contact patterns BC, and are electrically connected to the buried contact patterns BC.

[0144] According to this embodiment, the landing pad LP includes a lower portion that is filled between the bit line structures BLS and an upper portion that extends from the lower portion onto a portion of the bit line structures BLS. That is, the upper portions of the landing pad LP overlap a portion of the bit line structures BLS in a plan view. Each upper portion of the landing pad LP covers the upper surface of the hard mask pattern HM of the bit line structures BLS and has a width wider than the buried contact pattern BC. In other words, the upper width of the landing pad LP is greater than the distance between the bit line structures BLS or the width of the bit line structures BLS. As such, since the upper portions of the landing pad LP extend onto the bit line structures BLS, the area of ​​the upper surface of the landing pad LP increases.

[0145] The upper surface of the landing pad LP is located above the upper surface of the bit line structure BLS, and the lower surface of the landing pad LP is located below the upper surface of the bit line structure BLS.

[0146] In this embodiment, the upper portion of the landing pad LP has an elliptical shape with a major axis and a minor axis in a plan view, and the major axis of the upper portion of the landing pad LP is diagonal to the first direction D1 and the second direction D2. In this embodiment, the upper portion of the landing pad LP has a rounded rhomboid, a rounded trapezoid, or a rounded rectangle.

[0147] In one embodiment, each of the landing pads LP includes a contact silicide pattern, a barrier metal pattern, and a metal pattern.

[0148] The pad insulating pattern PIP fills the gap between the upper portions of the landing pads LP. The pad insulating pattern PIP has a rounded lower surface, and the lower surface of the pad insulating pattern PIP contacts a portion of the bit line spacer. The upper surface of the pad insulating pattern PIP is coplanar with the upper surface of the landing pads LP. The pad insulating pattern PIP includes a silicon oxide film, a silicon nitride film, and / or a silicon oxynitride film. The pad insulating pattern PIP may be formed of a single film or a multi-layer film.

[0149] According to this embodiment, the data storage patterns DS are disposed on the landing pads LP, respectively. The data storage patterns DS are electrically connected to the second impurity regions 1b through the landing pads LP and buried contact patterns BC. Each of the data storage patterns DS is disposed offset from each of the landing pads LP and contacts a portion of each of the landing pads LP. In one example, the data storage patterns DS are disposed in a honeycomb or zigzag shape in a plan view.

[0150] In one example, the data storage pattern DS is a capacitor and includes lower and upper electrodes and a dielectric layer interposed therebetween. Alternatively, the data storage pattern DS may be a variable resistance pattern that switches between two resistance states depending on an electrical pulse applied to the memory element. For example, the data storage pattern DS may include a phase-change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material, whose crystalline state changes depending on the amount of current.

[0151] In the peripheral circuit region PCR, a first transistor having a first threshold voltage is provided in the first region 10, and a second transistor having a second threshold voltage is provided in the second region 20.

[0152] The isolation film 101 defines a first active region ACT1 in the first region 10 and a second active region ACT2 in the second region 20.

[0153] A first gate structure GS1 is disposed on the first active region ACT1, and first source and drain regions SD1 are provided on both sides of the first gate structure GS1 in the semiconductor substrate 100. The first source and drain regions SD1 include impurities of a first conductivity type (e.g., n-type) doped into the semiconductor substrate 100.

[0154] A second gate structure GS2 is disposed on the semiconductor substrate 100 on the second active region ACT2, and second source and drain regions SD2 are provided in the semiconductor substrate 100 on both sides of the second gate structure GS2. The second source and drain regions SD2 include impurities of a second conductivity type (e.g., p-type) doped into the semiconductor substrate 100.

[0155] As described above, the first gate structure GS1 includes the first interface pattern IL1, the first high dielectric pattern HK1, the first metal pattern WF1, the first gate electrode EP1, and the first hard mask pattern HM1, and the lower portions of the first high dielectric pattern HK1 and the first metal pattern WF1 include a dipole material that adjusts the threshold voltage of the transistor.

[0156] As described above, the second gate structure GS2 includes a second interface pattern IL2, a second high-k dielectric pattern HK2, a second metal pattern WF2, a second gate electrode EP2, and a second hard mask pattern HM2. The second high-k dielectric pattern HK2 is formed of a metal oxide, and the oxygen content of the upper portion of the second high-k dielectric pattern HK2 is higher than that of the lower portion. The oxygen-rich upper portion of the second high-k dielectric pattern HK2 can adjust the threshold voltage of a transistor.

[0157] The first and second metal patterns WF1 and WF2 of the first and second gate structures GS1 and GS2 are formed of the same metal material.

[0158] The first and second gate electrodes (EP1, EP2) of the first and second gate structures (GS1, GS2) include a metal having a lower resistance than the first and second metal patterns (WF1, WF2), and the bit line BL of the bit line structure BLS includes the same metal as the first and second gate electrodes (EP1, EP2).

[0159] Furthermore, a channel layer 103 is disposed between the second gate structure GS2 and the semiconductor substrate 100. That is, the channel layer 103 is disposed between the second interface pattern IL2 and the semiconductor substrate 100. The channel layer 103 is formed by a selective epitaxial growth (SEG) process. The channel layer 103 includes a semiconductor material having a higher carrier mobility than silicon. For example, the channel layer 103 is a silicon germanium layer having a lattice constant different from that of the semiconductor substrate 100. For example, the channel layer 103 is formed to a thickness of approximately 80 Å to 120 Å.

[0160] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0161] 1a, 1b 1st and 2nd impurity regions 10 First area 20 Second area 100 Semiconductor substrate 101 Element isolation film 103 Channel Layer 110 Interfacial film 115 Buffer insulating film 120 High dielectric film 120a, 120b upper and lower parts 125 Polysilicon pattern 130 Sacrificial metal film 131 Sacrificial Metal Pattern 140 Dipole film (work function adjustment film) 150 work function metal film 150a, 150b First and second work function layers 160 Gate metal film ACT cell active area ACT1, ACT2 1st, 2nd active region AP1, AP2 1st and 2nd pin active pattern BC Buried Contact Pattern BL Bit Line BLS Bit Line Structure CAR cell array area CH1, CH2 1st and 2nd channel patterns Da dipole matter DC Bit Line Contact Pattern DCS Bit Line Contact Spacer DS Data Storage Pattern EP1, EP2 First and second gate electrodes GS1, GS2 First and second gate structures HK1, HK2 1st and 2nd high dielectric patterns HK2a 2nd lower part HK2b: Second upper part (second work function layer) HM Hard mask pattern HM1, HM2 First and second hard mask patterns IL1, IL2 First and second interface patterns ILD Interlayer insulating film IP sidewall insulation pattern LP Landing Pad MP Mask Pattern PCR peripheral circuit area PIP pad insulation pattern RS recess area SD1, SD2 First and second source and drain regions SP1, SP2 First and second semiconductor patterns SS spacer WL Word Line Structure WF1, WF2 First and second metal patterns WF1a First lower part (first work function layer) WF1b 1st upper part

Claims

1. a semiconductor substrate including a first region and a second region; a first gate structure disposed on the semiconductor substrate in the first region; a second gate structure disposed on the semiconductor substrate in the second region; the first gate structure includes a first metal pattern, a first high dielectric pattern between the semiconductor substrate and the first metal pattern, and a first work function layer between the first high dielectric pattern and the first metal pattern; the second gate structure includes a second metal pattern, a second high dielectric pattern between the semiconductor substrate and the second metal pattern, and a second work function layer between the second high dielectric pattern and the second metal pattern; the first work function layer includes a first metal element in the first metal pattern and a dipole material in the first high dielectric pattern; The semiconductor device according to claim 1, wherein the second work function layer and the second high dielectric constant pattern contain metal oxide, and an oxygen content in the second work function layer is greater than an oxygen content in the second high dielectric constant pattern.

2. The semiconductor device according to claim 1 , wherein the first work function layer and the second work function layer are located at different distances from the upper surface of the semiconductor substrate.

3. The semiconductor device of claim 1 , wherein the second high dielectric pattern and the second work function layer do not include the dipole material in the first high dielectric pattern.

4. 2. The semiconductor device of claim 1, wherein the dipole material in the first high dielectric pattern includes a lanthanum-based material.

5. 2. The semiconductor device according to claim 1, wherein the first high dielectric pattern and the second high dielectric pattern contain a second metal element, silicon (Si), and oxygen (O).

6. 2. The semiconductor device according to claim 1, wherein the first high dielectric pattern has the same thickness as the second high dielectric pattern.

7. 2. The semiconductor device of claim 1, wherein the first metal pattern and the second metal pattern include metal materials having the same work function.

8. The semiconductor device of claim 7 , wherein the first metal pattern has the same thickness as the second metal pattern.

9. The semiconductor device according to claim 1 , wherein the second work function layer contains the first metal element.

10. the first gate structure further includes a first interface pattern between the semiconductor substrate and the first high dielectric pattern; the second gate structure further includes a second interface pattern between the semiconductor substrate and the second high dielectric pattern; The semiconductor device of claim 1 , wherein the first and second interface patterns include the same dielectric material.

11. The semiconductor device of claim 10 , wherein the first interface pattern further includes the dipole material.

12. the first work function layer comprises LaTiN; The semiconductor device according to claim 1 , wherein the second work function layer includes TiHfON.

13. a semiconductor substrate including a first region and a second region; a first gate structure disposed on the semiconductor substrate in the first region; a second gate structure disposed on the semiconductor substrate in the second region; the first gate structure includes a first gate electrode, a first interface pattern between the first gate electrode and the semiconductor substrate, a first high dielectric pattern between the first interface pattern and the first gate electrode, and a first metal pattern between the first high dielectric pattern and the first gate electrode; the second gate structure includes a second gate electrode, a second interface pattern between the second gate electrode and the semiconductor substrate, a second high dielectric pattern between the second interface pattern and the second gate electrode, and a second metal pattern between the second high dielectric pattern and the second gate electrode; the first metal pattern and the second metal pattern include metal materials having the same work function; the first metal pattern includes a first lower portion in contact with an upper surface of the first high dielectric pattern and a first upper portion spaced apart from the first high dielectric pattern; the second high dielectric pattern includes a second lower portion adjacent to the second interface pattern and a second upper portion adjacent to the second metal pattern; the first high dielectric pattern and the first lower portion of the first metal pattern include a lanthanide material; The semiconductor device according to claim 1, wherein the oxygen content of the second upper portion of the second high dielectric pattern is greater than the oxygen content of the second lower portion.

14. The semiconductor device of claim 13 , wherein the first interface pattern includes the lanthanide material.

15. The semiconductor device of claim 13 , wherein the second interface pattern and the second high dielectric pattern do not contain the lanthanide material.

16. 14. The semiconductor device of claim 13, wherein the first high dielectric pattern has the same thickness as the second high dielectric pattern.

17. a semiconductor substrate including a cell array region and a peripheral region including a first region and a second region; an isolation layer defining a cell active region in the cell array region, a first active region in the first region, and a second active region in the second region; a bit line structure crossing a cell active region of the cell array region; a first gate structure disposed over the first active region; a second gate structure disposed over the second active region; the first gate structure includes a first gate electrode, a first interface pattern between the first gate electrode and the semiconductor substrate, a first high dielectric pattern between the first interface pattern and the first gate electrode, and a first metal pattern between the first high dielectric pattern and the first gate electrode; the second gate structure includes a second gate electrode, a second interface pattern between the second gate electrode and the semiconductor substrate, a second high dielectric pattern between the second interface pattern and the second gate electrode, and a second metal pattern between the second high dielectric pattern and the second gate electrode; The bit line structure includes a bit line extending in one direction and a bit line contact pattern between the bit line and the cell active region. the first high dielectric pattern and a lower portion of the first gate electrode contacting the first high dielectric pattern include a dipole material; the second high dielectric pattern includes a lower portion adjacent to the second interface pattern and an upper portion adjacent to the second metal pattern; The semiconductor device according to claim 1, wherein the oxygen content of the upper portion of the second high dielectric constant pattern is greater than the oxygen content of the lower portion of the second high dielectric constant pattern.

18. the first gate electrode and the second gate electrode include the same first metal material as the bit line; 18. The semiconductor device of claim 17, wherein the first metal pattern and the second metal pattern include the same second metal material.

19. 18. The semiconductor device according to claim 17, wherein the first high dielectric pattern and the second high dielectric pattern contain a first metal element and oxygen.

20. further comprising a channel layer disposed between the second gate structure and the semiconductor substrate; 18. The semiconductor device according to claim 17, wherein the channel layer has a lattice constant different from that of the semiconductor substrate.

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