Staircase structure in three-dimensional memory device, and method for forming them

Abstract

To provide a staircase structure in a three-dimensional memory device, and provide a method for forming them.SOLUTION: The present invention discloses an embodiment of a three-dimensional memory device having a staircase structure and a method for forming them. As an example, the three-dimensional memory device contains a memory array structure and the staircase structure. The staircase structure is positioned at a position of a middle of a memory array structure, and devices the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure contains: a plurality of steps extended along the lateral direction; and a bridge structure contacted to the memory array structure. Each step contains one step of one or a plurality of dielectric pairs. Each step contains a conductive part electrically connected to the bridge structure, and is electrically connected to the memory array structure via the bridge structure. As separated from the bridge structure along a second lateral direction of a right angel of the lateral direction, a width of the conductive part is reduced.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods for fabricating the same. [Background technology]

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as memory cell feature sizes approach lower limits, planar processes and fabrication techniques become difficult and expensive. As a result, memory densities for planar memory cells approach upper limits.

[0003] 3D memory architectures can address the density limitations of planar memory cells and include a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention [Means for solving the problem]

[0004] SUMMARY OF THE INVENTION Embodiments of a 3D memory device having a staircase structure and a method for forming the same are disclosed herein.

[0005] In one example, a 3D memory device includes a memory array structure and a staircase structure. The staircase structure is located in the middle of the memory array structure and divides the memory array structure into a first memory array structure and a second memory array structure along a horizontal direction. The staircase structure includes multiple steps extending along the horizontal direction and a bridge structure in contact with the first memory array structure and the second memory array structure. The multiple steps include one step on one or more dielectric pairs. The step includes a conductor portion located on an upper surface of the step and in contact with the bridge structure for electrical connection, and a dielectric portion at the same level and in contact with the conductor portion. The step is electrically connected to at least one of the first memory array structure and the second memory array structure via the bridge structure. The width of the conductor portion decreases as the distance from the bridge structure increases along a second horizontal direction perpendicular to the horizontal direction.

[0006] In another example, a 3D memory device includes a memory array structure and a landing structure in contact with the memory array structure. The landing structure includes a plurality of landing regions at respective depths, each extending along a lateral direction, and a bridge structure in contact with the memory array structure. Each of the plurality of landing regions includes a conductor portion on a respective upper surface and a dielectric portion at the same level and in contact with the conductor portion. The conductor portion is electrically connected to the memory array structure via the bridge structure. The width of the conductor portion decreases as it moves away from the bridge structure along a second lateral direction perpendicular to the lateral direction. Each of the plurality of landing regions overlies one or more dielectric pairs.

[0007] In yet another example, a 3D memory device includes a memory array structure and a staircase structure. The staircase structure includes a plurality of steps extending along a lateral direction. The plurality of steps includes steps each having a conductor portion on an upper surface of the step and a dielectric portion at the same level and in contact with the conductor portion. The conductor portion is electrically connected to the memory array structure. A width of the conductor portion varies along a second lateral direction perpendicular to the lateral direction.

[0008] In yet another example, a method for forming a staircase structure for a 3D memory device includes the following operations: First, a plurality of steps are formed, the plurality of steps having a plurality of first sacrificial layers and a plurality of first dielectric layers interleaved among the plurality of steps; A bridge structure is formed in contact with the plurality of steps, the bridge structure having a plurality of second sacrificial layers and a plurality of second dielectric layers interleaved; Each first sacrificial layer is in contact with a respective second sacrificial layer at the same level, and each first dielectric layer is in contact with a respective second dielectric layer at the same level; A sacrificial portion is formed in the first sacrificial layer corresponding to at least one of the steps; The sacrificial portion is on an upper surface of each step and is cut at an edge of the upper step; The second sacrificial layer and the sacrificial portion are removed by the same etching process to form a plurality of lateral recesses and one lateral recess portion, respectively; A plurality of conductor layers are formed in the lateral recesses, and a conductor portion is formed in the lateral recess portion and contacts a respective one of the conductor layers.

[0009] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure and to enable those skilled in the art to make and use the disclosure. [Brief explanation of the drawings]

[0010] [Figure 1A] 1 is a schematic diagram of an exemplary 3D memory device having a staircase structure, in accordance with some embodiments of the present disclosure. [Figure 1B] 1B is a top perspective view of an exemplary staircase structure of the 3D memory device shown in FIG. 1A according to some embodiments of the present disclosure. [Figure 1C] 1B is a plan view of the exemplary 3D memory device shown in FIG. 1A, according to some embodiments of the present disclosure. [Figure 1D] 1B is another plan view of the exemplary 3D memory device shown in FIG. 1A, according to some embodiments of the present disclosure. [Figure 1E] 1B is a detailed top perspective view of an exemplary staircase structure of the 3D memory device shown in FIG. 1A, according to some embodiments of the present disclosure. FIG. [Figure 2A] 1 is a schematic diagram of another exemplary 3D memory device having a staircase structure, in accordance with some embodiments of the present disclosure. [Figure 2B] 2B is a top perspective view of an exemplary staircase structure of the 3D memory device shown in FIG. 2A according to some embodiments of the present disclosure. [Figure 2C] 2B is a plan view of the exemplary 3D memory device shown in FIG. 2A, according to some embodiments of the present disclosure. [Figure 3A] 1A and 1B are cross-sectional views of an exemplary 3D memory device having a staircase structure in accordance with some embodiments of the present disclosure. [Figure 3B] 3B is another cross-sectional view of the 3D memory device shown in FIG. 3A according to some embodiments of the present disclosure. [Figure 3C] 3B is another cross-sectional view of the 3D memory device shown in FIG. 3A according to some embodiments of the present disclosure. [Figure 3D] FIG. 3D is a detailed cross-sectional view of the conductor portion shown in FIG. 3C according to some embodiments of the present disclosure. [Figure 4A] 1A-1C illustrate a fabrication process for forming an exemplary staircase structure of a 3D memory device according to some embodiments of the present disclosure. [Figure 4B] 1A-1C illustrate a fabrication process for forming an exemplary staircase structure of a 3D memory device according to some embodiments of the present disclosure. [Figure 4C] 1A-1C illustrate a fabrication process for forming an exemplary staircase structure of a 3D memory device according to some embodiments of the present disclosure. [Figure 4D] 1A-1C illustrate a fabrication process for forming an exemplary staircase structure of a 3D memory device according to some embodiments of the present disclosure. [Figure 4E] 1A-1C illustrate a fabrication process for forming an exemplary staircase structure of a 3D memory device according to some embodiments of the present disclosure. [Figure 5A] 1A-1C illustrate exemplary steps prior to an ion implantation process, according to some embodiments. [Figure 5B]1A-1C illustrate exemplary steps following an ion implantation process, according to some embodiments. [Figure 6] 1 is a flowchart of a method for forming an exemplary staircase structure of a 3D memory device, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0011] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0012] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will also be apparent to those skilled in the art that the present disclosure can be employed in a variety of other applications.

[0013] It should be noted that references herein to "one embodiment," "an embodiment," "one exemplary embodiment," "some embodiments," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0014] Generally, terminology can be understood, at least in part, from its usage in context. For example, as used herein, the term "one or more" may be used to describe a feature, structure, or characteristic in the singular sense, or may be used to describe a combination of features, structures, or characteristics in the plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may be understood to convey a singular usage or a plural usage, again depending at least in part on the context. Additionally, the term "based on" is not necessarily intended to convey an exclusive set of factors, and instead may be understood to allow for the presence of additional factors not necessarily stated, again depending at least in part on the context.

[0015] It will be readily understood that the meanings of "on," "above," and "over" in this disclosure are to be interpreted broadly, so that "on" not only means "directly on" something, but can also include the meaning "on" something with intermediate features or intervening layers, and "above" or "over" not only means "above" or "over" something, but can also include the meaning of it being "above" or "over" something without intermediate features or intervening layers (i.e., directly on top of something).

[0016] Additionally, spatial terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to facilitate description to explain the relationship of one element or feature to another element or feature as shown in the figures. Spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatial descriptors used herein may likewise be interpreted accordingly.

[0017] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself may be patterned. Materials added on top of the substrate may be patterned or left unpatterned. Additionally, substrates can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, substrates may be made of non-conductive materials, such as glass, plastic, or a sapphire wafer.

[0018] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend throughout an underlying or overlying structure, or may have an extent that is smaller than the extent of the underlying or overlying structure. Furthermore, a layer can be a region of a homogeneous or heterogeneous continuous structure that has a thickness that is smaller than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal surfaces between the upper and lower surfaces of a continuous structure, or at the upper and lower surfaces. A layer can extend laterally, vertically, and / or along a tapered surface. A substrate can be a layer and can include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect access (VIA) contacts are formed) and one or more dielectric layers.

[0019] As used herein, the term "nominal" refers to a desired or target value of a characteristic or parameter for a component or process operation, as set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations or tolerances in the manufacturing process. As used herein, the term "about" indicates a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may indicate, for example, a value of a given quantity that varies between 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0020] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (such as NAND memory strings, referred to herein as "memory strings") on a laterally oriented substrate, such that the memory strings extend perpendicular to the substrate. As used herein, the term "vertical" nominally means perpendicular to the outer surface of the substrate.

[0021] In some 3D memory devices, memory cells for storing data are vertically stacked via stacked memory structures (e.g., memory stacks). 3D memory devices typically include a staircase structure formed near the stacked memory structures for purposes such as word line fanout. As the demand for higher storage capacity continues to increase, the number of vertical levels of the stacked memory structures also increases, making it more difficult to form word line via contacts on the steps without drilling the contacts and creating shorts. For example, word line via contacts are often formed by forming openings in contact with the steps (e.g., landing areas of the steps) in an insulating structure on which the staircase structure is located and filling the openings with a conductive material. Conventionally, these openings formed to contact the steps at different depths / heights are formed using the same etching process. Due to variations in opening depth, the openings are often not etched evenly or as desired. For example, openings in contact with lower steps (e.g., deeper openings) and openings in contact with higher steps (e.g., shallower openings) are exposed to the same etching time, resulting in over-etching of the openings in contact with the higher steps. Over-etching can cause conductor layers (e.g., word lines) on the top surface of higher steps to be unnecessarily damaged or even etched. Word line via contacts can unnecessarily contact other conductor layers below the respective conductor layer, causing punch-through that leads to short circuits or unnecessary leakage. To solve this problem, efforts have been made to thicken the conductor layers for landing. However, thicker landing regions still cannot adequately reduce the possibility of punch-through, and the fabrication process becomes more difficult.

[0022] Various embodiments according to the present disclosure provide a staircase structure and a method for fabricating the same. A staircase structure having multiple steps may include a conductor portion on the top surface of at least one step and a dielectric structure including one or more dielectric pairs below the conductor portion. The conductor portion covers at least the landing area of ​​each step (e.g., a portion of the step) so that a word line via contact can contact and be electrically connected to the respective step. The thickness of the dielectric structure may be equal to the distance from the bottom surface of the conductor portion to the top surface of the substrate, and is a thickness desired to prevent interference between conductor portions in different steps due to punch-through. Along a lateral direction perpendicular to the direction in which the steps extend, the width of each conductor portion may gradually decrease from the end.

[0023] In embodiments of the present disclosure, the conductor portion includes an overlapping portion and a non-overlapping portion. An overlapping portion refers to a portion of the conductor portion (or a conductor portion of the tier above / below) that overlaps with the tier immediately above and / or below. A non-overlapping portion refers to a portion of the conductor portion that does not overlap with the tier above or below. Word line via contacts may be formed on the non-overlapping portions of the conductor portion. The non-overlapping portions of the conductor portion may have a large landing area that is desirable for forming the respective word line via contacts on. In some embodiments, the dimensions of the non-overlapping portions of the conductor portion along the direction in which the tier extends are nominally the same as the dimensions of the tier.

[0024] In some embodiments, the dielectric structure below the conductors includes a respective dielectric layer and one or more lower dielectric pairs, each dielectric pair including a dielectric portion and a dielectric layer in a lower step. In some embodiments, the number of dielectric pairs below the conductors in each step is equal to the number of steps / levels below the step. Even if punch-through occurs in any conductor, the word line via contact does not have contact on the conductor (or word line) in the lower step, and leakage or shorting can be reduced / eliminated. As a result, it is easier to form openings.

[0025] In various embodiments, the steps are formed in a staircase structure located in the middle of the memory array structure or on the side of the memory array structure. The staircase structure can include a bridge structure having multiple interleaved conductor layers and dielectric layers. The conductor layers are conductively connected to memory cells in the memory array structure. The conductor portions of each step can contact the conductor layers at the same level along a direction perpendicular to the direction in which the steps extend so that voltages can be applied to the memory cells via the conductor portions and conductor layers at the same level.

[0026] To form the conductor portions, an ion implantation process is performed before the gate exchange. The ion implantation process is employed to form sacrificial portions, which are ion-implanted portions of the respective sacrificial layers on the top surfaces of the steps. The ion implantation process can change the physical properties of the portions so that the sacrificial portions can be etched faster than other portions of the sacrificial layer not treated by the ion implantation. As a result, one etching process can be applied to simultaneously remove the sacrificial layer (e.g., for forming word lines in the bridge structure) and the sacrificial portions, so that lateral recesses and lateral recessed portions can be formed. The dielectric structure below the sacrificial portions can be retained. In some embodiments, the lateral recesses include over-etched portions of the sacrificial layer below the immediately upper step due to the higher etching rate on the sacrificial portions. A conductor material is deposited to fill the lateral recesses in each step and in the bridge structure. Multiple conductor layers can be formed in the bridge structure. Multiple conductor portions, each at a respective step and overlying a respective dielectric structure, can be formed in the staircase. In some embodiments, the over-etched portions form overlaps between adjacent conductor portions after being filled with the conductor portions.

[0027] FIGS. 1A-1C and 2A-2C show schematic diagrams of 3D memory devices 100 and 200, respectively, having a staircase structure, according to some embodiments. Specifically, FIGS. 1A-1C show layouts in which the staircase structure is located in the middle of the memory plane, and FIGS. 2A-2C show layouts in which the staircase structure is located on both sides of the memory plane. The staircase structure of the present disclosure can be formed in both 3D memory devices 100 and 200. As an example for illustrating the present disclosure, the embodiments focus on the structure and fabrication process of the staircase structure in 3D memory device 100. In some embodiments, the staircase structure in 3D memory device 200 can be formed in a similar fabrication process. Note that x- and y-axes are included in FIGS. 1A and 2A to indicate two orthogonal (perpendicular) directions in the wafer plane. The x-direction is the wordline direction of each 3D memory device, and the y-direction is the bitline direction of each 3D memory device. It should be noted that the structures in this disclosure are for illustrative purposes only and therefore do not represent the dimensions, proportions, or shape of the actual product.

[0028] FIG. 1A shows a schematic diagram of an exemplary 3D memory device 100 having a staircase structure 102 in accordance with some embodiments of the present disclosure. In some embodiments, the 3D memory device 100 includes multiple memory planes. The memory planes may include a first memory array structure 104-1, a second memory array structure 104-2, and a staircase structure 102 intermediate the first and second memory array structures 104-1 and 104-2. The first and second memory array structures 104-1 and 104-2, which are both considered memory array structures, may or may not have the same area. In some embodiments, the staircase structure 102 is located in the center of the first and second memory array structures 104-1 and 104-2. For example, the first and second memory array structures 104-1 and 104-2 may be symmetrical in the x-direction with respect to the staircase structure 102. It is understood that in some examples, the staircase structure 102 may be midway between the first and second memory array structures 104-1 / 104-2 rather than at the center (centre) thereof, such that the first and second memory array structures 104-1 and 104-2 may have different sizes and / or numbers of memory cells. In some embodiments, the 3D memory device 100 is a NAND flash memory device in which memory cells are provided in the first and second memory array structures 104-1 and 104-2 in the form of an array of NAND memory strings (not shown in FIG. 1A ). The first and second memory array structures 104-1 and 104-2 may include any other suitable components, including, but not limited to, gate line slits (GLS), through array contacts (TAC), array common sources (ACS), etc.

[0029] Each word line (not shown in FIG. 1A ) in the memory plane extending laterally in the x-direction may be separated into two portions by a staircase structure 102: a first word line portion that crosses a first memory array structure 104-1 and a second word line portion that crosses a second memory array structure 104-2. The two portions of each word line may be electrically connected by a bridge structure (shown as bridge structure 108 in staircase structure 102 in FIGS. 1B and 1C ) at each step in staircase structure 102. A row decoder (not shown) may be formed directly above, below, or immediately adjacent to each staircase structure 102. Each row decoder may bidirectionally drive word lines in opposite directions from the middle of the memory plane.

[0030] The detailed structure of the staircase structure 102 is shown in FIGS. 1B and 1C. FIG. 1B shows a top plan view of the staircase structure 102 within the 3D memory device 100. FIG. 1C shows a top view of the staircase structure 102 and its spatial relationship with adjacent first and second memory array structures 104-1 and 104-2. For ease of illustration, FIG. 1C depicts only one staircase structure 102. In various embodiments, the 3D memory device 100 includes multiple staircase structures, for example, between the first and second memory array structures 104-1 and 104-2 aligned with the staircase structure 102 along the y-direction. For example, another staircase structure may be identical to the staircase structure 102 and may be a mirror staircase structure 102 along the y-direction. Also, other possible structures, such as dummy stairs, are omitted within the staircase structure 102 for ease of illustration.

[0031] Figure 1B shows a staircase structure 102 having a staircase 106 and a bridge structure 108 that are in contact with each other. Figure 1E shows a detailed 3D perspective view of the staircase structure 102. The staircase structure 102 may be on a substrate 10 (shown in Figure 1D), which may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0032] The staircase 106 may include multiple steps 114 extending along a wordline direction, e.g., the x-direction. Each step 114 may have a different depth along the z-direction and a landing area, e.g., for forming contact with a corresponding wordline VIA contact. Each step 114 (denoted as a "level") of the staircase 106 may include one or more pairs of material layers. In some embodiments, the upper material layer of each step 114 includes a conductor portion for interconnection with a wordline VIA contact in the vertical direction. In some embodiments, every two adjacent steps 114 of the staircase 106 are offset by nominally the same distance in the z-direction and nominally the same distance in the x-direction. In this manner, each offset can form a "landing area" for interconnection with a wordline contact of a 3D memory device in the z-direction. In some embodiments, each step 114 includes at least one dielectric layer below the conductor portion.

[0033] The bridge structure 108 can include vertically interleaved conductor layers and dielectric layers (not shown), and the conductor layers (e.g., metal layers or polysilicon layers) can function as part of the word lines. Unlike the staircase 106, in which the word lines in the staircase 106 are disconnected from the memory array structures (e.g., 104-1 and / or 104-2) in the x-direction (e.g., in the positive x-direction, the negative x-direction, or both), the word lines in the bridge structure 108 can be preserved to bridge the word line VIA contacts resting on the steps 114 and the memory array structures (e.g., 104-1 and / or 104-2) to achieve a bidirectional word line drive scheme. In some embodiments, at least one step 114 in one of the steps 106 is electrically connected to at least one of the first memory array structure 104-1 and the second memory array structure 104-2 via the bridge structure 108. At least one word line can extend laterally within the memory array structures (e.g., 104-1 and / or 104-2) and the bridge structure 108 such that at least one rung 114 can be electrically connected to at least one of the first and second memory array structures (e.g., 104-1 and / or 104-2) via the bridge structure 108 by at least one word line. In one example, the rungs 114 in the staircase 106 can be electrically connected (in the negative x-direction) to the first memory array structure 104-1 via the bridge structure 108 by respective word line portions extending in the negative x-direction. In some embodiments, at least one rung 114 in the staircase 106 is electrically connected to each of the first memory array structure 104-1 and the second memory array structure 104-2 via the bridge structure 108, for example, by respective word line portions extending in the negative and positive x-directions, respectively.

[0034] The conductor portions in the steps 106 and the conductor layers in the bridge structure 108 may each comprise a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. The dielectric layers in the steps 106 and the bridge structure 108 may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductor portions and the conductor layers comprise the same material, e.g., a metal such as tungsten, and the dielectric layers comprise the same material, such as silicon oxide.

[0035] 1C and 1D show a staircase structure 102 between the first and second memory array structures 104-1 and 104-2. As shown in FIGS. 1C and 1D , the staircase 106 may include multiple steps 114 extending along the x-direction, and a word line via contact 116 is formed on at least one (e.g., each) step 114. Each of the first and second memory array structures 104-1 and 104-2 may include one or more memory blocks, each including one or more memory fingers 120. In some embodiments, the staircase structure 102 may be between a pair of memory fingers 120 along the y-direction. Each memory finger 120 may include multiple memory strings 112 extending along the z-direction. The memory string 112 may include a channel structure having a blocking layer, a memory layer, a tunnel layer, a semiconductor layer, and optionally a dielectric core disposed within the channel hole and radially arranged from the sidewall toward the center of the channel hole. The memory strings 112 may intersect with multiple word lines (e.g., conductor layers within memory fingers 120) to form multiple memory cells. The memory cells may form memory cell arrays within respective memory array structures. In some embodiments, the GLS 110 extending along the x and z directions divides the memory cells within the first and second memory array structures 104-1 and 104-2 into multiple memory fingers 120 along the y direction.

[0036] According to some embodiments, a bridge structure 108 connects (both physically and electrically) the first memory array structure 104-1 and / or the second memory array structure 104-2 to achieve a bidirectional word line drive scheme. That is, according to some embodiments, the staircase structure 102 does not necessarily completely cut the memory array structures in the middle, but instead leaves the first and second memory array structures 104-1 and 104-2 connected by the bridge structure 108 of the staircase structure. In this way, each word line can be driven bidirectionally (in both the positive and negative x-directions) from a respective word line VIA contact 116 in the middle of the 3D memory device 100 via the bridge structure 108. FIGS. 1C and 1D show exemplary current paths of a bidirectional word line drive scheme with the staircase structure 102. The current paths indicated by arrows represent currents passing through separate word lines at different levels.

[0037] 2A-2C show schematic diagrams of a 3D memory device 200 having staircase structures 202-1 and 202-2, each on either side of a memory array structure 204. The staircase structures 202-1 and 202-2 and the memory array structure 204 may be on a substrate 101 similar to that of the 3D memory device 100. The 3D memory device 200 may include a memory plane having a memory cell array within the memory array structure 204. Unlike the 3D memory device 100, the 3D memory device 200 includes two staircase structures 202-1 and 202-2 on either side of the memory array structure 204 in the x-direction. Each word line of the memory plane extends laterally in the x-direction across the entire memory plane to a respective level within the staircase structure 202-1 or 202-2. A row decoder (not shown) is formed directly above, below, or immediately adjacent to each staircase structure. That is, each row decoder drives half of the memory cells in one direction (in either the positive or negative x direction, but not both) via half of the word lines, each of which traverses the entire memory plane.

[0038] The staircase structures 202-1 and 202-2 may have similar / identical structures. FIG. 2B shows a front top view of a staircase structure that may represent each of the staircase structures 202-1 and 202-2. The staircase structure may include a staircase 206 having multiple steps 214 extending along the x-direction, similar to the staircase 106. The staircase structure also includes a bridge structure 208 electrically and physically connected to the staircase 206. The bridge structure 208 may include interleaved conductor layers and dielectric layers, similar to those of the bridge structure 108. In some embodiments, the bridge structure 208 includes multiple steps extending along the x-direction, each corresponding to a respective step of the staircase 206. The staircase 206 may be similar to the staircase 106, for example, in that at least one step 214 includes a conductor portion on its top surface and is electrically connected to a conductor layer at the same level within the bridge structure 208. The conductor layers in the bridge structure 208 may be word line portions electrically connected to word lines (eg, conductor layers) in the memory array structure 204 .

[0039] FIG. 2C illustrates staircase structures 202-1 and 202-2, each on a respective side of a memory array structure 204. As shown in FIG. 2C, the staircase 206 may include multiple steps 214 extending along the x-direction, with word line via contacts 216 formed on at least one (e.g., each) step 214. The memory array structure 204 may include one or more memory blocks, each including one or more memory fingers 220. Each memory finger 220 may include multiple memory strings 212, similar to the memory strings 112 in the 3D memory device 200. The memory strings 212 may intersect with multiple word lines (e.g., conductor layers within the memory fingers 220) to form multiple memory cells that form a memory cell array within the respective memory array structure. In some embodiments, the GLS 210 extending along the x- and z-directions divide the memory cells in the memory array structure 204 into multiple memory fingers 220 along the y-direction.

[0040] According to some embodiments, bridge structures 208 each connect (both physically and electrically) memory array structures 204 to achieve a unidirectional word line drive scheme. In this manner, each word line can be driven in one direction (in either the positive or negative x-direction) from a respective word line VIA contact 216 on one side of the 3D memory device 200 via bridge structures 208. As shown in FIG. 2C , the current paths indicated by arrows represent currents passing through two separate word lines at different levels.

[0041] 3A-3D show three cross-sectional views of a staircase structure (e.g., 102), each perpendicular to one another. Specifically, FIGS. 3A and 3B show cross-sectional views of staircase structure 102 along the A-A' and B-B' directions, respectively, as shown in FIG. 1B. FIG. 3A shows a cross-sectional view of staircase 106, illustrating the non-overlapping portions of the conductor portions. As shown in FIG. 1B, the A-A' direction represents the x-z plane, and the B-B' direction represents the zy plane. FIG. 3C shows an x-y cross-sectional view of a step / level of staircase structure 102. FIG. 3D shows a detailed cross-sectional view of an exemplary conductor portion. FIGS. 3A-3D can also represent cross-sectional views of staircase structures 202-1 / 202-2 along the same direction (shown in FIG. 2B), except that the bridge structures may have different numbers of conductor / dielectric layer pairs along the z direction.

[0042] As previously described, in a 3D memory device, the staircase structure may include a stair and a bridge structure in contact with the stair. As shown in FIGS. 3A and 3B, the staircase structure may include a stair 306 and a bridge structure 308 (only a portion of which is shown in FIG. 3B) in contact with the stair 306. The staircase structure may be formed on a substrate 302 similar to the substrate in the 3D memory device 100. An insulating structure 350 may be formed on at least the stair 306 such that at least the stair 306 is located within the insulating structure 350. Wordline via contacts 316 may be formed in the insulating structure 350 and rest on the landing areas of each step. For ease of illustration, only one wordline via contact 316 is shown. The insulating structure 350 may include any suitable dielectric material, such as silicon oxide, silicon nitride, and / or silicon oxynitride. The wordline via contacts 316 may include tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof. The bridge structure 308 may include multiple interleaved conductor layers 330 and dielectric layers 336 similar to those in the 3D memory device 100.

[0043] 3A and 3B , the staircase 306 includes multiple steps 314 extending along the x-direction, e.g., the wordline direction. Each step 314 may have a different depth along the z-direction. In some embodiments, except for the top step, the staircase 306 includes a conductor portion 320 on the top surface of at least one step 314, electrically and physically connected to a conductor layer 330 at the same level within the bridge structure 308. In some embodiments, each step 314 in the staircase 306 may include a respective conductor portion 320. The conductor portion 320 may contact a dielectric portion 324 at the same level (e.g., extending along the x-direction). Optionally, in each step 314, the conductor portion 320 may be on top of and in contact with another dielectric portion that is on top of and in contact with the underlying dielectric layer 326. In some embodiments, in each step 314, the conductor portion 320 may be on top of and in contact with the dielectric layer 326 without any other intervening dielectric portion. In some embodiments, each dielectric layer 326 in the staircase 306 contacts a dielectric layer 326 at the same level in the bridge structure 308. In some embodiments, the conductor portion 320 may be on more than one dielectric layer 336 in each step 314.

[0044] As shown in FIG. 3A , along the x-direction, the conductor portions 320 extend into the landing areas of the respective steps 314. The non-overlapping portions of the conductor portions 320 (shown in FIG. 3D ) may be cut off (e.g., do not extend into) the upper step 314 (e.g., directly above the step 314) at the end thereof. That is, little or no overlap is formed between the non-overlapping portions of adjacent conductor portions 320 along the x-direction. In some embodiments, no overlap is formed between the non-overlapping portions of any conductor portions 320 along the x-direction. In some embodiments, the width d of the non-overlapping portions of the conductor portions 320 along the x-direction may be less than or equal to the dimension of the step 314. Each word line via contact may be formed on the non-overlapping portions of the conductor portions 320.

[0045] In some embodiments, in step 314, dielectric portion 324 and the other dielectric portions (if formed) may have the same material, different from the material of dielectric layer 326. In some embodiments, dielectric layer 326 includes silicon oxide. In some embodiments, dielectric portion 324 includes silicon nitride. In some embodiments, the other dielectric portions (if formed) have the same dimensions along the x-direction as conductor portion 320. In step 314, the bottom surfaces of dielectric portion 324 and the other dielectric portions may be coplanar along the z-direction. Along the z-direction, the thickness of conductor portion 320 may be equal to or less than the thickness of dielectric portion 324, and the thickness of the other dielectric portions (if formed) may be less than the thickness of dielectric portion 324.

[0046] As shown in FIG. 3B , along the y-direction, the length D of the conductor portion 320 can be less than or equal to the dimension of each step 314. In some embodiments, the length D is equal to the dimension of each step 314 along the y-direction. In some embodiments, the length D is less than the dimension of each step 314, and the second dielectric portion 323 is formed at the end of the step 314 away from the bridge structure 308. The second dielectric portion 323 can have the same thickness as the dielectric portion 324 along the z-direction and can be made of the same material as the dielectric portion 324. Along the x-direction, the width of the second dielectric portion 323 can be less than, equal to, or greater than the width d of the conductor portion 320. The length D and width d of the conductor portion 320 can each be large enough to cover the landing area of ​​each step 314 and allow each word line via contact 316 to be formed at a desired location.

[0047] 3A and 3B , the conductor portions 320 may be on at least one respective dielectric layer 326 in the same step 314. In some embodiments, in each step 314, the conductor portions 320 are in contact with and on the respective dielectric layer 326. Meanwhile, the dielectric portions 324 may extend into the step 306 along the x-direction (e.g., along the negative x-direction), for example, from the boundary with the respective conductor portion 320 to the boundary between the step 306 and the memory array structure. In some embodiments, along the z-direction, at least one conductor portion 320 is on multiple interleaved dielectric layers 326 and dielectric portions 324. For example, the dielectric layer 326 may include a respective dielectric layer 326 in the same step and one or more dielectric layers 326 in the lower step 314. The dielectric portion 324 may include one or more dielectric portions 324 in the lower step 314. In some embodiments, at least one conductor portion 320 is also above other dielectric portions in the same step 314 along the z direction. As shown in FIG. 3A , all of the dielectric portions 324 and dielectric layers 326 below the conductor portions 320 may be referred to as a dielectric structure 340, and the thickness of the dielectric structure 340 along the z direction is equal to the distance between the bottom surface of each conductor portion 320 and the top surface of the substrate 302. In some embodiments, the length of the dielectric structure 340 along the y direction is equal to the length of the conductor portion 320 (e.g., length D). In some embodiments, the width of the dielectric structure 340 along the x direction is equal to the width of the conductor portion 320 (e.g., width d). In some embodiments, except for the bottom step 314 (e.g., step 314 at the bottom of the staircase 306), the dielectric structure 340 includes at least one pair of dielectric portions 324 and dielectric layers 326 corresponding to a lower step 314 (e.g., step 314 at a lower height / greater depth along the negative z direction). In some embodiments, except for the bottom step 314, each dielectric structure 340 includes at least one pair of dielectric portion 324 and dielectric layer 326 corresponding to the lower step 314 and the dielectric layer 326 within each step 314.

[0048] FIG. 3C shows a side cross-sectional view of the stair structure, illustrating the spatial relationship between the GLS 310, the conductor layer 330, the conductor portion 320, and the dielectric portion 324. As shown in FIGS. 3B and 3C , in some embodiments, the stair 306 includes a connecting structure 321 in contact with the bridge structure 308. The connecting structure 321, which is part of the stair 306 and extends along the x direction, may include at least one conductor strip and at least one dielectric strip interleaved on the substrate 302. In some embodiments, the length L of the connecting structure 321 along the y direction is greater than or equal to zero. For each step 314, the dimension of the connecting structure 321 along the x direction may be the length of the respective dielectric layer 326 (e.g., the sum of the widths of the dielectric portion 324 and the conductor portion 320). That is, along the x direction, the dimension of the connecting structure 321 may be the same as the length of the contact area between the step 314 and the bridge structure 308. The thickness of the connecting structure 321 along the z direction may be the same as the height of the respective step 314. That is, the thickness of connecting structure 321 may be equal to the distance from the top surface of step 314 / conductor portion 320 to the top surface of substrate 302. Each conductor strip may contact conductor layer 330 and dielectric portion 324 at the same level, and each dielectric strip may contact dielectric layer 336 and dielectric layer 326 at the same level. The material of the conductor strip may be the same as the material of conductor layer 330, and the material of the dielectric strip may be the same as the material of dielectric layer 336.

[0049] For each step 314, the top conductor strip may also contact the respective conductor portion 320, thus electrically connecting the conductor portion 320 and conductor layer 330 at the same level. Along the z-direction, the thickness of each conductor strip may be the same as the thickness of the respective conductor layer 330. In some embodiments, the conductor strips and dielectric strips that are part of the staircase 306 may be considered as extensions of the conductor layer 330 and dielectric layer 336 that enter the staircase 306 along the y-direction. In some embodiments of each step 314, the dielectric structure 340 is in contact with the respective connecting structure 321.

[0050] As shown in FIG. 3C , the GLS 310 may extend along the x-direction and be in contact with the bridge structure 308 (e.g., or the conductor layer 330 within the bridge structure 308). In some embodiments, the bridge structure 308 may be between the GLS 310 and the staircase 306. In some embodiments, the width d of the conductor portion 320 may decrease along the negative y-direction. In various embodiments, the width d may continue to decrease by a first distance d1 (e.g., from the boundary of the bridge structure 308 or the connecting structure 321, if present) and remain unchanged by a second distance d2 along the negative y-direction. As shown in FIG. 3C , the sum of d1 and d2 may be equal to D when the connecting structure 321 is not formed, or may be equal to (DL) when the connecting structure 321 is formed. In some embodiments, it is desirable for d1 to be small so that d1 is negligible compared to d2. For example, d1 can be about 2% to about 20% (eg, 2%, 3%, 5%, 8%, 10%, 15%, 18%, 20%) of d2.

[0051] FIG. 3D shows the detailed structure of the conductor portion 320. For ease of illustration, different patterns / shades are used in FIG. 3D to indicate various portions of the conductor portion 320. In some embodiments, the conductor portion 320 may be divided into a non-overlapping portion 320-1 and overlapping portions 320-2 and 320-3. The overlapping portion 320-2 may represent the portion of the conductor portion 320 (or the conductor portion 320 of the tier immediately above) that overlaps with the tier immediately above along the z-direction. The overlapping portion 320-3 may represent the portion of the conductor portion 320 (or the conductor portion 320 of the tier immediately below) that overlaps with the tier immediately below along the z-direction. The non-overlapping portion 320-1 may represent the portion of the conductor portion 320 that does not overlap with the tier above or below. The non-overlapping portion 320-1 and the overlapping portion 320-3 together may form the portion of the conductor portion 320 that is exposed on the top surface of the tier 314. The boundary between overlapping portion 320-2 and non-overlapping portion 320-1 is not physically formed, but may be the edge of the immediately upper step 314. As shown in Figures 3C and 3D, non-overlapping portion 320-1 contacts each of overlapping portions 320-2 and 320-3. As a result, the total area of ​​conductor portion 320 may be the sum of non-overlapping portion 320-1 and overlapping portions 320-2 and 320-3 along the xy plane.

[0052] In some embodiments, overlapping portion 320-2 and 320-3 may have nominally the same shape and / or nominally the same dimensions. In some embodiments, as shown in FIG. 3C , overlapping portion 320-2 has the shape of a right triangle, with the right angle formed by the edge of the immediately above step 314 and the boundary of dielectric portion 324 along the x-direction. The lateral dimension of overlapping portion 320-2 may gradually decrease along the negative y-direction. In some embodiments, the boundary of dielectric portion 324 may include the hypotenuse of the right triangle (e.g., overlapping portion 320-2) as well as a boundary along the y-direction (e.g., aligned with the edge of the immediately above step 314) and a boundary along the x-direction (e.g., with connecting structure 321 or bridge structure 308). In some embodiments, non-overlapping portion 320-1 may have the shape of a right-angled trapezoid. The lateral dimension of non-overlapping portion 320-1 may increase along the negative y-direction. That is, the width d of the conductor portion may decrease along the negative y direction or may remain unchanged.

[0053] 4A-4D illustrate a fabrication process for forming an exemplary staircase structure of a 3D memory device according to various embodiments of the present disclosure. FIGS. 5A and 5B illustrate the staircase before and after an ion implantation process according to some embodiments. FIG. 6 is a flowchart of a method 600 for forming an exemplary staircase structure of a 3D memory device according to some embodiments. It is understood that the operations illustrated in method 600 are not comprehensive, and that other operations may similarly be performed before, after, or during any of the illustrated operations. Furthermore, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 6 .

[0054] 6, method 600 begins at operation 602 where a stair structure having stair and bridge structures is formed. Figure 4A shows the corresponding structure.

[0055] As shown in FIG. 4A , a stair structure having a stair 406 and a bridge structure 408 is formed on a substrate 402. The stair 406 may be in contact with the bridge structure 408. The stair 406 may include a plurality of interleaved sacrificial layers 429 and a plurality of dielectric layers 426, forming a plurality of steps 414 extending along the x-direction (see, for example, steps 314 in FIG. 3A ). Each step 414 may include at least one sacrificial layer 429 / dielectric layer 426 pair. The bridge structure 408 may include a plurality of interleaved sacrificial layers 439 and a plurality of dielectric layers 436. In some embodiments, each sacrificial layer 439 is in contact with a respective sacrificial layer 429 at the same level, and each dielectric layer 436 is in contact with a respective dielectric layer 426 at the same level. In some embodiments, the sacrificial layers 439 and 429 include the same material, such as silicon nitride. In some embodiments, the dielectric layers 436 and 426 include the same material, such as silicon oxide.

[0056] To form the stack structure, a material stack may first be formed. The material stack may include vertically alternating first and second dielectric material layers. In some embodiments, the material stack is a dielectric stack, and the first and second material layers include different dielectric materials. The alternating first and second dielectric material layers may be alternately deposited on the substrate 402. In some embodiments, the first dielectric material layer includes a layer of silicon nitride, and the second dielectric material layer includes a layer of silicon oxide. The material stack may be formed by one or more thin film deposition processes, including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0057] Portions of the material stack may be patterned to form the stack structure. In some embodiments, separate masks, e.g., separate etching processes, may be used to form the staircase 406 and the bridge structure 408. In some embodiments, forming the staircase 406 includes repeatedly etching the material stack using an etch mask (e.g., a patterned photoresist or PR layer) over the material stack. The etch mask may be repeatedly trimmed, often incrementally inward from all directions, to expose portions of the material stack to be etched. The amount of PR trimmed may be directly related to (e.g., may be determinative of) the dimensions of the step. For example, the amount of PR trimmed along the x-direction may determine the width of the step 414 along the x-direction. The trimming of the PR layer may be obtained using a suitable etch, e.g., an isotropic etch such as a wet etch. One or more PR layers may be formed and trimmed sequentially to form the step. In some embodiments, the trimming of the PR layer is followed by etching of the material stack using a suitable etch process, e.g., a dry etch and / or a wet etch. In some embodiments, the material stack is etched a step depth along the z-direction following trimming of each PR layer. The step depth may be equal to the number of dielectric material layer pairs included in the step (e.g., the number of first / second dielectric material layers). In some embodiments, the number of dielectric material layer pairs is one. The photoresist mask trimming process followed by the material stack etching process is referred to herein as a trim etch cycle. The number of trim etch cycles can determine the number of steps formed in the material along the y-axis. In some embodiments, after forming the steps, the first dielectric material layer may form a sacrificial layer 429, and the second dielectric material layer may form a dielectric layer 426. The staircase 406 may be formed. In some embodiments, each step 414 includes a pair of a sacrificial layer 429 and an underlying dielectric layer 426 (e.g., one sacrificial / dielectric pair).

[0058] In various embodiments, the bridge structure 408 can be formed by patterning another portion of the material stack. An etch mask may or may not be used, depending on the design of the bridge structure 408. In various embodiments, the bridge structure 408 can have a "wall-shaped" structure as shown in FIG. 1B or a stair-shaped structure as shown in FIG. 2B. The bridge structure 408 can be formed with the stair 406 by the same etching process or by a different etching process. In some embodiments, the formation of the bridge structure 408 includes a photolithography process followed by a suitable etching process, such as dry etching and / or wet etching. A stair structure having the stair 406 and the bridge structure 408 can be formed.

[0059] In some embodiments, the sacrificial layer 429 is exposed at the top surface of each step 414 after the steps 406 are formed. In each step 414, a dielectric layer 426 may be below the sacrificial layer 429. In some embodiments, as shown in FIG. 4A , a protective layer 425 may be formed on the top surface of the step 414 to provide buffering and protection during a subsequent ion implantation process on the step 414 so that the underlying sacrificial layer 429 can have optimized physical properties. The protective layer 425 may cover at least a portion of the step 414 (i.e., the sacrificial layer 429) that is to undergo the ion implantation process. For example, the protective layer 425 may cover at least a landing area (or a possible landing area) of the step 414 (e.g., the sacrificial layer 429). The protective layer 425 may include any suitable material having a suitable thickness along the z-direction and may be formed using any suitable method. In some embodiments, the protective layer 425 includes a layer of a dielectric material. In some embodiments, the protective layer 425 includes a portion of the second dielectric material layer (e.g., silicon oxide) that is not completely etched away during the formation of the step 414. That is, at least a portion of the second dielectric material layer directly above the first dielectric material layer in the step 406 may be retained during the etching of the material stack. In some embodiments, the etching time for forming the step 414 is controlled to ensure that the protective layer 425 has a desired thickness. In some embodiments, the protective layer 425 may also be formed by a suitable deposition process, such as CVD, ALD, and / or PVD, alone or in conjunction with a controlled etch, to deposit a layer of dielectric material, such as silicon oxide, over the step 414 (i.e., the sacrificial layer 429).

[0060] 5A shows a close-up view 500 of the steps 414 before the ion implantation process. As shown in FIG. 5A, in some embodiments, the sacrificial layer 429 in each step 414 may be covered by a protective layer 425 that includes the entire layer of second dielectric material immediately above the sacrificial layer 429. In some embodiments, before the ion implantation process, the steps 414 include the protective layer 425 and the underlying sacrificial layer 429. A dielectric layer 426 may be below each sacrificial layer 429 and may be in contact with the protective layer 425 of the step 414 immediately below.

[0061] 6, the method 600 proceeds to operation 604 where an ion implantation process is performed to form a sacrificial layer on the top surface of each step. Figure 4B shows the corresponding structure.

[0062] As shown in FIG. 4B , an ion implantation process may be performed to form a sacrificial portion 419 on the top surface of at least one step 414. In some embodiments, multiple sacrificial portions 419 are formed on each step 414. The sacrificial portion 419 may cover at least the landing area of ​​each step 414. In some embodiments, the sacrificial portion 419 covers the entire width d of each step 414 (e.g., along the x direction, referring back to FIG. 3A ). The sacrificial portion 419 may be cut at the edge of the immediately upper step 414 so that the sacrificial portion 419 does not extend below the upper step 414 along the x direction. In various embodiments, the sacrificial portion 419 having the length D may or may not cover the entire length of each step 414 (e.g., along the y direction, referring back to FIG. 3B ). The sacrificial portion 419 may or may not be cut at the boundary between the bridge structure 408 and the staircase 406, depending on the ion implantation process. Along the z direction, the thickness of the sacrificial portion 419 may be less than or equal to the thickness of the sacrificial layer 429. In some embodiments, the thickness of the sacrificial portion 419 is equal to the thickness of the sacrificial layer 429 .

[0063] The ion implantation may alter the physical properties of the treated portion of the sacrificial layer 429 (i.e., the sacrificial portion 419). In some embodiments, the sacrificial portion 419 may be irradiated with ions to have higher porosity so that, in a subsequent gate exchange process, an etchant for removing the sacrificial layer 429 may have a higher etching rate on the sacrificial portion 419 above the sacrificial layer 429. That is, the etchant for removing the sacrificial layer 429 may selectively etch the sacrificial portion 419 above the sacrificial layer 429. In some embodiments, the sacrificial portion 419 has a lower density than the sacrificial layer 429, making it easier to etch. In some embodiments, the ratio between the etching rate on the sacrificial portion 419 and the etching rate on the sacrificial layer 429 may be about 3:1. In various embodiments, the ion implantation process employs a tilted ion implantation process using suitable ions at any suitable energy. In some embodiments, the tilted ion implantation process may also implant ions into the bridge structure 408. In some embodiments, the ions include boron (B) ions. Optionally, a heat treatment, such as an annealing process, can be performed after the ion implantation.

[0064] In some embodiments, portions of the sacrificial layer 429 (referring back to FIG. 4A ) underlying the upper step 414 that do not experience the ion implantation process may form a dielectric portion within each step 414. The dielectric portion may contact the sacrificial portion 419 at the edge of the step 414 immediately above. In some embodiments, if the thickness of the sacrificial portion 419 is less than the thickness of the sacrificial layer 429, an initial other dielectric portion (not shown) is formed below the sacrificial portion 419. The initial other dielectric portion may be formed by portions of the sacrificial layer 429 underlying the sacrificial portion 419 that do not experience the ion implantation process. In some embodiments, the width of the initial other dielectric portion along the x direction is the same as the respective sacrificial portion 419, and the width of the initial other dielectric portion along the z direction is less than the width of the respective dielectric portion (or sacrificial layer 429). In some embodiments, the length of the initial other dielectric portion along the y direction may be equal to the length of the conductor portion 420 (e.g., length D). In some embodiments, along the z-direction, each step 414 includes a sacrificial portion 419 and at least an underlying dielectric layer 426 (and other earlier dielectric portions, if formed). Furthermore, except for the bottom step 414, each step 414 may rest on one or more pairs of dielectric portion and dielectric layer 426 of the lower step 414.

[0065] Optionally, the sacrificial portions 419 may not completely cover the steps 414 along the y-direction, and the second dielectric portions 423 may be formed from portions of the sacrificial layer 429 outside of the portions that experienced the ion implantation process. In some embodiments, the width of the second dielectric portions 423 along the x-direction may be less than, equal to, or greater than the width (e.g., width d) of the respective steps 414. In some embodiments, the thickness of the second dielectric portions 423 along the z-direction may be less than or equal to the thickness of the respective sacrificial layers 429.

[0066] FIG. 5B shows an enlarged view 502 of the steps 414 after the ion implantation process. As shown in FIG. 5B, a sacrificial portion 419 may be formed in each step 414 below a respective protective layer 425. The sacrificial portions 419 of adjacent steps 414 do not overlap along any direction. Optionally, the protective layer 425 may be removed after the ion implantation process to expose the underlying sacrificial portions 419. In some embodiments, a suitable etching process, such as dry etching and / or wet etching, is performed to remove the protective layer 425. In this manner, the dielectric layer 426 of each step 414 may be cut at the edges of the respective step 414. In some embodiments, the protective layer 425 is retained.

[0067] 6, the method 600 proceeds to operation 606 where a plurality of lateral recesses are formed in the bridge structure, with a lateral recess portion formed from each sacrificial portion. Figure 4C shows the corresponding structure.

[0068] As shown in FIG. 4C , multiple lateral recesses 428 may be formed in the bridge structure 408, and lateral recess portions 418 may be formed from respective sacrificial portions 419. In some embodiments, a GLS (e.g., a slit structure, see back to GLS 310 in FIG. 3C ) may be formed in contact with the bridge structure 408 before forming the lateral recesses 428 and lateral recess portions 418. The GLS may extend into the staircase structure in the xz plane, exposing the substrate 402 and the sacrificial / dielectric pair (439 / 436) in the bridge structure 408. An etching process employing a suitable etchant, such as phosphoric acid, may be used to remove the sacrificial layer 439 and sacrificial portions 419 through the GLS. In some embodiments, the etching process includes an isotropic etching process, such as a wet etch. The etchant removes all sacrificial layer 439 and sacrificial portions 419 exposed on the sidewalls of the GLS in the same etching process, e.g., simultaneously. The dielectric layer 436 may be retained. Lateral recess 428 may be formed from the removal of sacrificial layer 439 and lateral recess portion 418 may be formed from the removal of sacrificial portion 419 .

[0069] In some embodiments, if protective layer 425 is removed before the etching process, each lateral recess 418 is exposed above the top surface of each step 414. In some embodiments, if protective layer 425 is retained, lateral recess 418 is formed below each protective layer 425. In some embodiments, lateral recess 418 is in laterally (along the negative y-direction) contact with second dielectric portion 423. In some embodiments, lateral recess 418 is in contact with underlying dielectric layer 426.

[0070] In some embodiments, the etchant has a higher etch rate on the sacrificial portion 419 than on the sacrificial layer 439. The ratio of the etch rate on the sacrificial portion 419 to the sacrificial layer 439 can be in a range of about 5:1 to about 2:1. In some embodiments, the ratio is about 3:1. Because the etchant approaches the steps 406 from the GLS, portions of the dielectric portion can be over-etched as a result of the higher etch rate on the sacrificial portion 419. The over-etched portions of the dielectric portion can overlap the step 414 directly above, corresponding to overlapping portions of the conductor portion to be formed later (e.g., see back to overlapping portion 320-2 in FIG. 3D ). The over-etched portions can be part of the lateral recesses 418. In some embodiments, the etch time is controlled to retain at least one desired portion (e.g., a desired length along the y-direction) of the dielectric material beneath each lateral recess 418. The reserved dielectric material beneath the lateral recesses 418 may form respective dielectric structures (see back to FIG. 3A) beneath the landing areas upon which respective wordline VIA contacts are to be formed.

[0071] In some embodiments, a portion of the step 406 below the sacrificial portion 419 may be removed during the etching process. As shown in FIG. 4C , the removed portion of the step 406 may include a portion of the dielectric portion and a portion of the dielectric layer 426 below the sacrificial portion 419 (e.g., the lower step 414). In some embodiments, the removed portion of the step 406 may nominally have a length L along the y-direction and the same length as the sacrificial layer 429 along the x-direction. In some embodiments, if the thickness of the sacrificial portion 419 is less than the thickness of the sacrificial layer 429 along the z-direction, the etchant also removes a portion of each of the initial other dielectric portions, forming respective other dielectric portions below and in contact with the lateral recesses 418.

[0072] In some embodiments, insulating structure 450 is formed on the staircase structure prior to the etching process, such that at least staircase 406 is within insulating structure 450. Isolation structure 450 may comprise a suitable dielectric material and is deposited by any suitable deposition method, such as CVD, ALD, and / or PVD. In some embodiments, insulating structure 450 comprises silicon oxide and is deposited by CVD. In some embodiments, if protective layer 425 is removed before insulating structure 450 is formed, a dielectric material may be deposited in contact with sacrificial portion 419 to form insulating structure 450. In some embodiments, if protective layer 425 is retained, the deposited dielectric material may accumulate on protective layer 425. As a result, insulating structure 450 may include protective layer 425 and a dielectric material deposited on protective layer 425. Note that insulating structure 450 may be formed at any suitable time after staircase 406 is formed and before wordline via contacts are formed. The specific timing for forming insulating structure 450 should not be limited by the embodiments of the present disclosure.

[0073] 6, the method 600 proceeds to operation 608 where multiple conductor layers are formed in the lateral recesses and conductor portions are formed in each lateral recess portion. Figure 4D shows the corresponding structure.

[0074] As shown in FIG. 4C , multiple conductor layers 430 may be formed within the bridge structure 408, and a conductor portion 420 may be formed within each step 414 within the staircase 406. In some embodiments, a suitable deposition process, such as ALD, CVD, and / or PVD, is performed to deposit a suitable conductor material to fill the lateral recesses 428 and 418 within the same process. The conductor material may fill the lateral recesses 428 and 418 from the GLS. The over-etched portion of each lateral recess 418 may be filled with a conductive material to form an overlapping portion of the conductor portion 420 below the step 414 immediately above. Other portions of the lateral recesses 418 may be filled with a conductive material to form a non-overlapping portion and another overlapping portion (e.g., see back to FIG. 3D for non-overlapping portion 320-1 and overlapping portion 320-3, respectively), both above the top surface of each step 414. In some embodiments, the conductive material may also fill the removed portion of the step 406 below the sacrificial portion 419 (or conductive portion 420), forming a connecting structure 421 (see back to FIG. 3C). The conductive material may include tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.

[0075] 6, the method 600 proceeds to operation 610 where wordline VIA contacts are formed in contact with the respective conductor portions. Figure 4E shows the corresponding structure.

[0076] As shown in FIG. 4E , word line via contacts 416 are formed in insulating structure 450 and contact the respective conductor portions 420. In some embodiments, word line via contacts 416 are formed on the non-overlapping portions of the respective conductor portions 420. The word line via contacts 416 can be formed by patterning insulating structure 450 to form openings that expose the conductor portions 420 and depositing a suitable conductive material to fill the openings. In some embodiments, patterning insulating structure 450 includes a suitable etching process, such as a photolithography process followed by dry etching and / or wet etching. The conductive material can include tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, after conductor layer 430 and conductor portions 420 are formed, an ACS is formed in the GLS.

[0077] An embodiment of the present disclosure provides a 3D memory device. The 3D memory device includes a memory array structure and a staircase structure. The staircase structure is located in the middle of the memory array structure and divides the memory array structure into a first memory array structure and a second memory array structure along a horizontal direction. The staircase structure includes multiple steps extending along the horizontal direction and a bridge structure in contact with the first memory array structure and the second memory array structure. The multiple steps include one step on top of one or more dielectric pairs. The step includes a conductor portion located on an upper surface of the step and in contact with the bridge structure for electrical connection, and a dielectric portion at the same level and in contact with the conductor portion. The step is electrically connected to at least one of the first memory array structure and the second memory array structure via the bridge structure. The width of the conductor portion decreases as the distance from the bridge structure increases along a second horizontal direction perpendicular to the horizontal direction.

[0078] In some embodiments, a portion of the conductor portion overlaps the upper step.

[0079] In some embodiments, the lateral dimension of some of the conductor portions decreases along the second lateral direction.

[0080] In some embodiments, a portion of the conductor portion has a side profile of a right triangle.

[0081] In some embodiments, the step further comprises a dielectric layer below the conductor portion and the dielectric portion.

[0082] In some embodiments, the conductor portion and the dielectric layer each overlie one or more dielectric pairs.

[0083] In some embodiments, the width of another portion of the conductor along the lateral direction is equal to the dimension of the step.

[0084] In some embodiments, along the second lateral direction, the length of the conductor portion is less than or equal to the second dimension of the step.

[0085] In some embodiments, the thickness of the conductor portion is less than or equal to the thickness of the dielectric portion along the vertical direction.

[0086] In some embodiments, the conductor portion comprises at least one of tungsten, cobalt, copper, aluminum, silicide, and polysilicon. In some embodiments, the dielectric portion comprises silicon nitride. In some embodiments, the dielectric layer comprises silicon oxide.

[0087] In some embodiments, the bridge structure includes a plurality of interleaved conductor layers each in contact with the first and second memory array structures, hi some embodiments, the conductor portions contact and are electrically connected to respective conductor layers at the same level.

[0088] In some embodiments, each of the one or more dielectric pairs includes a dielectric portion and a dielectric layer corresponding to a lower step.

[0089] An embodiment of the present disclosure provides a 3D memory device. The 3D memory device includes a memory array structure and a landing structure in contact with the memory array structure. The landing structure includes a plurality of landing regions at respective depths, each extending along a lateral direction, and a bridge structure in contact with the memory array structure. Each of the plurality of landing regions includes a conductor portion on a respective upper surface and a dielectric portion at the same level and in contact with the conductor portion. The conductor portion is electrically connected to the memory array structure via the bridge structure. The width of the conductor portion decreases as it moves away from the bridge structure along a second lateral direction perpendicular to the lateral direction. Each of the plurality of landing regions overlies one or more dielectric pairs.

[0090] In some embodiments, a portion of the conductor portion overlaps with the upper landing area.

[0091] In some embodiments, the lateral dimension of some of the conductor portions decreases along the second lateral direction.

[0092] In some embodiments, a portion of the conductor portion has a side profile of a right triangle.

[0093] In some embodiments, the plurality of landing regions further comprises a dielectric layer below the conductor portion and the dielectric portion.

[0094] In some embodiments, the conductor portion and the dielectric layer each overlie one or more dielectric pairs.

[0095] In some embodiments, along the lateral direction, the width of another portion of the conductor is equal to the dimension of the respective landing area.

[0096] In some embodiments, along the second lateral direction, the length of the conductor portion is less than or equal to the second dimension of each landing area.

[0097] In some embodiments, the landing structure includes a plurality of laterally extending steps, hi some embodiments, each of the plurality of landing areas is above an upper surface of a respective step.

[0098] In some embodiments, the thickness of the conductor portion is less than or equal to the thickness of the dielectric portion along the vertical direction.

[0099] In some embodiments, the conductor portion comprises at least one of tungsten, cobalt, copper, aluminum, silicide, and polysilicon. In some embodiments, the dielectric portion comprises silicon nitride. In some embodiments, the dielectric layer comprises silicon oxide.

[0100] In some embodiments, the bridge structure includes a plurality of interleaved conductor layers, each in contact with a memory array structure, and in some embodiments, the conductor portions contact and are electrically connected to respective ones of the second conductors at the same level.

[0101] In some embodiments, each of the one or more dielectric pairs includes a dielectric portion and a dielectric layer corresponding to an underlying landing region.

[0102] An embodiment of the present disclosure provides a 3D memory device. The 3D memory device includes a memory array structure and a staircase structure. The staircase structure includes a plurality of steps extending along a lateral direction. The plurality of steps includes steps each having a conductor portion on an upper surface of the step and a dielectric portion at the same level and in contact with the conductor portion. The conductor portion is electrically connected to the memory array structure. The width of the conductor portion varies along a second lateral direction perpendicular to the lateral direction.

[0103] In some embodiments, a portion of the conductor portion overlaps the upper step.

[0104] In some embodiments, the lateral dimension of some of the conductor portions decreases along the second lateral direction.

[0105] In some embodiments, a portion of the conductor portion has a side profile of a right triangle.

[0106] In some embodiments, the staircase structure further comprises a dielectric layer below the conductor portion and the dielectric portion.

[0107] In some embodiments, the conductor portion and the dielectric layer each overlie one or more dielectric pairs.

[0108] In some embodiments, the width of another portion of the conductor along the lateral direction is equal to the dimension of the step.

[0109] In some embodiments, along the second lateral direction, the length of the conductor portion is less than or equal to the second dimension of the step.

[0110] In some embodiments, the thickness of the conductor portion is less than or equal to the thickness of the dielectric portion along the vertical direction.

[0111] In some embodiments, the conductor portion comprises at least one of tungsten, cobalt, copper, aluminum, silicide, and polysilicon. In some embodiments, the dielectric portion comprises silicon nitride. In some embodiments, the dielectric layer comprises silicon oxide.

[0112] In some embodiments, the 3D memory device further includes a bridge structure in contact with the staircase structure and the memory array structure. The bridge structure includes a plurality of interleaved conductor layers, each in contact with the memory array structure. The conductor portions are in contact with and electrically connected to one of the conductor layers at the same level. The staircase structure is electrically connected to the memory array structure via the bridge structure.

[0113] In some embodiments, each of the one or more dielectric pairs includes a dielectric portion and a dielectric layer corresponding to a lower step.

[0114] An embodiment of the present disclosure provides a method for forming a staircase structure for a 3D memory device. The method includes the following operations: First, a plurality of steps are formed, the plurality of steps having a plurality of first sacrificial layers and a plurality of first dielectric layers interleaved therein; A bridge structure is formed in contact with the plurality of steps, the bridge structure having a plurality of second sacrificial layers and a plurality of second dielectric layers interleaved therein; Each first sacrificial layer is in contact with a respective second sacrificial layer at the same level, and each first dielectric layer is in contact with a respective second dielectric layer at the same level; A sacrificial portion is formed in the first sacrificial layer corresponding to at least one of the steps; The sacrificial portion is on an upper surface of each step and is cut at an edge of the upper step; The second sacrificial layer and the sacrificial portion are removed by the same etching process to form a plurality of lateral recesses and one lateral recess portion, respectively; A plurality of conductor layers are formed in the lateral recesses, and a conductor portion is formed in the lateral recess portion and contacts a respective one of the conductor layers.

[0115] In some embodiments, the method further comprises forming a dielectric portion in each first sacrificial layer, the sacrificial portion contacting and at the same level as the sacrificial layer.

[0116] In some embodiments, the etching process has an etch rate above the sacrificial portion that is higher than an etch rate above the second sacrificial layer.

[0117] In some embodiments, the ratio of the etch rate on the sacrificial portion to the etch rate on the second sacrificial layer is about 3:1.

[0118] In some embodiments, forming the lateral recess further comprises removing a portion of the dielectric portion below the upper step by an etching process.

[0119] In some embodiments, forming the sacrificial portion includes performing an ion implantation process on exposed portions of the first sacrificial layer of at least one of the steps to change an etching rate of the exposed portions of the first sacrificial layer in the etching process.

[0120] In some embodiments, the ion implantation process includes an angled ion implantation process using boron (B).

[0121] In some embodiments, the method further includes forming a protective layer over the first sacrificial layer prior to the ion implantation process.

[0122] In some embodiments, the method further comprises removing the protective layer after the ion implantation process.

[0123] In some embodiments, the method further includes reserving a portion of the first sacrificial layer and the first dielectric layer corresponding to the lower step below the sacrificial portion.

[0124] In some embodiments, the method further includes removing another portion of the first sacrificial layer and the first dielectric layer below the sacrificial portion by an etching process.

[0125] In some embodiments, the method further includes forming a slit structure in the staircase structure, and removing the plurality of second sacrificial layers and the sacrificial portion through the slit structure.

[0126] In some embodiments, forming the plurality of conductors and conductor portions includes depositing a conductor material to fill the lateral recesses and lateral recess portions.

[0127] In some embodiments, the method further comprises forming a contact on the conductor portion.

[0128] The above description of specific embodiments discloses the general nature of the present disclosure such that others may readily modify and / or adapt such specific embodiments to various applications by applying the knowledge of those skilled in the art without undue experimentation and without departing from the general concepts of the present disclosure. Such adaptations and modifications are therefore intended to be within the meaning and range of equivalents of the embodiments of the present disclosure, based on the teaching and guidance presented herein. It will be understood that the phraseology or terminology herein is intended to be descriptive rather than limiting, as interpreted by those skilled in the art in light of the teaching and guidance.

[0129] The embodiments of the present disclosure have been described above using functional components that illustrate implementation forms of specific functions and relationships thereof. The boundaries of these functional components have been arbitrarily defined herein for the convenience of description. Alternative boundaries may be defined as long as the specific functions and relationships thereof are appropriately performed.

[0130] The Summary and Abstract sections may describe one or more, but not all, of the exemplary embodiments of the present disclosure contemplated by the inventors, and thus are not intended to be limiting of the scope of the disclosure and appended claims in any way.

[0131] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0132] 100 Three-dimensional (3D) memory devices 101 Substrate 102 Staircase structure 104-1 First Memory Array Structure 104-2 Second Memory Array Structure 106 Stairs 108 Bridge Structure 110 Gate line slit (GLS) 112 Memory String 114 steps 116 word line vertical interconnect access (VIA) contacts 120 Memory Finger 200 3D memory devices 202-1 Stair structure 202-2 Stair structure 204 Memory Array Structure 206 Stairs 208 Bridge Structure 210 GLS 212 Memory String 214 steps 216 word line via contact 220 Memory Finger 302 Substrate 306 Stairs 308 Bridge Structure 310 GLS 314 steps 316 word line via contact 320 Conductor 320-1 Non-overlapping part 320-2 Overlapping section 320-3 Overlapping section 321 Connection Structure 323 Second Dielectric Section 324 Dielectric section 326 Dielectric Layer 330 Conductor layer 336 Dielectric Layer 340 Dielectric Structure 350 Insulation Structure 402 board 406 Stairs 408 Bridge Structure 414 steps 418 Horizontal recess 419 Sacrificial Section 420 Conductor 421 Connection Structure 423 Second Dielectric Section 425 Protective layer 426 Dielectric Layer 428 Horizontal recess 429 Sacrificial Layer 430 Conductor layer 436 Dielectric Layer 439 Sacrificial Layer 450 Insulation Structure Enlarged view of 500 steps 414 502 Enlarged view of step 414

Claims

1. a memory array structure; a staircase structure including a plurality of steps extending along a first lateral direction, one of the steps including a conductor portion on an upper surface of the step, the conductor portion being connected to the memory array structure; the width of the conductor portion varies in a second lateral direction perpendicular to the first lateral direction; A three-dimensional (3D) memory device, wherein the step further includes a dielectric portion at the same level and in direct contact with an end of the conductor portion and a sidewall of the conductor portion along the second lateral direction.

2. 10. The 3D memory device of claim 1, wherein a thickness of the conductor portion is equal to or less than a thickness of the dielectric portion along a vertical direction.

3. The 3D memory device of claim 1 , wherein the step further comprises a dielectric layer below the conductor portion and the dielectric portion.

4. The 3D memory device of claim 3 , wherein the thickness of the dielectric layer is less than the thickness of the dielectric portion.

5. 4. The 3D memory device of claim 3, wherein the conductor portion and the dielectric layer each overlie one or more dielectric pairs.

6. The 3D memory device of claim 1 , wherein a portion of the conductor overlaps an upper step.

7. The 3D memory device of claim 6 , wherein the portion of the conductor portion has a side profile of a right triangle.

8. the conductor portion includes at least one of tungsten, cobalt, copper, aluminum, silicide, or polysilicon; The 3D memory device of claim 1 , wherein the dielectric portion comprises silicon nitride.

9. 2. The 3D memory device of claim 1, wherein the memory array structure further comprises a first memory array structure and a second memory array structure, each including a plurality of memory cells, disposed on one side of the staircase structure along the second lateral direction.

10. further comprising a bridge structure contacting the first memory array structure and the second memory array structure; 10. The 3D memory device of claim 9, wherein the conductor portion is connected to the first memory array structure and the second memory array structure via the bridge structure.

11. 11. The 3D memory device of claim 10, wherein the conductor portion is connected via the bridge structure to a first word line portion of the first memory array structure and a second word line portion at the same level as the first word line portion of the second memory array structure.

12. 12. The 3D memory device of claim 11, wherein the bridge structure includes a plurality of conductor layers, each of the conductor layers contacting the first word line portion and the second word line portion.

13. a memory array structure; a staircase structure including a plurality of steps extending along a first lateral direction, one of the steps including a conductor portion on an upper surface of the step, the conductor portion being connected to the memory array structure; the width of the conductor portion varies in a second lateral direction perpendicular to the first lateral direction; In the second lateral direction, the conductor portion extends to physically and electrically connect to a conductor layer of the memory array structure at the same level as the conductor portion.

14. The 3D memory device of claim 13 , wherein the staircase structure includes a dielectric portion at the same level and in contact with the conductor portion.

15. The 3D memory device of claim 14 , wherein the staircase structure further comprises a dielectric layer below the conductor portion and the dielectric portion.

16. 16. The 3D memory device of claim 15, wherein the thickness of the dielectric layer is less than the thickness of the dielectric portion.

17. 16. The 3D memory device of claim 15, wherein the conductor portion and the dielectric layer each overlie one or more dielectric pairs.

18. the conductor portion includes at least one of tungsten, cobalt, copper, aluminum, silicide, or polysilicon; The 3D memory device of claim 14 , wherein the dielectric portion comprises silicon nitride.

19. The 3D memory device of claim 13 , wherein a portion of the conductor overlaps an upper step.

20. 20. The 3D memory device of claim 19, wherein the portion of the conductor portion has a side profile of a right triangle.

Images