Semiconductor device

Abstract

To provide a semiconductor device to reduce time for rewriting data in memory cells.SOLUTION: A memory module 10 includes a first memory cell MC[1], a second memory cell MC[2], a selection transistor DTr, and a wiring WBL1. Each memory cell has a memory node electrically connected to either a source or a drain of a transistor WTr, a gate of a transistor RTr, and one of electrodes of a capacitive element CS. One side of the first memory cell is electrically connected to the wiring via the selection transistor, the other side of the first memory cell is electrically connected to one side of the second memory cell, and the other side of the second memory cells is electrically connected to the wiring WBL1. The memory node of the first memory cell is rewritten by a signal applied to the wiring via the selection transistor when the selection transistor is in an on state, and is rewritten by a signal applied to the wiring via the memory node of the second memory cell when it is in an off state.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to a product, a method, or a manufacturing method. , machine, manufacture, or composition of matter In particular, one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, The present invention relates to a method for driving these devices or a method for manufacturing these devices.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. It refers to a semiconductor element, circuit, or device, etc. Examples include a transistor, a diode, and other semiconductor elements. In another example, a circuit having a semiconductor element is a semiconductor device. As another example, a device including a circuit having a semiconductor element is a semiconductor device. do. [Background technology]

[0004] Mobile devices such as smartphones, tablets, e-books, and personal computers Electronic devices having semiconductor devices such as servers are required to handle large amounts of data. Therefore, semiconductor devices are required to have large storage capacities and high processing speeds. It is being done.

[0005] In particular, in recent years, the electronic devices mentioned above have become increasingly equipped with applications that handle high-definition images, videos, audio, etc. As the number of applications increases, the amount of data handled is also increasing. Patent Document 1 discloses a semiconductor device in which memory cells are stacked three-dimensionally. Furthermore, a device with a large memory capacity without changing the size of the semiconductor device chip is disclosed. To realize semiconductor devices with high capacity, technology to miniaturize the circuits of semiconductor devices is required. It is being done. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-258458 Summary of the Invention [Problem to be solved by the invention]

[0007] Applications running on electronic devices may be connected to the Internet or a network. It is required to handle large amounts of data such as images and audio comfortably by using In electronic devices characterized by portability, such as mobile devices, the battery In electronic devices, power gating and other power saving techniques are being used to reduce power consumption. However, power reduction techniques such as power gating can be used. To do this, there is a problem that requires the evacuation of data in use.

[0008] For example, in a NAND flash memory, which is known as a semiconductor device, data In order to rewrite, it is necessary to update data other than the specified address. Therefore, in NAND flash memory, etc., the processing time required to write a large amount of data is Furthermore, there is a problem that power consumption increases according to the amount of data.

[0009] In view of the above problems, one object of one embodiment of the present invention is to provide a storage device with a novel configuration. Another embodiment of the present invention is to provide a memory device with a reduced rewrite time. Another object of one embodiment of the present invention is to provide a memory device with reduced power consumption. This is one of the challenges.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc.

[0011] Note that the problems of one embodiment of the present invention are not limited to the above-listed problems. This does not preclude the existence of other problems. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by understanding the specification or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least the above-listed and / or other objects. It solves one problem. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device having a memory module, has a first memory cell, a second memory cell, a selection transistor, and a first wiring, The first memory cell has a first memory node and the second memory cell has a second memory node. One of the first memory cells is electrically connected to the first wiring via a selection transistor. the other of the first memory cell is electrically connected to one of the second memory cells; The other of the second memory cells is electrically connected to the first wiring, and is connected to the first memory node and The memory node 2 has the function of holding a voltage as a signal, and when the selection transistor is in the on state, In this state, the first memory node receives a signal given to the first wiring via the selection transistor. The second memory node has a function of being rewritten by a signal, and the second memory node has a selection transistor, and A function that can be rewritten by a signal applied to the first wiring via the first memory node When the select transistor is in an off state, the first memory node is connected to the second memory node. The second memory has a function of being rewritten by a signal given to the first wiring through the The memory node has a function of being rewritten by a signal given to the first wiring. The semiconductor device is characterized by the above.

[0013] In the above configuration, the memory module further includes a second wiring, a third wiring, and a fourth wiring. The first memory cell further includes a first transistor and a first capacitance element. , and the second memory cell further includes a second transistor and a second capacitor element. the first memory node is connected to one of the source and drain of the first transistor and the first The second memory node is formed by electrically connecting one of the electrodes of the capacitor element to the first memory node. , one of the source and drain of the second transistor and one of the electrodes of the second capacitor element The source or drain of the select transistor is electrically connected to the The other of the source and the drain of the selection transistor is electrically connected to the first wiring. The gate of the select transistor is electrically connected to the fourth wiring. and the other of the source and drain of the first transistor is connected to a second memory node. The gate of the first transistor is electrically connected to the second wiring, and the gate of the second transistor is electrically connected to the second wiring. The other of the source and the drain of the second transistor is electrically connected to the first wiring. a gate of the transistor electrically connected to a third wiring; Positioning is preferred.

[0014] In the above configuration, the memory module further has a fifth wiring, One of the terminals is electrically connected to the fifth wiring via the selection transistor. When the select transistor is in an on state, the first memory node is connected to the fifth wiring via the select transistor. The second memory node has a function of being rewritten by a signal obtained from the first wiring. A semiconductor device having a function of being rewritten by a given signal is preferred. It's nice.

[0015] In the above configuration, the first transistor, the second transistor, or the selection transistor In particular, a semiconductor device having a metal oxide in the semiconductor layer is preferred.

[0016] In the above structure, the semiconductor layer of the first transistor is A semiconductor device characterized in that it is formed in the same opening as the semiconductor device described above is preferred.

[0017] In the above structure, the transistor having a metal oxide in a semiconductor layer has a back gate A semiconductor device having the following is preferred.

[0018] An electronic device having the above-described semiconductor device and a housing is preferred. [Effects of the Invention]

[0019] One embodiment of the present invention can provide a storage device with a novel structure. According to one aspect of the present invention, a storage device with a reduced rewrite time can be provided. An aspect can provide a storage device that consumes less power.

[0020] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to a person skilled in the art from the description or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention has at least the above-listed effects and / or other effects. Therefore, one aspect of the present invention is to provide the above-mentioned series of In some cases, the effects may not be as expected. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 2] FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 3] 1 is a timing chart showing an example of the operation of a semiconductor device. [Figure 4] 1 is a timing chart showing an example of the operation of a semiconductor device. [Figure 5] 1 is a timing chart showing an example of the operation of a semiconductor device. [Figure 6] FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 7] 1 is a timing chart showing an example of the operation of a semiconductor device. [Figure 8] 1 is a timing chart showing an example of the operation of a semiconductor device. [Figure 9] FIG. 1 is a block diagram illustrating an example of a storage device. [Figure 10] FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 11] FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 12] FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating a structural example of a semiconductor device. [Figure 14] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 15] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 17] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 18] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 19] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 20] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 21] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 22] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 23] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 24] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 25] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 26] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 27] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 28] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 29] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 30] FIG. 2 is a diagram for explaining the range of atomic ratios of metal oxides. [Figure 31] Block diagram explaining a CPU. [Figure 32] FIG. 1 is a perspective view showing an example of an electronic device. [Figure 33] FIG. 1 is a perspective view showing an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0022] (Embodiment 1) In this embodiment, a semiconductor device for shortening the rewrite time of a memory cell will be described with reference to FIGS. This will be explained using Figure 7.

[0023] First, the circuit configuration of the semiconductor device will be described with reference to FIG. The semiconductor device shown in FIG. 1 is a memory module 10 having n memory cells. The module 10 includes memory cells MC[1] to MC[n], a selection transistor DTr, and a Line WWL_D, wiring WWL[1] to WWL[n], wiring RWL[1] to RWL[n] , wiring WBL1, wiring RBL1, and wiring RBL2. WL[1] to WWL[n]) function as rewrite word lines, and wiring RWL (wiring RW L[1] to RWL[n]) function as read word lines, and the wiring WBL1 functions as a rewrite The wiring RBL1 and the wiring RBL2 function as read bit lines. n is an integer of 2 or greater.

[0024] FIG. 1A shows an example in which memory cells MC[1] to MC[n] are connected in series. At one end of the serially connected memory cells MC[1] to MC[n], It is preferable that a selection transistor DTr is connected. 1 shows an example in which a transistor DTr is connected to a memory cell MC[1].

[0025] Each memory cell includes a transistor WTr, a transistor RTr, a capacitance element CS, The transistor WTr functions as a write transistor. The transistor RTr functions as a readout transistor.

[0026] The memory node is connected to one of the source and drain of the transistor WTr and the transistor R It is formed by electrically connecting the gate of Tr and one of the electrodes of the capacitance element CS. The gate of the transistor WTr is electrically connected to the wiring WWL, and the voltage of the capacitance element CS is The other pole is electrically connected to the wiring RWL. The other of the source and drain of the transistor WTr is connected in series with the memory cell MC[1]. It is electrically connected to the memory node of the memory cell MC[2].

[0027] One of the source and drain of the selection transistor DTr is electrically connected to the wiring WBL1. The other of the source and drain of the selection transistor DTr is connected to the The gate of the select transistor DTr is electrically connected to the memory node. In addition, the transistor WTr of the memory cell MC[n] is electrically connected to The other of the source and drain is electrically connected to the wiring WBL1. One end of the connected series of memory cells is connected to the select transistor DTr via the wiring WBL1. It is electrically connected to the other end of the series of memory cells.

[0028] One of the source and drain of the transistor RTr in the memory cell MC[1] is The line RBL2 is electrically connected to the source of the transistor RTr of the memory cell MC[1]. The other of the source and drain is connected to the transistor of the memory cell MC[2] connected in series. The memory cell MC The other of the source and drain of the transistor RTr included in [n] is electrically connected to the wiring RBL1. That is, the wiring RBL1 is connected to the transistors of the memory cells connected in series. It is electrically connected to the wiring RBL2 via the transistor RTr.

[0029] In the configuration of the memory module 10 described above, memory cells MC[1] to MC[2] To rewrite the data of any one of the memory cells MC[n], It can be rewritten via the transistor WTr and the memory node. To rewrite the data in the memory cell MC[j] close to the memory cell MC[1], It is preferable that data is given from the wiring WBL1 via the transistor DTr. To rewrite the data in the memory cell MC[j] close to the memory cell MC[n], It is preferable that data is given from the wiring WBL1 connected to C[n]. It is an integer up to and including n.

[0030] For a memory module 10 having a circuit configuration different from that shown in FIG. 1(A), please refer to FIG. 1(B). The transistor WTr shown in FIG. 1B is a transistor with a small off-state current. The transistor WTr is preferably a transistor with a small off-state current. By using this, it is possible to ensure the independence of data stored in adjacent memory nodes. Furthermore, the transistor WTr may be a transistor having a back gate. By applying a voltage to the gate, the threshold voltage of the transistor WTr can be controlled. Note that the wiring BGL shown in FIG. 1B is connected to each of the memory cells MC[1] to MC[2]. The memory cell MC[n] is electrically connected to the back gate of the transistor WTr. In addition, the selection transistor DTr has a back gate like the transistor WTr. It is preferable that

[0031] Unlike the example shown in FIG. 1B, the wiring BGL is The back gates of the transistors WTr in MC[n] are electrically connected independently. Alternatively, they may be configured to supply different potentials.

[0032] The channel formation region of the transistor WTr is made of a metal oxide material as described in the third embodiment. In particular, indium, element M (as element M, for example, aluminum) In the case of metal oxides selected from one or more of the following: zinc, gallium, yttrium, tin, etc. Since the metal oxide functions as a wide-gap semiconductor, The transistor included in the channel formation region has a characteristic of having a very low off-state current. The transistor WTr that controls data retention has low off-current characteristics. By applying this, data can be retained in the memory cell MC for a long time. This reduces the number of times the stored data is refreshed, thereby reducing power consumption of the semiconductor device. Power consumption can be reduced.

[0033] The channel formation region of the transistor RTr is formed by the field effect mobility of the transistor. It is preferable to use a material with a high conductivity. For example, the channel forming region of the transistor RTr can be Materials included in the region include semiconductors such as metal oxides and silicon, which will be described in the third embodiment. The material may be:

[0034] Regarding the memory module 10 having a circuit configuration different from that shown in FIG. 1(B), please refer to FIG. 1(C). In FIG. 1C, the transistor RTr is further configured as a transistor having a back gate. By applying a voltage to the back gate, the threshold voltage of the transistor RTr can be controlled. The wiring BGL shown in FIG. 1C is a wiring The transistors RTr and W included in the memory cells MC[1] to MC[n] An example in which the transistor is electrically connected to the back gate is shown.

[0035] Metal oxide is used in the channel formation region of transistors RTr and WTr. Thus, the memory module 10 is formed above the transistors formed on the silicon substrate. Therefore, it is possible to provide a semiconductor device with a high information density per unit area. can be done.

[0036] Unlike the example shown in FIG. 1C, the wiring BGL is The back gates of the transistors RTr and WTr of the MC[n] are Alternatively, they may be electrically connected independently and supplied with different potentials. In (A), although not shown, the transistor RTr may have a circuit configuration with a back gate. good.

[0037] The semiconductor device shown in FIG. 2 is configured by using the memory module 10 shown in FIG. 1(C) as one row, and The memory cells are arranged in columns, and the wiring RWL and wiring WWL are shared with the memory cells MC in the same row. In other words, the semiconductor device shown in FIG. The semiconductor device can be expressed two-dimensionally in m columns, and includes memory cells MC[1,1] to MC In FIG. 2, for the sake of simplicity, the depth d is not shown. By providing the memory cell MC[1,1,1], the semiconductor device can be formed into a three-dimensional memory cell MC[ In the second embodiment, the semiconductor device can have a three-dimensional memory cell. Detailed description of an example having memory cells MC[1,1,1] to MC[m,n,d] m, n, or d is an integer of 2 or more.

[0038] The semiconductor device shown in FIG. 2 includes wiring WWL_D, wiring RWL[1] to wiring RWL[n], Wiring WWL[1] to wiring WWL[n], wiring RBL1[1] to wiring RBL1[m], Wiring RBL2[1] to wiring RBL2[m], wiring WBL1[1] to wiring WBL1[m ] and wirings BGL[1] to BGL[m].

[0039] Specifically, the other electrode of the capacitance element CS of the memory cell MC[i,j] (not shown) is The transistor WTr of the memory cell MC[i,j] is electrically connected to the wiring RWL[j]. The gate of the selected One of the source or drain of the transistor DTr[i] and the memory cell MC[i,n] The other of the source and the drain of the transistor WTr is electrically connected to the wiring RB. L1[i] is the source or drain of the transistor RTr of the memory cell MC[i,n]. The wiring RBL2[i] is electrically connected to the other side of the memory cell MC[i,1]. It is electrically connected to either the source or the drain of the transistor RTr. i is 1 or more and m where j is an integer between 1 and n.

[0040] The structure of data stored in the memory module of the semiconductor device shown in FIG. It is preferable to express it in bits, which are the smallest unit. For example, the first row, the second row, n-1 The operation of rewriting data in the 1st and nth rows is explained with reference to the timing chart in Figure 3. Reveal.

[0041] At T11, when “H” is applied to the wiring WWL_D, the select transistor DTr[1 ] to DTr[m] are turned on. Furthermore, "H" is given to the wiring WWL[1]. As a result, the transistors WTr included in the memory cells MC[1,1] to MC[m,1] The wirings WBL1[1] to WBL1[m] are connected to the select transistors DTr[ Data D[2] is transferred to memory cells MC[1,2] through DTr[m]. At this time, the memory cell MC[1,1] can be applied to the memory node MC[1,1]. Data D[2] is also given to the memory nodes up to MC[m,1]. The data D is preferably digital data having a data width of 128 bits. Alternatively, the data D may be analog data. The analog data may be controlled by a voltage. If each bit can have different analog data, the data that can be stored in the semiconductor device The amount of data can be dramatically improved.

[0042] At T12, the wiring WWL[1] is given a low level, and the memory cell MC[1,1] The transistors WTr included in the memory cells MC[m,1] to MC[m,1] are turned off. The memory nodes MC[1,2] to MC[m,2] hold data D[2]. Furthermore, the data D[1] given to the wirings WBL1[1] to WBL1[m] is The memory cells MC[1,1] to MC[m] are connected via the select transistors DTr[1] to DTr[m]. The data in the memory node of MC[m,1] can be rewritten.

[0043] At T13, when “L” is applied to the wiring WWL_D, the select transistor DTr[1 ] to DTr[m] are turned off. , 1] has a memory node that holds data D[1].

[0044] At T14, the wiring WWL[n-1] is given a high level, and the memory cell MC[ The transistors WTr included in the MC[1, n-1] to MC[m, n-1] are turned on. Furthermore, when "H" is applied to the wiring WWL[n], the memory cells MC[1,n] to M The transistors WTr included in the wirings WBL1[1] to WBL1[2] are turned on. The data D[n-1] given to BL1[m] is stored in the memory cells MC[1,n] to MC[ memory cells MC[1,n-1] to MC[m,n-1] via memory nodes MC[1,n-1] to MC[m,n-1] The data in the memory node can be rewritten.

[0045] At T15, the wiring WWL[n-1] is given "L", so that the memory cells MC[1, The transistors WTr included in the transistors MC[m,n-1] to MC[m,n-1] are turned off. The memory nodes of the memory cells MC[1, n-1] to MC[m, n-1] have Furthermore, the wirings WBL1[1] to WBL1[m] hold the data D[n-1]. By providing data D[n] to the memory nodes of memory cells MC[1,n] to MC[m,n], This can be done.

[0046] At T16, the wiring WWL[n] is given a low level, so that the memory cell MC[1,n] The transistors WTr included in the memory cells MC[m,n] to MC[m,n] are turned off. The memory nodes MC[1,n] to MC[m,n] hold data D[n]. can be.

[0047] NAND flash memory is a memory module in which memory cells are connected in series. To update any one memory cell, data in all rows of the memory module is updated. However, in the configuration shown in this embodiment, data can be read from any row of the memory module. Since data can be rewritten, data can be rewritten at high speed.

[0048] In FIG. 4, a plurality of memory modules included in the semiconductor device are arranged in a wiring WWL, a wiring RWL, a wiring The data structure connected by the line WWL_D and stored is as follows for an example with a data width of m columns: As an example, let us write the data on the first, second, third, n-1th, and nth lines. The switching operation will be described with reference to the timing chart of FIG.

[0049] The basic operation is the same as that explained in Figure 3, so the explanation is omitted. As an example, Figure 4 explains how to rewrite the data in the third line. In a memory module having multiple rows, any row to be rewritten is selected by the selected transistor. The memory cell MC in the first row or the memory cell MC in the nth row to which the transistor DTr is connected It is preferable to access from the closest side. Therefore, the number of lines up to the line to be rewritten is By accessing from the other side, the rewriting time can be reduced.

[0050] In FIG. 4, a plurality of memory cells are arranged in m columns. The data to be transmitted is synchronized with the data provided to the wirings WBL1[1] to WBL1[m]. That is, in the configuration shown in this embodiment mode, the semiconductor device can be rewritten at any address. It can be said that it is a memory device with a data width of m bits.

[0051] For the operation of reading the data rewritten in Figure 3, refer to the timing chart in Figure 5. I will explain.

[0052] In T30, the wirings RBL1[1] to RBL1[m] can be initialized to any potential. In addition, the wirings RBL2[1] to RBL2[m] can store arbitrary data in the memory cells. A reference potential is given to confirm that the value is stored. The arbitrary potential to be initialized is It is preferable that the potential is the same as the "L" level of the data or a potential lower than the "L" level of the data.

[0053] In T31, the memory cells MC[1,1] to MC[m, The data stored in the RWL[1] can be read by applying "L" to the wiring RWL[1]. The other wirings RWL[2] to RWL[n] are given "H". are connected in series, any of the memory cells MC[1,1] to MC[m,1] If the data "H" is held in the memory cell M A signal of the reference potential is output to the wiring RBL1 of the target column of C.

[0054] The memory cells MC connected to the wirings RWL[2] to RWL[n] are connected to the wirings R By applying “H” to WL[2] to RWL[n], the capacitance element CS is This allows the gate of the transistor RTr to be in a state where "H" is applied. Therefore, in the series-connected transistors RTr, the transistors other than the one to be read All RTrs are turned on. Therefore, when the data in the memory cell to be read is "L", Therefore, the reference potential applied to the wiring RBL2 cannot be output to the wiring RBL1. When the data of the memory cell to be read is “H”, the reference potential applied to the wiring RBL2 is output to the wiring RBL1. Therefore, the memory cells MC[1,1] to MC[m,1 ] is output to the wirings RBL1[1] to RBL1[m].

[0055] In T32, “L” is applied to the wirings RWL[1] to RWL[n], and the wiring RBL1 [1] to RBL1[m] are initialized to an arbitrary potential. It is preferable that "H" is given to RBL2[m], but "L" may also be given. good.

[0056] In T33, the memory cells MC[1,2] to MC[m, The data stored in the RWL[2] can be read by applying "L" to the RWL[2]. The other wirings RWL[1], RWL[3] to RWL[n] are given "H". , the operation is the same as reading data from the line RWL[1], so the explanation will be omitted.

[0057] The operation of T34 is the same as that of T32, so the explanation will be omitted. The data stored in the memory cell MC connected to WL[n] can be read. Therefore, data is read from the memory cells MC sequentially in the row direction of the memory cells. It is possible.

[0058] A semiconductor device different from that shown in FIG. 2 will be described with reference to FIG. 6. The semiconductor device shown in FIG. 2 in that it has a wiring WBL2. The following description will be given using the memory module 10 as an example.

[0059] The wiring WBL2 is electrically connected to one of the source and drain of the selection transistor DTr. Therefore, the memory module 10 is configured such that the wiring WBL1 and the wiring WBL2 are Data can be rewritten to the memory cells MC from either one or both.

[0060] In other words, by giving "H" to the wire WWL_D, the wire WBL2[1] The data in the memory node of the memory cell MC[1,1] can be rewritten via the register DTr. Also, by giving "H" to the wiring WWL[n], the wiring WBL1[1] becomes The data of the memory node of the memory cell MC[1,n] can be rewritten. By simultaneously applying “H” to the line WWL[1] and the wiring WWL[n], the memory cell MC The data of the memory nodes of [1,1] and memory cell MC[1,n] can be rewritten simultaneously. This can be done.

[0061] Using a method different from that shown in Figure 3, the data in the first, second, n-1th, and nth lines are written. The switching operation will be described with reference to the timing chart of FIG.

[0062] In T41, when “H” is applied to the wiring WWL_D, the select transistor DTr[1 ] to DTr[m] are turned on. And, "H" is given to the wiring WWL[1]. As a result, the transistors WTr in the memory cells MC[1,1] to MC[m,1] are turned on. Therefore, the data given to the wiring WBL2[1] to WBL2[m] D[2] is connected to the memory cell MC[ At this time, the data in the memory cells MC[1,2] to MC[m,2] can be rewritten. Data D[2] is also given to MC[1,1] through MC[m,1].

[0063] Furthermore, when “H” is applied to the wiring WWL[n], the memory cells MC[1,n] The transistor WTr of the wiring WWL[n] is turned on. By giving “H” to memory cells MC[1,n−1] to MC[m,n− Therefore, the transistor WTr of the wiring WBL1[1] is turned on. Data D[n-1] given to WBL1[m] is stored in memory cells MC[1,n-1]. The data in the memory nodes up to MC[m,n-1] can be rewritten. Data D[n-1] is also provided to memory cells MC[1,n] through MC[m,n].

[0064] Therefore, the memory cells MC[1,2] to MC[m,2] and the memory cells MC[1,n Data is rewritten simultaneously in memory nodes MC[m,n-1] to MC[m,n-1].

[0065] At T42, "L" is applied to the wire WWL[1], and the memory cell MC[1,1] The transistors WTr included in the wirings MC[m,1] to MC[m,1] are turned off, and the wirings WWL[ By applying "L" to memory cells MC[1,n-1] to MC[m,n- Therefore, the transistor WTr in the memory cell MC[1,2] is turned off. The memory nodes of MC[m,2] to MC[m,2] hold data D[2], and The memory nodes of the resellers MC[1,n-1] to MC[m,n-1] contain data D [n-1] is retained.

[0066] Furthermore, the data D[1] given to the wirings WBL2[1] to WBL2[m] is The memory cells MC[1,1] to MC[m] are connected via the transistors DTr[1] to DTr[m]. The data of [m, 1] can be rewritten. The data D[n] given to the select transistors DTr[1] to DTr[m] The data in the memory cells MC[1, n] to MC[m, n] can be rewritten via do.

[0067] In FIG. 8, a plurality of memory modules included in the semiconductor device are arranged in a wiring WWL, a wiring RWL, a wiring The data structure connected by the line WWL_D and stored is as follows for an example with a data width of m columns: As an example, let us write the data on the first, second, third, n-1th, and nth lines. The switching operation will be described with reference to the timing chart of FIG.

[0068] The basic operation is the same as that explained in Figure 7, so the explanation is omitted. For example, in T51, the data in the second and n-1 rows are the same. In the T52, the data on the first and nth lines are rewritten at the same time. .

[0069] In a memory module with n rows, for example, if two different rows are to be rewritten, The memory cell MC in the first row or the memory cell MC in the nth row to which the selection transistor DTr is connected It is preferable to access each row simultaneously from either side of the row MC. Since two rows can be rewritten simultaneously, the rewriting time to the memory cells is further reduced. Therefore, it is possible to access any line to be rewritten from the nearest side. This can reduce the rewriting time.

[0070] In FIG. 8, a plurality of memory cells are arranged in m columns. The data to be transmitted includes data to be provided to the wirings WBL1[1] to WBL1[m] and data to be provided to the wirings WBL1[1] to WBL1[m]. The data given to BL2[1] through WBL2[m] is simultaneously rewritten by That is, in the configuration shown in this embodiment mode, the semiconductor device has m bits for any address. It can be said that it is a memory device with a data width of .

[0071] 6 to 8, data is written simultaneously to any row of the memory module from different directions. This allows data to be rewritten at a higher speed than the circuit configuration described in Figure 2. You can do this.

[0072] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0073] (Embodiment 2) In this embodiment mode, a memory device including the semiconductor device described in the above embodiment mode will be described. Reveal.

[0074] 9A shows an example of the configuration of a memory device. The memory device 2600 includes a peripheral circuit 2601, and a memory cell array 2610. The peripheral circuit 2601 includes a row decoder 2621, A word line driver circuit 2622, a bit line driver circuit 2630, an output circuit 2640, The control logic circuit 2660 is included.

[0075] The semiconductor device illustrated in FIG. 1(A), (B), or (C) described in the first embodiment is a metal The present invention can be applied to the memory cell array 2610.

[0076] The bit line driver circuit 2630 includes a column decoder 2631 and a precharge circuit 263 2, a sense amplifier 2633, and a write circuit 2634. 32 has a function of precharging the wiring RBL2 described in the first embodiment to a predetermined potential. The sense amplifier 2633 decodes the potential output from the memory cell MC to the wiring RBL1. The amplified data signal is then amplified. The signal is output to the storage device 26 as a digital data signal RDATA via an output circuit 2640. 00 is output externally.

[0077] The storage device 2600 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and A high power supply voltage (VDD) for the circuit 2601, a high power supply voltage (VI L) is supplied.

[0078] The memory device 2600 also receives control signals (CE, WE, RE) and an address signal ADDR. The data signal WDATA is input from the outside. The address signal ADDR is input from the row decoder. 2621 and the column decoder 2631, and the data signal WDATA is input to the write circuit It is entered into 2634.

[0079] The control logic circuit 2660 processes external input signals (CE, WE, RE). It processes the signals to generate control signals for the row decoder 2621 and the column decoder 2631. , is the chip enable signal, WE is the write enable signal, and RE is the read enable signal. The control logic circuit 2660 processes this signal. The present invention is not limited to this, and other control signals may be input as required.

[0080] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as required.

[0081] In FIG. 9B, the memory device 2600 is configured with a p-channel Si transistor and a The oxide semiconductor of the embodiment (preferably an oxide containing In, Ga, and Zn) is used as a channel 9B shows an example in which the transistor is included in the formation region. The memory device 2600 shown in FIG. 1 has a logic layer in which peripheral circuits are made up of Si transistors. The logic layer 1000 has a memory layer 2000. A memory layer 2000 formed by transistors containing a compound semiconductor in a channel formation region is formed.

[0082] Therefore, by arranging the sense amplifier 2633 under the memory layer 2000, the sense amplifier The length of the wiring RBL1 connecting the amplifier 2633 and the memory cell MC can be shortened. Therefore, the influence of the time constant of the wiring RBL1 is reduced, and the memory cell M The speed of data read from C can be improved. By using a transistor in the memory cell MC, the off-current of the memory cell MC can be reduced. This can suppress data leakage between adjacent memory cells MC. This allows data to be stored for a long period of time. This allows for a reduction in power consumption of the storage device 2600. By using only p-channel type capacitors, manufacturing costs can be kept low. The Si transistor may be only an n-channel type.

[0083] 10 to 12 show the configuration of the memory cell array 2610 of FIG. In FIG. 12, some elements are omitted for clarity of illustration.

[0084] In FIG. 10, the memory cell MC[m,n,d] is connected to the wiring RBL1[m] and the wiring WBL1[ m], wire WWL[n,d], and wire RWL[n,d] are connected. The semiconductor device shown by 10 has memory cells MC[1 ,1,1] to MC[m,n,d].

[0085] The wiring RBL1, the wiring RBL2, and the wiring WBL1 are arranged in columns and in the depth direction d. 2630A. Cells MC[1,1] to MC[m,n] are processed as a data access unit. This indicates that the data width is m bits. The present invention can be easily applied not only to general-purpose memories but also to frame memories of display devices.

[0086] However, the wiring RBL2 may be fixed at an arbitrary high potential. One end and the other end of the memory module 10 are connected via a selection transistor DTr and a wiring WBL1. Each memory module 10 is connected to a wiring WBL1. By shortening the wiring length, the variation caused by wiring resistance can be reduced, and the data This can reduce the changeover time.

[0087] FIG. 11 shows a configuration of the memory cell array 2610 that is different from that shown in FIG. The memory cell further includes a wiring WBL2, which is connected to the memory cell via a selection transistor DTr. In FIG. 10, the wiring WBL1 is electrically connected to the memory module 10. The memory modules 10 share the wiring WBL1 to connect the bit line drivers. In FIG. 11, the memory module 10 is connected to the wiring WBL1 or 2 shows an example in which the bit line driver circuit 2630A is connected via a wiring WBL2. The wiring WBL1 or the wiring WBL2 shown in FIG. It is preferable that the bit line driver circuit 2630A is connected to the memory cell 2630B. The array 2610 improves the data density of the semiconductor device compared to the configuration shown in FIG. This can be done.

[0088] FIG. 12 shows a configuration of a memory cell array 2610 that is different from that shown in FIG. 11. , further select transistors DTr1 and DTr2, wiring RWL_D1, and wiring RWL_D The wiring RBL2 is connected to the memory module via the selection transistor DTr1. 10, and the wiring RBL1 is connected to the memory module 10 via the selection transistor DTr2. The wiring RWL_D2 is electrically connected to the gate of the selection transistor DTr1. The wiring RWL_D1 is electrically connected to the gate of the selection transistor DTr2. The selection transistor DTr1 selects data for each memory module 10. The select transistor can be precharged to a predetermined potential used for reading data. DTr2 can select the memory module 10 from which data is read. The read wiring RBL1 is connected to the selection transistor connected to the unselected memory module 10. Therefore, the unselected memory module 1 can be turned off. 0 can be separated, the signal of the data read from the selected memory cell to the wiring RBL1 In particular, the data stored in the memory module 100 can be read in an analog format. In the case of data, it is preferable to have a select transistor DTr2. When reading data from the wiring RBL2, the selection transistor DTr1 is controlled. The selection transistor DTr1 or DTr2 may be provided as needed.

[0089] Furthermore, FIG. 12 shows that one of the memory modules 10 is connected via a select transistor DTr. The wiring WBL1 and the wiring RBL1 are connected to the bit line driver circuit 2630A, and the wiring WBL2 and the wiring RBL2 are connected to the bit line driver circuit 263 0B. Therefore, the memory module 10 has a bit line driver circuit 2 A signal is applied to the wiring WBL1 from the bit line driver circuit 2630A and a signal is applied to the wiring WBL2 from the bit line driver circuit 2630B. Data can be rewritten by a signal applied to the line WBL2.

[0090] <Structure examples and manufacturing methods> In order to facilitate understanding of the structure of the semiconductor device of this embodiment, a manufacturing method thereof will be described below. Reveal.

[0091] 13A and 13B are schematic diagrams showing the semiconductor device shown in FIGS. 1A to 1C. FIG. 13(A) shows a top view of the semiconductor device, and FIG. 13(B) shows a top view of the semiconductor device. ) shows a cross-sectional view corresponding to the dashed dotted line A1-A2.

[0092] The semiconductor device includes a wiring RWL, a wiring WWL, and an insulator (hatched in FIG. 13). and a structure in which the above-mentioned (not shown) and the above-mentioned (not shown) are laminated, and an opening is provided in the structure, and the opening The conductor PG is formed so that the part is buried. The wiring ER is formed on the conductor PG. As a result, the wiring ER and the wiring RWL or the wiring WWL are electrically connected. are.

[0093] In addition, the structure is provided with a wiring RWL and a wiring WWL that penetrate the structure at once. An opening is formed. The wiring WWL_D, the wiring RWL, and the wiring WWL penetrate through the opening. In order to provide the select transistor DTr in the region DM and the memory cell MC in the region AR, To achieve this, an insulator, a conductor, and a semiconductor are formed in the opening. The body functions as the wiring WBL and the wiring RBL, and the semiconductor functions as the selection transistor DTr, This functions as the channel formation region for the transistors WTr and RTr. The region where the insulator, the conductor, and the semiconductor are formed in the opening is defined as region HL. The transistor in the memory cell MC is provided with a back gate. When the back gate is connected to the conductor of the region HL, the conductor of the region HL is electrically connected to the back gate. It may also function as the wiring BGL.

[0094] That is, in FIG. 13, the semiconductor device shown in any one of FIGS. 1(A), (B), and (C) is 2 or 6 is configured in the area SD2. This shows that:

[0095] In the following manufacturing method example 1 and manufacturing method example 2, in order to form memory cells MC in the region AR, This article explains how to do this.

[0096] <<Production method example 1>> 14 to 18 are cross-sectional views illustrating a manufacturing example of the semiconductor device shown in FIG. In particular, cross-sectional views of the transistors WTr and RTr in the channel length direction are shown. In addition, in the cross-sectional views of FIGS. 14 to 18, some elements are omitted for clarity. Illustrated.

[0097] As shown in FIG. 14A, the semiconductor device of FIG. 1C has a substrate (not shown) above it. an insulator 101A disposed on the insulator 101A, a conductor 131A disposed on the insulator 101A, and a conductor The insulator 101B is disposed on the conductor 131A, and the conductor 13 is disposed on the insulator 101B. 2A, an insulator 101C disposed on the conductor 132A, and a a conductor 131B, an insulator 101D disposed on the conductor 131B, and an insulator 101D. a conductor 132B disposed on the insulating layer 101B, and an insulator 101E disposed on the conductor 132B. Hereinafter, a laminate having a plurality of conductors and a plurality of insulators will be referred to as a laminate. It is written as 100.

[0098] The substrate may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, and stabilized Zirconia substrates (such as yttria-stabilized zirconia substrates) and resin substrates are also available. The semiconductor substrate may be, for example, a semiconductor substrate of silicon, germanium, or silicon carbide. Silicon, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Furthermore, there are compound semiconductor substrates made of silicon. A semiconductor substrate having a region, such as an SOI (Silicon On Insulator) substrate Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, and the like. Furthermore, a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or a semiconductor is provided on a semiconductor substrate, The substrates include those with an insulator provided thereon, and those with a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate having elements mounted thereon may be used. The elements include a capacitance element, a resistance element, a switch element, a light-emitting element, a memory element, and the like.

[0099] A flexible substrate may also be used as the substrate. As a method of providing a transistor, a transistor is fabricated on a non-flexible substrate, and then the transistor is Another method is to peel off the transistor and transfer it to a flexible substrate. It is advisable to provide a release layer between the substrate and the transistor. A film or foil may be used. The substrate may be stretchable. The material may have the property of returning to its original shape when the bending or pulling is stopped. The substrate may have a thickness of, for example, 5 μm or more and 700 μm or less, preferably Preferably, it is 10 μm or more and 500 μm or less, and more preferably, it is 15 μm or more and 300 μm or less. The thickness of the substrate is reduced, and the weight of the semiconductor device having the transistor is reduced. Furthermore, by making the substrate thin, it is possible to achieve stretchability even when glass or other materials are used. Some have the property of returning to their original shape when bending or pulling is stopped. Therefore, it is possible to reduce the impact that is applied to the semiconductor device on the board when it is dropped, etc. That is, a robust semiconductor device can be provided.

[0100] The flexible substrate may be, for example, a metal, an alloy, a resin, a glass, or a fiber thereof. The lower the linear expansion coefficient of the flexible substrate, the less deformation caused by the environment can be suppressed. As a flexible substrate, for example, a substrate having a linear expansion coefficient of 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less. Examples of such materials include polyester, polyolefin, polyamide (nylon, aramid, etc.) ), polyimide, polycarbonate, acrylic, etc. In particular, aramid has a linear expansion coefficient Since the resistance is low, it is suitable for flexible substrates.

[0101] In the manufacturing example described in this embodiment, a heat treatment is included in the manufacturing process. It is preferable to use a material that has high heat resistance and a low coefficient of thermal expansion.

[0102] The conductor 131A (conductor 131B) functions as the wiring WWL shown in FIG. 1(C) and The conductor 132A (the conductor 132B) functions as the wiring RWL shown in FIG.

[0103] The conductors 131A, 131B, 132A, and 132B may be, for example, , aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum , tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconia Materials containing one or more metal elements selected from the group consisting of sulphur, beryllium, indium, ruthenium, etc. In addition, polycrystalline silicon containing impurity elements such as phosphorus can be used. Alternatively, a semiconductor having high electrical conductivity, such as nickel silicide, may be used. .

[0104] The conductors, particularly the conductors 131A and 131B, are made of semiconductor 1 51, semiconductor 152, semiconductor 153a, and semiconductor 153b are included in the applicable metal oxides A conductive material containing the metal element and oxygen may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Conductive materials may also be used. Indium tin oxide, indium containing tungsten oxide, etc. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon-added Indium tin oxide containing nitrogen may also be used. By using such a material, water can be prevented from entering from surrounding insulators. It may be possible to capture the element.

[0105] In addition, the conductors, particularly the conductors 132A and 132B, may be water or hydrogen. It is preferable to use a conductive material that has the function of suppressing the permeation of impurities. tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. It is preferable that the layer is a single layer or a multilayer.

[0106] Furthermore, a plurality of conductors made of the above materials may be stacked. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated layer that combines the material containing the metal element and the conductive material containing nitrogen is also available. In addition, a material containing the above-mentioned metal element, a conductive material containing oxygen, and a material containing nitrogen may be used. A laminated structure may be formed by combining an insulating material that is in contact with the conductor and a conductive material that contains an element. By applying an insulator having an excess oxygen region as an insulator, the region where the conductor contacts the insulator In this case, oxygen may diffuse. This may cause a problem where the material containing the metal element and the material containing oxygen are mixed. A laminated structure can be formed by combining a conductive material with the conductive material. By applying an insulator having an excess nitrogen region as an insulator in contact with a conductor, Nitrogen may diffuse into the contact area. This may cause a difference between the material containing the metal element and the A laminated structure can be formed by combining a conductive material containing nitrogen.

[0107] The conductors 131A, 131B, 132A, and 132B are The materials may be the same or different from each other. Conductor 131A, conductor 131B, and conductor 132A that constitute a semiconductor device according to one embodiment of the present invention The materials for the conductor 132B can be appropriately selected and used.

[0108] The insulators 101A to 101E are made of a material having a reduced concentration of impurities such as water or hydrogen. For example, the hydrogen of the insulators 101A to 101E is preferably The amount of desorption was measured by thermal desorption spectroscopy (TDS). In ectroscopy), the surface temperature of the film was in the range of 50℃ to 500℃. The amount of desorption converted into hydrogen molecules is Converted to a hit, it is 2 x 10 15 molecules / cm 2 Less than 1 × 10 15 molecules / cm 2 Less than or equal to 5 × 10 14 molecules / cm 2 Furthermore, the insulators 101A to 101E can be made oxidized by heating. The conductor 13 may be formed using an insulator from which the electrons are emitted. 1A, the conductor 131B, the conductor 132A, and the conductor 132B are made of a material containing a metal element and an acid. The conductive material may have a laminated structure in which the conductive material includes a silicon dioxide.

[0109] The insulators 101A to 101E may include, for example, boron, carbon, nitrogen, oxygen, and fluorine. Fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, gel Magnesium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum Insulators containing silicon dioxide can be used in a single layer or a multilayer structure. Materials including silicon nitride or silicon oxynitride can be used.

[0110] In this specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen in its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. In this specification, aluminum oxynitride refers to a material with a high content. Aluminum oxide nitride is a material that has a higher oxygen content than nitrogen. It refers to a material that contains more nitrogen than oxygen as a constituent.

[0111] In the next step, as shown in FIG. 14(B), a resist mask is formed and an etching process is performed. As a result, an opening 191 is formed in the laminate 100 shown in FIG.

[0112] The resist mask is formed by using a lithography method, a printing method, an inkjet method, or the like. If the resist mask is formed by the inkjet method, a photomask can be used. As no etching is required, the manufacturing cost can be reduced. Either a rubbing method or a wet etching method may be used, or both may be used.

[0113] Then, as shown in FIG. 15(A), the side of the opening 191 is removed by etching or the like. The conductor 132A (conductor 132B) on the surface is removed, and a recess 192A is formed in the side surface. Here, the conductor 132A (the conductor 132B) is In the laminate 100, the conductor 132A (the conductor 132B) is selectively removed. Materials (insulators 101A to 101E and conductor 131A (conductor 131B) It is assumed that a material with a high etching rate is used.

[0114] The recess 192A (recess 192B) is formed in the manufacturing process of the semiconductor device shown in FIG. At this stage, a sacrificial layer is provided in the area where the opening 191 and the recess 192A (recess 192B) are to be formed. 14B, the opening 191 may be formed at the same time as the opening 192. Furthermore, when the opening 191 is formed without providing a sacrificial layer, the recess 192A (recess 192B) can also be formed.

[0115] In the next step, as shown in FIG. 15(B), the side surface of the opening 191 shown in FIG. 15(A), An insulator 102 is then deposited in the recessed portion.

[0116] The insulator 102 may be made of an insulating material that has a function of suppressing oxygen permeation. For example, the insulator 102 may be silicon nitride, silicon nitride oxide, or silicon oxide nitride. It is preferable to use silicon, aluminum nitride, aluminum oxide nitride, etc. By forming such an insulator 102, oxygen can penetrate through the insulator 102 and enter the It is possible to prevent the conductivity of the conductor 133 from decreasing due to oxidation of the conductor 133. .

[0117] In the next step, as shown in FIG. 16(A), the side surface of the opening 191 shown in FIG. 15(B), In other words, a conductive material 133 is formed on the insulator 102. A body 133 is formed.

[0118] The conductor 133 may be the conductor 131A, the conductor 131B, the conductor 132A, and the conductor 131B. Materials applicable to the conductive body 132B can be used. In particular, conductive materials can be used. Preferably, a high-quality material is applied to the conductor 133 .

[0119] In the next step, as shown in FIG. 16(B), a resist mask is formed and an etching process is performed. Therefore, the conductor 133 included in the opening 191 is removed so that the conductor 133 remains only in the recess. 133 is removed. This forms the conductors 133a and 133b. At this time, the insulators 101A to 101E, the conductor 131A, and the conductor 131 A part of the insulator 102 may be removed so long as B is not exposed in the opening 191. stomach.

[0120] The formation of the resist mask and the etching process are explained in FIG. 14(B). I will take your opinion into consideration.

[0121] Incidentally, the conductor 133a (conductor 133b) is not only a capacitor element CS shown in FIG. In other words, the area 181A (area 181B) shown in FIG. In this region, a capacitance element CS is formed.

[0122] In the next step, as shown in FIG. 17(A), the insulator 1 positioned on the side surface of the opening 191 is 02, a semiconductor 151 is formed over the conductor 133a and the conductor 133b.

[0123] The semiconductor 151 is made of a material containing a metal oxide described in the third embodiment. It is preferable to do so.

[0124] When the semiconductor 151 contains a metal oxide, the insulating layer in contact with the semiconductor 151 The body 102 is an insulator that has the function of suppressing the permeation of not only oxygen but also impurities such as water or hydrogen. It is preferable to use a conductive material. Impurities such as water or hydrogen penetrate through O2 and react with oxygen contained in the semiconductor 151. When water is generated in the semiconductor 151, the semiconductor 151 Oxygen vacancies may be formed within the crystal. Impurities such as hydrogen may enter these oxygen vacancies. Therefore, electrons that become carriers may be generated in the semiconductor 151. If a region containing a large amount of hydrogen exists, the region is included in the channel formation region. The transistor tends to have a normally-on characteristic. and an insulating material that has the function of suppressing the permeation of not only oxygen but also impurities such as water and hydrogen. It is desirable to use

[0125] Furthermore, when the semiconductor 151 contains a metal oxide, the semiconductor 151 has a region where the metal oxide is formed. In FIG. 17A, the conductivity may differ depending on the region. Among the regions, the regions in contact with the insulator 102 are illustrated as regions 151a and 151b, and the regions in contact with the conductor 102 are illustrated as regions 151a and 151b. The region in contact with 133a (conductor 133b) is shown as region 151c. The region 51a overlaps with the side surface of the conductor 131A (conductor 131B), and the region 151b is a region overlapping with the side surface of the insulator 101A (insulators 101B to 101E). The region 151c is in contact with the conductor 133a (conductor 133b). Impurities such as hydrogen or water contained in 33a (conductor 133b) diffuse into region 151c. As described above, when impurities such as water or hydrogen are diffused into the semiconductor 151, Since electrons that serve as carriers may be generated, the region 151c is made to have a low resistance. Therefore, the region 151c has higher conductivity than the regions 151a and 151b. It becomes an area.

[0126] The region 151a is a region that will become a channel formation region of a transistor. When the transistor is in an on state, the region 151a has a lower resistance than the region 151b. The conductivity increases.

[0127] In the next step, as shown in FIG. 17(B), the semiconductor 1 positioned on the side of the opening 191 is On the substrate 51, an insulator 103 and a semiconductor 152 are formed in this order.

[0128] The insulator 103 may be made of any of the materials applicable to the insulator 102 described above. In particular, when the semiconductor 151 contains a metal oxide, the insulator 103 is oxygen. In addition, it must be an insulating material that has the function of suppressing the permeation of impurities such as water or hydrogen. is preferred.

[0129] In the area 182A (area 182B) shown in FIG. 17(B), Specifically, the transistor WTr shown in FIG. 18 is configured in the region 182A (region 182B). In this case, the region 151a of the semiconductor 151 is used as a channel forming region of the transistor WTr. Each of the two regions 151b of the semiconductor 151 functions as a source voltage source for the transistor WTr. The conductor 132A functions as the gate electrode of the transistor WTr. In particular, when a material containing a metal oxide is used as the semiconductor 151, The transistor WTr is an oxide semiconductor (OS) transistor.

[0130] The semiconductor 152 includes the metal oxide described in Embodiment 3, similarly to the semiconductor 151. In addition, as an alternative to the semiconductor 152, polycrystalline silicon, Semiconductor materials such as amorphous silicon can be used.

[0131] In the next step, as shown in FIG. 18(A), an insulator 104 is formed on the semiconductor 152. Then, a conductor 134 is deposited so as to fill the remaining opening 191 .

[0132] The insulator 104 is made of a material that can be used for the insulators 102 and 103 described above. It is possible.

[0133] The conductor 134 may be the above-mentioned conductor 131A, conductor 131B, conductor 132A, Materials applicable to the conductor 132B, the conductor 133a, and the conductor 133b can be used. do.

[0134] In the area 183A (area 183B) shown in FIG. 18(A), Specifically, the transistor RTr shown in FIG. 18 is configured in the region 183A (region 183B). In the figure, the region 151c of the semiconductor 151, the two regions 151b, and the conductor 133a (conductor The semiconductor 133b functions as the gate electrode of the transistor RTr, and the semiconductor 152 functions as the gate electrode of the transistor RTr. The conductor 134 functions as a channel forming region of the transistor RTr. In particular, a material containing a metal oxide is used as the semiconductor 152. In this case, the transistor RTr constitutes an OS transistor.

[0135] By carrying out the steps from FIG. 14(A) to FIG. 18(A), the semiconductor shown in FIG. 1(C) can be obtained. A body device can be created.

[0136] One embodiment of the present invention is not limited to the structural example of the semiconductor device illustrated in FIG. One embodiment of the present invention is to use the semiconductor device shown in FIG. 18(A) as needed, depending on the situation, or as required. The conductor device may be modified as appropriate.

[0137] For example, as described above, one embodiment of the present invention is a transistor W It is also possible to provide a semiconductor device in which the back gate is not provided for the transistors Tr and RTr. When manufacturing the semiconductor device shown in FIG. 1(A), the semiconductor device shown in FIG. In the process of forming the semiconductor device, if the step shown in FIG. 18(B) is performed instead of the step shown in FIG. 18(A), In FIG. 18(B), an opening 191 is provided instead of the conductor 134 in FIG. 18(A). The insulator 105 is formed to fill the gap. Any material that can be used as the insulator 104 can be used.

[0138] Furthermore, for example, one embodiment of the present invention improves the switching characteristics of the transistor WTr. For this purpose, the configuration of the gate electrode of the transistor WTr is changed from that shown in FIG. 19(A), (B), and 20(A) and (B) show a method for manufacturing the semiconductor device. 19(A) shows an example of the opening 191 in FIG. The conductor 131A (conductor 131B) is removed to form the recess 193A (recess 193B). Here, the conductor 131A (conductor 131B) is In the laminate 100, the conductor 131A (the conductor 131B) is selectively removed. The material (the conductor 132A (the conductor 132B), the insulators 101A to 101E) is more elastic than the material (the conductor 132A (the conductor 132B), the insulators 101A to 101E). It is assumed that materials with high etching rates are used.

[0139] The recess 193A (recess 193B) is formed in the manufacturing process of the semiconductor device shown in FIG. At this stage, a sacrificial layer is applied to the area where the opening 191 and the recess 193A (recess 193B) are to be formed. 14B, the opening 191 may be formed at the same time as the opening 191. Furthermore, when the opening 191 is formed without providing a sacrificial layer, the recess 193A (recess In some cases, a section 193B) can be formed.

[0140] In the next step, as shown in FIG. 19(B), the side surface of the opening 191 shown in FIG. 19(A), The semiconductor 153 is deposited in the recess 193A (recess 193B).

[0141] The semiconductor 153 is a material containing a metal oxide described in Embodiment 3. This shall be done.

[0142] In the next step, as shown in FIG. 20(A), a resist mask is formed and an etching process is performed. By this, the opening is formed so that the semiconductor 153 remains only in the recess 193A (recess 193B). The semiconductor 153 included in the portion 191 is removed, and the semiconductor 153a (semiconductor 153b) is formed. In addition, simultaneously with or after this treatment, an etching treatment is performed to form a conductive film. The conductive body 132A (conductive body 132B) is removed to form the recess 192A (recess 192B).

[0143] Next, similarly to the process of FIG. 16(B), the semiconductor 153a ( The insulator 102 is formed so as to cover the semiconductor 153a (semiconductor 153b). When a material containing a metal oxide is used as the semiconductor 153a (semiconductor 15b), 3b) is in contact with the insulator 102, and impurities such as hydrogen and water contained in the insulator 102 are removed. The semiconductor 153a (semiconductor 153b) is diffused. ) contacts the conductor 133a (conductor 133b), Impurities such as hydrogen and water contained in b) diffuse into the semiconductor 153a (semiconductor 153b). In other words, the semiconductor 153a (semiconductor 153b) has the role of capturing impurities such as hydrogen and water. This reduces the resistance of the semiconductor 153a (semiconductor 153b), It can function as the gate electrode of the WTr. After this, By carrying out the same steps as up to A), the semiconductor device shown in FIG. 20(B) can be fabricated. This can be done.

[0144] For example, one embodiment of the present invention may be a transistor having a first terminal, Or to reduce the electrical resistance between the second terminal and the gate of the transistor RTr. The configuration of the gate electrode of the transistor RTr is changed from that shown in FIG. 21A and 21B show an example of a method for manufacturing the semiconductor device. 1(A), the conductor 132A (conductive Insulators 101A to 101E are removed, not just insulator 132B. This shows a step in which recesses 194B (recesses 194A, recesses 194C) are formed. Here, the conductor 132A (conductor 132B) and the insulators 101A to 101E are In the laminate 100, the conductor 132A (conductor 132B) and the insulators 101A to The insulator 101E is made of a material (such as the conductor 131A (or the conductor 131B)) that can be selectively removed. It is assumed that a material with a higher etching rate than that of the insulating film is used.

[0145] The recess 194B (recess 194A, recess 194C) is formed in the semiconductor device shown in FIG. In the manufacturing process of the device, the opening 191 and the recess 194B (recess 194A, recess 194C) A sacrificial layer is provided in a region where an opening is to be formed, and the opening is formed in the manufacturing process of the semiconductor device shown in FIG. Alternatively, the opening 191 may be formed at the same time as the sacrificial layer. In some cases, the recess 194B (recess 194A, recess 194C) can be automatically formed.

[0146] In addition, in FIG. 21(A), the recess 194B (recess 194A, recess 194C) has an insulating Insulator 101B, insulator 101C (insulator 101A, insulator 101D, insulator 101E) The conductor 132A (conductor 132B) is more largely removed than the conductor 132B. 2A (conductor 132B), the insulator 101B, the insulator 101C (insulator 101A, The insulating layer 101B may be removed to a greater extent than the insulating layer 101D. , insulator 101C (insulator 101A, insulator 101D, insulator 101E), and conductor 13 2A (conductor 132B) may be formed to the same depth.

[0147] FIG. 21(B) shows an example of the structure of a semiconductor device after going through the process of FIG. 21(A). After the step of FIG. 21(A), the recess 194B (recess 194A, recess 194C) is filled. A conductor 133 is formed as a film so as to form the gate electrode of the transistor RTr. In FIG. 1(B), a conductor 133a functions as the gate electrode of the transistor RTr, a conductor 17(A) to 18(A) are shown. By carrying out similar steps in the above, the semiconductor device shown in FIG. 21(B) can be fabricated. This semiconductor device has a structure in which the semiconductor 151 and the conductor 152 are arranged in a more uniform manner than the semiconductor device shown in FIG. The contact area with the semiconductor 151 is increased. When a material containing a metal oxide is used, the semiconductor device shown in FIG. 21(B) can be obtained by ) does not exist, the first terminal or the second terminal of the transistor WTr and the gate of the transistor RTr can be made small.

[0148] <<Production method example 2>> Here, as a semiconductor device of this embodiment, an example of a structure different from that of Manufacturing Method Example 1 will be described. This will be explained with reference to FIGS. 22 to 24.

[0149] 22 to 24 show the manufacturing method of the semiconductor device shown in FIG. 1C, similarly to FIGS. 14 to 18. 1 is a cross-sectional view for explaining an example, in particular, the transistors WTr and RTr. 22 to 24 show cross-sectional views in the channel length direction. As with FIG. 18, some elements have been omitted for clarity of illustration.

[0150] The first step is the same as that described in Example 1 of Fabrication Method 1 from FIG. 14(A) to FIG. 15(B). Please refer to the explanation.

[0151] The process shown in FIG. 22(A) is a continuation of the process shown in FIG. 15(B). 2(A), the side surface of the opening 191 shown in FIG. 15(B) and the recess formed therein are A semiconductor 151 is formed. That is, the semiconductor 151 is formed on the insulator 102.

[0152] As the semiconductor 151, it is preferable to use the semiconductor described in the third embodiment.

[0153] In the next step, as shown in FIG. 22(B), the side surface of the opening 191 shown in FIG. 22(A), A conductor 133 is deposited in the recess formed.

[0154] For the conductor 133, the description of the conductor 133 in Manufacturing Method Example 1 can be referred to.

[0155] In the next step, as shown in FIG. 23(A), a resist mask is formed and an etching process is performed. Therefore, the conductor 133 included in the opening 191 is removed so that the conductor 133 remains only in the recess. 133 is removed. This forms the conductors 133a and 133b. At this time, if the insulator 102 is not exposed in the opening 191, the semiconductor 151 A portion may be removed.

[0156] The formation of the resist mask and the etching process are explained in FIG. 14(B). I will take your opinion into consideration.

[0157] Incidentally, the conductor 133a (conductor 133b) is not only a capacitor element CS shown in FIG. In other words, the area 181A (area 181B) shown in FIG. In this region, a capacitance element CS is formed.

[0158] For the semiconductor 151, the description of the semiconductor 151 in Fabrication Method Example 1 can be referred to. In addition, when the semiconductor 151 contains a metal oxide, the semiconductor 151 has a region 151a, a region The area can be divided into areas 151a, 151b, and 151c. Regarding 51c, the regions 151a, 151b, and 151c described in Example 1 of the manufacturing method are Please refer to the description below.

[0159] In the next step, as shown in FIG. 23(B), the conductor 1 located on the side surface of the opening 191 is The insulator 103 is formed on the insulating layer 33a, the conductor 133b, and the semiconductor 151. A semiconductor 152 is deposited on the insulating body 103 .

[0160] For the insulator 103, the description of the insulator 103 in Manufacturing Method Example 1 can be referred to.

[0161] For the semiconductor 152, the description of the semiconductor 152 in Manufacturing Method Example 1 can be referred to.

[0162] By the way, in the region 182A (region 182B) shown in FIG. 23(B), Specifically, the transistor WTr shown in FIG. 18 is configured in the region 182A (region 182B). In this case, the region 151a of the semiconductor 151 is used as a channel forming region of the transistor WTr. Each of the two regions 151b of the semiconductor 151 functions as a source voltage source for the transistor WTr. The conductor 132A functions as the gate electrode of the transistor WTr. In particular, when a material containing a metal oxide is used as the semiconductor 151, The transistor WTr constitutes an OS transistor.

[0163] In the next step, as shown in FIG. 24(A), an insulator 104 is formed on the semiconductor 152. Then, a conductor 134 is deposited so as to fill the remaining opening 191 .

[0164] For the insulator 104, the description of the insulator 104 in Manufacturing Method Example 1 can be referred to.

[0165] For the conductor 134, the description of the conductor 134 in the manufacturing method example 1 can be referred to.

[0166] In the area 183A (area 183B) shown in FIG. 24(A), Specifically, the transistor RTr shown in FIG. 18 is configured in the region 183A (region 183B). In the figure, the region 151c of the semiconductor 151, the two regions 151b, and the conductor 133a (conductor The semiconductor 133b functions as the gate electrode of the transistor RTr, and the semiconductor 152 functions as the gate electrode of the transistor RTr. The conductor 134 functions as a channel forming region of the transistor RTr. In particular, a material containing a metal oxide is used as the semiconductor 152. In this case, the transistor RTr constitutes an OS transistor.

[0167] Carry out the steps from FIG. 14(A) to FIG. 15(B) and FIG. 22(A) to FIG. 24(A). In this way, the semiconductor device shown in FIG. 1C can be manufactured.

[0168] One embodiment of the present invention is not limited to the structural example of the semiconductor device illustrated in FIG. One aspect of this is to use the semiconductor device shown in FIG. 24(A) depending on the situation, circumstances, or needs. The conductor device may be modified as appropriate.

[0169] For example, as described above, one embodiment of the present invention is a transistor W It is also possible to provide a semiconductor device in which the back gate is not provided for the transistors Tr and RTr. When manufacturing the semiconductor device shown in FIG. 1(A), the semiconductor device shown in FIG. In the process of this, the step shown in FIG. 24(B) should be carried out instead of the step shown in FIG. 24(A). In FIG. 24(B), the opening 191 is filled in place of the conductor 134 in FIG. The insulator 105 is formed as a film, for example. Any material that can be used as the insulator 104 can be used.

[0170] Furthermore, for example, one embodiment of the present invention improves the switching characteristics of the transistor WTr. For this purpose, the configuration of the gate electrode of the transistor WTr is changed from that shown in FIG. FIG. 25 shows an example of the configuration of the semiconductor device. The semiconductor device shown in FIG. When manufacturing the recess 19, as in the configuration example shown in FIG. 20(B) described in the manufacturing method example 1, The semiconductor 153a (semiconductor 153b) is formed so as to fill the recess 193B. Then, an insulating layer is formed on the side surface of the opening 191 so as to cover the semiconductor 153a (semiconductor 153b). The body 102 is formed. After that, the same steps as those shown in FIG. 22(A) to FIG. 24(A) are performed. By doing so, the semiconductor device shown in Fig. 25 can be constructed. The effect of this is as shown in FIGS. 19(A), (B), 20(A), and 20(B) in Example 1 of the manufacturing method. Please refer to the explanation in B).

[0171] For example, one embodiment of the present invention may be a transistor having a first terminal, Or to reduce the electrical resistance between the second terminal and the gate of the transistor RTr. The configuration of the gate electrode of the transistor RTr is changed from that shown in FIG. FIG. 26 shows an example of the configuration of the semiconductor device. When manufacturing the device, the configuration example shown in FIG. 21(A) explained in Manufacturing Method Example 1 is manufactured. By carrying out the same steps as those shown in FIG. 22(A) to FIG. 24(A), the semiconductor device shown in FIG. The effect of constructing the device shown in FIG. 26 can be seen in the example of the manufacturing method. Please refer to the description of Figure 21(B) explained in 1.

[0172] A semiconductor capable of storing a large amount of data by the above-described Manufacturing Method Example 1 or Manufacturing Method Example 2 A device can be fabricated.

[0173] Here, the semiconductor device shown in FIG. 18(A) is placed in the region SD2 of the semiconductor device shown in FIG. 13(B). The cross-sectional view of the device (circuit configuration of FIG. 1(C)) is shown in FIG. 27. As shown in FIG. 27, the conductive wirings RWL and WWL correspond to the memory cells MC. An opening is formed in the laminated structure of the insulating material and the insulating material in a lump, and the above-mentioned manufacturing method example is performed. 1 or 2, the circuit configuration of FIG. 1C is realized. It is possible.

[0174] <Example of connection to peripheral circuits> The semiconductor device shown in Manufacturing Method Example 1 or Manufacturing Method Example 2 has a readout circuit and a processor in a lower layer. A peripheral circuit of the memory cell array, such as a recharge circuit, may be formed. The peripheral circuit is formed by forming a Si transistor on a silicon substrate or the like, and then In Example 1 or Manufacturing Method Example 2, a semiconductor device according to one embodiment of the present invention is formed on the peripheral circuit. In Figure 28(A), the peripheral circuit is made up of planar type Si transistors, and the upper layer 29A is a cross-sectional view of a semiconductor device according to one embodiment of the present invention formed in a peripheral circuit. The circuit is configured with a FIN type Si transistor, and the semiconductor device according to one embodiment of the present invention is mounted on the upper layer. 28(A) and 29(A) are merely examples. Therefore, the configuration of FIG. 18(A) is applied.

[0175] In FIG. 28(A) and FIG. 29(A), the Si transistors constituting the peripheral circuits are The element isolation layer 1701 is formed between a plurality of Si transistors. Conductors 1712 are formed as the source and drain of the Si transistor. The conductor 1730 is formed to extend in the channel width direction, and is connected to other Si transistors or It is connected to a conductor 1712 (not shown).

[0176] The substrate 1700 may be a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor Conductor substrates, compound semiconductor substrates made of silicon germanium, SOI substrates, etc. are used. It is possible.

[0177] The substrate 1700 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, or the like. Substrates, flexible substrates, laminated films, paper containing fibrous materials, or base films, etc. Alternatively, a semiconductor element may be formed on a certain substrate, and then the semiconductor element may be transferred to another substrate. The conductive elements may be transposed. In FIG. 28(A) and FIG. 29(A), as an example, Figure 0 shows an example using a single crystal silicon wafer.

[0178] Here, the details of the Si transistor will be explained. The Si transistor is a planar type shown in FIG. 28(B) which is a cross section in the channel length direction. The Si transistor is shown in a cross section in the channel width direction. A channel forming region 1793, a low concentration impurity region 1794, and High concentration impurity region 1795 (collectively referred to as impurity region) and the impurity region A conductive region 1796 is provided in contact with the channel forming region 1793. a gate insulating film 1797, a gate electrode 1790 provided on the gate insulating film 1797, The gate electrode 1790 has a sidewall insulating layer 1798 and a sidewall insulating layer 1799 formed on its side. The conductive region 1796 may be made of metal silicide or the like.

[0179] The FIN type Si transistor shown in FIG. 29(A) has a cross section in the channel length direction. The FIN type Si transistor shown in FIG. 29(B) is a cross-sectional view in the channel width direction. The Si transistor shown in FIGS. 29(A) and 29(B) has a channel forming region 1793 has a convex shape, and the gate insulating film 1797 and the gate electrode 179 are formed along the side and upper surfaces thereof. In this embodiment, when a part of a semiconductor substrate is processed to form a convex portion, However, the SOI substrate may be processed to form a semiconductor layer having a convex shape. The reference numerals shown in FIGS. 29(A) and (B) are the same as those shown in FIGS. 28(A) and (B).

[0180] It should be noted that the insulators, conductors, semiconductors, etc. disclosed in this specification and the like may be deposited by PVD (Physical Vapor Deposition). cal vapor deposition) method, CVD (Chemical Vapor Deposition) method, CVD (Chemical Vapor Deposition) method, The PVD method can be, for example, , sputtering method, resistance heating evaporation method, electron beam evaporation method, PLD (Pulsed Laser Deposition) In addition, the CVD method is a plasma Examples of the thermal CVD method include MOCV. D(Metal Organic Chemical Vapor Depositio n) method and ALD (Atomic Layer Deposition) method. do.

[0181] The thermal CVD method is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no further processing is required.

[0182] In the thermal CVD method, the source gas and oxidant are simultaneously fed into a chamber, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the material near or on the substrate under reduced pressure and depositing the material on the substrate. You may go.

[0183] In addition, in the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating this gas introduction sequence. For example, by switching each switching valve (also called high-speed valve), two or more types of The above source gases are supplied to the chamber in order, and the first An inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the raw material gas. The second source gas is introduced. When an inert gas is introduced at the same time, the inert gas is It acts as a carrier gas, and even if an inert gas is introduced at the same time as the second source gas is introduced, Alternatively, instead of introducing an inert gas, the first source gas may be discharged by vacuum evacuation. After that, a second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first thin film. The first thin layer is formed, and then reacts with the second source gas introduced later, and the second thin layer is formed on the first thin layer. The order of gas introduction is controlled until the desired thickness is reached. By repeating the above steps several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas introduction sequence is repeated. This is possible and is suitable for fabricating miniaturized FETs.

[0184] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It is possible to form various films such as metal films, semiconductor films, and inorganic insulating films. When forming a-Zn-O film, trimethylindium (In(CH3)3), trimethylindium (Tm(CH3)3) Using methylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) Furthermore, the present invention is not limited to these combinations, and trimethylgallium may be replaced with triethylgallium. Zinc (Ga(C2H5)3) can also be used, and diethylzinc ( Zn(C2H5)2) can also be used.

[0185] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl Hafnium amides (hafnium amides such as TDMAH and Hf[N(CH3)2]4) Two types of gases are used: the vaporized source gas and ozone (O3) as an oxidizing agent. Other materials include tetrakis(ethylmethylamido)hafnium.

[0186] For example, when forming an aluminum oxide film using an ALD film forming device, A liquid containing a catalyst and an aluminum precursor compound (trimethylaluminum (TMA), Al(C) Two types of gases are used: vaporized H3)3) and H2O as an oxidizing agent. Other materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanediol), Onato), etc.

[0187] For example, when forming a silicon oxide film using a film forming device that uses ALD, Chlorodisilane is adsorbed onto the surface to be coated, and the radicals of oxidizing gases (O2, nitrous oxide) are removed. The adsorbate is reacted with the adsorbate.

[0188] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film was formed by sequentially introducing BH gas and BH gas. The tungsten film is formed by repeatedly introducing B2H6 gas and H2 gas in sequence. SiH4 gas may be used instead of gas.

[0189] For example, an oxide semiconductor film, such as In-Ga-Zn- When forming an O film, In(CH3)3 gas and O3 gas are introduced in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced repeatedly to form a Ga After that, Zn(CH3)2 gas and O3 gas were introduced repeatedly to form an O layer. The order of these layers is not limited to this example. Mixed oxide layers such as In-Ga-O, In-Zn-O, and Ga-Zn-O are formed using It is also possible to use an inert gas such as Ar instead of O3 gas to bubble water. Although H2O gas may be used, it is preferable to use O3 gas that does not contain H. Instead of (CH3)3 gas, In(C2H5)3 gas may be used. 3) Ga(C2H5)3 gas may be used instead of Zn(CH3)2 Gas may also be used.

[0190] Note that the respective configuration examples of the semiconductor device described in this embodiment mode may be combined with each other as appropriate. It can be done.

[0191] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0192] (Embodiment 3) In this embodiment, the channel formation region of the OS transistor used in the above embodiment is This section explains the metal oxides contained in these materials.

[0193] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, magnesium, etc. One or more of these may be included.

[0194] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or Other elements that can be used for element M include boron, silicon, and titanium. Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, Odium, hafnium, tantalum, tungsten, magnesium, etc. However, elements In some cases, M may be a combination of two or more of the above elements.

[0195] Next, with reference to Figures 30(A), 30(B), and 30(C), the metal according to the present invention will be described. A preferred range of the atomic ratio of indium, element M, and zinc contained in the oxide will be explained. In addition, in Fig. 30(A), Fig. 30(B), and Fig. 30(C), the atomic ratio of oxygen is In addition, the number of atoms of indium, element M, and zinc contained in the metal oxide is not described. The respective terms in the ratio are [In], [M], and [Zn].

[0196] In Figures 30(A), 30(B), and 30(C), the dashed lines indicate the ratio of [In]:[M ]:[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):2, [ The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):3 is n]:[M]:[Zn]=(1+α):(1-α):4, and The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):5 is shown. vinegar.

[0197] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=2:1:β is ]:[M]:[Zn]=1:1:β, the atomic ratio line, [In]:[M]:[Zn ]=1:2:β, and the atomic ratio of [In]:[M]:[Zn]=1:3:β. The atomic ratio of [In]:[M]:[Zn]=1:4:β Represents a line.

[0198] In addition, the [In]:[M]: Metal oxides with an atomic ratio of [Zn]=0:2:1 and values ​​close to that ratio form spinel-type crystals. Easy to structure.

[0199] In addition, multiple phases may coexist in metal oxides (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is close to [In]:[M]:[Zn]=0:2:1, the spinel The two phases of the hexagonal crystal structure and the layered crystal structure tend to coexist. When [M]:[Zn] is close to 1:0:0, the bixbyite-type crystal structure and the layered structure When multiple phases coexist in a metal oxide, different crystal structures are formed. Grain boundaries may be formed between the crystal structures.

[0200] The region A shown in FIG. 30(A) is a region containing indium, element M, and zinc contained in the metal oxide. 1 shows an example of a preferable range of the atomic ratio.

[0201] By increasing the indium content of metal oxides, the carrier mobility of the metal oxides ( Therefore, metal oxides with a high indium content can be used The material has higher carrier mobility compared to metal oxides with a lower indium content.

[0202] On the other hand, when the content of indium and zinc in the metal oxide is low, the carrier mobility Therefore, the atomic ratio of [In]:[M]:[Zn]=0:1:0 and When the value is close to (for example, region C shown in FIG. 30(C)), the insulating property is high.

[0203] Therefore, the metal oxide of one embodiment of the present invention has high carrier mobility and The atomic ratio shown in region A in FIG. 30(A) is such that a layered structure with little is preferred.

[0204] In particular, in the area B shown in FIG. 30(B), the CAAC (c-axis a It is easy to become an optically active (ligned crystalline)-OS, and has excellent carrier mobility. The resulting metal oxide is

[0205] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted and has a distortion. In this case, the direction of the lattice arrangement is changed between an area with a uniform lattice arrangement and another area with a uniform lattice arrangement. indicates the point where a change occurs.

[0206] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in CAAC-OS, clear grain boundaries (grain bows) are not observed even near the strain. It is not possible to confirm the presence of grain boundaries (also called grain boundaries). This is because the CAAC-OS has a crystalline structure in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms is shortened by the substitution of metal elements. This is thought to be because distortion can be tolerated by changing the thickness of the film.

[0207] CAAC-OS is a highly crystalline metal oxide. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility due to the grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides is reduced by the incorporation of impurities and the generation of defects. Therefore, CAAC-OS is a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0208] Region B is [In]:[M]:[Zn]=4:2:3 to 4.1 and its vicinity. Near values ​​include, for example, [In]:[M]:[Zn]=5:3:4 In addition, region B is [In]:[M]:[Zn]=5:1:6 and its neighboring values, and and [In]:[M]:[Zn]=5:1:7, and their neighboring values.

[0209] The properties of metal oxides are not uniquely determined by the atomic ratio. Even if the ratio is the same, the properties of the metal oxide may differ depending on the formation conditions. When depositing a film of an oxide using a sputtering device, the atomic ratio may be different from the atomic ratio of the target. Also, depending on the substrate temperature during film formation, the film may be formed with [Zn] rather than the target [Zn]. The [Zn] of the film may be small. Therefore, the area shown is the area where the metal oxide is specific. The boundary between region A and region C is not strict. There is no.

[0210] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0211] (Fourth embodiment) In this embodiment, a CPU that can include the semiconductor device of the above embodiment will be described. explain.

[0212] FIG. 31 shows a configuration of an example of a CPU that partially uses the semiconductor device described in the first embodiment. FIG.

[0213] The CPU shown in FIG. 31 includes an ALU 1191 (Arithmetic and logic unit) on a board 1190. tic logic unit, arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI substrate, The ROM 1199 and the ROM interface 1189 are It may be provided on a separate chip. Of course, the CPU shown in FIG. 31 is a simplified version of the configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their uses. For example, 31 is a core, and a configuration including a CPU or an arithmetic circuit shown in FIG. 31 is a core. , each core can be configured to operate in parallel, i.e., like a GPU. In addition, the number of bits that a CPU can handle in its internal arithmetic circuit and data bus is, for example, 8 bits, 16 bits, It can be 32-bit, 64-bit, etc.

[0214] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, Interrupt controller 1194, register controller 1197, timing controller It is entered into La1195.

[0215] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to trigger the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it accordingly. Generates an address and reads or writes register 1196 depending on the CPU state. .

[0216] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generator supplies an internal clock signal to the various circuits.

[0217] In the CPU shown in FIG. 31, a memory cell is provided in the register 1196. The transistor described in the above embodiment can be used as the memory cell of the memory cell 1196. Cut.

[0218] In the CPU shown in FIG. 31, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0219] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0220] (Embodiment 5) The storage device in the above embodiment is a memory card (for example, an SD card), a USB (Universal Serial Serial Bus) memory, SSD (Solid State Drive The present embodiment can be applied to various removable storage devices such as Some configuration examples of the removable storage device will be described with reference to FIG.

[0221] 32A is a schematic diagram of a USB memory. , a cap 5102, a USB connector 5103, and a substrate 5104. are housed in a housing 5101. A substrate 5104 includes a memory device and a drive circuit for the memory device. For example, the substrate 5104 is provided with a memory chip 5105, a controller The memory chip 5105 is the same as that in the second embodiment. The memory cell array 2610, the word line driver circuit 2622, and the row decoder 26 21, sense amplifier 2633, precharge circuit 2632, column decoder 2631, etc. The controller chip 5106 specifically includes a processor, a work memory, and The memory chip 5105 and the controller chip are The circuit configuration of each of the chips 5106 is not limited to the above description, but may be changed depending on the situation or occasion. For example, the word line driver circuit 2622, Row decoder 2621, sense amplifier 2633, precharge circuit 2632, column decoder The memory chip 5105 is not equipped with the controller 2631, but with the controller chip 5106. The USB connector 5103 may be an interface for connecting to an external device. It functions as a

[0222] Figure 32(B) is a schematic diagram of the external appearance of an SD card, and Figure 32(C) is a schematic diagram of the internal structure of an SD card. The SD card 5110 is a schematic diagram of the structure. The SD card 5110 includes a housing 5111, a connector 5112, and a board. A connector 5112 serves as an interface for connecting to an external device. The board 5113 is housed in a housing 5111. The board 5113 has a memory device. For example, the substrate 5113 is provided with a memory chip. The chip 5114 and controller chip 5115 are installed. 4 includes the memory cell array 2610 and the word line driver circuit 26 described in the second embodiment. 22, row decoder 2621, sense amplifier 2633, precharge circuit 2632, color The controller chip 5115 includes a processor It incorporates a processor, work memory, ECC circuit, etc. The circuit configuration of the controller chip 5115 is not limited to the above description, and may vary depending on the situation. The circuit configuration may be changed accordingly or in some cases. For example, the word line driver circuit 2622, row decoder 2621, sense amplifier 2633, precharge circuit 263 2. The column decoder 2631 is not located on the memory chip 5114 but on the controller chip 511. 5 may be incorporated.

[0223] By providing a memory chip 5114 on the back side of the substrate 5113, the SD card 5110 In addition, a wireless chip having a wireless communication function can be mounted on the substrate 5113. This allows wireless communication between an external device and the SD card 5110. This allows data to be read from and written to the memory chip 5114.

[0224] FIG. 32(D) is a schematic diagram of the external appearance of the SSD, and FIG. 32(E) is a schematic diagram of the internal structure of the SSD. The SSD 5150 includes a housing 5151, a connector 5152, and a board 5153. A connector 5152 functions as an interface for connecting to an external device. The board 5153 is housed in the housing 5151. The board 5153 includes a memory device and a For example, the substrate 5153 includes a memory chip 5154. , memory chip 5155, and controller chip 5156 are installed. The chip 5154 includes the memory cell array 2610 and the word line driver 2610 described in the second embodiment. a buffer circuit 2622, a row decoder 2621, a sense amplifier 2633, a precharge circuit 26 32, column decoder 2631, etc. are built in. There is also a memory card on the back side of the board 5153. By adding a chip 5154, the capacity of the SSD 5150 can be increased. The chip 5155 has a built-in working memory. For example, the memory chip 5155 has The controller chip 5156 includes a processor, an E CC circuits and other circuits are built in. The circuit configurations of the controller chip 5115 and the controller chip 5116 are not limited to those described above. Depending on the situation or circumstances, the circuit configuration may be changed as appropriate. The controller chip 5156 may also be provided with a memory that functions as a work memory.

[0225] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0226] (Embodiment 6) In this embodiment, an example of an electronic device to which the storage device of the above embodiment can be applied is described. This article explains:

[0227] <Notebook personal computer> FIG. 33A shows a notebook personal computer, which includes a housing 5401 and a display unit 540. 2, a keyboard 5403, a pointing device 5404, etc. The storage device can be provided in a notebook personal computer.

[0228] <Smartwatch> FIG. 33(B) shows a smart watch, which is a type of wearable terminal, and includes a housing 5901 , a display unit 5902, operation buttons 5903, an operator 5904, a band 5905, etc. The storage device of one embodiment of the present invention can be included in a smartwatch. A display device with a function as a position input device may be used as 5902. In addition, the function as a position input device can be added by providing a touch panel to the display device. Alternatively, the function as a position input device can be realized by using a photoelectric sensor, also known as a photosensor. It can also be added by providing a conversion element in the pixel section of the display device. The 5903 includes a power switch to start the smartwatch, and a smartwatch application. Buttons for operating the functions, volume adjustment buttons, or turning on or off the display 5902 In addition, the smart switch shown in FIG. The smartwatch has two operation buttons 5903. The number of operation buttons is not limited to this. The operator 5904 also functions as a crown for adjusting the time. It is used as an input interface to operate smartwatch applications. In the smart watch shown in FIG. 33(B), the operation element 590 4, but is not limited to this, and may be configured without the operator 5904. That's fine.

[0229] <Video camera> FIG. 33C shows a video camera, which includes a first housing 5801, a second housing 5802, and a display unit 5 803, operation keys 5804, a lens 5805, a connection part 5806, etc. Such a storage device can be provided in the video camera. 5805 is provided in a first housing 5801, and a display unit 5803 is provided in a second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connection part 5806. The angle between the first housing 5801 and the second housing 5802 is determined by the connection part 5806. The image on the display unit 5803 can be displayed on the first housing at the connection unit 5806. It may be configured to switch according to the angle between 5801 and the second housing 5802.

[0230] <Mobile phone> FIG. 33D shows a mobile phone having an information terminal function, which includes a housing 5501, a display unit 55 02, a microphone 5503, a speaker 5504, and an operation button 5505. The display portion 5502 may include a position input device. A display device with the function of a position input device may be used. This function can be added by providing a touch panel to the display device. The function of the position input device is to connect a photoelectric conversion element, also called a photosensor, to the image of the display device. It can also be added by providing it in the base part. Power switch, buttons to operate mobile phone applications, volume control buttons or a switch for turning on or off the display unit 5502. can be done.

[0231] In addition, the mobile phone shown in FIG. 33(D) has two operation buttons 5505. However, the number of operation buttons on a mobile phone is not limited to this. The mobile phone shown in FIG. 33(D) is equipped with a light-emitting device for use as a flashlight or illumination. The configuration may include a device.

[0232] <Television equipment> 33(E) is a perspective view showing a television device. 000, display unit 9001, speaker 9003, operation keys 9005 (power switch or including operation switches), connection terminal 9006, sensor 9007 (force, displacement, position, speed, acceleration Speed, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field , current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared measurement The storage device according to one embodiment of the present invention is provided in a television device. The television device may have a large screen, for example, 50 inches or more, or 100 It is possible to incorporate a display unit 9001 of 1 inch or more.

[0233] <Mobile object> The above-mentioned storage device can also be applied to the vicinity of the driver's seat of an automobile, which is a mobile object.

[0234] For example, FIG. 33(F) is a diagram showing the area around the windshield inside the interior of an automobile. In FIG. 33(F), a display panel 5701 attached to the dashboard and a display panel 5702 are shown. 702, a display panel 5703, and a display panel 5704 attached to the pillar are also shown. are.

[0235] The display panels 5701 to 5703 display navigation information, a speedometer, and tachometer, mileage, fuel level, gear status, air conditioning settings, and various other information. In addition, the display items and layout displayed on the display panel can be It can be changed as needed to suit the user's preferences, improving the design. The display panels 5701 to 5703 can also be used as lighting devices. be.

[0236] The display panel 5704 displays an image captured by an imaging means provided on the vehicle body. This allows the driver to compensate for the blind spot (blind spot) that is blocked by the pillar. By displaying images from the provided imaging means, blind spots can be compensated for and safety can be improved. In addition, by projecting images that complement the invisible parts, it is possible to make the sense of incongruity appear more natural. The display panel 5704 can also be used as a lighting device. can.

[0237] The storage device according to one embodiment of the present invention can be provided in a mobile object. The device is used to display images on the display panels 5701 to 5704, for example. The frame memory that temporarily stores image data and the system that drives the moving object are also used. It can be used as a storage device for storing programs.

[0238] Although not shown, the electronic devices shown in FIGS. 33(A) to 33(C), (E), and (F) The device may have a microphone and a speaker. The electronic device can be equipped with a voice input function.

[0239] Although not shown, the electronic devices shown in FIGS. 33(A), (B), (D) to (F) may be configured to include a camera.

[0240] Although not shown, the electronic devices shown in FIGS. 33(A) to 33(F) have a built-in Sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetic, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration The sensor may have a function to measure movement, smell, infrared rays, etc. In addition, the mobile phone shown in FIG. 33(D) is equipped with a sensor for detecting tilt such as a gyro or an acceleration sensor. By providing a detection device having a sensor, the orientation of the mobile phone (the mobile phone in the vertical direction) can be detected. The screen display of the display unit 5502 is adjusted to match the orientation of the mobile phone. It is possible to automatically switch depending on the

[0241] Although not shown, the electronic devices shown in FIGS. 33(A) to 33(F) can be used to identify fingerprints, veins, The configuration may include a device for acquiring biometric information such as an iris or a voiceprint. By using this, an electronic device with a biometric authentication function can be realized.

[0242] In addition, flexible substrates are used as the display units of the electronic devices shown in FIGS. Specifically, the display unit may be formed by mounting transistors, capacitors, etc., on a flexible substrate. By applying this configuration, Not only flat-surfaced housings like those shown in Figures 33(A) to 33(F), but also curved housings are available. It is possible to realize an electronic device having a housing with a surface.

[0243] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0244] (Notes regarding the present specification) The following additional notes will be given regarding the description of each component in the above embodiment.

[0245] <Additional Notes Regarding One Aspect of the Present Invention Described in the Embodiments> The configurations shown in each embodiment may be appropriately combined with the configurations shown in other embodiments to realize the present invention. In addition, in one embodiment, multiple configuration examples may be shown. In this case, the configuration examples can be appropriately combined with each other.

[0246] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the embodiment and one or more other embodiments The content described (or a part of the content) is applied to, combined with, or at least one of the contents. or replacement, etc.

[0247] The contents described in the embodiments are explained using various drawings in each embodiment. This refers to the content stated in the specification or the content stated using the text in the specification.

[0248] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. In the embodiment, another figure (or a part thereof) and one or more other embodiments may be used. At least one of the drawings (or a part thereof) described in the embodiment is combined with By adding more, more figures can be constructed.

[0249] <Note on ordinal numbers> In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of constituent elements. Therefore, the number of components is not limited. The order of the components is not limited. The element referred to as "first" in one embodiment may be used in other embodiments or in the claims. In addition, for example, the second component may be the component referred to as "second" in the specification. A component referred to as "first" in one embodiment may be used in other embodiments, or It may be omitted in the claims.

[0250] <Notes regarding the description of the drawings> The embodiments are described with reference to the drawings. It is possible to implement the invention in various ways, and the form may be changed without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the mode and details of the present invention. The present invention should not be construed as being limited to the description of the embodiment. In the structure of the invention, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. The same is used in common between the two, and the repeated explanation will be omitted.

[0251] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship is used for convenience in explaining the relationship with reference to the drawings. The terms and expressions indicating the arrangement may be changed as appropriate depending on the direction in which each configuration is depicted. The present invention is not limited to the above description and can be rephrased appropriately depending on the situation.

[0252] In addition, the terms "above" and "below" refer to the positional relationship of the components directly above or below and directly connected to each other. For example, if the expression is "electrode B on insulating layer A," The electrode B does not need to be formed directly on the insulating layer A, and the insulating layer A and the electrode B This does not exclude the inclusion of other components in between.

[0253] In addition, in the drawings, the size, layer thickness, and area are shown at arbitrary scales for the convenience of explanation. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely schematic illustrations for the purpose of clarity, and are not limited to the shapes or values ​​shown in the drawings. fluctuations in signal, voltage, or current due to noise, or signal due to timing deviations These may include variations in signal, voltage, or current.

[0254] In addition, in the drawings, some components are shown in perspective views and the like in order to clarify the drawings. The description of the element may be omitted.

[0255] In addition, in the drawings, the same elements or elements having similar functions, elements made of the same material, or In some cases, the same reference numerals may be used to designate elements that are formed at the same time, and repeated explanations thereof will be omitted. It may be omitted.

[0256] <Notes regarding possible paraphrases> In this specification and the like, when describing the connection relationship of a transistor, The first electrode or the first terminal is referred to as the "source or drain" (or the first electrode or the first terminal). The other of the source and drain is referred to as the "other of the source or drain" (or second electrode, or second terminal). This means that the source and drain of a transistor are This is because the names of the source and drain of a transistor change depending on the operating conditions. In this case, the term source (drain) terminal, source (drain) electrode, etc. may be used appropriately depending on the situation. In this specification, the two terminals other than the gate are referred to as the first terminal and the second terminal. In this specification, etc., The channel formation region is the region where a channel is formed by applying a potential to the gate. The formation of this region allows current to flow between the source and drain.

[0257] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0258] Furthermore, when the transistor described in this specification has two or more gates (this configuration These gates are called the first gate and the second gate. It is sometimes called a front gate or a back gate. " can be simply interchanged with the word "gate." The phrase "backgate" is interchangeable with the phrase "gate." The bottom gate is a gate electrode formed on a lower side than the channel formation region during the manufacture of a transistor. The term "top gate" refers to a terminal that is formed first during the manufacturing of a transistor. The terminal is formed after the channel forming region.

[0259] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably with "electrodes" and "wiring." This also includes cases where the wiring is formed integrally.

[0260] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. It is the potential difference from the reference potential. For example, the reference potential is the ground potential (earth potential). If we use the term "potential"), we can translate voltage into potential. Ground potential is not necessarily 0V. It does not necessarily mean that the potential is relative, and depending on the reference potential, The potential applied to wiring etc. may be changed.

[0261] In this specification, the terms "film" and "layer" may be used in some cases or depending on the situation. For example, the term "conductive layer" can be used interchangeably with "conductive layer" It may be possible to change the term to "insulating film" or, for example, The term may be changed to "insulating layer" in some cases. Alternatively, depending on the situation, words such as "film" and "layer" may be replaced with other terms. For example, the term "conductive layer" or "conductive film" can be changed to "conductor." In some cases, it may be possible to change the term to, for example, "insulating layer" or "insulating film." It may be possible to change the term to "insulator."

[0262] In this specification, terms such as "wiring," "signal line," and "power line" may be used in some cases. For example, "wiring" and "wiring" can be interchangeable. In some cases, it may be possible to change the term "signal line" to "signal line." It may be possible to change the term "wiring" to a term such as "power line." , and vice versa, terms such as "signal line" and "power line" will be changed to the term "wiring." It may be possible to change terms such as "power line" to terms such as "signal line". The reverse is also true, and terms such as "signal line" may be used interchangeably with "power line" In some cases, it may be possible to change the term to "potential" applied to the wiring. Changing the term to "signal" or similar, as the case may be, or depending on the situation. And vice versa, terms such as "signal" may be used in conjunction with "potential." It may be possible to change it to a different word.

[0263] <Notes on definitions of terms> The following provides definitions of terms used in the above embodiments.

[0264] <<About impurities in semiconductors>> The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor layer. Elements with less than 0.1 atomic % are impurities. The formation of DOS (Density of States) and the carrier mobility The semiconductor may become an oxide semiconductor, and the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1 and Group 2. There are elements, group 13 elements, group 14 elements, group 15 elements, and transition metals other than the main component. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, In the case of oxide semiconductors, for example, impurities such as hydrogen can be mixed in. In addition, if the semiconductor is a silicon layer, the characteristics of the semiconductor may be affected. The impurities that change the value of the valence band include, for example, oxygen, group 1 elements excluding hydrogen, group 2 elements, and group 1 elements. These include Group 3 elements and Group 15 elements.

[0265] <<About the switch>> In this specification, a switch is a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It is a device that has the function of controlling whether or not current flows by entering a state where it is in a switched state. A switch is a device that has the function of selecting and switching the path through which current flows.

[0266] For example, an electrical switch or a mechanical switch can be used. The switch is not limited to a specific one as long as it can control the current.

[0267] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these There is.

[0268] When a transistor is used as a switch, the "conduction state" of the transistor is The state in which the source and drain electrodes of a transistor can be considered to be electrically shorted is called Also, the "non-conducting state" of a transistor means that the source electrode and drain electrode of the transistor are This refers to a state in which the electrodes can be considered to be electrically disconnected. When the transistor is operated as a transistor having a polarity (conductivity type), there is no particular limitation.

[0269] An example of a mechanical switch is a digital micromirror device (DMD). In 2013, a switch using MEMS (microelectromechanical systems) technology was developed. The switch has a mechanically movable electrode, and when the electrode moves, Therefore, the device operates by controlling conduction and non-conduction.

[0270] <<About connection>> In this specification, when it is stated that X and Y are connected, it means that X and Y are electrically connected. There are cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, a predetermined connection relationship, for example, a diagram or It is not limited to the connection relationships shown in the text, but also includes connection relationships other than those shown in the drawings or text. It shall be.

[0271] X, Y, etc. used here refer to objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, etc.). , conductive film, layer, etc.).

[0272] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. It has a function to control whether or not water is flushed.

[0273] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the signal potential level, etc. ), voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if X is transmitted to Y.

[0274] When it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is inserted between X and Y) X and Y are functionally connected (i.e., there is no connection between X and Y) When X and Y are connected directly, the two are functionally connected via another circuit. (That is, when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it is not simply The same applies if the document is explicitly stated as being connected to the

[0275] For example, if the source (or first terminal, etc.) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. It may be electrically connected to Y through Z2 (or not), or the source of the transistor may be The first terminal (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. When a part of Z2 is directly connected to Y, and another part of Z2 is directly connected to Y, it can be expressed as follows: It can be manifested.

[0276] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" 2 terminals) are electrically connected to each other, and X, the source (or The first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and the Y are electrically connected in this order. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Or, "X is the source (or first terminal, etc.) of the transistor. ) and the drain (or second terminal, etc.) of the transistor Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor , Y are provided in this connection order." By using this expression, the order of connections in the circuit configuration can be specified. A distinction is made between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above expressions. Here, X, Y, Z1, and Z2 are the coordinates of the object (for example, the device, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0277] Note that the circuit diagram shows independent components as if they are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0278] <<About parallel and perpendicular>> In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to a state in which two lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Explanation of symbols]

[0279] BGL wiring ER wiring RBL Wiring RBL1 wiring RBL2 wiring RWL wiring WBL wiring WBL1 wiring WBL2 wiring WWL Wiring WWL_D Wiring 10 Memory Modules 100 laminate 101A Insulator 101B Insulator 101C Insulator 101D Insulator 101E Insulator 102 Insulator 103 Insulator 104 Insulator 105 Insulator 131A Conductor 131B Conductor 132A Conductor 132B Conductors 133 Conductors 133a Conductor 133b Conductor 133c conductor 134 Conductors 151 Semiconductors 151a area 151b area 151c area 152 Semiconductors 153 Semiconductors 153a Semiconductors 153b Semiconductors 181A area 181B area 182A area 182B area 183A area 183B area 191 Opening 192A Recess 192B Recess 193A Recess 193B Recess 194A Recess 194B Recess 194C Recess 1000 logic layers 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1700 board 1701 Element isolation layer 1712 Conductors 1730 Conductors 1790 gate electrode 1792 wells 1793 Channel formation region 1794 Low concentration impurity region 1795 High concentration impurity region 1796 Conductive region 1797 Gate insulating film 1798 Sidewall insulating layer 1799 Sidewall insulating layer 2000 memory tier 2600 storage device 2601 Peripheral circuit 2610 Memory Cell Array 2621 Low Decoder 2622 Word Line Driver Circuit 2630 Bit Line Driver Circuit 2630A bit line driver circuit 2630B bit line driver circuit 2631 Column Decoder 2632 Precharge Circuit 2633 Sense Amplifier 2634 circuits 2640 output circuit 2660 Control Logic Circuit 5100 USB memory 5101 Housing 5102 Cap 5103 USB connector 5104 Circuit Board 5105 memory chip 5106 controller chip 5110 SD card 5111 Case 5112 Connector 5113 Circuit Board 5114 memory chip 5115 controller chip 5150 SSD 5151 Case 5152 Connector 5153 Circuit Board 5154 memory chip 5155 memory chip 5156 controller chip 5401 Housing 5402 Display section 5403 Keyboard 5404 Pointing Device 5501 Housing 5502 Display section 5503 Microphone 5504 Speaker 5505 Operation button 5701 Display panel 5702 Display panel 5703 Display Panel 5704 Display panel 5801 Housing 5802 Housing 5803 Display section 5804 Operation key 5805 Lens 5806 Connection 5901 Housing 5902 Display section 5903 Operation button 5904 Operator 5905 Band 9000 chassis 9001 Display section 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor

Claims

[Claim 1] a first to n-th memory cell (n is an integer of 2 or more), a selection transistor, and a first wiring; the first to n-th memory cells are connected in series; one of the source and the drain of the selection transistor is electrically connected to the first wiring; the other of the source and the drain of the select transistor is electrically connected to a first terminal of the first memory cell; The second terminal of the nth memory cell is electrically connected to the first wiring.

Images