Sic semiconductor device

Abstract

To provide a SiC semiconductor device capable of suppressing temporal degradation of a gate threshold voltage Vth.SOLUTION: The SiC semiconductor device includes: a SiC semiconductor layer 102 including an active region 106 and an outer region 107 outside the active region; an impurity region 171 of a second conductivity type formed in a surface layer portion of the outer region and forming a pn-junction diode D with a drift region 127; and a contact region of the second conductivity type formed in a surface layer portion of the active region, located on a side opposite to a trench with respect to a source region, and having an impurity concentration of the second conductivity type of 1.0×1020 cm-3 or less.SELECTED DRAWING: Figure 28

Description

[Technical Field]

[0001] The present invention relates to a SiC semiconductor device. [Background technology]

[0002] Patent Document 1 describes a semiconductor device including an n-type SiC semiconductor layer, a trench, a gate insulating layer, a gate electrode, a p-type body region, and an n + The source region and p + The present invention discloses a SiC semiconductor device including a contact region of a p-type. A trench is formed in a main surface of a SiC semiconductor layer. A gate electrode is buried in the trench with a gate insulating layer sandwiched therebetween. A body region is formed on a side of the trench in a surface layer portion of the main surface. A source region is formed on a side of the trench in a surface layer portion of the body region. A contact region is formed in a region on the opposite side of the trench from the source region in the surface layer portion of the body region. The contact region has a p-type impurity concentration that exceeds the p-type impurity concentration of the body region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-235546 Summary of the Invention [Problem to be solved by the invention]

[0004] SiC semiconductor devices have a problem of degradation of the gate threshold voltage Vth over time due to long-term use. The inventors of the present application have studied the impurity concentration in the contact region and discovered that the time-dependent characteristics of the gate threshold voltage Vth vary depending on the impurity concentration in the contact region.

[0005] An embodiment of the present invention provides a SiC semiconductor device capable of suppressing deterioration of the gate threshold voltage Vth over time. [Means for solving the problem]

[0006] an SiC semiconductor layer having a first main surface on one side and a second main surface on the other side, the SiC semiconductor layer including an active region and an outer region outside the active region; a trench formed in the first main surface in the active region; a gate insulating layer formed on an inner wall of the trench; a gate electrode embedded in the trench with the gate insulating layer sandwiched between the trench and the source region; a first conductivity type source region formed in a surface layer portion of the first main surface in the active region and located on a side of the trench; a second conductivity type body region formed in a surface layer portion of the first main surface in the active region and located in a region on the second main surface side with respect to the source region; a first conductivity type drift region formed in a surface layer portion of the first main surface in the active region and the outer region, the first conductivity type drift region including a portion located in a region on the second main surface side with respect to the body region; an impurity region of the second conductivity type formed in the surface layer portion of the first main surface in the outer region, forming a pn junction diode with the drift region; 20 cm -3 and a second conductivity type contact region having the following second conductivity type impurity concentration:

[0007] This SiC semiconductor device can suppress deterioration of the gate threshold voltage Vth over time.

[0008] The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a unit cell of a 4H—SiC single crystal. [Figure 2] FIG. 2 is a plan view showing the silicon surface of the unit cell shown in FIG. [Figure 3]FIG. 3 is a plan view showing the SiC semiconductor device according to the first embodiment of the present invention. [Figure 4] FIG. 4 is a plan view of FIG. 3 with the resin layer removed. [Figure 5] FIG. 5 is an enlarged view of a region V shown in FIG. 4, and is an enlarged view for explaining the structure of the first main surface of the SiC semiconductor layer. [Figure 6] FIG. 6 is a cross-sectional perspective view of region VI shown in FIG. 5, illustrating the structure of the gate trench with the structure on the first main surface of the SiC semiconductor layer removed. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 9A] FIG. 9A is a graph for explaining a first example of the p-type impurity concentration of the contact region shown in FIG. [Figure 9B] FIG. 9B is a graph for explaining the p-type impurity concentration of the contact region according to the reference example. [Figure 10] FIG. 10 is a graph for explaining the time characteristics of the gate threshold voltage Vth. [Figure 11] FIG. 11 is a graph for explaining a second example of the p-type impurity concentration in the contact region shown in FIG. [Figure 12] FIG. 12 is a graph for explaining the time characteristics of the gate threshold voltage Vth. [Figure 13] FIG. 13 is a plan view of a region corresponding to FIG. 5, showing a SiC semiconductor device according to a second embodiment of the present invention. [Figure 14] FIG. 14 is a plan view of a region corresponding to FIG. 5, showing a SiC semiconductor device according to a third embodiment of the present invention. [Figure 15] FIG. 15 is a cross-sectional view taken along line XV-XV shown in FIG. [Figure 16] FIG. 16 is a plan view of a region corresponding to FIG. 14, showing the SiC semiconductor device according to the fourth embodiment of the present invention. [Figure 17] FIG. 17 is a cross-sectional view of a region corresponding to FIG. 15, showing the SiC semiconductor device according to the fifth embodiment of the present invention. [Figure 18] FIG. 18 is a plan view of a region corresponding to FIG. 14, showing the SiC semiconductor device according to the sixth embodiment of the present invention. [Figure 19] FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. [Figure 20] FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. [Figure 21] FIG. 21 is a cross-sectional view of a region corresponding to FIG. 19, showing the SiC semiconductor device according to the seventh embodiment of the present invention. [Figure 22] FIG. 22 is a plan view showing a SiC semiconductor device according to the eighth embodiment of the present invention. [Figure 23] FIG. 23 is a plan view of FIG. 22 with the resin layer removed. [Figure 24] FIG. 24 is an enlarged view of region XXIV shown in FIG. 23, and is a view for explaining the structure of the first main surface of the SiC semiconductor layer. [Figure 25] FIG. 25 is a cross-sectional view taken along line XXV-XXV shown in FIG. [Figure 26] 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. [Figure 27] FIG. 27 is an enlarged view of area XXVII shown in FIG. [Figure 28] FIG. 28 is a cross-sectional view taken along line XXVIII-XXVIII shown in FIG. [Figure 29] FIG. 29 is an enlarged view of area XXIX shown in FIG. [Figure 30] FIG. 30 is a graph for explaining the sheet resistance. [Figure 31] FIG. 31 is an enlarged view of a region corresponding to FIG. 24, showing the SiC semiconductor device according to the ninth embodiment of the present invention. [Figure 32]32 is a cross-sectional view taken along line XXXII-XXXII shown in FIG. [Figure 33] FIG. 33 is an enlarged view of a region corresponding to FIG. 27, showing the SiC semiconductor device according to the tenth embodiment of the present invention. [Figure 34] FIG. 34 is an enlarged view of a region corresponding to FIG. 24, showing the SiC semiconductor device according to the eleventh embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Fig. 1 is a diagram showing a unit cell of a 4H-SiC single crystal (hereinafter simply referred to as a "unit cell") Fig. 2 is a plan view showing the silicon surface of the unit cell shown in Fig. 1.

[0011] In the embodiments of the present invention, an example in which a 4H-SiC single crystal is applied will be described as an example of a hexagonal SiC single crystal. The hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal, depending on the period of the atomic arrangement. The embodiments of the present invention do not exclude polytypes other than 4H-SiC single crystal.

[0012] 1 and 2, the unit cell includes a tetrahedral structure in which one Si atom is bonded to four C atoms in a tetrahedral arrangement. The unit cell has an atomic arrangement in which the tetrahedral structures are stacked in a four-layer period. The unit cell has a hexagonal prism structure with hexagonal silicon faces, hexagonal carbon faces, and six side faces connecting the silicon faces and the carbon faces.

[0013] The silicon surface is a surface terminated by Si atoms. In the silicon surface, one Si atom is located at each of the six vertices of a hexagon, and one Si atom is located at the center of the hexagon. The carbon surface is a surface terminated by C atoms. In the carbon surface, one C atom is located at each of the six vertices of a hexagon, and one C atom is located at the center of the hexagon.

[0014] The crystal plane of the unit cell is defined by four coordinate axes (a1, a2, a3, c), including the a1, a2, a3, and c axes. Of the four coordinate axes, the value of a3 is -(a1 + a2). Below, the structure of 4H-SiC single crystal is explained based on the silicon plane.

[0015] The a1, a2, and a3 axes are set along the direction of the arrangement of the nearest Si atoms (hereinafter simply referred to as "nearest-neighbor atomic direction") with the Si atom located at the center as the reference in a plan view of the silicon surface seen from the c-axis. The a1, a2, and a3 axes are set at angles shifted by 120° from each other, following the arrangement of the Si atoms.

[0016] The c-axis is set in the normal direction of the silicon surface, with the Si atom located at the center as the reference. The silicon surface is the (0001) surface. The carbon surface is the (000-1) surface. The side surface of the hexagonal prism includes six crystal planes aligned along the nearest-neighbor atomic direction in a planar view of the silicon surface seen from the c-axis. More specifically, the side surface of the hexagonal prism includes six crystal planes formed by the nearest-neighbor Si atoms.

[0017] In a plan view of the silicon surface viewed from the c-axis, the side surfaces of the unit cell include, clockwise from the tip of the a1 axis, the (1-100), (0-110), (-1010), (-1100), (01-10), and (10-10) planes.

[0018] In a unit cell, the diagonal planes that do not pass through the center include six crystal planes that are aligned along the intersecting direction of the nearest-neighbor atom in a planar view of the silicon surface from the c-axis. When viewed from the central Si atom, the intersecting direction of the nearest-neighbor atom is perpendicular to the nearest-neighbor atom. More specifically, in a hexagonal prism, the diagonal planes that do not pass through the center include six crystal planes formed by Si atoms that are not nearest-neighbor.

[0019] Diagonal planes that do not pass through the center of the unit cell include the (11-20), (1-210), (-2110), (-1-120), (-12-10), and (2-1-10) planes in a plan view of the silicon surface from the c-axis.

[0020] The crystal directions of the unit cell are defined by the normal directions of the crystal planes. The normal direction of the (1-100) plane is the [1-100] direction. The normal direction of the (0-110) plane is the [0-110] direction. The normal direction of the (-1010) plane is the [-1010] direction. The normal direction of the (-1100) plane is the [-1100] direction. The normal direction of the (01-10) plane is the [01-10] direction. The normal direction of the (10-10) plane is the [10-10] direction.

[0021] The normal direction of the (11-20) plane is the [11-20] direction. The normal direction of the (1-210) plane is the [1-210] direction. The normal direction of the (-2110) plane is the [-2110] direction. The normal direction of the (-1-120) plane is the [-1-120] direction. The normal direction of the (-12-10) plane is the [-12-10] direction. The normal direction of the (2-1-10) plane is the [2-1-10] direction.

[0022] Hexagonal crystals have six-fold symmetry and have equivalent crystal planes and directions every 60°. For example, the (1-100), (0-110), (-1010), (-1100), (01-10), and (10-10) planes form equivalent crystal planes. Also, the (11-20), (1-210), (-2110), (-1-120), (-12-10), and (2-1-10) planes form equivalent crystal planes.

[0023] The [1-100], [0-110], [-1010], [-1100], [01-10], and [10-10] directions are equivalent crystal directions, while the [11-20], [1-210], [-2110], [-1-120], [-12-10], and [2-1-10] directions are equivalent crystal directions.

[0024] The

[0001] and [000-1] directions are called c-axes. The (0001) and (000-1) planes are called c-planes. The [11-20] and [-1-120] directions are called a-axes. The (11-20) and (-1-120) planes are called a-planes. The [1-100] and [-1100] directions are called m-axes. The (1-100) and (-1100) planes are called m-planes.

[0025] Fig. 3 is a plan view showing the SiC semiconductor device 1 according to the first embodiment of the present invention, and Fig. 4 is a plan view showing Fig. 3 from which the resin layer 17 has been removed.

[0026] 3 and 4, SiC semiconductor device 1 includes a SiC semiconductor layer 2. SiC semiconductor layer 2 includes a 4H—SiC single crystal as an example of a SiC single crystal made of a hexagonal crystal. SiC semiconductor layer 2 is formed in the shape of a rectangular parallelepiped chip.

[0027] The SiC semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4. In this embodiment, the first main surface 3 and the second main surface 4 are formed in a quadrangular shape (more specifically, a square shape) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0028] The first main surface 3 is an element formation surface on which a semiconductor element is formed. The second main surface 4 may be a ground surface having grinding marks. In this embodiment, the first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. The first main surface 3 faces the (0001) plane (silicon plane). The second main surface 4 faces the (000-1) plane (carbon plane) of the SiC single crystal. The first main surface 3 has an off-angle θ inclined at an angle of 10° or less in the [11-20] direction with respect to the (0001) plane of the SiC single crystal. The normal direction Z is inclined by the off-angle θ with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0029] The off angle θ may be 0° or more and 5.0° or less. The off angle θ may be set in the range of 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, 2.5° or more and 3.0° or less, 3.0° or more and 3.5° or less, 3.5° or more and 4.0° or less, 4.0° or more and 4.5° or less, or 4.5° or more and 5.0° or less. The off angle θ may be more than 0° and less than 4.0°.

[0030] The off angle θ may be set in the range of 3.0° to 4.5°. In this case, the off angle θ is preferably set in the range of 3.0° to 3.5°, or 3.5° to 4.0°. The off angle θ may be set in the range of 1.5° to 3.0°. In this case, the off angle θ is preferably set in the range of 1.5° to 2.0°, or 2.0° to 2.5°.

[0031] More specifically, the side surfaces 5A to 5D include a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D. In this embodiment, the first side surface 5A and the third side surface 5C extend along a first direction X and face a second direction Y that intersects with the first direction X. In this embodiment, the second side surface 5B and the fourth side surface 5D extend along the second direction Y and face the first direction X. More specifically, the second direction Y is a direction perpendicular to the first direction X. The length of each of the side surfaces 5A to 5D may be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0032] The side surfaces 5A to 5D may each be a smooth cleavage plane facing the crystal plane of the SiC single crystal. The side surfaces 5A to 5D may each be a ground surface having grinding marks. In this embodiment, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

[0033] That is, the first side surface 5A and the third side surface 5C are formed by the a-plane of the SiC single crystal and face each other in the a-axis direction. The first side surface 5A is formed by the (-1-120) plane of the SiC single crystal. The third side surface 5C is formed by the (11-20) plane of the SiC single crystal. The second side surface 5B and the fourth side surface 5D are formed by the m-plane of the SiC single crystal and face each other in the m-axis direction. The second side surface 5B is formed by the (-1100) plane of the SiC single crystal. The fourth side surface 5D is formed by the (1-100) plane of the SiC single crystal.

[0034] When the normal to first main surface 3 is taken as a reference, first side surface 5A and third side surface 5C may form an inclined surface that is inclined toward the c-axis direction (0001 direction) of the SiC single crystal with respect to the normal. In other words, when the normal to first main surface 3 is set to 0°, first side surface 5A and third side surface 5C may be inclined with respect to the normal at an angle corresponding to off angle θ. The angle corresponding to off angle θ may be equal to off angle θ or may be an angle greater than 0° and less than off angle θ.

[0035] The SiC semiconductor layer 2 includes an active region 6 and an outer region 7. The active region 6 is a region in which a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed. In plan view, the active region 6 is formed in the center of the SiC semiconductor layer 2, spaced apart from the side surfaces 5A to 5D toward the inner region. In plan view, the active region 6 is formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D.

[0036] The outer region 7 is a region outside the active region 6. The outer region 7 is formed in a region between the side surfaces 5A to 5D and the active region 6. The outer region 7 is formed in an endless shape (a quadrangular ring in this embodiment) surrounding the active region 6 in a plan view.

[0037] The SiC semiconductor device 1 includes a gate principal surface electrode layer 8 as one of the first principal surface electrode layers formed on the first principal surface 3. A gate voltage is applied to the gate principal surface electrode layer 8. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). The gate principal surface electrode layer 8 includes a gate pad 9 and gate fingers 10. The gate pad 9 and the gate fingers 10 are arranged in the active region 6.

[0038] The gate pad 9 is formed in a region along the first side surface 5A in a plan view. In this embodiment, the gate pad 9 is formed in a region along the center of the first side surface 5A in a plan view. The gate pad 9 may be formed in a quadrangular shape in a plan view. The gate pad 9 may be formed in a region along a corner connecting any two of the side surfaces 5A to 5D in a plan view.

[0039] The gate fingers 10 are drawn out from the gate pad 9 and extend in a strip shape along the periphery of the active region 6. In this embodiment, the gate fingers 10 are formed along the three side surfaces 5A, 5B, and 5D, and define the inner region of the active region 6 from three directions. The gate fingers 10 have a pair of open ends 11 and 12. The pair of open ends 11 and 12 are formed in a region facing the gate pad 9 with the inner region of the active region 6 in between. In this embodiment, the pair of open ends 11 and 12 are formed in a region along the third side surface 5C.

[0040] The SiC semiconductor device 1 includes a source main surface electrode layer 13 as one of the first main surface electrode layers formed on the first main surface 3. A source voltage is applied to the source main surface electrode layer 13. The source voltage may be a reference voltage (e.g., a GND voltage). In this embodiment, the source main surface electrode layer 13 includes a source pad 14, a source lead-out wiring 15, and a source connection portion 16.

[0041] The source pad 14 is formed in the active region 6 at a distance from the gate main surface electrode layer 8. The source pad 14 covers a C-shaped region (an inverted C-shape in FIGS. 3 and 4) defined by the gate pad 9 and the gate fingers 10. The source pad 14 is formed in a C-shape (an inverted C-shape in FIGS. 3 and 4) in plan view.

[0042] The source lead-out line 15 is formed in the outer region 7. The source lead-out line 15 extends in a strip shape along the active region 6. In this embodiment, the source lead-out line 15 is formed in an endless shape (a quadrangular ring shape in this embodiment) surrounding the active region 6 in a plan view. The source lead-out line 15 is electrically connected to the SiC semiconductor layer 2 in the outer region 7.

[0043] The source connection portion 16 connects the source pad 14 and the source lead-out line 15. The source connection portion 16 is provided in the region between the pair of open ends 11, 12 of the gate finger 10. The source connection portion 16 extends from the source pad 14 across the boundary region between the active region 6 and the outer region 7 and is connected to the source lead-out line 15.

[0044] The MISFET formed in the active region 6 includes an npn-type parasitic bipolar transistor due to its structure. When an avalanche current generated in the outer region 7 flows into the active region 6, the parasitic bipolar transistor turns on. In this case, there is a possibility that the control of the MISFET becomes unstable due to, for example, latch-up.

[0045] Therefore, in the SiC semiconductor device 1, an avalanche current absorption structure is formed that absorbs the avalanche current generated in the outer region 7 by utilizing the structure of the source principal surface electrode layer 13. More specifically, the avalanche current generated in the outer region 7 is absorbed by the source lead-out wiring 15. The avalanche current absorbed by the source lead-out wiring 15 reaches the source pad 14 via the source connection portion 16.

[0046] If a conductor (e.g., a bonding wire) for external connection is connected to the source pad 14, the avalanche current is extracted by this conductor. This prevents the parasitic bipolar transistor from turning on due to unwanted current generated in the outer region 7. This prevents latch-up, thereby improving the stability of MISFET control.

[0047] The SiC semiconductor device 1 includes a resin layer 17 formed on the first main surface 3. In FIG. 3, the resin layer 17 is indicated by hatching. The resin layer 17 may include a negative-type or positive-type photosensitive resin. In this embodiment, the resin layer 17 includes polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 17 may also include polyimide as an example of a negative-type photosensitive resin.

[0048] The resin layer 17 selectively covers the gate principal surface electrode layer 8 and the source principal surface electrode layer 13. The resin layer 17 includes a gate pad opening 18 and a source pad opening 19. The gate pad opening 18 exposes the gate pad 9. The source pad opening 19 exposes the source pad 14.

[0049] The peripheral edge portion 17a of the resin layer 17 is formed at a distance inward from the side surfaces 5A to 5D. As a result, the peripheral edge portion 17a of the resin layer 17 defines a dicing street DS between the side surfaces 5A to 5D in a plan view, exposing the peripheral edge portion of the SiC semiconductor layer 2. The dicing street DS eliminates the need to physically cut the resin layer 17. Therefore, the SiC semiconductor device 1 can be smoothly cut out from one SiC semiconductor wafer. Furthermore, the insulation distance from the side surfaces 5A to 5D can be increased.

[0050] The width of the dicing street DS may be 1 μm or more and 25 μm or less. The width of the dicing street DS is the width in a direction perpendicular to the direction in which the dicing street DS extends. The width of the dicing street DS may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less.

[0051] Fig. 5 is an enlarged view of region V shown in Fig. 4, and is an enlarged view for explaining the structure of first main surface 3. Fig. 6 is a cross-sectional perspective view for explaining the structure of gate trench 32, with the structure on first main surface 3 removed. Fig. 7 is a cross-sectional view taken along line VII-VII shown in Fig. 5. Fig. 8 is a cross-sectional view taken along line VIII-VIII shown in Fig. 3.

[0052] 5 to 8, in this embodiment, the SiC semiconductor layer 2 is + The MISFET has a layered structure including an n-type SiC semiconductor substrate 21 and an n-type SiC epitaxial layer 22. The SiC semiconductor substrate 21 is formed as a drain region 24 of the MISFET. The SiC epitaxial layer 22 is formed as a drift region 25 of the MISFET. The SiC semiconductor substrate 21 forms a second main surface 4. The SiC epitaxial layer 22 forms a first main surface 3. The SiC semiconductor substrate 21 and the SiC epitaxial layer 22 form side surfaces 5A to 5D.

[0053] The n-type impurity concentration of the SiC epitaxial layer 22 is equal to or lower than the n-type impurity concentration of the SiC semiconductor substrate 21. More specifically, the n-type impurity concentration of the SiC epitaxial layer 22 is lower than the n-type impurity concentration of the SiC semiconductor substrate 21. The n-type impurity concentration of the SiC semiconductor substrate 21 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The n-type impurity concentration of the SiC epitaxial layer 22 may be 1.0×10 or less. 15 cm -3 Over 1.0 x 10 18 cm-3 It may be the following:

[0054] The thickness of the SiC semiconductor substrate 21 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor substrate 21 may be 1 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, 500 μm or more and 600 μm or less, 600 μm or more and 700 μm or less, 700 μm or more and 800 μm or less, 800 μm or more and 900 μm or less, or 900 μm or more and 1000 μm or less. The thickness of the SiC semiconductor substrate 21 is preferably 10 μm or more and 150 μm or less. Thinning the SiC semiconductor substrate 21 shortens the current path, thereby reducing the resistance value.

[0055] The thickness of the SiC epitaxial layer 22 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 22 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, or 90 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 22 is preferably less than the thickness of the SiC semiconductor substrate 21. The thickness of the SiC epitaxial layer 22 is preferably 5 μm or more and 15 μm or less.

[0056] The SiC semiconductor device 1 includes a drain electrode layer 23 as a second principal surface electrode layer formed on the second principal surface 4. The drain electrode layer 23 forms an ohmic contact with the second principal surface 4. A drain voltage is applied to the drain electrode layer 23. In the off state, the maximum voltage that can be applied between the source principal surface electrode layer 13 and the drain electrode layer 23 may be 1000 V or more and 10000 V or less.

[0057] The drain electrode layer 23 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The drain electrode layer 23 may have a single layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The drain electrode layer 23 may have a layered structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are stacked in any manner. The drain electrode layer 23 may have a layered structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in this order from the second main surface 4.

[0058] The SiC semiconductor device 1 includes a p-type body region 31 formed in a surface layer portion of the first main surface 3 in the active region 6. In this embodiment, the body region 31 is formed over the entire area of ​​the first main surface 3 that forms the active region 6. In other words, the body region 31 defines the active region 6.

[0059] The peak value of the p-type impurity concentration of the body region 31 is 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 The peak value means the maximum value of the concentration gradient (the same applies hereinafter). When multiple maximum values ​​appear in the concentration gradient, the peak value means the maximum value with the highest numerical value among the multiple maximum values. The lower limit of the peak value of the p-type impurity concentration in the body region 31 is 1.0×10 18 cm -3 It is preferable that this is equal to or greater than this.

[0060] 5 to 7, SiC semiconductor device 1 includes gate trenches 32 (trench) formed in first main surface 3 in active region 6. In this embodiment, gate trenches 32 are formed in a lattice shape in plan view. Gate trenches 32 penetrate body region 31 and reach drift region 25.

[0061] The gate trench 32 includes sidewalls and a bottom wall. The sidewalls of the gate trench 32 are formed by the m-plane and a-plane of the SiC single crystal. That is, the sidewalls of the gate trench 32 are formed by the (11-20) plane, the (1-100) plane, the (-1-120) plane, and the (-1100) plane.

[0062] More specifically, the gate trench 32 includes a plurality of first gate trenches 33 and a plurality of second gate trenches 34. The plurality of first gate trenches 33 are each formed in a band shape extending along a first direction X (the m-axis direction of the SiC single crystal) and are formed at intervals in a second direction Y (the a-axis direction of the SiC single crystal). The plurality of first gate trenches 33 are formed in a stripe shape extending along the first direction X in a plan view.

[0063] The sidewalls forming the long sides of each first gate trench 33 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of each first gate trench 33 are formed by the m-plane of the SiC single crystal.

[0064] The second gate trenches 34 are formed at intervals in the first direction X (the m-axis direction of the SiC single crystal) and are each formed in a band shape extending along the second direction Y (the a-axis direction of the SiC single crystal). The second gate trenches 34 are formed in a stripe shape extending along the second direction Y in a plan view.

[0065] The sidewalls forming the long sides of each second gate trench 34 are formed by the m-plane of the SiC single crystal. The sidewalls forming the short sides of each second gate trench 34 are formed by the a-plane of the SiC single crystal.

[0066] The plurality of second gate trenches 34 intersect with the plurality of first gate trenches 33. This forms one gate trench 32 having a lattice shape in plan view. The gate trench 32 may be formed in a honeycomb shape, which is one embodiment of the lattice shape, in plan view.

[0067] The sidewalls of the gate trench 32 may extend along the normal direction Z. The sidewalls of the gate trench 32 may be formed substantially perpendicular to the first main surface 3. The angle that the sidewalls of the gate trench 32 form with the first main surface 3 in the SiC semiconductor layer 2 may be not less than 90° and not more than 95° (for example, not less than 91° and not more than 93°). The gate trench 32 may be formed in a tapered shape such that the bottom area is less than the opening area.

[0068] The bottom wall of the gate trench 32 is located in the drift region 25 (SiC epitaxial layer 22). The bottom wall of the gate trench 32 faces the c-plane of the SiC single crystal. The bottom wall of the gate trench 32 has an off angle θ inclined in the [11-20] direction with respect to the (0001) plane of the SiC single crystal. The bottom wall of the gate trench 32 may be formed parallel to the first main surface 3. The bottom wall of the gate trench 32 may be formed in a convex curved shape facing the second main surface 4.

[0069] 6 and 7 , the opening edge 35 of the gate trench 32 includes an inclined portion 36 that slopes downward from the first main surface 3 toward the inside of the gate trench 32. The opening edge 35 of the gate trench 32 is a corner that connects the first main surface 3 and the sidewall of the gate trench 32. In this embodiment, the inclined portion 36 is formed in a convex curve toward the inside of the gate trench 32. The inclined portion 36 may also be formed in a concave curve toward the inside of the SiC semiconductor layer 2. The inclined portion 36 reduces electric field concentration at the opening edge 35.

[0070] The depth of each gate trench 32 in the normal direction Z may be 0.5 μm to 3.0 μm inclusive. The depth of the gate trench 32 may be 0.5 μm to 1.0 μm inclusive, 1.0 μm to 1.5 μm inclusive, 1.5 μm to 2.0 μm inclusive, 2.0 μm to 2.5 μm inclusive, or 2.5 μm to 3.0 μm inclusive.

[0071] The width of the gate trench 32 may be 0.1 μm or more and 2 μm or less. The width of the gate trench 32 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0072] The SiC semiconductor device 1 includes a gate insulating layer 37 formed on the inner wall of the gate trench 32. The SiC semiconductor device 1 also includes a gate electrode layer 38 (gate electrode) embedded in the gate trench 32 with the gate insulating layer 37 sandwiched therebetween. In FIG. 5, the gate insulating layer 37 and the gate electrode layer 38 are indicated by hatching.

[0073] The gate insulating layer 37 is formed in a film shape along the inner wall of the gate trench 32, and defines a recess space within the gate trench 32. The gate insulating layer 37 includes a first region 37a, a second region 37b, and a third region 37c. The first region 37a is formed along the side wall of the gate trench 32. The second region 37b is formed along the bottom wall of the gate trench 32. The third region 37c is formed along the first main surface 3.

[0074] The thickness Ta of the first region 37a is less than the thickness Tb of the second region 37b and the thickness Tc of the third region 37c. The ratio Tb / Ta of the thickness Tb of the second region 37b to the thickness Ta of the first region 37a may be 2 or more and 5 or less. The ratio Tc / Ta of the thickness Tc of the third region 37c to the thickness Ta of the first region 37a may be 2 or more and 5 or less. The thickness Ta of the first region 37a may be 0.01 μm or more and 0.2 μm or less. The thickness Tb of the second region 37b may be 0.05 μm or more and 0.5 μm or less. The thickness Tc of the third region 37c may be 0.05 μm or more and 0.5 μm or less.

[0075] The thinning of the first region 37a can suppress an increase in carriers induced in the body region 31 near the sidewall of the gate trench 32. This can suppress an increase in channel resistance. The thickening of the second region 37b can reduce electric field concentration on the bottom wall of the gate trench 32.

[0076] The thickening of the third region 37c improves the breakdown voltage of the gate insulating layer 37 near the opening edge 35 of the gate trench 32. Furthermore, the thickening of the third region 37c can suppress the loss of the third region 37c due to the etching method. This suppresses further loss of the first region 37a due to the etching method. Therefore, the gate electrode layer 38 can be appropriately opposed to the SiC semiconductor layer 2 (body region 31) with the gate insulating layer 37 interposed therebetween.

[0077] The gate insulating layer 37 further includes a bulging portion 37d that bulges into the gate trench 32 at the opening edge portion 35. The bulging portion 37d is formed at a corner that connects the first region 37a and the third region 37c. The bulging portion 37d bulges inward of the gate trench 32 in a convex curved shape.

[0078] The bulging portion 37d narrows the opening of the gate trench 32 at the opening edge portion 35. The bulging portion 37d increases the dielectric strength voltage of the gate insulating layer 37 at the opening edge portion 35. A gate insulating layer 37 without the bulging portion 37d may be formed. Alternatively, a gate insulating layer 37 having a uniform thickness may be formed.

[0079] The gate insulating layer 37 includes at least one of a silicon oxide (SiO2) layer, a silicon nitride (SiN) layer, an aluminum oxide (Al2O3) layer, a zirconium oxide (ZrO2) layer, and a tantalum oxide (Ta2O3) layer. The gate insulating layer 37 may have a stacked structure including a SiN layer and a SiO2 layer stacked in this order from the first main surface 3 side.

[0080] The gate insulating layer 37 may have a laminated structure including an SiO2 layer and a SiN layer laminated in this order from the first main surface 3 side. The gate insulating layer 37 may have a single-layer structure made of an SiO2 layer or a SiN layer. In this embodiment, the gate insulating layer 37 has a single-layer structure made of an SiO2 layer.

[0081] The gate electrode layer 38 is embedded in a recess space defined by the gate insulating layer 37 within the gate trench 32. The gate electrode layer 38 is controlled by a gate voltage.

[0082] The gate electrode layer 38 may include conductive polysilicon. The gate electrode layer 38 may include n-type polysilicon or p-type polysilicon, as examples of conductive polysilicon. Instead of or in addition to conductive polysilicon, the gate electrode layer 38 may include at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy.

[0083] 5 to 7, SiC semiconductor device 1 includes a plurality of cell regions 39 partitioned into areas surrounded by gate trenches 32. The plurality of cell regions 39 are arranged in a matrix at intervals in a first direction X and a second direction Y in a plan view. The plurality of cell regions 39 are formed in a quadrangular shape in a plan view.

[0084] When the gate trench 32 is formed in a honeycomb shape in plan view, the multiple cell regions 39 may be formed in a hexagonal shape in plan view. In this case, the multiple cell regions 39 may be arranged in a staggered pattern with intervals in the first direction X and the second direction Y.

[0085] The body region 31 associated with each cell region 39 is exposed from the sidewall of the gate trench 32. The body region 31 associated with each cell region 39 is exposed from the sidewall of the gate trench 32 formed by the m-plane and a-plane of the SiC single crystal.

[0086] The SiC semiconductor device 1 has n-type MOS transistors formed in the surface layer of the body region 31 in each cell region 39. +The body region 31 includes a source region 41 of a type. The source region 41 is formed in a region along the sidewall of the gate trench 32 in a surface layer portion of the body region 31. The source region 41 is formed in a strip shape extending along the sidewall of the gate trench 32 in a plan view. More specifically, the source region 41 is formed in an endless shape (a square ring shape in this embodiment) surrounding the inner region of each cell region 39 in a plan view.

[0087] The source region 41 is exposed from the sidewall of the gate trench 32. The source region 41 is exposed from the sidewall of the gate trench 32 formed by the m-plane and a-plane of the SiC single crystal. The peak value of the n-type impurity concentration of the source region 41 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The lower limit of the peak value of the n-type impurity concentration of the source region 41 may be 1.0×10 20 cm -3 The n-type impurity of the source region 41 may be phosphorus (P).

[0088] As described above, in a region along the sidewall of the gate trench 32 in the surface layer portion of the first main surface 3, the source region 41, the body region 31, and the drift region 25 are formed in this order from the first main surface 3 to the second main surface 4. A channel of the MISFET is formed in a region along the sidewall of the gate trench 32 in the body region 31. The channel is formed along the sidewall of the gate trench 32 in the body region 31, which is formed by the m-plane and a-plane of the SiC single crystal. The ON / OFF of the channel is controlled by the gate electrode layer 38.

[0089] The SiC semiconductor device 1 has p +Each contact region 42 is formed in a region of each cell region 39 on the opposite side of the gate trench 32 with respect to the source region 41. In other words, each contact region 42 is formed in a region of each cell region 39 facing the gate trench 32 with the source region 41 in between.

[0090] Each contact region 42 is formed in the center of each cell region 39 in plan view. More specifically, each contact region 42 is formed in an inner region surrounded by the source region 41 in each cell region 39. Each contact region 42 is electrically connected to the body region 31 and the source region 41.

[0091] In this embodiment, the bottom of each contact region 42 is formed in a region between the bottom of the body region 31 and the bottom of the source region 41. The bottom of each contact region 42 may also be formed in a region between the first main surface 3 and the bottom of the source region 41. Hereinafter, the p-type impurity concentration of the contact region 42 will be specifically described with reference to FIG. 9A.

[0092] Fig. 9A is a graph for explaining a first example of the p-type impurity concentration of the contact region 42 shown in Fig. 7. In Fig. 9A, the vertical axis represents the p-type impurity concentration, and the horizontal axis represents the distance from the first main surface 3.

[0093] 9A shows the p-type impurity concentration of the contact region 42 when the contact region 42 is formed by introducing a p-type impurity into the SiC epitaxial layer 22 (drift region 25). In this example, the contact region 42 is formed by introducing a p-type impurity into the SiC epitaxial layer 22 (drift region 25) only once. The p-type impurity in the contact region 42 may be aluminum (Al).

[0094] In this embodiment, the p-type impurity concentration of the contact region 42 has one peak value P at the middle of the thickness direction of the SiC semiconductor layer 2. The peak value P is 1.0×10 20 cm-3 The peak value P is 1.0 x 10 20 cm -3 The peak value P is preferably less than 1.0×10 17 cm -3 Over 1.0 x 10 20 cm -3 It is preferable that the peak value P is in the range of 1.0×10 17 cm -3 Beyond 1.0 x 10 20 cm -3 It is more preferable that the lower limit of the peak value P is in the range of less than 1.0 × 10 18 cm -3 The lower limit of the peak value P is preferably 1.0×10 19 cm -3 More preferably, it is equal to or greater than this.

[0095] The peak value P is 1.0 x 10 17 cm -3 Over 5.0 x 10 17 cm -3 Below, 5.0 x 10 17 cm -3 Over 1.0 x 10 18 cm -3 Below, 1.0 x 10 18 cm -3 Over 5.0 x 10 18 cm -3 Below, 5.0 x 10 18 cm -3 Over 1.0 x 10 19 cm -3 Below, 1.0 x 10 19 cm -3 Over 5.0 x 10 19 cm -3 or less, or 5.0 x 10 19 cm -3 Over 1.0 x 10 20 cm -3 It may be less than.

[0096] The peak value P is 1.0 x 10 19 cm -3 Beyond 3.0 x 10 19 cm-3 cm -3 In this embodiment, the peak value P is located in a range exceeding the peak value of the p-type impurity concentration in the body region 31 and less than the peak value of the n-type impurity concentration in the source region 41.

[0097] The number of times the p-type impurity is introduced merely controls the number of maximum values ​​of the p-type impurity concentration in the contact region 42, the depth range of the peak value P, and the like. The contact region 42 may be formed by introducing the p-type impurity multiple times into the surface layer portion of the SiC epitaxial layer 22 (drift region 25). In this case, the p-type impurity may be introduced into different regions in the thickness direction in the surface layer portion of the SiC epitaxial layer 22 (drift region 25). In other words, the p-type impurity concentration in the contact region 42 may have multiple (two or more) peak values ​​P in the middle of the SiC semiconductor layer 2 in the thickness direction.

[0098] Referring to FIG. 8, SiC semiconductor device 1 has p + The diode region 45 includes a diode region 45 (impurity region) of a type. The diode region 45 is formed at a distance from the active region 6 and the side surfaces 5A to 5D. The diode region 45 extends in a strip shape along the active region 6 in a plan view. More specifically, the diode region 45 is formed in an endless shape (a square ring shape in this embodiment) surrounding the active region 6 in a plan view.

[0099] The diode region 45 forms a pn junction with the SiC semiconductor layer 2. More specifically, the diode region 45 is located within the SiC epitaxial layer 22, and forms a pn junction with the SiC epitaxial layer 22. This forms a pn junction diode D having the diode region 45 as an anode and the SiC semiconductor layer 2 as a cathode.

[0100] The diode region 45 overlaps with the source lead-out wiring 15 in plan view. The diode region 45 is electrically connected to the source lead-out wiring 15. The diode region 45 forms a part of the avalanche current absorption structure.

[0101] The peak value of the p-type impurity concentration in the diode region 45 is 1.0×10 20 cm -3 The peak value of the p-type impurity concentration in the diode region 45 is 1.0×10 17 cm -3 Over 1.0 x 10 20 cm -3 It is preferable that it is in the following range:

[0102] The thickness (depth) of the diode region 45 is preferably approximately equal to the thickness (depth) of the contact region 42. The diode region 45 preferably has a p-type impurity concentration equal to the p-type impurity concentration of the contact region 42. With this structure, the contact region 42 and the diode region 45 can be formed using the same mask.

[0103] The diode region 45 may have a p-type impurity concentration that exceeds the p-type impurity concentration of the contact region 42. The diode region 45 may have a p-type impurity concentration that is greater than 1.0×10 20 cm -3 The p-type impurity concentration may be higher than the p-type impurity concentration of the contact region 42 while having a p-type impurity concentration of 0.1 to 1.0 μm or less.

[0104] The diode region 45 is 1.0×10 20 cm -3 The peak value of the p-type impurity concentration of the diode region 45 may be greater than 1.0×10 20 cm -3 Beyond 1.0 x 10 21 cm -3 The contact region 42 and the diode region 45 may be located in the following range: In this case, the contact region 42 and the diode region 45 cannot be formed at the same time, but the design can be made with attention paid to the characteristics of the pn junction diode D.

[0105] In this case, the diode region 45 may have a thickness (depth) different from the thickness (depth) of the contact region 42. The thickness (depth) of the diode region 45 may be equal to or greater than the thickness (depth) of the contact region 42, or may be less than the thickness (depth) of the contact region 42.

[0106] The SiC semiconductor device 1 includes a p-type well region 46 formed in a surface layer portion of the first main surface 3 in the outer region 7. The well region 46 is formed at a distance from the active region 6 and the side surfaces 5A to 5D. In this embodiment, the well region 46 is formed in a region that overlaps with the diode region 45 in plan view. The well region 46 extends in a strip shape along the active region 6 in plan view.

[0107] More specifically, the well region 46 is formed in an endless shape (a quadrangular ring in this embodiment) surrounding the active region 6 in plan view. The bottom of the well region 46 is located closer to the second main surface 4 than the bottom of the diode region 45. In this embodiment, the well region 46 covers the diode region 45 from the second main surface 4 side.

[0108] The well region 46 is electrically connected to the source lead-out line 15 via the diode region 45. The well region 46 overlaps with the source lead-out line 15 in plan view. The well region 46 may form part of a pn junction diode D. The well region 46 may form part of an avalanche current absorption structure.

[0109] The width of the well region 46 may be equal to or greater than the width of the diode region 45. The width of the well region 46 preferably exceeds the width of the diode region 45. The width of the well region 46 may further be equal to or greater than the width of the source lead-out line 15. The width of the well region 46 preferably exceeds the width of the source lead-out line 15.

[0110] The width of the well region 46 is the width in a direction perpendicular to the extension direction of the well region 46. The width of the diode region 45 is the width in a direction perpendicular to the extension direction of the diode region 45. The width of the source lead-out line 15 is the width in a direction perpendicular to the extension direction of the source lead-out line 15.

[0111] The thickness (depth) of the well region 46 is approximately equal to the thickness (depth) of the body region 31. The peak value of the p-type impurity concentration of the well region 46 is 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 The lower limit of the peak value of the p-type impurity concentration of the well region 46 is 1.0×10 18 cm -3 Preferably, the well region 46 has a p-type impurity concentration equal to the p-type impurity concentration of the body region 31. With this structure, the body region 31 and the well region 46 can be formed using the same mask.

[0112] 7 and 8, SiC semiconductor device 1 includes interlayer insulating layer 51 formed on first main surface 3. Interlayer insulating layer 51 selectively covers active region 6 and outer region 7. Interlayer insulating layer 51 is formed in the form of a film along first main surface 3. The peripheral portion of interlayer insulating layer 51 may be formed flush with side surfaces 5A to 5D.

[0113] The interlayer insulating layer 51 may contain silicon oxide or silicon nitride. The interlayer insulating layer 51 may contain PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide. The interlayer insulating layer 51 may have a layered structure including a PSG layer and a BPSG layer stacked in this order from the first main surface 3 side. The interlayer insulating layer 51 may have a layered structure including a BPSG layer and a PSG layer stacked in this order from the first main surface 3 side.

[0114] The interlayer insulating layer 51 includes a plurality of source contact holes 52. The plurality of source contact holes 52 expose the plurality of cell regions 39 in a one-to-one correspondence. Each source contact hole 52 selectively exposes the source region 41 and the contact region 42 in each cell region 39. The opening edge of each source contact hole 52 is formed in a convex curve facing inward.

[0115] The interlayer insulating layer 51 includes a diode contact hole 53. The diode contact hole 53 exposes the diode region 45 in the outer region 7. The diode contact hole 53 may be formed in a strip shape (more specifically, endless) extending along the diode region 45 in a plan view. The diode contact hole 53 may expose the well region 46. The opening edge portion of the diode contact hole 53 is formed in a convex curved shape facing inward of the diode contact hole 53.

[0116] Although not shown, the interlayer insulating layer 51 further includes a gate contact hole. The gate electrode layer 38 is exposed through the gate contact hole. The gate contact hole may be formed in a strip shape extending along the gate finger 10 in a plan view. The opening edge portion of the gate contact hole is formed in a convex curved shape facing into the gate contact hole.

[0117] The aforementioned gate principal surface electrode layer 8 and source principal surface electrode layer 13 are formed on an interlayer insulating layer 51. The gate principal surface electrode layer 8 and source principal surface electrode layer 13 each have a laminated structure including a barrier electrode layer 54 and a main electrode layer 55 laminated in this order from the first principal surface 3 side.

[0118] The barrier electrode layer 54 may have a single layer structure including a titanium layer or a titanium nitride layer, or may have a multilayer structure including a titanium layer and a titanium nitride layer stacked in this order from the first main surface 3 side.

[0119] The thickness of the main electrode layer 55 exceeds the thickness of the barrier electrode layer 54. The main electrode layer 55 includes a conductive material having a resistance value less than the resistance value of the barrier electrode layer 54. The main electrode layer 55 may include at least one of aluminum, copper, an aluminum alloy, and a copper alloy. The main electrode layer 55 may include at least one of an AlSi alloy, an AlSiCu alloy, and an AlCu alloy. In this embodiment, the main electrode layer 55 includes an AlSiCu alloy.

[0120] The gate main surface electrode layer 8 (gate finger 10) extends into the gate contact hole (not shown) from above the interlayer insulating layer 51. The gate main surface electrode layer 8 is electrically connected to the gate electrode layer 38 in the gate contact hole.

[0121] The source main surface electrode layer 13 (source pad 14) extends from above the interlayer insulating layer 51 into the source contact hole 52. The source main surface electrode layer 13 is electrically connected to the source region 41 and the contact region 42 within the source contact hole 52. More specifically, the source main surface electrode layer 13 forms an ohmic contact with the source region 41. In this embodiment, the source main surface electrode layer 13 also forms a Schottky junction with the contact region 42.

[0122] The source main surface electrode layer 13 (source lead-out wiring 15) extends from above the interlayer insulating layer 51 into the diode contact hole 53. The source main surface electrode layer 13 is electrically connected to the diode region 45 in the diode contact hole 53.

[0123] The source principal surface electrode layer 13 may form a Schottky junction with the diode region 45. That is, the diode region 45 may have a p-type impurity concentration that forms a Schottky junction with the source principal surface electrode layer 13. In this case, the diode region 45 has a p-type impurity concentration of 1.0×10 20 cm -3 The p-type impurity concentration may have the following peak value:

[0124] The source principal surface electrode layer 13 may form an ohmic contact with the diode region 45. That is, the diode region 45 may have a p-type impurity concentration that forms an ohmic contact with the source principal surface electrode layer 13. In this case, the diode region 45 has a p-type impurity concentration of 1.0×10 20 cm -3 The p-type impurity concentration may have a peak value exceeding

[0125] Referring to FIG. 8, the SiC semiconductor device 1 includes a passivation layer 56 formed on an interlayer insulating layer 51. The passivation layer 56 may have a single-layer structure made of a silicon oxide layer or a silicon nitride layer. The passivation layer 56 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on a silicon nitride layer. The silicon nitride layer may be formed on a silicon oxide layer. The passivation layer 56 preferably includes an insulating material different from that of the interlayer insulating layer 51. In this embodiment, the passivation layer 56 has a single-layer structure made of a silicon nitride layer.

[0126] The passivation layer 56 is formed in a film shape along the interlayer insulating layer 51. The passivation layer 56 selectively covers the active region 6 and the outer region 7 via the interlayer insulating layer 51. The passivation layer 56 includes a gate subpad opening 57 and a source subpad opening 58 (see also FIG. 3 ). The gate subpad opening 57 exposes the gate pad 9. The source subpad opening 58 exposes the source pad 14.

[0127] The peripheral edge of the passivation layer 56 may be formed flush with the side surfaces 5A to 5D. The peripheral edge of the passivation layer 56 may be formed at an interval inward from the side surfaces 5A to 5D. The peripheral edge of the passivation layer 56 may expose the first main surface 3 (interlayer insulating layer 51) in plan view. The peripheral edge of the passivation layer 56 may be continuous with the peripheral edge 17a of the resin layer 17.

[0128] The peripheral portion of the passivation layer 56 may define a part of the dicing street DS. By exposing the first main surface 3 from the peripheral portion of the passivation layer 56, it is not necessary to physically cut the passivation layer 56. Therefore, the SiC semiconductor device 1 can be smoothly cut out from one SiC semiconductor wafer.

[0129] The resin layer 17 described above is formed on the passivation layer 56. The resin layer 17 is formed in the form of a film along the passivation layer 56. The resin layer 17 selectively covers the active region 6 and the outer region 7, with the passivation layer 56 and the interlayer insulating layer 51 sandwiched between them.

[0130] The gate pad opening 18 communicates with the gate subpad opening 57. The inner wall of the gate pad opening 18 may be located outside the inner wall of the gate subpad opening 57. The inner wall of the gate pad opening 18 may be located inside the inner wall of the gate subpad opening 57. In other words, the resin layer 17 may cover the inner wall of the gate subpad opening 57.

[0131] The source pad opening 19 communicates with the source subpad opening 58. The inner wall of the source pad opening 19 may be located outside the inner wall of the source subpad opening 58. The inner wall of the source pad opening 19 may be located inside the inner wall of the source subpad opening 58. In other words, the resin layer 17 may cover the inner wall of the source subpad opening 58.

[0132] 9B is a graph for explaining the p-type impurity concentration of the contact region 42 according to the reference example. In FIG. 9B, the vertical axis represents the p-type impurity concentration, and the horizontal axis represents the distance from the first main surface 3.

[0133] 9B shows the p-type impurity concentration of the contact region 42 according to the reference example when the contact region 42 is formed by introducing p-type impurities into the SiC epitaxial layer 22 (drift region 25). The peak value P of the p-type impurity concentration of the contact region 42 according to the reference example is 1.0×10 20 cm -3 Beyond 1.0 x 10 21 cm -3 It is located in the following range:

[0134] The contact region 42 according to the reference example is formed by doping p-type impurities multiple times (four or more times in this example) into the surface layer portion of the SiC epitaxial layer 22 (drift region 25). The p-type impurities are doped into different regions in the thickness direction in the surface layer portion of the SiC epitaxial layer 22 (drift region 25).

[0135] The p-type impurity concentration of contact region 42 according to the reference example has one peak value P at a midpoint in the thickness direction of SiC semiconductor layer 2. The number of times the p-type impurity is introduced merely controls the number of maximum values ​​of the p-type impurity concentration in contact region 42 according to the reference example and the depth range of peak value P. In this example, p-type impurity is introduced multiple times to form contact region 42 according to the reference example, but the p-type impurity may be introduced only once.

[0136] Fig. 10 is a graph for explaining the characteristics of gate threshold voltage Vth over time. In Fig. 10, the vertical axis represents gate threshold voltage Vth [V] and the horizontal axis represents time [h]. Fig. 10 is a graph obtained by simulating the characteristics of gate threshold voltage Vth over time when SiC semiconductor device 1 is operated for several hundred to several thousand hours.

[0137] 10 shows a first characteristic S1 (see dashed line) and a second characteristic S2 (see solid line). The first characteristic S1 is 1.0×10 20 cm -3 The second characteristic S2 shows the time characteristic of the gate threshold voltage Vth when the contact region 42 according to the reference example having a peak value P exceeding 1.0×1020 cm -3 10 shows the time characteristics of the gate threshold voltage Vth when the contact region 42 according to this embodiment having the following peak value P is used.

[0138] Referring to the first characteristic S1, when the contact region 42 according to the reference example was used, the gate threshold voltage Vth increased over time. In contrast, referring to the second characteristic S2, when the contact region 42 according to the present embodiment was used, the increase in the gate threshold voltage Vth over time was suppressed compared to the first characteristic S1.

[0139] The degradation of the gate threshold voltage Vth over time is suppressed more effectively as the peak value P is reduced. In view of the significance of the existence of the contact region 42, it is preferable that the lower limit of the peak value P be set to a value exceeding the peak value of the p-type impurity concentration in the body region 31.

[0140] The present inventors have also conducted extensive research into Si (silicon) semiconductor devices to determine whether the gate threshold voltage Vth varies over time depending on the p-type impurity concentration in the contact region 42. However, in the Si semiconductor device, even when the p-type impurity concentration in the contact region 42 is changed, no variation in the gate threshold voltage Vth over time characteristics due to an increase or decrease in the p-type impurity concentration in the contact region 42 was observed.

[0141] That is, it was found that the phenomenon in which the time-dependent characteristics of the gate threshold voltage Vth vary depending on the increase or decrease in the p-type impurity concentration in the contact region 42 is a phenomenon specific to SiC semiconductor devices. It was also found that the increase in the gate threshold voltage Vth over time is due to a problem specific to SiC semiconductor devices that include the contact region 42.

[0142] As described above, according to the SiC semiconductor device 1, the deterioration of the gate threshold voltage Vth over time can be suppressed.

[0143] Fig. 11 is a graph for explaining a second example of the p-type impurity concentration of the contact region 42 shown in Fig. 7. In Fig. 11, the vertical axis represents the p-type impurity concentration of the contact region 42, and the horizontal axis represents the distance from the first main surface 3.

[0144] The aforementioned FIG. 9A shows the p-type impurity concentration of the contact region 42 when the contact region 42 is formed by introducing p-type impurities into the SiC epitaxial layer 22 (drift region 25).

[0145] 11 shows the p-type impurity concentration of a contact region 42 that contains n-type impurities and p-type impurities, where the n-type impurities compensate for some of the p-type impurities. Hereinafter, the contact region 42 according to the second example will be referred to as a "contact region of a compensation type." "Compensation" is also referred to as "offset," "compensation," "carrier offset," or "carrier compensation."

[0146] Hereinafter, for convenience of explanation, the n-type impurity before being offset-compensated will be referred to as a "donor," and the p-type impurity before being offset-compensated will be referred to as an "acceptor." An n-type impurity of the same species as the n-type impurity forming the SiC epitaxial layer 22 may be used as the donor. An n-type impurity of a different species from the n-type impurity forming the SiC epitaxial layer 22 may be used as the donor.

[0147] The donors are further introduced into the SiC epitaxial layer 22 (drift region 25) and exist independently of the n-type impurities that define the conductivity type of the SiC epitaxial layer 22. The n-type impurity concentration in the region of the SiC epitaxial layer 22 into which the donors have been introduced exceeds the n-type impurity concentration of the SiC epitaxial layer 22 (drift region 25).

[0148] 11 shows a first line L1 (see dashed line), a second line L2 (see thin solid line), and a third line L3 (see thick solid line). The first line L1 indicates the donor concentration. The second line L2 indicates the acceptor concentration. The third line L3 indicates the p-type impurity concentration of the offset compensation contact region 42. The offset compensation contact region 42 is formed by introducing donors into the entire cell region 39 to form the source region 41, and then introducing acceptors into the source region 41.

[0149] Referring to the first line L1, the donor concentration is 1.0 x 10 in this example. 20 cm -3 Over 5.0 x 10 20 cm -3 The donor concentration has a peak value in the following range: The donor concentration is equal to the n-type impurity concentration of the source region 41. The peak value of the n-type impurity concentration of the source region 41 is 1.0×10 20 cm -3 Over 1.0 x 10 21 cm -3 It may be located in the following ranges:

[0150] Referring to the second line L2, the acceptor concentration exceeds the donor concentration. In this example, the acceptor concentration is 5.0 x 10 20 cm -3 Over 1.0 x 10 21 cm -3 The acceptor concentration may be equal to the p-type impurity concentration of the diode region 45. The peak value of the p-type impurity concentration of the diode region 45 is greater than the peak value of the n-type impurity concentration of the source region 41, and may be 1.0×10 20 cm -3 Beyond 1.0 x 10 21 cm -3 It may be located in the following ranges:

[0151] Referring to the third line L3, in this example, the offset compensation contact region 42 is formed by doping p-type impurities multiple times (four times in this example) into the surface layer portion of the SiC epitaxial layer 22 (drift region 25). The p-type impurities are doped into different regions in the thickness direction of the surface layer portion of the SiC epitaxial layer 22 (drift region 25). The p-type impurity concentration of the offset compensation contact region 42 has multiple maximum values ​​in the middle of the thickness direction of the SiC epitaxial layer 22.

[0152] The number of times the p-type impurity is introduced merely controls the number of maximum values ​​of the p-type impurity concentration and the depth range of the peak value P in the offset compensation contact region 42. In this example, the p-type impurity is introduced multiple times, but the offset compensation contact region 42 may also be formed by introducing the p-type impurity only once, as shown in FIG.

[0153] In this example, the p-type impurity concentration of the offset compensation contact region 42 has a peak value P located in a range greater than the donor concentration and less than the acceptor concentration. The p-type impurity concentration of the offset compensation contact region 42 may also have a peak value P in a range greater than the n-type impurity concentration of the source region 41 and less than the p-type impurity concentration of the diode region 45.

[0154] The peak value P is 1.0 x 10 in this example. 20 cm -3 Over 5.0 x 10 20 cm -3 The peak value P is located in the range of 1.0×10 under the condition that it exceeds the peak value of the n-type impurity concentration of the source region 41 and is less than the peak value of the p-type impurity concentration of the diode region 45. 20 cm -3 Over 1.0 x 10 21 cm -3 It may be located in the following ranges:

[0155] The peak value P is 1.0 x 10 20 cm -3 Over 2.5 x 10 20 cm -3Below, 2.5 x 10 20 cm -3 Over 5.0 x 10 20 cm -3 Below, 5.0 x 10 20 cm -3 Over 7.5 x 10 20 cm -3 or less, or 7.5 x 10 20 cm -3 Over 1.0 x 10 21 cm -3 It may be located in the following ranges:

[0156] With reference to the first to third lines L1 to L3, the bottom of the offset compensation type contact region 42 is located closer to the second main surface 4 than the bottom of the source region 41. More specifically, in this example, the bottom of the offset compensation type contact region 42 is formed in a region between the bottom of the body region 31 and the bottom of the source region 41.

[0157] The offset compensation type contact region 42 includes a surface region and a bottom region. The surface region is located on the first main surface 3 side of the bottom of the source region 41. The bottom region is located on the second main surface 4 side of the bottom of the source region 41.

[0158] In the surface region, some of the acceptors are offset by donors. As a result, the p-type impurity concentration in the surface region is lower than the acceptor concentration. On the other hand, in the bottom region, the acceptors are not in contact with the donors, so offset compensation of the acceptors by donors is suppressed. This results in the formation of an offset-compensation type contact region 42, which has a surface region where some of the acceptors are offset by donors and a bottom region where the acceptors are not offset by donors.

[0159] The aforementioned source principal surface electrode layer 13 (source pad 14) may form an ohmic contact with the source region 41, and may also form an ohmic contact with the offset compensation type contact region 42. The source principal surface electrode layer 13 (source pad 14) may also form an ohmic contact with the diode region.

[0160] Under the condition that the n-type impurity concentration (donor concentration) of the source region 41 exceeds the peak value and the p-type impurity concentration (acceptor concentration) of the diode region 45 is less than the peak value, the offset compensation type contact region 42 has a value of 1.0×10 20 cm -3 In this case, the p-type impurity concentration of the contact region 42 according to the first example may be applied to the offset compensation type contact region 42 (see also FIG. 9A).

[0161] In this case, the aforementioned source principal surface electrode layer 13 (source pad 14) may form an ohmic contact with the source region 41, and may form a Schottky junction with the offset compensation type contact region 42. The source principal surface electrode layer 13 (source pad 14) may also form an ohmic contact or a Schottky junction with the diode region.

[0162] 12 is a graph illustrating the time characteristics of the gate threshold voltage Vth when the offset compensation type contact region 42 according to the second example is employed. In FIG. 12, the vertical axis represents the gate threshold voltage Vth [V], and the horizontal axis represents time [h].

[0163] 12 is a graph showing the results of simulation of the characteristics of gate threshold voltage Vth over time when SiC semiconductor device 1 is operated for several hundred to several thousand hours. In addition to third characteristic S3 (see solid line), Fig. 12 also shows the first characteristic S1 (see dashed line) described above. Third characteristic S3 shows the characteristics of gate threshold voltage Vth over time when offset compensation type contact region 42 is used.

[0164] With reference to the third characteristic S3, it has been confirmed that when the offset compensation type contact region 42 is employed, the increase in the gate threshold voltage Vth over time is suppressed compared to the first characteristic S1. The deterioration of the gate threshold voltage Vth over time is suppressed to the extent that the peak value P of the p-type impurity concentration in the contact region 42 is reduced. In view of the significance of the existence of the contact region 42, it is preferable that the lower limit of the peak value P of the p-type impurity concentration in the contact region 42 be set to a value that exceeds the peak value of the p-type impurity concentration in the body region 31.

[0165] In contrast to the non-offset compensated contact region 42 shown in FIG. 9A, the offset compensated contact region 42 shown in FIG. 11 has a relatively high p-type impurity concentration (1.0×10 20 cm -3 Although the gate threshold voltage Vth exhibited a high MOSFET characteristic, the degradation of the gate threshold voltage Vth over time was suppressed.

[0166] In the offset compensation type contact region 42, crystal defects are formed due to offset compensation between donors (n-type impurities) and acceptors (p-type impurities). In the offset compensation type contact region 42, in addition to the offset compensation, these crystal defects are also thought to contribute to suppressing the degradation of the gate threshold voltage Vth over time.

[0167] In this way, the SiC semiconductor device 1 employing the offset compensation type contact region 42 can also suppress deterioration of the gate threshold voltage Vth over time. Furthermore, when the offset compensation type contact region 42 is employed, the contact region 42 and the diode region 45 can be simultaneously formed, and a design that focuses on the characteristics of the pn junction diode D can be performed. This makes it possible to improve the diode characteristics in the outer region 7 while suppressing deterioration of the gate threshold voltage Vth over time.

[0168] 13 is a plan view of a region corresponding to FIG. 5, showing a SiC semiconductor device 61 according to a second embodiment of the present invention. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0169] 13 , SiC semiconductor device 61 includes gate trenches 32 formed in a stripe shape in plan view. That is, gate trench 32 includes only one of a plurality of first gate trenches 33 and a plurality of second gate trenches 34. In this embodiment, gate trench 32 does not include second gate trenches 34, but only includes a plurality of first gate trenches 33.

[0170] In this embodiment, the body region 31 extends in a strip shape along the gate trench 32 in a region between two adjacent gate trenches 32. The source region 41 is formed in a surface layer portion of the body region 31 in a region between two adjacent gate trenches 32. The source region 41 extends in a strip shape along the sidewall of the corresponding gate trench 32. The channel of the MISFET is formed in the body region 31 in a region along the sidewall formed by the a-plane of the SiC single crystal of the gate trench 32.

[0171] The contact region 42 is formed in a surface layer portion of the body region 31 in a region between two adjacent gate trenches 32. The contact region 42 shown in FIG. 9A or the offset compensation type contact region 42 shown in FIG. 11 may be formed. The contact region 42 is formed in the center of the body region 31 and spaced apart from the gate trench 32 in a plan view. In this embodiment, the contact region 42 is formed in a strip shape extending along the gate trench 32.

[0172] A plurality of contact regions 42 may be formed in a region between two adjacent gate trenches 32. In this case, the plurality of contact regions 42 may be formed at intervals along the gate trench 32. A source region 41 may be interposed in a region between the plurality of adjacent contact regions 42 in the surface layer portion of the body region 31.

[0173] As described above, SiC semiconductor device 61 can also achieve the same effects as those described for SiC semiconductor device 1.

[0174] Fig. 14 is a plan view of a region corresponding to Fig. 5, showing a SiC semiconductor device 62 according to a third embodiment of the present invention. Fig. 15 is a cross-sectional view taken along line XV-XV shown in Fig. 14. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 will be given the same reference numerals and will not be described again.

[0175] 14 and 15, the SiC semiconductor device 62 includes source trenches 63 (second trenches) formed in each cell region 39. Each source trench 63 is formed in the center of each cell region 39 in a plan view. Each source trench 63 is formed in a pattern that appears alone on a cross section of each cell region 39 taken along the first direction X. Furthermore, each source trench 63 is formed in a pattern that appears alone on a cross section of each cell region 39 taken along the second direction Y.

[0176] More specifically, each source trench 63 is formed in a quadrangular shape in plan view. The planar shape of each source trench 63 is arbitrary. Each source trench 63 may be formed in a polygonal shape such as a triangular shape, a pentagonal shape, or a hexagonal shape, or may be formed in a circular or elliptical shape in plan view.

[0177] Each source trench 63 penetrates the body region 31 and reaches the drift region 25 (SiC epitaxial layer 22). Each source trench 63 includes a sidewall and a bottom wall. The sidewalls of each source trench 63 are formed by the m-plane and a-plane of the SiC single crystal.

[0178] The sidewalls of each source trench 63 may extend along the normal direction Z. The sidewalls of each source trench 63 may be formed substantially perpendicular to the first main surface 3. The angle that the sidewalls of each source trench 63 form with the first main surface 3 in the SiC semiconductor layer 2 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). In other words, the source trench 63 may be formed in a tapered shape with a bottom area less than an opening area.

[0179] The bottom wall of each source trench 63 is located on the SiC epitaxial layer 22 side of the boundary between the SiC semiconductor substrate 21 and the SiC epitaxial layer 22. The bottom wall of each source trench 63 is located in the drift region 25 (SiC epitaxial layer 22). The bottom wall of each source trench 63 faces the c-plane of the SiC single crystal. The bottom wall of each source trench 63 has an off-angle θ tilted in the [11-20] direction with respect to the (0001) plane of the SiC single crystal. The bottom wall of each source trench 63 may be formed parallel to the first main surface 3. The bottom wall of each source trench 63 may be formed in a convex curved shape facing the second main surface 4.

[0180] An opening edge 64 of each source trench 63 includes an inclined portion 65 that slopes downward from the first main surface 3 toward the inside of each source trench 63. The opening edge 64 of each source trench 63 is a corner that connects the first main surface 3 and the sidewall of each source trench 63. In this embodiment, the inclined portion 65 is formed in a convex curve toward the inside of the source trench 63. The inclined portion 65 may also be formed in a concave curve toward the inside of the SiC semiconductor layer 2. The inclined portion 65 reduces electric field concentration at the opening edge 64.

[0181] The depth of each source trench 63 in the normal direction Z may be 0.5 μm or more and 3.0 μm or less. The depth of each source trench 63 may be 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, 1.5 μm or more and 2.0 μm or less, 2.0 μm or more and 2.5 μm or less, or 2.5 μm or more and 3.0 μm or less. The depth of each source trench 63 is preferably approximately equal to the depth of the gate trench 32. With this structure, the gate trench 32 and each source trench 63 can be formed simultaneously.

[0182] The width of each source trench 63 may be 0.1 μm or more and 2 μm or less. The width of each source trench 63 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less. The width of each source trench 63 is preferably equal to the width of the gate trench 32.

[0183] The SiC semiconductor device 62 includes a source insulating layer 66 formed on the inner wall of each source trench 63. The SiC semiconductor device 62 also includes a source electrode layer 67 embedded in each source trench 63 with the source insulating layer 66 sandwiched therebetween. In FIG. 14, the source insulating layer 66 and the source electrode layer 67 are indicated by hatching.

[0184] The source insulating layer 66 is formed in a film shape along the inner wall of each source trench 63, and defines a recess space within each source trench 63. The source insulating layer 66 includes a first region 66a and a second region 66b. The first region 66a is formed along the side wall of each source trench 63. The second region 66b is formed along the bottom wall of each source trench 63.

[0185] The thickness Tsa of the first region 66a is less than the thickness Tsb of the second region 66b. The ratio Tsb / Tsa of the thickness Tsb of the second region 66b to the thickness Tsa of the first region 66a may be 2 or more and 5 or less. The thickness Tsa of the first region 66a may be 0.01 μm or more and 0.2 μm or less. The thickness Tsb of the second region 66b may be 0.05 μm or more and 0.5 μm or less.

[0186] The thickness Tsa of the first region 66a may be approximately equal to the thickness Ta of the first region 37a of the gate insulating layer 37. The thickness Tsb of the second region 66b may be approximately equal to the thickness Tb of the second region 37b of the gate insulating layer 37. The source insulating layer 66 may be formed to have a uniform thickness.

[0187] The source insulating layer 66 includes at least one of a silicon oxide (SiO2) layer, a silicon nitride (SiN) layer, an aluminum oxide (Al2O3) layer, a zirconium oxide (ZrO2) layer, and a tantalum oxide (Ta2O3) layer. The source insulating layer 66 may have a laminated structure including a SiN layer and a SiO2 layer laminated in this order from the first main surface 3 side.

[0188] The source insulating layer 66 may have a layered structure including an SiO2 layer and a SiN layer stacked in this order from the first main surface 3 side. The source insulating layer 66 may have a single-layer structure made of an SiO2 layer or an SiN layer. The source insulating layer 66 may contain the same insulating material as the gate insulating layer 37. In this embodiment, the source insulating layer 66 has a single-layer structure made of an SiO2 layer.

[0189] More specifically, the source electrode layer 67 is embedded in a recess space defined by the source insulating layer 66 in each source trench 63. The source electrode layer 67 is controlled by a source voltage. The source electrode layer 67 may include at least one of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, and a copper alloy.

[0190] The source electrode layer 67 preferably contains conductive polysilicon, which has properties similar to those of SiC. This reduces stress generated in the SiC semiconductor layer 2. The source electrode layer 67 may contain n-type polysilicon or p-type polysilicon, which are examples of conductive polysilicon. The source electrode layer 67 may contain the same conductive material as the gate electrode layer 38.

[0191] The contact region 42 for each cell region 39 is formed in a region along the inner wall of each source trench 63 in the surface layer portion of the SiC semiconductor layer 2. The contact region 42 shown in FIG. 9A or the offset compensation type contact region 42 shown in FIG. 11 may be formed.

[0192] Each contact region 42 covers the sidewall of each source trench 63. More specifically, each contact region 42 covers the sidewall and bottom wall of each source trench 63. Each contact region 42 has a bottom located on the second main surface 4 side of the bottom wall of the gate trench 32. The bottom of each contact region 42 may be formed parallel to the bottom wall of each source trench 63.

[0193] More specifically, each contact region 42 integrally includes a surface region 68 and an inner wall region 69 (bottom region). The surface region 68 is formed in a region along the sidewall of each source trench 63 in the surface portion of the body region 31. The surface region 68 is electrically connected to the body region 31 and the source region 41.

[0194] In plan view, the surface region 68 extends in a strip shape along the sidewall of each source trench 63. More specifically, the surface region 68 is formed in an endless shape (a quadrangular ring in this embodiment) surrounding the sidewall of each source trench 63 in plan view.

[0195] In this embodiment, the surface region 68 has a bottom that extends parallel to the first main surface 3. The surface region 68 is located in a region on the first main surface 3 side of the bottom of the source region 41. In this embodiment, the bottom of the surface region 68 is located in a region between the first main surface 3 and the bottom of the source region 41. The bottom of the surface region 68 may also be located in a region between the bottom of the body region 31 and the bottom of the source region 41.

[0196] The surface region 68 extends from the sidewall of each source trench 63 toward the gate trench 32. The surface region 68 may extend to an intermediate region between each source trench 63 and the gate trench 32. An end of the surface region 68 is located in the region between the source trench 63 and the gate trench 32.

[0197] The inner wall region 69 is formed in a region along the inner wall of each source trench 63 in the SiC semiconductor layer 2. The inner wall region 69 is located in a region on the second main surface 4 side with respect to the surface region 68 (the bottom of the source region 41).

[0198] The inner wall region 69 covers the sidewall of each source trench 63. The inner wall region 69 covers the corners connecting the sidewall and bottom wall of each source trench 63. The inner wall region 69 covers the sidewall of each source trench 63 through the corners and the bottom wall of each source trench 63. The bottom of each contact region 42 is formed by the inner wall region 69.

[0199] When the offset compensation type contact region 42 (see also FIG. 11) is employed, a portion of the p-type impurities (acceptors) in the surface region 68 is offset by the n-type impurities (donors) in the source region 41. This makes the surface region 68 of each contact region 42 an offset compensation type.

[0200] On the other hand, since the inner wall region 69 of each contact region 42 does not contact the source region 41, the p-type impurities (acceptors) in the inner wall region 69 are prevented from being offset by the n-type impurities (donors) in the source region 41. As a result, each contact region 42 has an offset-compensated region (surface region 68) in the surface region and an uncompensated region (inner wall region 69) in the bottom region.

[0201] The SiC semiconductor device 62 further includes a p-type deep well region 70 formed in the SiC semiconductor layer 2 in a region along the inner wall of each source trench 63. Each deep well region 70 is also referred to as a breakdown voltage adjusting region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 2 in the active region 6.

[0202] Each deep well region 70 is formed along the inner wall of each source trench 63 so as to cover each contact region 42. Each deep well region 70 is electrically connected to each contact region 42.

[0203] Each deep well region 70 covers the sidewall of each source trench 63. Each deep well region 70 covers the corners connecting the sidewall and bottom wall of each source trench 63. Each deep well region 70 covers the sidewall of each source trench 63 through the corners and the bottom wall of each source trench 63. Each deep well region 70 is continuous with the body region 31 on the sidewall of each source trench 63.

[0204] Each deep well region 70 has a bottom located on the second main surface 4 side relative to the bottom wall of the gate trench 32. The bottom of each deep well region 70 may be formed parallel to the bottom wall of each source trench 63. The distance between the bottom wall of the source trench 63 and the bottom of the deep well region 70 may be equal to the distance between the first main surface 3 and the bottom of the body region 31.

[0205] The peak value of the p-type impurity concentration of each deep well region 70 may be approximately equal to the p-type impurity concentration of the body region 31. The peak value of the p-type impurity concentration of each deep well region 70 may be greater than the peak value of the p-type impurity concentration of the body region 31. The peak value of the p-type impurity concentration of each deep well region 70 may be less than the peak value of the p-type impurity concentration of the body region 31.

[0206] The peak value of the p-type impurity concentration of each deep well region 70 may be equal to or less than the peak value P of the p-type impurity concentration of the contact region 42. It is preferable that the peak value of the p-type impurity concentration of each deep well region 70 is less than the peak value P of the p-type impurity concentration of the contact region 42.

[0207] The peak value of the p-type impurity concentration of each deep well region 70 is 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 The lower limit of the peak value of the p-type impurity concentration of each deep well region 70 may be 1.0×10 18 cm -3 It is preferable that this is equal to or greater than this.

[0208] Each deep well region 70 forms a pn junction with the SiC semiconductor layer 2 (drift region 25). A depletion layer extends from this pn junction toward the gate trench 32. This depletion layer extends toward a region on the second main surface 4 side of the bottom wall of the gate trench 32. The depletion layer extending from each deep well region 70 may overlap the bottom wall of the gate trench 32. The depletion layer extending from the bottom of each deep well region 70 may overlap the bottom wall of the gate trench 32.

[0209] In a SiC semiconductor device having only a pn junction diode, the problem of electric field concentration in the SiC semiconductor layer 2 is reduced due to the structure not having a trench. Each deep well region 70 brings the trench gate type MISFET closer to the structure of a pn junction diode. This allows the electric field in the SiC semiconductor layer 2 to be alleviated in the trench gate type MISFET.

[0210] Therefore, in order to alleviate electric field concentration, it is effective to narrow the pitch between adjacent deep well regions 70. Furthermore, by having each deep well region 70 having its bottom on the second main surface 4 side with respect to the bottom wall of the gate trench 32, the depletion layer can appropriately alleviate electric field concentration in the gate trench 32.

[0211] It is preferable that the distance between the bottom of each deep well region 70 and the second main surface 4 is approximately constant. This can prevent variations in the distance between the bottom of each deep well region 70 and the second main surface 4. This can prevent the breakdown voltage (e.g., breakdown resistance) of the SiC semiconductor layer 2 from being limited by the shape of each deep well region 70, thereby enabling the breakdown voltage to be appropriately improved.

[0212] The aforementioned source main surface electrode layer 13 (source pad 14) is electrically connected to the source region 41, the contact region 42, and the source electrode layer 67 in each source contact hole 52. The source main surface electrode layer 13 (source pad 14) forms ohmic contact with the source region 41.

[0213] 9A is formed, the source principal surface electrode layer 13 may form a Schottky junction with the contact region 42. When the contact region 42 shown in FIG. 11 is formed, the source principal surface electrode layer 13 may form an ohmic contact or a Schottky junction with the contact region 42.

[0214] As described above, SiC semiconductor device 62 can also achieve the same effects as those described for SiC semiconductor device 1.

[0215] Fig. 16 is a plan view of a region corresponding to Fig. 14, showing a SiC semiconductor device 71 according to a fourth embodiment of the present invention. In the following, structures corresponding to those described for the SiC semiconductor device 62 according to the third embodiment are given the same reference numerals, and descriptions thereof will be omitted.

[0216] 16, SiC semiconductor device 71 includes gate trenches 32 formed in a stripe shape in plan view. That is, gate trench 32 includes only one of a plurality of first gate trenches 33 and a plurality of second gate trenches 34. In this embodiment, gate trench 32 does not include second gate trenches 34, and includes only a plurality of first gate trenches 33.

[0217] In this embodiment, the body region 31 extends in a strip shape along the gate trench 32 in the region between two adjacent gate trenches 32. In this embodiment, each source trench 63 is formed in the region between two adjacent gate trenches 32.

[0218] In this embodiment, each source trench 63 is formed in a strip shape extending along the gate trench 32. The source trenches 63 are formed in a stripe shape extending along the first direction X in a plan view.

[0219] Each source region 41 is formed in a region between the gate trench 32 and the source trench 63 in a surface layer portion of the body region 31. Each source region 41 is formed in a strip shape extending along the gate trench 32. The multiple source regions 41 are formed in stripes extending along the first direction X in a plan view.

[0220] Each source region 41 is exposed from the sidewall of the gate trench 32 and the sidewall of the source trench 63. The channel of the MISFET is formed in the body region 31 in a region along the sidewall of the gate trench 32 formed by the a-plane of the SiC single crystal.

[0221] In this embodiment, each contact region 42 is formed in a region along the sidewall of each source trench 63 in the surface layer portion of the body region 31. The contact region 42 shown in FIG. 9A or the offset compensation type contact region 42 shown in FIG. 11 may be formed. In this embodiment, a plurality of contact regions 42 are formed at intervals for one source trench 63. Although specific illustration is omitted, each contact region 42 integrally includes a surface region 68 and an inner wall region 69 (bottom region).

[0222] In this embodiment, each deep well region 70 is formed in a region along the sidewall of each source trench 63 in the surface layer portion of the body region 31. In this embodiment, a plurality of deep well regions 70 are formed in a one-to-one correspondence with a plurality of source trenches 63. In other words, one deep well region 70 is formed for one source trench 63.

[0223] Each deep well region 70 is formed in a strip shape extending along each source trench 63 in a plan view. Each deep well region 70 may be exposed from the first main surface 3 in a region between adjacent contact regions 42.

[0224] As described above, the SiC semiconductor device 71 can also achieve the same effects as those described for the SiC semiconductor device 1.

[0225] Fig. 17 is a cross-sectional view of a region corresponding to Fig. 15, showing a SiC semiconductor device 72 according to a fifth embodiment of the present invention. In the following, structures corresponding to those described for the SiC semiconductor device 62 according to the third embodiment are given the same reference numerals, and descriptions thereof will be omitted.

[0226] 17 , in this embodiment, the depth of each source trench 63 in the SiC semiconductor device 72 is equal to or greater than the depth of the gate trench 32. More specifically, the depth of each source trench 63 exceeds the depth of the gate trench 32. The bottom wall of each source trench 63 is located on the second main surface 4 side relative to the bottom wall of the gate trench 32. The bottom wall of each source trench 63 is located on the SiC epitaxial layer 22 side relative to the boundary between the SiC semiconductor substrate 21 and the SiC epitaxial layer 22.

[0227] The depth of each source trench 63 in the normal direction Z may be 0.5 μm or more and 10 μm or less. The ratio of the depth of each source trench 63 to the depth of the gate trench 32 may be 1.5 or more. The ratio of the depth of each source trench 63 to the depth of the gate trench 32 is preferably 2 or more.

[0228] As described above, the SiC semiconductor device 72 can also achieve the same effects as those described for the SiC semiconductor device 1. The structure of the source trench 63 of the SiC semiconductor device 72 may be applied to the SiC semiconductor device 71 according to the fourth embodiment (see FIG. 16).

[0229] Fig. 18 is a plan view of a region corresponding to Fig. 14, showing a SiC semiconductor device 75 according to a sixth embodiment of the present invention. Fig. 19 is a cross-sectional view taken along line XIX-XIX shown in Fig. 18. Fig. 20 is a cross-sectional view taken along line XX-XX shown in Fig. 18. In the following, structures corresponding to those described with respect to the SiC semiconductor device 71 will be given the same reference numerals and will not be described again.

[0230] The SiC semiconductor device 62 according to the third embodiment includes a source trench 63 formed in a pattern in which one trench appears on a cross section of each cell region 39 taken along the first direction X and the second direction Y. In contrast, referring to FIGS. 18 to 20, the SiC semiconductor device 75 includes a source trench 63 formed in a pattern in which two trenches appear on a cross section of each cell region 39 taken along the first direction X. The source trenches 63 are further formed in a pattern in which two trenches appear on a cross section of each cell region 39 taken along the second direction Y.

[0231] More specifically, each source trench 63 is formed in an endless shape (for example, a rectangular ring shape) extending along the first direction X and the second direction Y so as to define the inner region of each cell region 39 in plan view. The sidewalls forming the inner peripheral wall of each source trench 63 are formed by the m-plane and a-plane of the SiC single crystal. In addition, the sidewalls forming the outer peripheral wall of each source trench 63 are formed by the m-plane and a-plane of the SiC single crystal.

[0232] The planar shape of each source trench 63 is arbitrary. Each source trench 63 may be formed in a polygonal ring shape such as a triangular ring, a pentagonal ring, or a hexagonal ring, or in a circular or elliptical ring shape in plan view.

[0233] Each cell region 39 includes a mesa portion 76 and an annular portion 77 defined by the gate trench 32 and each source trench 63. The mesa portion 76 and the annular portion 77 each form the first main surface 3. Each mesa portion 76 is defined by the inner peripheral wall of each source trench 63. In this embodiment, each mesa portion 76 is defined in a quadrangular shape in plan view. The planar shape of each mesa portion 76 can take various shapes depending on the planar shape of each source trench 63.

[0234] Each annular portion 77 is defined by the outer peripheral wall of each source trench 63 and the side wall of each gate trench 32. Each annular portion 77 is defined in an endless shape (for example, a rectangular ring) in plan view. The planar shape of each mesa portion 76 can take various shapes depending on the planar shapes of the gate trench 32 and each source trench 63.

[0235] The body region 31 is formed in a surface layer portion of the mesa portion 76 and a surface layer portion of the annular portion 77 in each cell region 39. The body region 31 is exposed from the sidewall of the gate trench 32 and the inner and outer peripheral walls of the source trench 63 in each cell region 39.

[0236] Each source region 41 is formed in a surface layer portion of the annular portion 77 in each cell region 39. The source region 41 is exposed from the sidewall of the gate trench 32 and the outer peripheral wall of the source trench 63 in each cell region 39.

[0237] Each contact region 42 is formed in a region along the inner wall of each source trench 63 in the surface layer portion of the SiC semiconductor layer 2. The contact region 42 shown in FIG. 9A or the offset compensation type contact region 42 shown in FIG. 11 may be formed.

[0238] Each contact region 42 is formed in a surface layer portion of the mesa portion 76 in each cell region 39. Each contact region 42 is formed in a surface layer portion of the annular portion 77 in each cell region 39. Each contact region 42 is formed in a region of the SiC semiconductor layer 2 that covers the inner wall of each source trench 63. The bottom of each contact region 42 may be formed parallel to the bottom wall of each source trench 63.

[0239] More specifically, each contact region 42 integrally includes an inner surface region 78, an outer surface region 79, and an inner wall region 80 (bottom region). The inner surface region 78 is formed in the surface portion of the body region 31 in the mesa portion 76. The inner surface region 78 is formed over the entire surface portion of the body region 31 in the mesa portion 76. The inner surface region 78 is electrically connected to the body region 31.

[0240] In this embodiment, the inner surface region 78 has a bottom that extends parallel to the first main surface 3. The inner surface region 78 is exposed from the inner circumferential wall of the source trench 63. The entire area of ​​the exposed portion of the mesa portion 76 that is exposed from the first main surface 3 is formed by the contact region 42.

[0241] The inner surface region 78 may extend in a strip shape along the inner circumferential wall of the source trench 63 in a plan view, exposing the body region 31 from the mesa portion 76. The inner surface region 78 may be formed in an endless shape (for example, a rectangular ring shape) along the inner circumferential wall of the source trench 63 in a plan view. In this case, the inner surface region 78 may expose the body region 31 from the center of the mesa portion 76.

[0242] The outer surface region 79 is formed in the surface portion of the body region 31 in the annular portion 77. The outer surface region 79 is electrically connected to the body region 31 and the source region 41. The outer surface region 79 is selectively formed in a region along the outer peripheral wall of the source trench 63 in the surface portion of the body region 31.

[0243] In this embodiment, the outer surface region 79 has a bottom that extends parallel to the first main surface 3. The depth of the outer surface region 79 is approximately equal to the depth of the inner surface region 78. The outer surface region 79 is located in a region on the first main surface 3 side of the bottom of the source region 41. In this embodiment, the bottom of the outer surface region 79 is located in a region between the first main surface 3 and the bottom of the source region 41. The bottom of the outer surface region 79 may also be located in a region between the bottom of the body region 31 and the bottom of the source region 41.

[0244] In this embodiment, the outer surface region 79 extends from the outer peripheral wall of the source trench 63 toward the gate trench 32. The outer surface region 79 is formed at an interval from the gate trench 32 toward the source trench 63. An end of the outer surface region 79 is located in the region between the gate trench 32 and the source trench 63.

[0245] In this embodiment, a plurality of outer surface regions 79 are selectively formed in a surface portion of the body region 31 in regions along the outer peripheral wall of the source trench 63. The plurality of outer surface regions 79 are formed at intervals along the outer peripheral wall of the source trench 63. In this embodiment, one outer surface region 79 is formed for each of the two outer peripheral walls extending in the first direction X and the two outer peripheral walls extending in the second direction Y in the source trench 63.

[0246] The two outer surface layer regions 79 formed along the two outer peripheral walls of the source trench 63 extending in the first direction X face each other in the second direction Y. The two outer surface layer regions 79 formed along the two outer peripheral walls of the source trench 63 extending in the first direction X may be shifted in the first direction X so as not to face each other in the second direction Y.

[0247] The two outer surface layer regions 79 formed along the two outer peripheral walls of the source trench 63 extending in the second direction Y face each other in the first direction X. The two outer surface layer regions 79 formed along the two outer peripheral walls of the source trench 63 extending in the second direction Y may be shifted in the second direction Y so as not to face each other in the first direction X.

[0248] A plurality of outer surface layer regions 79 may be formed on the outer peripheral wall of each source trench 63. Alternatively, an outer surface layer region 79 extending in a strip shape along the outer peripheral wall of the source trench 63 may be formed. Alternatively, an endless (for example, rectangular ring-shaped) outer surface layer region 79 may be formed surrounding the outer peripheral wall of the source trench 63.

[0249] The inner wall region 80 is located in a region closer to the second main surface 4 than the inner surface region 78 and the outer surface region 79 (the bottom of the source region 41). The inner wall region 80 includes a first region 81 and a second region 82. The first region 81 is connected to the inner surface region 78 and covers the inner peripheral wall of the source trench 63. The second region 82 is connected to the outer surface region 79 and covers the outer peripheral wall of the source trench 63.

[0250] The first region 81 covers a corner portion connecting the inner peripheral wall and the bottom wall of the source trench 63. The first region 81 covers from the inner peripheral wall of the source trench 63 through the corner portion to the bottom wall of the source trench 63. The first region 81 has a first end portion located on the bottom wall of the source trench 63.

[0251] The second region 82 covers a corner portion connecting the outer peripheral wall and bottom wall of the source trench 63. The second region 82 covers from the outer peripheral wall of the source trench 63 through the corner portion to the bottom wall of the source trench 63. The second region 82 has a second end portion located on the bottom wall of the source trench 63. The second end portion of the second region 82 is continuous with the first end portion of the first region 81 at the bottom wall of the source trench 63.

[0252] When the offset compensation type contact region 42 (see also FIG. 11 ) is employed, the inner surface region 78 does not contact the source region 41, and therefore, the p-type impurities (acceptors) in the inner surface region 78 are prevented from being offset compensated by the n-type impurities (donors) in the source region 41. In addition, the inner wall region 80 does not contact the source region 41, and therefore, the p-type impurities (acceptors) in the inner wall region 80 are prevented from being offset compensated by the n-type impurities (donors) in the source region 41.

[0253] On the other hand, a portion of the p-type impurities (acceptors) in the outer surface region 79 is offset by the n-type impurities (donors) in the source region 41. This makes the outer surface region 79 of each contact region 42 an offset-compensated type. In this way, each contact region 42 has an offset-compensated region (outer surface region 79) in the surface region and an uncompensated region (inner wall region 80) in the bottom region.

[0254] Each deep well region 70 is formed along the inner wall of each source trench 63 so as to cover each contact region 42, similar to the case of the SiC semiconductor device 62 according to the third embodiment.

[0255] As described above, SiC semiconductor device 75 can also achieve the same effects as those described for SiC semiconductor device 1.

[0256] Fig. 21 is a cross-sectional view of a region corresponding to Fig. 19, showing a SiC semiconductor device 85 according to a seventh embodiment of the present invention. In the following, structures corresponding to those described for the SiC semiconductor device 75 according to the sixth embodiment are given the same reference numerals, and descriptions thereof will be omitted.

[0257] 21 , in this embodiment, the depth of each source trench 63 in the SiC semiconductor device 85 is equal to or greater than the depth of the gate trench 32. More specifically, the depth of each source trench 63 exceeds the depth of the gate trench 32. The bottom wall of each source trench 63 is located on the second main surface 4 side relative to the bottom wall of the gate trench 32. The bottom wall of each source trench 63 is located on the SiC epitaxial layer 22 side relative to the boundary between the SiC semiconductor substrate 21 and the SiC epitaxial layer 22.

[0258] The depth of each source trench 63 in the normal direction Z may be 0.5 μm or more and 10 μm or less. The ratio of the depth of each source trench 63 to the depth of the gate trench 32 may be 1.5 or more. The ratio of the depth of each source trench 63 to the depth of the gate trench 32 is preferably 2 or more.

[0259] As described above, SiC semiconductor device 85 can also achieve the same effects as those described for SiC semiconductor device 1.

[0260] Fig. 22 is a plan view showing a SiC semiconductor device 101 according to an eighth embodiment of the present invention. Fig. 23 is a plan view of Fig. 22 from which a resin layer 118 has been removed.

[0261] 22 and 23, SiC semiconductor device 101 includes a SiC semiconductor layer 102. SiC semiconductor layer 102 includes a 4H—SiC single crystal as an example of a SiC single crystal made of a hexagonal crystal. SiC semiconductor layer 102 is formed in the shape of a rectangular parallelepiped chip.

[0262] The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, and 105D connecting the first main surface 103 and the second main surface 104. The first main surface 103 and the second main surface 104 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0263] The first main surface 103 is an element formation surface on which a semiconductor element is formed. The second main surface 104 may be a ground surface having grinding marks. In this embodiment, the first main surface 103 and the second main surface 104 face the c-plane of the SiC single crystal. The first main surface 103 faces the (0001) plane (silicon plane). The second main surface 104 faces the (000-1) plane (carbon plane) of the SiC single crystal. The first main surface 103 has an off-angle θ inclined at an angle of 10° or less in the [11-20] direction with respect to the (0001) plane of the SiC single crystal. The normal direction Z is inclined by the off-angle θ with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0264] The off angle θ may be 0° or more and 5.0° or less. The off angle θ may be set in the range of 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, 2.5° or more and 3.0° or less, 3.0° or more and 3.5° or less, 3.5° or more and 4.0° or less, 4.0° or more and 4.5° or less, or 4.5° or more and 5.0° or less. The off angle θ is preferably greater than 0°. The off angle θ may be less than 4.0°.

[0265] The off angle θ may be set in the range of 3.0° to 4.5°. In this case, the off angle θ is preferably set in the range of 3.0° to 3.5°, or 3.5° to 4.0°. The off angle θ may be set in the range of 1.5° to 3.0°. In this case, the off angle θ is preferably set in the range of 1.5° to 2.0°, or 2.0° to 2.5°.

[0266] More specifically, the side surfaces 105A to 105D include a first side surface 105A, a third side surface 105C, and a fourth side surface 105D. In this embodiment, the first side surface 105A and the third side surface 105C extend along a first direction X and face a second direction Y that intersects with the first direction X. The first side surface 105A and the third side surface 105C form the short sides of the SiC semiconductor layer 102 in a plan view.

[0267] In this embodiment, the second side surface 105B and the fourth side surface 105D extend along the second direction Y and face the first direction X. The second side surface 105B and the fourth side surface 105D form the long sides of the SiC semiconductor layer 102 in a plan view. More specifically, the second direction Y is a direction perpendicular to the first direction X. The length of each of the side surfaces 105A to 105D may be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0268] The side surfaces 105A to 105D may each be a smooth cleavage plane facing the crystal plane of the SiC single crystal. The side surfaces 105A to 105D may each be a ground surface having grinding marks. In this embodiment, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

[0269] That is, the first side surface 105A and the third side surface 105C are formed by the a-plane of the SiC single crystal and face each other in the a-axis direction of the SiC single crystal. The first side surface 105A is formed by the (-1-120) plane of the SiC single crystal. The third side surface 105C is formed by the (11-20) plane of the SiC single crystal. The second side surface 105B and the fourth side surface 105D are formed by the m-plane of the SiC single crystal and face each other in the m-axis direction of the SiC single crystal. The second side surface 105B is formed by the (-1100) plane of the SiC single crystal. The fourth side surface 105D is formed by the (1-100) plane of the SiC single crystal.

[0270] When the normal to first main surface 103 is taken as a reference, first side surface 105A and third side surface 105C may form an inclined surface that is inclined toward the c-axis direction (0001 direction) of the SiC single crystal with respect to the normal. When the normal to first main surface 103 is set to 0°, first side surface 105A and third side surface 105C may be inclined at an angle corresponding to off angle θ with respect to the normal to first main surface 103. The angle corresponding to off angle θ may be equal to off angle θ or may be an angle greater than 0° and less than off angle θ.

[0271] The SiC semiconductor layer 102 includes an active region 106 and an outer region 107. The active region 106 is a region in which a vertical MISFET is formed. In plan view, the active region 106 is formed in the center of the SiC semiconductor layer 102, spaced apart from the side surfaces 105A to 105D toward the inner region. In plan view, the active region 106 is formed in a quadrangular shape (rectangular in this embodiment) having four sides parallel to the side surfaces 105A to 105D.

[0272] The outer region 107 is a region outside the active region 106. The outer region 107 is formed in a region between the side surfaces 105A to 105D and the active region 106. The outer region 107 is formed in an endless shape (a quadrangular ring in this embodiment) surrounding the active region 106 in a plan view.

[0273] The SiC semiconductor device 101 includes a gate principal surface electrode layer 108 as one of the first principal surface electrode layers formed on the first principal surface 103. A gate voltage is applied to the gate principal surface electrode layer 108. The gate voltage may be 10 V or more and 50 V or less (for example, approximately 30 V). The gate principal surface electrode layer 108 includes a gate pad 109 and gate fingers 110 and 111. The gate pad 109 and the gate fingers 110 and 111 are arranged in the active region 106.

[0274] Gate pad 109 is formed in a region along first side surface 105A in plan view. In this embodiment, gate pad 109 is formed in a region along the center of first side surface 105A in plan view. Gate pad 109 may be formed in a quadrangular shape in plan view. Gate pad 109 may be formed along a corner connecting any two of side surfaces 105A to 105D in plan view.

[0275] The gate fingers 110, 111 include outer gate fingers 110 and inner gate fingers 111. The outer gate fingers 110 are drawn out from the gate pad 109 and extend in a strip shape along the periphery of the active area 106. In this embodiment, the outer gate fingers 110 are formed along three side surfaces 105A, 105B, and 105D, and define the inner area of ​​the active area 106 from three directions.

[0276] The outer gate finger 110 has a pair of open ends 112, 113. The pair of open ends 112, 113 are formed in a region facing the gate pad 109 across an inner region of the active region 106. In this embodiment, the pair of open ends 112, 113 are formed in a region along the third side surface 105C.

[0277] The inner gate finger 111 is drawn out from the gate pad 109 to an inner region of the active region 106. The inner gate finger 111 extends in a strip shape in the inner region of the active region 106. The inner gate finger 111 extends from the gate pad 109 toward the third side surface 105C.

[0278] The SiC semiconductor device 101 includes a source main surface electrode layer 114 as one of the first main surface electrode layers formed on the first main surface 103. A source voltage is applied to the source main surface electrode layer 114. The source voltage may be a reference voltage (e.g., a GND voltage). In this embodiment, the source main surface electrode layer 114 includes a source pad 115, a source lead-out wiring 116, and a source connection portion 117.

[0279] The source pad 115 is formed in the active region 106 at a distance from the gate main surface electrode layer 108. The source pad 115 is formed in a C-shape (an inverted C-shape in FIGS. 22 and 23) in plan view so as to cover a C-shaped region (an inverted C-shape in FIGS. 22 and 23) defined by the gate pad 109 and the gate fingers 110 and 111.

[0280] The source lead-out wiring 116 is formed in the outer region 107. The source lead-out wiring 116 extends in a strip shape along the active region 106. In this embodiment, the source lead-out wiring 116 is formed in an endless shape (a quadrangular ring shape in this embodiment) surrounding the active region 106 in a plan view. The source lead-out wiring 116 is electrically connected to the SiC semiconductor layer 102 in the outer region 107.

[0281] The source connection portion 117 connects the source pad 115 and the source lead-out line 116. The source connection portion 117 is provided in a region between a pair of open ends 112, 113 of the outer gate finger 110. The source connection portion 117 extends from the source pad 115 across the boundary region between the active region 106 and the outer region 107, and is connected to the source lead-out line 116.

[0282] The MISFET formed in the active region 106 includes an npn-type parasitic bipolar transistor due to its structure. When an avalanche current generated in the outer region 107 flows into the active region 106, the parasitic bipolar transistor turns on. In this case, there is a possibility that the control of the MISFET becomes unstable due to, for example, latch-up.

[0283] Therefore, in the SiC semiconductor device 101, an avalanche current absorption structure is formed that absorbs the avalanche current generated in the outer region 107 by utilizing the structure of the source principal surface electrode layer 114. More specifically, the avalanche current generated in the outer region 107 is absorbed by the source lead-out wiring 116. The avalanche current absorbed by the source lead-out wiring 116 reaches the source pad 115 via the source connection portion 117.

[0284] When a conductor (e.g., a bonding wire) for external connection is connected to the source pad 115, the avalanche current is extracted by this conductor. This prevents the parasitic bipolar transistor from turning on due to unwanted current generated in the outer region 107. This prevents latch-up, thereby improving the stability of MISFET control.

[0285] The SiC semiconductor device 101 includes a resin layer 118 formed on the first main surface 103. In FIG. 22, the resin layer 118 is indicated by hatching. The resin layer 118 may include a negative-type or positive-type photosensitive resin. In this embodiment, the resin layer 118 includes polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 118 may also include polyimide as an example of a negative-type photosensitive resin.

[0286] The resin layer 118 selectively covers the gate principal surface electrode layer 108 and the source principal surface electrode layer 114. The resin layer 118 includes a gate pad opening 119 and a source pad opening 120. The gate pad opening 119 exposes the gate pad 109. The source pad opening 120 exposes the source pad 115.

[0287] The peripheral portion 118a of the resin layer 118 is formed at a distance inward from the side surfaces 105A to 105D. As a result, the resin layer 118 defines dicing streets DS between the side surfaces 105A to 105D in a plan view, exposing the peripheral portion of the SiC semiconductor layer 102. The dicing streets DS eliminate the need to physically cut the resin layer 118. This allows the SiC semiconductor devices 101 to be smoothly cut out from a single SiC semiconductor wafer. Furthermore, the insulation distance from the side surfaces 105A to 105D can be increased.

[0288] The width of the dicing street DS may be 1 μm or more and 25 μm or less. The width of the dicing street DS is the width in a direction perpendicular to the direction in which the dicing street DS extends. The width of the dicing street DS may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less.

[0289] Fig. 24 is an enlarged view of region XXIV shown in Fig. 23 and is a view for explaining the structure of the first main surface 103. Fig. 25 is a cross-sectional view taken along line XXV-XXV shown in Fig. 24. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI shown in Fig. 24. Fig. 27 is an enlarged view of region XXVII shown in Fig. 25. Fig. 28 is a cross-sectional view taken along line XXVIII-XXVIII shown in Fig. 23. Fig. 29 is an enlarged view of region XXIX shown in Fig. 28.

[0290] 24 to 28, in this embodiment, the SiC semiconductor layer 102 is + The MISFET has a layered structure including an n-type SiC semiconductor substrate 121 and an n-type SiC epitaxial layer 122. The SiC semiconductor substrate 121 is formed as a drain region 126 of the MISFET. The SiC epitaxial layer 122 is formed as a drift region 127 of the MISFET. The SiC semiconductor substrate 121 forms a second main surface 104. The SiC epitaxial layer 122 forms a first main surface 103. The SiC semiconductor substrate 121 and the SiC epitaxial layer 122 form side surfaces 105A to 105D.

[0291] The thickness of the SiC semiconductor substrate 121 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor substrate 121 may be 1 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, 500 μm or more and 600 μm or less, 600 μm or more and 700 μm or less, 700 μm or more and 800 μm or less, 800 μm or more and 900 μm or less, or 900 μm or more and 1000 μm or less. The thickness of the SiC semiconductor substrate 121 is preferably 10 μm or more and 150 μm or less. By thinning the SiC semiconductor substrate 121, the resistance value can be reduced by shortening the current path.

[0292] The n-type impurity concentration of the SiC epitaxial layer 122 is equal to or lower than the n-type impurity concentration of the SiC semiconductor substrate 121. More specifically, the n-type impurity concentration of the SiC epitaxial layer 122 is lower than the n-type impurity concentration of the SiC semiconductor substrate 121. The n-type impurity concentration of the SiC semiconductor substrate 121 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The n-type impurity concentration of the SiC epitaxial layer 122 may be 1.0×10 or less. 15 cm -3 Over 1.0 x 10 18 cm -3 It may be the following:

[0293] In this embodiment, the SiC epitaxial layer 122 has a plurality of regions having different n-type impurity concentrations along the normal direction Z. More specifically, the SiC epitaxial layer 122 includes a high-concentration region 123 having a relatively high n-type impurity concentration, and a low-concentration region 124 having a lower n-type impurity concentration than the high-concentration region 123.

[0294] The n-type impurity concentration of the high concentration region 123 is 1.0×10 16 cm -3 Over 1.0 x 10 18 cm -3The n-type impurity concentration of the low concentration region 124 may be 1.0×10 15 cm -3 Over 1.0 x 10 16 cm -3 It may be the following:

[0295] The high concentration region 123 is formed in a region on the first main surface 103 side. The low concentration region 124 is formed in a region on the second main surface 104 side of the high concentration region 123. The thickness of the high concentration region 123 is equal to or less than the thickness of the low concentration region 124. More specifically, the thickness of the high concentration region 123 is less than the thickness of the low concentration region 124. The thickness of the high concentration region 123 is less than half the total thickness of the SiC epitaxial layer 122.

[0296] The thickness of the SiC epitaxial layer 122 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 122 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, or 90 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 122 is preferably less than the thickness of the SiC semiconductor substrate 121. The thickness of the SiC epitaxial layer 122 is preferably 5 μm or more and 15 μm or less.

[0297] The SiC semiconductor device 101 includes a drain electrode layer 125 as a second principal surface electrode layer formed on the second principal surface 104. The drain electrode layer 125 forms an ohmic contact with the second principal surface 104. A drain voltage is applied to the drain electrode layer 125. In the off state, the maximum voltage that can be applied between the source principal surface electrode layer 114 and the drain electrode layer 125 may be 1000 V or more and 10000 V or less.

[0298] The drain electrode layer 125 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The drain electrode layer 125 may have a single layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The drain electrode layer 125 may have a layered structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are stacked in any manner. The drain electrode layer 125 may have a layered structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in this order from the second main surface 104.

[0299] The SiC semiconductor device 101 includes a p-type body region 131 formed in a surface layer portion of the first main surface 103 in the active region 106. In this embodiment, the body region 131 is formed over the entire area of ​​the first main surface 103 that forms the active region 106. In other words, the body region 131 defines the active region 106.

[0300] The peak value of the p-type impurity concentration of the body region 131 is 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 The lower limit of the peak value of the p-type impurity concentration in the body region 131 may be 1.0×10 18 cm -3 It is preferable that this is equal to or greater than this.

[0301] The SiC semiconductor device 101 includes a plurality of gate trenches 132 (trench) formed in a surface layer portion of the first main surface 103 in the active region 106. The plurality of gate trenches 132 are each formed in a band shape extending along a first direction X and are formed at intervals along a second direction Y. The plurality of gate trenches 132 are formed in a stripe shape extending along the first direction X in a plan view.

[0302] One end of each gate trench 132 is located on one side of the periphery of the active region 106. The other end of each gate trench 132 is located on the other side of the periphery of the active region 106. In this embodiment, each gate trench 132 extends in a strip shape from the periphery on one side (the second side surface 105B side) of the active region 106 to the periphery on the other side (the fourth side surface 105D side). Each gate trench 132 crosses the middle part between the periphery on one side and the periphery on the other side of the active region 106.

[0303] The length of each gate trench 132 may be 0.5 mm or more. The length of each gate trench 132 is the length from the end of the gate trench 132 and the gate fingers 110, 111 on the connection side to the opposite end in the cross section shown in FIG. 26. In this embodiment, the length of each gate trench 132 is 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). The total length of one or more gate trenches 132 per unit area is 0.5 μm / μm. 2 More than 0.75μm / μm 2 It may be the following:

[0304] Each gate trench 132 integrally includes an active trench portion 133 and a contact trench portion 134. The active trench portion 133 is a portion along the channel of the MISFET in the active region 106. The contact trench portion 134 is a portion of the gate trench 132 that is primarily intended for contact with the outer gate finger 110.

[0305] The contact trench portion 134 is drawn out from the active trench portion 133 to the peripheral edge portion of the active region 106. The contact trench portion 134 is formed in the region directly below the outer gate finger 110. The amount of drawing of the contact trench portion 134 is arbitrary.

[0306] Each gate trench 132 penetrates the body region 131 and reaches the drift region 127 (SiC epitaxial layer 122). Each gate trench 132 includes a sidewall and a bottom wall. The sidewalls forming the long sides of each gate trench 132 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of each gate trench 132 are formed by the m-plane of the SiC single crystal.

[0307] The sidewalls of each gate trench 132 may extend along the normal direction Z. The sidewalls of each gate trench 132 may be formed substantially perpendicular to the first main surface 103. The angle that the sidewalls of each gate trench 132 form with the first main surface 103 in the SiC semiconductor layer 102 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). Each gate trench 132 may be formed in a tapered shape such that the bottom area is less than the opening area.

[0308] The bottom wall of each gate trench 132 is located in the drift region 127 (SiC epitaxial layer 122). More specifically, the bottom wall of each gate trench 132 is located in the high-concentration region 123 of the SiC epitaxial layer 122. The bottom wall of each gate trench 132 faces the c-plane of the SiC single crystal. The bottom wall of each gate trench 132 has an off-angle θ inclined in the [11-20] direction with respect to the (0001) plane of the SiC single crystal. The bottom wall of each gate trench 132 may be formed parallel to the first main surface 103. The bottom wall of each gate trench 132 may be formed in a convex curved shape facing the second main surface 104.

[0309] The depth of each gate trench 132 in the normal direction Z may be 0.5 μm to 3.0 μm inclusive. The depth of each gate trench 132 may be 0.5 μm to 1.0 μm inclusive, 1.0 μm to 1.5 μm inclusive, 1.5 μm to 2.0 μm inclusive, 2.0 μm to 2.5 μm inclusive, or 2.5 μm to 3.0 μm inclusive.

[0310] The width of each gate trench 132 along the second direction Y may be 0.1 μm or more and 2 μm or less. The width of each gate trench 132 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0311] 27 , opening edge portion 136 of each gate trench 132 includes an inclined portion 137 that slopes downward from first main surface 103 toward the inside of each gate trench 132. Opening edge portion 136 of each gate trench 132 is a corner that connects first main surface 103 and the sidewall of each gate trench 132.

[0312] In this embodiment, the inclined portions 137 are formed in a concave curved shape directed inwardly of the SiC semiconductor layer 102. The inclined portions 137 may be formed in a convex curved shape directed inwardly of each gate trench 132. The inclined portions 137 reduce electric field concentration at the opening edge portions 136 of each gate trench 132.

[0313] The SiC semiconductor device 101 includes a gate insulating layer 138 formed on the inner wall of each gate trench 132. The SiC semiconductor device 101 also includes a gate electrode layer 139 embedded in each gate trench 132 with the gate insulating layer 138 sandwiched therebetween. In FIG. 24 , the gate insulating layer 138 and the gate electrode layer 139 are indicated by hatching.

[0314] The gate insulating layer 138 is formed in a film shape along the inner wall surface of the gate trench 132, and defines a recess space within the gate trench 132. The gate insulating layer 138 includes a first region 138a, a second region 138b, and a third region 138c. The first region 138a is formed along the side wall of the gate trench 132. The second region 138b is formed along the bottom wall of the gate trench 132. The third region 138c is formed along the first main surface 103.

[0315] The thickness Ta of the first region 138a is less than the thickness Tb of the second region 138b and the thickness Tc of the third region 138c. The ratio Tb / Ta of the thickness Tb of the second region 138b to the thickness Ta of the first region 138a may be equal to or greater than 2 and equal to or less than 5. The ratio Tc / Ta of the thickness Tc of the third region 138c to the thickness Ta of the first region 138a may be equal to or greater than 2 and equal to or less than 5.

[0316] The thickness Ta of the first region 138a may be 0.01 μm or more and 0.2 μm or less, the thickness Tb of the second region 138b may be 0.05 μm or more and 0.5 μm or less, and the thickness Tc of the third region 138c may be 0.05 μm or more and 0.5 μm or less.

[0317] By thinning the first region 138a, it is possible to suppress an increase in carriers induced in the body region 131 in the region near the sidewall of each gate trench 132. This makes it possible to suppress an increase in channel resistance. By thickening the second region 138b, it is possible to alleviate electric field concentration on the bottom wall of each gate trench 132.

[0318] The thickening of the third region 138c improves the breakdown voltage of the gate insulating layer 138 near the opening edge 136 of each gate trench 132. Furthermore, the thickening of the third region 138c can suppress the loss of the third region 138c due to the etching method. This suppresses further loss of the first region 138a due to the etching method. Therefore, the gate electrode layer 139 can be appropriately opposed to the SiC semiconductor layer 102 (body region 131) with the gate insulating layer 138 sandwiched therebetween.

[0319] The gate insulating layer 138 further includes a bulging portion 138d that bulges into each gate trench 132 at the opening edge portion 136 of each gate trench 132. The bulging portion 138d is formed at a corner that connects the first region 138a and the third region 138c of the gate insulating layer 138. The bulging portion 138d bulges in a convex curved shape toward the inside of each gate trench 132.

[0320] The bulging portion 138d narrows the opening of each gate trench 132 at the opening edge portion 136 of each gate trench 132. The bulging portion 138d increases the dielectric strength of the gate insulating layer 138 at the opening edge portion 136. A gate insulating layer 138 that does not have the bulging portion 138d may be formed. Alternatively, a gate insulating layer 138 having a uniform thickness may be formed.

[0321] The gate insulating layer 138 includes at least one of a silicon oxide (SiO2) layer, a silicon nitride (SiN) layer, an aluminum oxide (Al2O3) layer, a zirconium oxide (ZrO2) layer, and a tantalum oxide (Ta2O3) layer. The gate insulating layer 138 may have a layered structure including a SiN layer and a SiO2 layer stacked in this order from the first main surface 103 side.

[0322] The gate insulating layer 138 may have a layered structure including an SiO2 layer and an SiN layer stacked in this order from the first main surface 103 side. The gate insulating layer 138 may have a single-layer structure made of an SiO2 layer or an SiN layer. In this embodiment, the gate insulating layer 138 has a single-layer structure made of an SiO2 layer.

[0323] The gate electrode layer 139 is embedded in a recess space defined by the gate insulating layer 138 in each gate trench 132. The gate electrode layer 139 is controlled by a gate voltage. The gate electrode layer 139 has an upper end portion located on the opening side of each gate trench 132. The upper end portion of the gate electrode layer 139 is formed in a concave curved shape recessed toward the bottom wall of each gate trench 132. The upper end portion of the gate electrode layer 139 has a constricted portion that is constricted along the bulging portion 138d of the gate insulating layer 138.

[0324] The cross-sectional area of ​​the gate electrode layer 139 (the cross-sectional area perpendicular to the direction in which each gate trench 132 extends) is 0.05 μm 2 More than 0.5μm 2The cross-sectional area of ​​the gate electrode layer 139 is defined as the product of the depth of the gate electrode layer 139 and the width of the gate electrode layer 139. The depth of the gate electrode layer 139 is the distance from the top end to the bottom end of the gate electrode layer 139. The width of the gate electrode layer 139 is the width of the gate trench 132 at the midpoint between the top end and the bottom end of the gate electrode layer 139. When the top end of the gate electrode layer 139 is curved (concavely curved in this embodiment), the position of the top end of the gate electrode layer 139 is the midpoint of the top surface of the gate electrode layer 139.

[0325] The gate electrode layer 139 includes p-type polysilicon doped with p-type impurities. The p-type impurity concentration of the gate electrode layer 139 is equal to or greater than the p-type impurity concentration of the body region 131. More specifically, the p-type impurity concentration of the gate electrode layer 139 exceeds the p-type impurity concentration of the body region 131.

[0326] The p-type impurity concentration of the gate electrode layer 139 is 1.0×10 18 cm -3 Over 1.0 x 10 22 cm -3 The p-type impurity of the gate electrode layer 139 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga). The sheet resistance of the gate electrode layer 139 may be 10 Ω / □ or more and 500 Ω / □ or less (approximately 200 Ω / □ in this embodiment).

[0327] 24 and 26, the SiC semiconductor device 101 includes a gate wiring layer 140 formed on the first main surface 103 in the active region 106. More specifically, the gate wiring layer 140 is formed on a third region 138c of the gate insulating layer 138. The gate wiring layer 140 is electrically connected to the gate electrode layer 139, the gate pad 109, and the gate fingers 110 and 111. In FIG. 26, the gate wiring layer 140 is indicated by hatching.

[0328] In this embodiment, the gate wiring layer 140 is formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102, and defines the inner region of the active region 106 from three directions. The gate wiring layer 140 is formed along the outer gate fingers 110.

[0329] The gate wiring layer 140 is connected to the gate electrode layer 139 exposed from the contact trench portion 134 of each gate trench 132. In this embodiment, the gate wiring layer 140 is formed by an extended portion of the gate electrode layer 139 extended from each gate trench 132 onto the first main surface 103. An upper end portion of the gate wiring layer 140 is connected to an upper end portion of the gate electrode layer 139.

[0330] 24, 25, and 27, the SiC semiconductor device 101 includes a plurality of source trenches 145 (second trenches) formed in the first main surface 103 in the active region 106. Each source trench 145 is formed in a region between two adjacent gate trenches 132. The plurality of source trenches 145 are each formed in a band shape extending along the first direction X (the m-axis direction of the SiC single crystal). The plurality of source trenches 145 are formed in a stripe shape extending along the first direction X in a plan view. The pitch between the centers of adjacent source trenches 145 in the second direction Y may be 1.5 μm or more and 3 μm or less.

[0331] Each source trench 145 penetrates the body region 131 and reaches the drift region 127 (SiC epitaxial layer 122). Each source trench 145 includes a sidewall and a bottom wall. The sidewalls forming the long sides of each source trench 145 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of each source trench 145 are formed by the m-plane of the SiC single crystal.

[0332] The sidewalls of each source trench 145 may extend along the normal direction Z. The sidewalls of each source trench 145 may be formed substantially perpendicular to the first main surface 103. The angle that the sidewalls of each source trench 145 form with the first main surface 103 in the SiC semiconductor layer 102 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). Each source trench 145 may be formed in a tapered shape such that the bottom area is less than the opening area.

[0333] The bottom wall of each source trench 145 is located in the drift region 127 (SiC epitaxial layer 122). More specifically, the bottom wall of each source trench 145 is located in the high concentration region 123 of the SiC epitaxial layer 122. The bottom wall of each source trench 145 is located on the second main surface 104 side of the bottom wall of each gate trench 132. The bottom wall of each source trench 145 is located in a region between the bottom wall of each gate trench 132 and the low concentration region 124.

[0334] The bottom wall of each source trench 145 faces the c-plane of the SiC single crystal. The bottom wall of each source trench 145 has an off-angle θ inclined in the [11-20] direction with respect to the (0001) plane of the SiC single crystal. The bottom wall of each source trench 145 may be formed parallel to the first main surface 103. The bottom wall of each source trench 145 may be formed in a convex curve toward the second main surface 104.

[0335] In this embodiment, the depth of each source trench 145 is equal to or greater than the depth of each gate trench 132. More specifically, the depth of each source trench 145 exceeds the depth of each gate trench 132. With respect to the normal direction Z, the depth of each source trench 145 may be equal to or greater than 0.5 μm and equal to or less than 10 μm (for example, about 2 μm).

[0336] The ratio of the depth of each source trench 145 to the depth of each gate trench 132 may be 1.5 or greater. The ratio of the depth of each source trench 145 to the depth of each gate trench 132 is preferably 2 or greater. A source trench 145 having a depth equal to the depth of each gate trench 132 may be formed.

[0337] The first direction width of each source trench 145 may be equal to or greater than the first direction width of each gate trench 132. The first direction width of each source trench 145 may be approximately equal to the first direction width of each gate trench 132. The first direction width of each source trench 145 may be equal to or greater than 0.1 μm and equal to or less than 2 μm (for example, approximately 0.5 μm).

[0338] The SiC semiconductor device 101 includes a source insulating layer 146 formed on the inner wall of each source trench 145. The SiC semiconductor device 101 also includes a source electrode layer 147 embedded in each source trench 145 with the source insulating layer 146 sandwiched therebetween. In FIG. 24 , the source insulating layer 146 and the source electrode layer 147 are indicated by hatching.

[0339] The source insulating layer 146 is formed in a film shape along the inner wall surface of each source trench 145, and defines a recess space within each source trench 145. The source insulating layer 146 includes a first region 146a and a second region 146b. The first region 146a is formed along the sidewall of each source trench 145. The second region 146b is formed along the bottom wall of each source trench 145. A thickness Tsa of the first region 146a is less than a thickness Tsb of the second region 146b.

[0340] The ratio Tsb / Tsa of the thickness Tsb of the second region 146b to the thickness Tsa of the first region 146a may be equal to or greater than 2 and equal to or less than 5. The thickness Tsa of the first region 146a may be equal to or greater than 0.01 μm and equal to or less than 0.2 μm. The thickness Tsb of the second region 146b may be equal to or greater than 0.05 μm and equal to or less than 0.5 μm.

[0341] The thickness Tsa of the first region 146a may be approximately equal to the thickness Ta of the first region 146a of the gate insulating layer 138. The thickness Tsb of the second region 146b may be approximately equal to the thickness Tb of the second region 146b of the gate insulating layer 138. The source insulating layer 146 may be formed to have a uniform thickness.

[0342] The source insulating layer 146 includes at least one of a silicon oxide (SiO2) layer, a silicon nitride (SiN) layer, an aluminum oxide (Al2O3) layer, a zirconium oxide (ZrO2) layer, and a tantalum oxide (Ta2O3) layer. The source insulating layer 146 may have a layered structure including a SiN layer and a SiO2 layer stacked in this order from the first main surface 103 side.

[0343] The source insulating layer 146 may have a layered structure including an SiO2 layer and an SiN layer stacked in this order from the first main surface 103 side. The source insulating layer 146 may have a single-layer structure made of an SiO2 layer or an SiN layer. The source insulating layer 146 may contain the same insulating material as the gate insulating layer 138. In this embodiment, the source insulating layer 146 has a single-layer structure made of an SiO2 layer.

[0344] The source electrode layer 147 is embedded in a recess space defined by the source insulating layer 146 in each source trench 145. The source electrode layer 147 is controlled by a source voltage.

[0345] The source electrode layer 147 has an upper end portion located on the opening side of each source trench 145. The upper end portion of the source electrode layer 147 is formed in a concave curved shape recessed toward the bottom wall of each source trench 145. The upper end portion of the source electrode layer 147 may be formed parallel to the first main surface 103. The thickness of the source electrode layer 147 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

[0346] The upper end of the source electrode layer 147 is formed on the bottom wall side of each source trench 145 with respect to the first main surface 103. The upper end of the source electrode layer 147 may be located higher than the first main surface 103. The upper end of the source electrode layer 147 may protrude higher than the upper end of the source insulating layer 146. The upper end of the source electrode layer 147 may be located lower than the upper end of the source insulating layer 146.

[0347] The source electrode layer 147 may contain at least one of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. The source electrode layer 147 preferably contains conductive polysilicon, which has properties similar to those of SiC. This reduces stress generated in the SiC semiconductor layer 102. In this embodiment, the source electrode layer 147 contains p-type polysilicon doped with p-type impurities. In this case, the source electrode layer 147 can be formed simultaneously with the gate electrode layer 139.

[0348] The p-type impurity concentration of the source electrode layer 147 is equal to or higher than the p-type impurity concentration of the body region 131. More specifically, the p-type impurity concentration of the source electrode layer 147 exceeds the p-type impurity concentration of the body region 131. The p-type impurity concentration of the source electrode layer 147 is 1.0×10 18 cm -3 Over 1.0 x 10 22 cm -3 The p-type impurity concentration of the source electrode layer 147 may be approximately equal to the p-type impurity concentration of the gate electrode layer 139. The p-type impurity of the source electrode layer 147 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0349] The sheet resistance of the source electrode layer 147 may be 10 Ω / □ or more and 500 Ω / □ or less (approximately 200 Ω / □ in this embodiment). The sheet resistance of the source electrode layer 147 may be approximately equal to the sheet resistance of the gate electrode layer 139. The source electrode layer 147 may include n-type polysilicon instead of or in addition to p-type polysilicon.

[0350] Thus, the SiC semiconductor device 101 has a plurality of trench gate structures 151 and a plurality of trench source structures 152. Each trench gate structure 151 includes a gate trench 132, a gate insulating layer 138, and a gate electrode layer 139. Each trench source structure 152 includes a source trench 145, a source insulating layer 146, and a source electrode layer 147.

[0351] The SiC semiconductor device 101 has n-type junctions formed in the surface layer of the body region 131 along the sidewalls of the gate trenches 132. + The peak value of the n-type impurity concentration of the source region 153 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The lower limit of the peak value of the n-type impurity concentration of the source region 153 may be 1.0×10 20 cm -3 The n-type impurity of the source region 153 may be phosphorus (P).

[0352] In this embodiment, a plurality of source regions 153 are formed along one sidewall and the other sidewall of each gate trench 132. The plurality of source regions 153 are each formed in a band shape extending along the first direction X. The plurality of source regions 153 are formed in a stripe shape extending along the first direction X in plan view. Each source region 153 is exposed from the sidewall of each gate trench 132 and the sidewall of each source trench 145.

[0353] As described above, in a region along the sidewall of the gate trench 132 in the surface layer portion of the first main surface 103, the source region 153, the body region 131, and the drift region 127 are formed in this order from the first main surface 103 to the second main surface 104. A channel of the MISFET is formed in a region along the sidewall of the gate trench 132 in the body region 131. The channel is formed along the sidewall of the gate trench 132 in the body region 131, which is formed by the a-plane of the SiC single crystal. The ON / OFF of the channel is controlled by the gate electrode layer 139.

[0354] The SiC semiconductor device 101 has a plurality of p-type electrodes formed in the surface layer of the first main surface 103 in the active region 106. + The p-type contact regions 154 each include a p-type contact region 154. A peak value P of the p-type impurity concentration of each contact region 154 exceeds the peak value of the p-type impurity concentration of the body region 131. The p-type impurity of the contact region 154 may be aluminum (Al).

[0355] 9A or the offset-compensation type contact region 42 shown in Fig. 11 may be formed as the contact region 154. That is, each contact region 154 may have the p-type impurity concentration shown in Fig. 9A or the p-type impurity concentration shown in Fig. 11.

[0356] Each contact region 154 is formed in a region between two adjacent gate trenches 132 in a plan view. Each contact region 154 is formed in a region on the opposite side of each source region 153 from the gate trench 132. Each contact region 154 is formed along the inner wall of each source trench 145. In this embodiment, multiple contact regions 154 are formed at intervals along the inner wall of each source trench 145. Each contact region 154 is formed at an interval from each gate trench 132.

[0357] Each contact region 154 covers the sidewall and bottom wall of each source trench 145. The bottom of each contact region 154 may be formed parallel to the bottom wall of each source trench 145. More specifically, each contact region 154 integrally includes a first surface region 154a, a second surface region 154b, and an inner wall region 154c (bottom region).

[0358] The first surface region 154a covers one sidewall of the source trench 145 in the surface portion of the body region 131. The first surface region 154a is electrically connected to the body region 131 and the source region 153. The first surface region 154a is located in a region on the first main surface 103 side of the bottom of the source region 153. In this embodiment, the first surface region 154a has a bottom that extends parallel to the first main surface 103.

[0359] In this embodiment, the bottom of first surface region 154a is located in a region between the bottom of body region 131 and the bottom of source region 153. The bottom of first surface region 154a may also be located in a region between first main surface 103 and the bottom of body region 131.

[0360] In this embodiment, the first surface region 154a extends from the source trench 145 toward the adjacent gate trench 132. The first surface region 154a may extend to an intermediate region between the gate trench 132 and the source trench 145. An end of the first surface region 154a is located in the region between the gate trench 132 and the source trench 145.

[0361] The second surface region 154b covers the other sidewall of the source trench 145 in the surface portion of the body region 131. The second surface region 154b is electrically connected to the body region 131 and the source region 153. The second surface region 154b is located in a region on the first main surface 103 side of the bottom of the source region 153. The depth of the second surface region 154b is approximately equal to the depth of the first surface region 154a. In this embodiment, the second surface region 154b has a bottom that extends parallel to the first main surface 103.

[0362] In this embodiment, the bottom of second surface region 154b is located in a region between the bottom of body region 131 and the bottom of source region 153. The bottom of second surface region 154b may also be located in a region between first main surface 103 and the bottom of body region 131.

[0363] In this embodiment, second surface region 154b extends from the other sidewall of source trench 145 toward the adjacent gate trench 132. Second surface region 154b may extend to an intermediate region between source trench 145 and gate trench 132. An end of second surface region 154b is located in a region between gate trench 132 and source trench 145.

[0364] The inner wall region 154c is located in a region closer to the second main surface 104 than the first surface region 154a and the second surface region 154b (the bottom of the source region 153). The inner wall region 154c is formed in a region along the inner wall of the source trench 145 in the SiC semiconductor layer 102. The inner wall region 154c covers the sidewall of the source trench 145.

[0365] The inner wall region 154c covers the corners connecting the side walls and bottom walls of the source trench 145. The inner wall region 154c covers the side walls of the source trench 145 through the corners and the bottom wall of the source trench 145. The bottom of the contact region 154 is formed by the inner wall region 154c.

[0366] When the offset compensation type contact region 154 (see also FIG. 11) is employed, part of the p-type impurities (acceptors) in the first surface region 154a is offset and compensated by the n-type impurities (donors) in the source region 153. Also, part of the p-type impurities (acceptors) in the second surface region 154b is offset and compensated by the n-type impurities (donors) in the source region 153.

[0367] This results in a counter-compensation type first surface region 154a and second surface region 154b of each contact region 154. Since the inner wall region 154c of each contact region 154 does not contact the source region 153, counter-compensation of the p-type impurities (acceptors) in the inner wall region 154c by the n-type impurities (donors) in the source region 153 is suppressed.

[0368] In this way, each contact region 154 has a compensated region (first surface region 154a and second surface region 154b) on the surface side and an uncompensated region (inner wall region 154c) on the bottom side.

[0369] The SiC semiconductor device 101 includes a plurality of deep well regions 155 formed in a surface layer portion of the first main surface 103. Each deep well region 155 is also referred to as a breakdown voltage adjusting region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the active region 106. Each deep well region 155 is formed in the drift region 127 (SiC epitaxial layer 122). More specifically, each deep well region 155 is formed in the high concentration region 123 of the SiC epitaxial layer 122.

[0370] Each deep well region 155 is formed in a strip shape extending along each source trench 145 in a plan view. Each deep well region 155 covers the sidewall of each source trench 145. Each deep well region 155 covers the corner connecting the sidewall and bottom wall of each source trench 145.

[0371] Each deep well region 155 covers the sidewalls and corners of each source trench 145 and the bottom wall of each source trench 145. The bottom of each deep well region 155 may be formed parallel to the bottom wall of each source trench 145. Each deep well region 155 has a bottom located on the second main surface 104 side relative to the bottom wall of each gate trench 132.

[0372] Each deep well region 155 is formed along the inner wall of each source trench 145 so as to cover each contact region 154. Each deep well region 155 is electrically connected to each contact region 154. Each deep well region 155 is continuous with the body region 131 on the sidewall of each source trench 145.

[0373] The peak value of the p-type impurity concentration of each deep well region 155 may be approximately equal to the peak value of the p-type impurity concentration of the body region 131. The peak value of the p-type impurity concentration of each deep well region 155 may be greater than the peak value of the p-type impurity concentration of the body region 131. The peak value of the p-type impurity concentration of each deep well region 155 may be less than the peak value of the p-type impurity concentration of the body region 131.

[0374] The peak value of the p-type impurity concentration of each deep well region 155 may be equal to or less than the peak value P of the p-type impurity concentration of the contact region 154. The peak value of the p-type impurity concentration of each deep well region 155 may be less than the peak value P of the p-type impurity concentration of the contact region 154. The peak value of the p-type impurity concentration of each deep well region 155 may be equal to or less than 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 The lower limit of the peak value of the p-type impurity concentration of each deep well region 155 may be 1.0×10 18 cm -3 It is preferable that this is equal to or greater than this.

[0375] Each deep well region 155 forms a pn junction with the SiC semiconductor layer 102 (high concentration region 123 of the SiC epitaxial layer 122). A depletion layer extends from this pn junction toward a region between adjacent gate trenches 132. This depletion layer extends toward a region on the second main surface 104 side of the bottom wall of each gate trench 132. The depletion layer extending from each deep well region 155 may overlap the bottom wall of each gate trench 132. The depletion layer extending from the bottom of each deep well region 155 may overlap the bottom wall of each gate trench 132.

[0376] In a semiconductor device having only a pn junction diode, the problem of electric field concentration in the SiC semiconductor layer 102 is less likely due to the structure not having a trench. Each deep well region 155 brings the trench gate type MISFET closer to the structure of a pn junction diode. This allows the electric field in the SiC semiconductor layer 102 to be alleviated in the trench gate type MISFET.

[0377] Therefore, in order to alleviate electric field concentration, it is effective to narrow the pitch between adjacent deep well regions 155. Furthermore, by having each deep well region 155 having a bottom on the second main surface 104 side with respect to the bottom wall of each gate trench 132, the depletion layer can appropriately alleviate electric field concentration in each gate trench 132.

[0378] It is preferable that the distance between the bottom of each deep well region 155 and the second main surface 104 is approximately constant. This can prevent variations in the distance between the bottom of each deep well region 155 and the second main surface 104. This can prevent the breakdown voltage (e.g., breakdown resistance) of the SiC semiconductor layer 102 from being limited by the shape of each deep well region 155, thereby enabling the breakdown voltage to be appropriately improved.

[0379] In this embodiment, a high concentration region 123 of the SiC epitaxial layer 122 is interposed in the region between the adjacent deep well regions 155. This makes it possible to reduce the JFET (Junction Field Effect Transistor) resistance in the region between the adjacent deep well regions 155.

[0380] Furthermore, in this embodiment, the bottom of each deep well region 155 is located within the high-concentration region 123 of the SiC epitaxial layer 122. This allows the current path to extend from the bottom of each deep well region 155 in a lateral direction parallel to the first main surface 103. This reduces current spreading resistance. In this structure, the low-concentration region 124 of the SiC epitaxial layer 122 increases the breakdown voltage of the SiC semiconductor layer 102.

[0381] By forming the source trenches 145, p-type impurities can be introduced into the inner walls of the source trenches 145. This allows each deep well region 155 to be formed conformally to the source trenches 145, thereby appropriately suppressing variations in the depth of each deep well region 155. Furthermore, by using each source trench 145, each deep well region 155 can be appropriately formed in a relatively deep region of the SiC semiconductor layer 102.

[0382] 24 and 26, SiC semiconductor device 101 includes a p-type peripheral deep well region 156 formed in the peripheral portion of active region 106. Peripheral deep well region 156 is formed in drift region 127 (SiC epitaxial layer 122). More specifically, peripheral deep well region 156 is formed in high concentration region 123 of SiC epitaxial layer 122.

[0383] The peripheral deep well region 156 is electrically connected to each deep well region 155. The peripheral deep well region 156 has the same potential as each deep well region 155. In this embodiment, the peripheral deep well region 156 is formed integrally with each deep well region 155.

[0384] The peripheral deep well region 156 is formed in a region along the inner wall of the contact trench portion 134 of each gate trench 132 at the periphery of the active region 106. The peripheral deep well region 156 covers the sidewall of each contact trench portion 134. The peripheral deep well region 156 covers the corners connecting the sidewall and bottom wall of each contact trench portion 134.

[0385] The peripheral deep well region 156 covers the sidewalls and corners of each contact trench portion 134 and the bottom wall of each contact trench portion 134. Each deep well region 155 is continuous with the body region 131 at the sidewall of each contact trench portion 134. The bottom of the peripheral deep well region 156 is located on the second main surface 104 side of the bottom wall of each contact trench portion 134.

[0386] In a plan view, the peripheral deep well region 156 overlaps the gate wiring layer 140. The peripheral deep well region 156 faces the gate wiring layer 140 with the gate insulating layer 138 (third region 138c) sandwiched therebetween.

[0387] The peripheral deep well region 156 includes a lead-out portion 156a led from each contact trench portion 134 to each active trench portion 133. The lead-out portion 156a is formed in the high-concentration region 123 of the SiC epitaxial layer 122. The lead-out portion 156a extends along the sidewall of each active trench portion 133, passes through the corners, and covers the bottom wall of the active trench portion 133. The lead-out portion 156a is continuous with the body region 131 on the sidewall of each active trench portion 133. The bottom of the lead-out portion 156a is located on the second main surface 104 side relative to the bottom wall of each active trench portion 133.

[0388] The peak value of the p-type impurity concentration of the peripheral deep well region 156 may be approximately equal to the p-type impurity concentration of the body region 131. The peak value of the p-type impurity concentration of the peripheral deep well region 156 may be greater than the peak value of the p-type impurity concentration of the body region 131. The peak value of the p-type impurity concentration of the peripheral deep well region 156 may be less than the peak value of the p-type impurity concentration of the body region 131.

[0389] The peak value of the p-type impurity concentration of the peripheral deep well region 156 may be approximately equal to the p-type impurity concentration of each deep well region 155. The peak value of the p-type impurity concentration of the peripheral deep well region 156 may be greater than the peak value of the p-type impurity concentration of each deep well region 155. The peak value of the p-type impurity concentration of the peripheral deep well region 156 may be less than the peak value of the p-type impurity concentration of each deep well region 155.

[0390] The peak value of the p-type impurity concentration of the peripheral deep well region 156 may be equal to or less than the peak value P of the p-type impurity concentration of the contact region 154. The peak value of the p-type impurity concentration of the peripheral deep well region 156 may be less than the peak value P of the p-type impurity concentration of the contact region 154. The peak value of the p-type impurity concentration of the peripheral deep well region 156 is 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 The lower limit of the peak value of the p-type impurity concentration of the peripheral deep well region 156 may be 1.0×10 18 cm -3 It is preferable that this is equal to or greater than this.

[0391] 27, SiC semiconductor device 101 includes a low-resistance electrode layer 157 formed on gate electrode layer 139. Low-resistance electrode layer 157 includes a conductive material having a sheet resistance lower than the sheet resistance of gate electrode layer 139. The sheet resistance of low-resistance electrode layer 157 may be 0.01 Ω / □ or more and 10 Ω / □ or less.

[0392] The low-resistance electrode layer 157 covers the upper end of the gate electrode layer 139 in each gate trench 132. The low-resistance electrode layer 157 is formed in a film shape. The low-resistance electrode layer 157 has a connection portion 157a that contacts the upper end of the gate electrode layer 139 and a non-connection portion 157b on the opposite side. The connection portion 157a and the non-connection portion 157b may be formed in a concave curved shape following the upper end of the gate electrode layer 139. The connection portion 157a and the non-connection portion 157b may take various forms.

[0393] The entire connecting portion 157a may be located above the first main surface 103. The entire connecting portion 157a may be located below the first main surface 103. The connecting portion 157a may include a portion located above the first main surface 103. The connecting portion 157a may include a portion located below the first main surface 103. For example, the central portion of the connecting portion 157a may be located below the first main surface 103, and the peripheral portion of the connecting portion 157a may be located above the first main surface 103.

[0394] The entire non-connected portion 157b may be located above the first main surface 103. The entire non-connected portion 157b may be located below the first main surface 103. The non-connected portion 157b may include a portion located above the first main surface 103. The non-connected portion 157b may include a portion located below the first main surface 103. For example, the central portion of the non-connected portion 157b may be located below the first main surface 103, and the peripheral portion of the non-connected portion 157b may be located above the first main surface 103.

[0395] The low-resistance electrode layer 157 has an edge 157c that contacts the gate insulating layer 138. The edge 157c contacts a corner of the gate insulating layer 138 that connects the first region 138a and the second region 138b. The edge 157c contacts the third region 138c of the gate insulating layer 138. More specifically, the edge 157c contacts the bulge 138d of the gate insulating layer 138.

[0396] The edge portion 157c is formed in a region on the side of the first main surface 103 with respect to the bottom of the source region 153. The edge portion 157c is formed in a region on the side of the first main surface 103 with respect to the boundary region between the body region 131 and the source region 153. Thereby, the edge portion 157c faces the source region 153 with the gate insulating layer 138 interposed therebetween. The edge portion 157c does not face the body region 131 with the gate insulating layer 138 interposed therebetween.

[0397] According to such a structure, it is possible to suppress the formation of a current path in the region between the low-resistance electrode layer 157 and the body region 131 in the gate insulating layer 138. The current path can be formed by an undesired diffusion of the electrode material of the low-resistance electrode layer 157 with respect to the gate insulating layer 138. In particular, the design of connecting the edge portion 157c of the low-resistance electrode layer 157 to the third region 138c (the corner portion of the gate insulating layer 138) of the relatively thick gate insulating layer 138 is effective in reducing the risk of forming a current path.

[0398] In the normal direction Z, the thickness TR of the low-resistance electrode layer 157 is less than or equal to the thickness TG of the gate electrode layer 139 (TR ≦ TG). Preferably, the thickness TR of the low-resistance electrode layer 157 is less than the thickness TG of the gate electrode layer 139 (TR < TG). More specifically, preferably, the thickness TR of the low-resistance electrode layer 157 is less than or equal to half of the thickness TG of the gate electrode layer 139 (TR ≦ TG / 2).

[0399] The ratio TR / TG of the thickness TR of the low-resistance electrode layer 157 to the thickness TG of the gate electrode layer 139 is 0.01 or more and 1 or less. The thickness TG of the gate electrode layer 139 may be 0.5 μm or more and 3 μm or less. The thickness TR of the low-resistance electrode layer 157 may be 0.01 μm or more and 3 μm or less.

[0400] The current supplied into each gate trench 132 flows through the low-resistance electrode layer 157 having a relatively low sheet resistance and is transmitted to the entire gate electrode layer 139. Thereby, since the entire gate electrode layer 139 (the entire active region 106) can be quickly shifted from the off state to the on state, the delay of the switching response can be suppressed.

[0401] In particular, in the case of gate trenches 132 having a length on the order of millimeters (length of 1 mm or more), it takes time for current to propagate, but delays in switching response can be appropriately suppressed by using the low-resistance electrode layer 157. In other words, the low-resistance electrode layer 157 is formed as a current diffusion electrode layer that diffuses current within each gate trench 132.

[0402] Furthermore, as the cell structure becomes smaller, the width, depth, cross-sectional area, etc. of the gate electrode layer 139 become smaller, which raises concerns about delays in switching response due to increased electrical resistance in each gate trench 132. However, the low-resistance electrode layer 157 allows the entire gate electrode layer 139 to quickly transition from the OFF state to the ON state, thereby appropriately suppressing delays in switching response due to miniaturization.

[0403] 26 , in this embodiment, the low-resistance electrode layer 157 also covers the upper end of the gate wiring layer 140. The portion of the low-resistance electrode layer 157 that covers the upper end of the gate wiring layer 140 is integrally formed with the portion of the low-resistance electrode layer 157 that covers the upper end of the gate electrode layer 139. As a result, the low-resistance electrode layer 157 covers the entire area of ​​the gate electrode layer 139 and the entire area of ​​the gate wiring layer 140.

[0404] Therefore, the current supplied from the gate principal surface electrode layer 108 to the gate wiring layer 140 is transmitted to the entire gate electrode layer 139 and the gate wiring layer 140 via the low-resistance electrode layer 157, which has a relatively low sheet resistance. This allows the entire gate electrode layer 139 (the entire active region 106) to be quickly transitioned from an OFF state to an ON state via the gate wiring layer 140, thereby suppressing delays in switching response. In particular, in the case of a gate trench 132 having a length on the order of millimeters, delays in switching response can be appropriately suppressed by the low-resistance electrode layer 157 covering the upper end of the gate wiring layer 140.

[0405] The low-resistance electrode layer 157 includes a polycide layer. The polycide layer is formed by silicidating the surface portion of the gate electrode layer 139 with a metal material. More specifically, the polycide layer is a p-type polycide layer containing p-type impurities added to the gate electrode layer 139 (p-type polysilicon). The polycide layer preferably has a resistivity of 10 μΩ·cm or more and 110 μΩ·cm or less.

[0406] The sheet resistance in the gate trench 132 in which the gate electrode layer 139 and the low resistance electrode layer 157 are buried is equal to or less than the sheet resistance of the gate electrode layer 139 alone. The sheet resistance in the gate trench 132 is preferably equal to or less than the sheet resistance of n-type polysilicon doped with n-type impurities.

[0407] The sheet resistance in the gate trench 132 is approximated to the sheet resistance of the low resistance electrode layer 157. That is, the sheet resistance in the gate trench 132 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The sheet resistance in the gate trench 132 is preferably less than 10 Ω / □.

[0408] The low-resistance electrode layer 157 may contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. Of these materials, NiSi, CoSi2, and TiSi2 are particularly suitable as a polycide layer for forming the low-resistance electrode layer 157 because of their relatively small resistivity and temperature dependency.

[0409] The SiC semiconductor device 101 includes a plurality of source sub-trenches 158 formed in a region along the upper end of the source electrode layer 147 on the first main surface 103 and communicating with the plurality of source trenches 145, respectively. Each source sub-trench 158 forms a part of the side wall of each source trench 145. In this embodiment, the source sub-trenches 158 are formed in an endless shape (in this embodiment, a quadrangular ring shape) surrounding the upper end of the source electrode layer 147 in plan view. The source sub-trenches 158 border the upper end of the source electrode layer 147.

[0410] The source sub-trench 158 is formed by digging down a portion of the source insulating layer 146. The source sub-trench 158 is formed in a tapered shape such that the bottom area is less than the opening area. The bottom wall of the source sub-trench 158 may be formed in a convex curved shape toward the second major surface 104. More specifically, the source sub-trench 158 is formed by digging down from the first major surface 103 to the upper end of the source insulating layer 146 and the upper end of the source electrode layer 147.

[0411] The upper end of the source electrode layer 147 has a shape that is narrowed inward relative to the lower end of the source electrode layer 147. The lower end of the source electrode layer 147 is a portion of the source electrode layer 147 that is located on the bottom wall side of each source trench 145. The width in the first direction of the upper end of the source electrode layer 147 may be smaller than the width in the first direction of the lower end of the source electrode layer 147.

[0412] The source region 153, the contact region 154, the source insulating layer 146, and the source electrode layer 147 are exposed from the inner wall of the source sub-trench 158. The first surface region 154a and the second surface region 154b of the contact region 154 are exposed from the inner wall of the source sub-trench 158.

[0413] At least the first region 146a of the source insulating layer 146 is exposed from the bottom wall of the source sub-trench 158. As a result, the upper end of the first region 146a of the source insulating layer 146 is located below the first main surface 103.

[0414] An opening edge 159 of each source trench 145 includes a sloped portion 160 that slopes downward from the first main surface 103 toward the inside of each source trench 145. The opening edge 159 of each source trench 145 is a corner that connects the first main surface 103 and the sidewall of each source trench 145. The sloped portion 160 of each source trench 145 is formed by a source sub-trench 158.

[0415] In this embodiment, the inclined portions 160 are formed in a concave curved shape directed inwardly of the SiC semiconductor layer 102. The inclined portions 160 may be formed in a convex curved shape directed inwardly of the source sub-trench 158. The inclined portions 160 reduce electric field concentration at the opening edge portions 159 of the source trenches 145.

[0416] 28 and 29, the active region 106 has an active main surface 161 that forms a part of the first main surface 103. The outer region 107 has an outer main surface 162 that forms a part of the first main surface 103. In this embodiment, the outer main surface 162 is connected to the side surfaces 105A to 105D.

[0417] The active principal surface 161 and the outer principal surface 162 each face the c-plane of the SiC single crystal, and each have an off-angle θ tilted in the [11-20] direction with respect to the (0001) plane of the SiC single crystal.

[0418] The outer principal surface 162 is located on the second principal surface 104 side relative to the active principal surface 161. In this embodiment, the outer region 107 is formed by recessing the first principal surface 103 toward the second principal surface 104 side. Therefore, the outer principal surface 162 is formed in a region recessed toward the second principal surface 104 side relative to the active principal surface 161.

[0419] The outer major surface 162 may be located closer to the second major surface 104 than the bottom wall of each gate trench 132. In this embodiment, the outer major surface 162 is formed at a depth substantially equal to the bottom wall of each source trench 145. That is, the outer major surface 162 is located on substantially the same plane as the bottom wall of each source trench 145. The distance between the outer major surface 162 and the second major surface 104 may also be substantially equal to the distance between the second major surface 104 and the bottom wall of each source trench 145.

[0420] The outer main surface 162 may be located on the second main surface 104 side with respect to the bottom wall of each source trench 145. The outer main surface 162 may be located on the second main surface 104 side with respect to the bottom wall of each source trench 145 within a range of 0 μm or more and 1 μm or less.

[0421] The outer principal surface 162 exposes the SiC epitaxial layer 122. More specifically, the outer principal surface 162 exposes the high concentration region 123 of the SiC epitaxial layer 122. The outer principal surface 162 faces the low concentration region 124 with the high concentration region 123 interposed therebetween.

[0422] In this embodiment, the active region 106 is partitioned into a plateau shape by the outer region 107. As a result, the active region 106 is formed as a plateau-shaped active plateau 163 that protrudes upward from the outer region 107. The active plateau 163 includes an active sidewall 164 that connects the active main surface 161 and the outer main surface 162. The active sidewall 164 defines a boundary region between the active region 106 and the outer region 107. The first main surface 103 is formed by the active main surface 161, the outer main surface 162, and the active sidewall 164.

[0423] In this embodiment, the active sidewall 164 extends along the normal direction Z of the active principal surface 161 (outer principal surface 162). The active sidewall 164 is formed by the m-plane and the a-plane of a SiC single crystal. The active sidewall 164 may have an inclined surface that slopes downward from the active principal surface 161 toward the outer principal surface 162. The inclination angle of the active sidewall 164 is the angle formed between the active sidewall 164 and the active principal surface 161 within the SiC semiconductor layer 102.

[0424] In this case, the inclination angle of the active sidewall 164 may be greater than 90° and less than or equal to 135°. The inclination angle of the active sidewall 164 may be greater than 90° and less than or equal to 95°, greater than or equal to 95° and less than or equal to 100°, greater than or equal to 100° and less than or equal to 110°, greater than or equal to 110° and less than or equal to 120°, or greater than or equal to 120° and less than or equal to 135°. The inclination angle of the active sidewall 164 is preferably greater than 90° and less than or equal to 95°.

[0425] The active sidewalls 164 expose the SiC epitaxial layer 122. More specifically, the active sidewalls 164 expose the high concentration regions 123 of the SiC epitaxial layer 122. The active sidewalls 164 expose at least the body region 131 in the region on the active main surface 161 side. FIGS. 28 and 29 show an example in which the active sidewalls 164 expose the body region 131 and the source region 153.

[0426] The SiC semiconductor device 101 has a p + The SiC semiconductor device 101 includes a p-type diode region 171 (impurity region). The SiC semiconductor device 101 also includes a p-type outer deep well region 172 formed in a surface layer portion of the outer principal surface 162. The SiC semiconductor device 101 also includes a p-type field limit structure 173 formed in a surface layer portion of the outer principal surface 162.

[0427] The diode region 171 is formed in the outer region 107 in a region between the active sidewall 164 and the side surfaces 105A to 105D. The diode region 171 is formed at a distance from the active sidewall 164 and the side surfaces 105A to 105D. The diode region 171 extends in a strip shape along the active region 106 in a planar view. In this embodiment, the diode region 171 is formed in an endless shape (a quadrangular ring shape in this embodiment) surrounding the active region 106 in a planar view. The diode region 171 overlaps with the source lead-out wiring 116 in a planar view.

[0428] The diode region 171 forms a pn junction with the SiC semiconductor layer 102. More specifically, the diode region 171 is located in the SiC epitaxial layer 122. Therefore, the diode region 171 forms a pn junction with the SiC epitaxial layer 122. More specifically, the diode region 171 is located in the high concentration region 123 of the SiC epitaxial layer 122. Therefore, the diode region 171 forms a pn junction with the high concentration region 123.

[0429] This forms a pn junction diode D having the diode region 171 as an anode and the SiC semiconductor layer 102 as a cathode. The diode region 171 is electrically connected to the source lead-out wiring 116. The diode region 171 forms part of an avalanche current absorption structure.

[0430] The entire diode region 171 is located on the second main surface 104 side with respect to the bottom walls of each gate trench 132. The bottom of the diode region 171 is located on the second main surface 104 side with respect to the bottom walls of each source trench 145. The bottom of the diode region 171 may be formed at a depth position substantially equal to the bottom of the contact region 154. The bottom of the diode region 171 may be located on substantially the same plane as the bottom of the contact region 154.

[0431] The distance between the bottom of diode region 171 and second main surface 104 may be approximately equal to the distance between the bottom of contact region 154 and second main surface 104. The bottom of diode region 171 may be located closer to second main surface 104 than the bottom of contact region 154. The bottom of diode region 171 may be located closer to second main surface 104 than the bottom of contact region 154 within a range of 0 μm to 1 μm.

[0432] 9A is used as the contact region 154, the diode region 171 may have a peak value of p-type impurity concentration that is approximately equal to the peak value P of the p-type impurity concentration of the contact region 154. The peak value of the p-type impurity concentration of the diode region 171 is 1.0×10 20 cm -3 The peak value of the p-type impurity concentration in the diode region 171 is 1.0×10 17 cm -3 Over 1.0 x 10 20 cm -3 It is preferable that it is in the following range:

[0433] The thickness (depth) of the diode region 171 is preferably approximately equal to the thickness (depth) of the contact region 154. Furthermore, the diode region 171 preferably has a p-type impurity concentration equal to the p-type impurity concentration of the contact region 154. With this structure, the contact region 154 and the diode region 171 can be formed using the same mask.

[0434] A separate mask may be used to form the contact region 154 and the diode region 171. In this case, the diode region 171 may have a p-type impurity concentration that exceeds the p-type impurity concentration of the contact region 154. The diode region 171 may have a p-type impurity concentration of 1.0×10 20 cm -3 The p-type impurity concentration may be greater than the p-type impurity concentration of the contact region 154 while having a p-type impurity concentration of 0.1 to 1.0 μm or less.

[0435] The diode region 171 is 1.0×10 20 cm -3 The peak value of the p-type impurity concentration of the diode region 171 may be greater than 1.0×10 20 cm -3 Beyond 1.0 x 10 21 cm -3The contact region 154 and the diode region 171 may be located in the following range: In this case, the contact region 154 and the diode region 171 cannot be formed at the same time, but the design can be made with attention paid to the characteristics of the pn junction diode D.

[0436] In this case, the diode region 171 may have a thickness (depth) different from that of the contact region 154. The thickness (depth) of the diode region 171 may be equal to or greater than the thickness (depth) of the contact region 154. The thickness (depth) of the diode region 171 may be less than the thickness (depth) of the contact region 154.

[0437] 11 is used as the contact region 154, the diode region 171 may have a peak value of p-type impurity concentration that exceeds the peak value P of the p-type impurity concentration of the contact region 154. In this case, the peak value of the p-type impurity concentration of the diode region 171 is 1.0×10 20 cm -3 Beyond 1.0 x 10 21 cm -3 It may be located in the following ranges:

[0438] In this case, the diode region 171 may have a thickness (depth) equal to the thickness (depth) of the contact region 154. With such a diode region 171, the contact region 154 and the diode region 171 can be formed using the same mask. Furthermore, when a cancellation compensation type contact region 154 is employed, the contact region 154 and the diode region 171 can be simultaneously formed, and a design that focuses on the characteristics of the pn junction diode D can be performed.

[0439] The outer deep well region 172 is formed in a region between the active sidewall 164 and the diode region 171 in a plan view. In this embodiment, the outer deep well region 172 is formed at an interval from the active sidewall 164 toward the diode region 171. The outer deep well region 172 is also referred to as a breakdown voltage adjusting region (breakdown voltage maintaining region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the outer region 107.

[0440] The outer deep well region 172 extends in a strip shape along the active region 106 in a plan view. In this embodiment, the outer deep well region 172 is formed in an endless shape (a square ring shape in this embodiment) surrounding the active region 106 in a plan view. The outer deep well region 172 is electrically connected to the source lead-out line 116 via the diode region 171. The outer deep well region 172 may form part of a pn junction diode D. The outer deep well region 172 may form part of an avalanche current absorption structure.

[0441] The entire outer deep well region 172 is located on the second main surface 104 side with respect to the bottom wall of each gate trench 132. The bottom of the outer deep well region 172 is located on the second main surface 104 side with respect to the bottom wall of each source trench 145.

[0442] The inner peripheral edge of the outer deep well region 172 may extend close to the boundary region between the active region 106 and the outer region 107. The outer deep well region 172 may cross the boundary region between the active region 106 and the outer region 107. The inner peripheral edge of the outer deep well region 172 may cover a corner connecting the active sidewall 164 and the outer major surface 162. The inner peripheral edge of the outer deep well region 172 may further extend along the active sidewall 164 and connect to the body region 131.

[0443] In this embodiment, the outer peripheral edge of the outer deep well region 172 covers the diode region 171 from the second main surface 104 side. The outer deep well region 172 may overlap the source lead-out line 116 in plan view. The outer peripheral edge of the outer deep well region 172 may be formed at a distance from the diode region 171 toward the active sidewall 164.

[0444] The bottom of outer deep well region 172 is located closer to second main surface 104 than the bottom of diode region 171. The bottom of outer deep well region 172 may be formed at a depth substantially equal to the bottom of each deep well region 155. The bottom of outer deep well region 172 may be located on substantially the same plane as the bottom of each deep well region 155.

[0445] The distance between the bottom of outer deep well region 172 and outer major surface 162 may be approximately equal to the distance between the bottom of each deep well region 155 and the bottom wall of each source trench 145. The distance between the bottom of outer deep well region 172 and second major surface 104 may be approximately equal to the distance between the bottom of each deep well region 155 and second major surface 104.

[0446] The bottom of the outer deep well region 172 may be located closer to the second main surface 104 than the bottom of each deep well region 155. The bottom of the outer deep well region 172 may be located closer to the second main surface 104 than the bottom of each deep well region 155 within a range of 0 μm to 1 μm.

[0447] This can prevent variations from occurring between the distance between the bottom of outer deep well region 172 and second main surface 104 and the distance between the bottom of each deep well region 155 and second main surface 104. This prevents the breakdown voltage (e.g., breakdown resistance) of SiC semiconductor layer 102 from being limited by the shape of outer deep well region 172 and the shape of each deep well region 155, thereby enabling the breakdown voltage to be appropriately improved.

[0448] The peak value of the p-type impurity concentration of the outer deep well region 172 may be equal to or less than the peak value of the p-type impurity concentration of the diode region 171. The peak value of the p-type impurity concentration of the outer deep well region 172 may be less than the peak value of the p-type impurity concentration of the diode region 171. The peak value of the p-type impurity concentration of the outer deep well region 172 may be approximately equal to the peak value of the p-type impurity concentration of each deep well region 155. The peak value of the p-type impurity concentration of the outer deep well region 172 may be approximately equal to the peak value of the p-type impurity concentration of the body region 131.

[0449] The peak value of the p-type impurity concentration of the outer deep well region 172 may exceed the peak value of the p-type impurity concentration of the body region 131. The peak value of the p-type impurity concentration of the outer deep well region 172 may be less than the peak value of the p-type impurity concentration of the body region 131. The peak value of the p-type impurity concentration of the outer deep well region 172 may be equal to or less than the peak value P of the p-type impurity concentration of the contact region 154. The peak value of the p-type impurity concentration of the outer deep well region 172 may be less than the peak value P of the p-type impurity concentration of the contact region 154.

[0450] The peak value of the p-type impurity concentration of the outer deep well region 172 is 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 The lower limit of the peak value of the p-type impurity concentration of the outer deep well region 172 may be 1.0×10 18 cm -3 It is preferable that this is equal to or greater than this.

[0451] The field limit structure 173 is formed in a region between the diode region 171 and the side surfaces 105A to 105D in a plan view. In this embodiment, the field limit structure 173 is formed at an interval from the side surfaces 105A to 105D toward the diode region 171.

[0452] The field limit structure 173 includes one or more (for example, two or more and twenty or less) field limit regions 174. In this embodiment, the field limit structure 173 includes a field limit region group having a plurality (five) of field limit regions 174A, 174B, 174C, 174D, and 174E.

[0453] The field limit regions 174A to 174E are formed in this order at intervals along a direction away from the diode region 171. Each of the field limit regions 174A to 174E extends in a strip shape along the periphery of the active region 106 in a plan view. More specifically, each of the field limit regions 174A to 174E is formed in an endless shape (a quadrangular ring shape in this embodiment) surrounding the active region 106 in a plan view. Each of the field limit regions 174A to 174E is formed by a Field Limiting Ring (FLR). It is also called the Ring region.

[0454] In this embodiment, the bottoms of the field limit regions 174A to 174E are located closer to the second main surface 104 than the bottom of the diode region 171. In this embodiment, the innermost field limit region 174A of the field limit regions 174A to 174E covers the diode region 171 from the second main surface 104 side. The field limit region 174A may overlap the above-mentioned source lead-out line 116 in plan view.

[0455] The field limit region 174A is electrically connected to the source lead-out wiring 116 via the diode region 171. The field limit region 174A may form a part of the pn junction diode D. The field limit region 174A may form a part of the avalanche current absorption structure.

[0456] The entire field limit regions 174A to 174E are located on the second main surface 104 side with respect to the bottom walls of the gate trenches 132. The bottoms of the field limit regions 174A to 174E are located on the second main surface 104 side with respect to the bottom walls of the source trenches 145.

[0457] The field limit regions 174A to 174E may be formed at a depth substantially equal to that of each deep well region 155 (outer deep well region 172). The bottoms of the field limit regions 174A to 174E may be located on substantially the same plane as the bottoms of each deep well region 155 (outer deep well region 172).

[0458] The bottoms of the field limit regions 174A to 174E may be located closer to the outer main surface 162 than the bottoms of the deep well regions 155 (outer deep well regions 172). The bottoms of the field limit regions 174A to 174E may be located closer to the second main surface 104 than the bottoms of the deep well regions 155 (outer deep well regions 172).

[0459] The width between adjacent field limit regions 174A to 174E may be different. The width between adjacent field limit regions 174A to 174E may increase in a direction away from the active region 106. The width between adjacent field limit regions 174A to 174E may decrease in a direction away from the active region 106.

[0460] The thickness (depth) of the field limit regions 174A to 174E may be different. The thickness (depth) of the field limit regions 174A to 174E may decrease in a direction away from the active region 106. The thickness (depth) of the field limit regions 174A to 174E may increase in a direction away from the active region 106.

[0461] The peak value of the p-type impurity concentration of the field limit regions 174A to 174E may be equal to or less than the peak value of the p-type impurity concentration of the diode region 171. The peak value of the p-type impurity concentration of the field limit regions 174A to 174E may be less than the peak value of the p-type impurity concentration of the diode region 171.

[0462] The peak value of the p-type impurity concentration of the field limit regions 174A-174E may be equal to or less than the peak value of the p-type impurity concentration of the outer deep well region 172. The peak value of the p-type impurity concentration of the field limit regions 174A-174E may be less than the peak value of the p-type impurity concentration of the outer deep well region 172.

[0463] The peak value of the p-type impurity concentration of the field limit regions 174A-174E may be equal to or greater than the peak value of the p-type impurity concentration of the outer deep well region 172. The peak value of the p-type impurity concentration of the field limit regions 174A-174E may exceed the peak value of the p-type impurity concentration of the outer deep well region 172.

[0464] The peak value of the p-type impurity concentration in the field limit regions 174A to 174E is 1.0×10 15 cm -3 Over 1.0 x 10 18 cm -3 It is preferable that the peak value of the p-type impurity concentration in the diode region 171>the peak value of the p-type impurity concentration in the outer deep well region 172>the peak value of the p-type impurity concentration in the field limit regions 174A to 174E.

[0465] The field limit structure 173 relieves electric field concentration in the outer region 107. The number, width, depth, p-type impurity concentration, etc. of the field limit regions 174 can take various values ​​depending on the electric field to be relieved.

[0466] In this embodiment, an example has been described in which the field limiting structure 173 includes one or more field limiting regions 174 formed in the region between the diode region 171 and the side surfaces 105A to 105D in a plan view. However, the field limiting structure 173 may include one or more field limiting regions 174 formed in the region between the active sidewall 164 and the diode region 171 in a plan view, instead of the region between the diode region 171 and the side surfaces 105A to 105D.

[0467] The field limit structure 173 may also include one or more field limit regions 174 formed in a region between the diode region 171 and the side surfaces 105A to 105D in a planar view, and one or more field limit regions 174 formed in a region between the active sidewall 164 and the diode region 171 in a planar view.

[0468] The SiC semiconductor device 101 includes an outer insulating layer 181 formed on the first main surface 103 in the outer region 107. The outer insulating layer 181 may include silicon oxide. The outer insulating layer 181 may also include other insulating materials such as silicon nitride. In this embodiment, the outer insulating layer 181 is formed of the same insulating material type as the gate insulating layer 138.

[0469] The outer insulating layer 181 selectively covers the diode region 171, the outer deep well region 172, and the field limit structure 173 in the outer region 107. The outer insulating layer 181 is formed in the form of a film along the active sidewall 164 and the outer main surface 162. The outer insulating layer 181 is continuous with the gate insulating layer 138 (more specifically, the third region 138c) on the active main surface 161.

[0470] The outer insulating layer 181 includes a first region 181a and a second region 181b. The first region 181a covers the active sidewall 164. The second region 181b covers the outer major surface 162. The thickness of the second region 181b may be equal to or less than the thickness of the first region 181a. The thickness of the second region 181b may be less than the thickness of the first region 181a.

[0471] The thickness of the first region 181a may be approximately equal to the thickness of the first region 181a of the gate insulating layer 138. The thickness of the second region 181b may be approximately equal to the thickness of the third region 138c of the gate insulating layer 138. The outer insulating layer 181 may be formed to have a uniform thickness.

[0472] 28 and 29, SiC semiconductor device 101 further includes a sidewall structure 182 covering active sidewall 164. Sidewall structure 182 protects and reinforces active plateau 163 from the outer region 107 side.

[0473] The sidewall structure 182 forms a step reduction structure that reduces the step formed between the active principal surface 161 and the outer principal surface 162. When an upper layer structure (covering layer) is formed to cover the boundary region between the active region 106 and the outer region 107, the sidewall structure 182 improves the flatness of the upper layer structure.

[0474] The sidewall structure 182 may have an inclined portion 183 that slopes downward from the active principal surface 161 toward the outer principal surface 162. The inclined portion 183 can appropriately reduce the step. The inclined portion 183 may be formed in a concave curve toward the SiC semiconductor layer 102 side. The inclined portion 183 may be formed in a convex curve toward the opposite side to the SiC semiconductor layer 102.

[0475] The inclined portion 183 may extend in a plane from the active principal surface 161 toward the outer principal surface 162. The inclined portion 183 may extend linearly from the active principal surface 161 toward the outer principal surface 162. The inclined portion 183 may be formed in a descending staircase shape extending from the active principal surface 161 toward the outer principal surface 162. In other words, the inclined portion 183 may have one or more steps recessed toward the outer principal surface 162. The multiple steps increase the surface area of ​​the inclined portion 183 and improve adhesion to the upper layer structure.

[0476] The inclined portion 183 may include a plurality of ridges that protrude outward from the sidewall structure 182. The plurality of ridges increases the surface area of ​​the inclined portion 183, enhancing adhesion to the upper layer structure. The inclined portion 183 may include a plurality of depressions that recess inward from the sidewall structure 182. The plurality of depressions increases the surface area of ​​the inclined portion 183, enhancing adhesion to the upper layer structure.

[0477] The sidewall structure 182 is formed in a self-aligned manner with respect to the active main surface 161. More specifically, the sidewall structure 182 is formed along the active sidewall 164. In this embodiment, the sidewall structure 182 is formed in an endless shape (a quadrangular ring in this embodiment) surrounding the active region 106 in plan view.

[0478] The sidewall structure 182 may contain at least one of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. The sidewall structure 182 preferably contains p-type polysilicon doped with p-type impurities. In this case, the sidewall structure 182 can be formed simultaneously with the gate electrode layer 139 and the source electrode layer 147.

[0479] In this case, the p-type impurity concentration of the sidewall structure 182 is equal to or higher than the p-type impurity concentration of the body region 131. More specifically, the p-type impurity concentration of the sidewall structure 182 exceeds the p-type impurity concentration of the body region 131. The p-type impurity concentration of the sidewall structure 182 is 1.0×10 18 cm -3 Over 1.0 x 10 22 cm -3 It may be the following:

[0480] The p-type impurity of the sidewall structure 182 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga). The p-type impurity concentration of the sidewall structure 182 may be approximately equal to the p-type impurity concentration of the gate electrode layer 139.

[0481] The sheet resistance of the sidewall structure 182 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this embodiment). The sheet resistance of the sidewall structure 182 may be approximately equal to the sheet resistance of the gate electrode layer 139.

[0482] The sidewall structures 182 may include n-type polysilicon instead of or in addition to p-type polysilicon. The sidewall structures 182 may also include an insulating material, which can improve the isolation of the active region 106 from the outer region 107.

[0483] 25 to 29, SiC semiconductor device 101 includes interlayer insulating layer 191 formed on first main surface 103. Interlayer insulating layer 191 selectively covers active region 106 and outer region 107. Interlayer insulating layer 191 is formed in the form of a film along active main surface 161 and outer main surface 162.

[0484] The interlayer insulating layer 191 selectively covers the trench gate structure 151, the gate wiring layer 140, and the trench source structure 152 in the active region 106. The interlayer insulating layer 191 selectively covers the diode region 171, the outer deep well region 172, and the field limit structure 173 in the outer region 107.

[0485] The interlayer insulating layer 191 is formed along the outer surface (inclined portion 183) of the sidewall structure 182 in the boundary region between the active region 106 and the outer region 107. The interlayer insulating layer 191 forms part of an upper layer structure that covers the sidewall structure 182. The peripheral edge of the interlayer insulating layer 191 may be formed flush with the side surfaces 105A to 105D.

[0486] The interlayer insulating layer 191 may contain silicon oxide or silicon nitride. The interlayer insulating layer 191 may contain PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide. The interlayer insulating layer 191 may have a layered structure including a PSG layer and a BPSG layer stacked in this order from the first main surface 103 side. The interlayer insulating layer 191 may have a layered structure including a BPSG layer and a PSG layer stacked in this order from the first main surface 103 side.

[0487] The interlayer insulating layer 191 includes a gate contact hole 192, a source contact hole 193, and a diode contact hole 194. The interlayer insulating layer 191 also includes an anchor hole 195.

[0488] The gate contact hole 192 exposes the gate wiring layer 140 in the active region 106. The gate contact hole 192 may be formed in a strip shape along the gate wiring layer 140. The opening edge portion of the gate contact hole 192 is formed in a convex curved shape facing inward of the gate contact hole 192.

[0489] The source contact hole 193 exposes the source region 153, the contact region 154, and the trench source structure 152 in the active region 106. The source contact hole 193 may be formed in a strip shape along the trench source structure 152, etc. The opening edge of the source contact hole 193 is formed in a convex curved shape facing inward of the source contact hole 193.

[0490] The diode contact hole 194 exposes the diode region 171 in the outer region 107. The diode contact hole 194 may be formed in a strip shape (more specifically, endless shape) extending along the diode region 171.

[0491] The diode contact hole 194 may expose the outer deep well region 172 and / or the field limit structure 173. The opening edge of the diode contact hole 194 is formed in a convex curve toward the inside of the diode contact hole 194.

[0492] The anchor holes 195 are formed by digging down the interlayer insulating layer 191 in the outer region 107. The anchor holes 195 are formed in a region between the diode region 171 and the side surfaces 105A to 105D in a plan view. More specifically, the anchor holes 195 are formed in a region between the field limit structure 173 and the side surfaces 105A to 105D in a plan view. The anchor holes 195 expose the first main surface 103 (the outer main surface 162). The opening edge portions of the anchor holes 195 are formed in a convex curved shape facing inward of the anchor holes 195.

[0493] 23, anchor hole 195 extends in a band shape along active region 106 in plan view. In this embodiment, anchor hole 195 is formed in an endless shape (a square ring shape in this embodiment) surrounding active region 106 in plan view. In this embodiment, one anchor hole 195 is formed in a portion of interlayer insulating layer 191 that covers outer region 107. However, multiple anchor holes 195 may be formed in a portion of interlayer insulating layer 191 that covers outer region 107.

[0494] The aforementioned gate principal surface electrode layer 108 and source principal surface electrode layer 114 are formed on an interlayer insulating layer 191. The gate principal surface electrode layer 108 and source principal surface electrode layer 114 each have a laminated structure including a barrier electrode layer 196 and a main electrode layer 197 laminated in this order from the first principal surface 103 side.

[0495] The barrier electrode layer 196 may have a single layer structure including a titanium layer or a titanium nitride layer, or may have a multilayer structure including a titanium layer and a titanium nitride layer stacked in this order from the first main surface 103 side.

[0496] The thickness of the main electrode layer 197 exceeds the thickness of the barrier electrode layer 196. The main electrode layer 197 includes a conductive material having a resistance value less than the resistance value of the barrier electrode layer 196. The main electrode layer 197 may include at least one of aluminum, copper, an aluminum alloy, and a copper alloy. The main electrode layer 197 may include at least one of an AlSi alloy, an AlSiCu alloy, and an AlCu alloy. In this embodiment, the main electrode layer 197 includes an AlSiCu alloy.

[0497] The gate main surface electrode layer 108 (outer gate fingers 110) extends from above the interlayer insulating layer 191 into the gate contact hole 192. The outer gate fingers 110 are electrically connected to the gate wiring layer 140 within the gate contact hole 192. This allows an electrical signal from the gate pad 109 to be transmitted to the gate electrode layer 139 via the outer gate fingers 110.

[0498] The source main surface electrode layer 114 (source pad 115) extends from above the interlayer insulating layer 191 into the source contact hole 193 and the source sub-trench 158. The source pad 115 is electrically connected to the source region 153, the contact region 154, and the source electrode layer 147 within the source contact hole 193 and the source sub-trench 158.

[0499] When the contact region 42 shown in FIG. 9A is formed as the contact region 154, the source principal surface electrode layer 114 (source pad 115) may form a Schottky junction with the contact region 154.

[0500] When the contact region 42 shown in FIG. 11 is formed as the contact region 154 , the source principal surface electrode layer 114 (source pad 115 ) may form an ohmic contact or a Schottky junction with the contact region 154 .

[0501] The source electrode layer 147 may be formed by utilizing a partial region of the source pad 115. In other words, the source electrode layer 147 may be formed by a portion of the source pad 115 that extends into each source trench 145.

[0502] The source principal surface electrode layer 114 (source lead-out wiring 116) extends from above the interlayer insulating layer 191 into the diode contact hole 194. The source lead-out wiring 116 is electrically connected to the diode region 171 in the diode contact hole 194.

[0503] The source main surface electrode layer 114 (source connection portion 117) is led out from the active region 106 to the outer region 107 across the sidewall structure 182. The source connection portion 117 forms part of an upper layer structure that covers the sidewall structure 182.

[0504] The SiC semiconductor device 101 includes a passivation layer 198 formed on the interlayer insulating layer 191. The passivation layer 198 may have a single-layer structure made of a silicon oxide layer or a silicon nitride layer. The passivation layer 198 may have a stacked structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. The passivation layer 198 preferably includes an insulating material different from that of the interlayer insulating layer 191. In this form, the passivation layer 198 has a single-layer structure made of a silicon nitride layer.

[0505] The passivation layer 198 is formed in a film shape along the interlayer insulating layer 191. The passivation layer 198 selectively covers the active region 106 and the outer region 107 via the interlayer insulating layer 191. The passivation layer 198 extends from the active region 106 across the sidewall structures 182 to the outer region 107. The passivation layer 198 forms part of an upper layer structure that covers the sidewall structures 182.

[0506] The passivation layer 198 includes a gate subpad opening 199 and a source subpad opening 200 (see also FIG. 23). The gate subpad opening 199 exposes the gate pad 109. The source subpad opening 200 exposes the source pad 115.

[0507] 28, passivation layer 198 extends from above interlayer insulating layer 191 into anchor hole 195 in outer region 107. Passivation layer 198 is connected to first main surface 103 (outer main surface 162) within anchor hole 195. Recesses 201 that are recessed in line with anchor hole 195 are formed in the outer surface of passivation layer 198 in regions located above anchor hole 195.

[0508] The peripheral edge of passivation layer 198 may be formed flush with side surfaces 105A to 105D. The peripheral edge of passivation layer 198 may be formed at an interval inward from side surfaces 105A to 105D. The peripheral edge of passivation layer 198 may expose first main surface 103 (interlayer insulating layer 191) in plan view.

[0509] The peripheral edge of passivation layer 198 may be continuous with peripheral edge 118a of resin layer 118. In other words, the peripheral edge of passivation layer 198 may define a part of dicing street DS. By exposing first main surface 103 from the peripheral edge of passivation layer 198, it is not necessary to physically cut passivation layer 198. Therefore, SiC semiconductor devices 101 can be smoothly cut out from one SiC semiconductor wafer.

[0510] The resin layer 118 described above is formed on the passivation layer 198. The resin layer 118 is formed in the form of a film along the passivation layer 198. The resin layer 118 selectively covers the active region 106 and the outer region 107, with the passivation layer 198 and the interlayer insulating layer 191 sandwiched between them. The resin layer 118 extends from the active region 106 across the sidewall structures 182 to the outer region 107. The resin layer 118 forms part of an upper layer structure that covers the sidewall structures 182.

[0511] The gate pad opening 119 in the resin layer 118 communicates with the gate subpad opening 199 in the passivation layer 198. The inner wall of the gate pad opening 119 may be located outside the inner wall of the gate subpad opening 199. The inner wall of the gate pad opening 119 may be located inside the inner wall of the gate subpad opening 199. In other words, the resin layer 118 may cover the inner wall of the gate subpad opening 199.

[0512] The source pad opening 120 in the resin layer 118 communicates with the source subpad opening 200 in the passivation layer 198. The inner wall of the gate pad opening 119 may be located outside the inner wall of the source subpad opening 200. The inner wall of the source pad opening 120 may be located inside the inner wall of the source subpad opening 200. In other words, the resin layer 118 may cover the inner wall of the source subpad opening 200.

[0513] 28, resin layer 118 has anchor portions that enter recesses 201 of passivation layer 198 in outer region 107. As a result, an anchor structure that increases the connection strength of resin layer 118 is formed in outer region 107.

[0514] The anchor structure includes an uneven structure formed on the first main surface 103 in the outer region 107. More specifically, the anchor structure (uneven structure) includes unevenness formed by utilizing an interlayer insulating layer 191 that covers the outer main surface 162. More specifically, the anchor structure (uneven structure) includes anchor holes 195 formed in the interlayer insulating layer 191.

[0515] The resin layer 118 is engaged with the anchor hole 195. In this embodiment, the resin layer 118 is engaged with the anchor hole 195 via the passivation layer 198. This increases the connection strength of the resin layer 118 to the first main surface 103, thereby preventing the resin layer 118 from peeling off.

[0516] As described above, SiC semiconductor device 101 can also achieve the same effects as those described for SiC semiconductor device 1. Furthermore, according to SiC semiconductor device 101, the depletion layer can be expanded from the boundary region (pn junction) between SiC semiconductor layer 102 and deep well region 155 toward the region on the second main surface 104 side with respect to the bottom wall of gate trench 132.

[0517] This narrows the current path of the short-circuit current flowing between the source principal surface electrode layer 114 and the drain electrode layer 125. Furthermore, the depletion layer extending from the boundary region between the SiC semiconductor layer 102 and the deep well region 155 reduces the reverse transfer capacitance Crss inversely proportionally. This provides the SiC semiconductor device 101 with improved short-circuit resistance and reduced reverse transfer capacitance Crss. The reverse transfer capacitance Crss is the electrostatic capacitance between the gate electrode layer 139 and the drain electrode layer 125.

[0518] The depletion layer extending from the boundary region (pn junction) between the SiC semiconductor layer 102 and the deep well region 155 may overlap the bottom wall of the gate trench 132. In this case, the depletion layer extending from the bottom of the deep well region 155 may overlap the bottom wall of the gate trench 132.

[0519] Furthermore, in the SiC semiconductor device 101, the distance between the bottom of each deep well region 155 and the second main surface 104 is approximately constant. This makes it possible to prevent variations in the distance between the bottom of each deep well region 155 and the second main surface 104. This prevents the breakdown voltage (e.g., breakdown resistance) of the SiC semiconductor layer 102 from being limited by the shape of the deep well region 155, thereby enabling the breakdown voltage to be appropriately improved.

[0520] Furthermore, according to the SiC semiconductor device 101, a diode region 171 is formed in the outer region 107. This diode region 171 is electrically connected to the source principal surface electrode layer 114. This allows an avalanche current generated in the outer region 107 to flow into the source principal surface electrode layer 114 via the diode region 171. This can improve the stability of the operation of the MISFET.

[0521] Furthermore, according to SiC semiconductor device 101, outer deep well region 172 is formed in outer region 107. This allows the breakdown voltage of SiC semiconductor layer 102 to be adjusted in outer region 107.

[0522] The outer deep well region 172 is formed at a depth substantially equal to that of the deep well region 155. More specifically, the bottom of the outer deep well region 172 is located on substantially the same plane as the bottom of the deep well region 155. In other words, the distance between the bottom of the outer deep well region 172 and the second main surface 104 is substantially equal to the distance between the bottom of the deep well region 155 and the second main surface 104.

[0523] This can prevent variations from occurring between the distance between the bottom of outer deep well region 172 and second main surface 104 and the distance between the bottom of deep well region 155 and second main surface 104. This prevents the breakdown voltage (e.g., breakdown resistance) of SiC semiconductor layer 102 from being limited by the shape of outer deep well region 172 and the shape of deep well region 155. As a result, the breakdown voltage can be appropriately improved.

[0524] Furthermore, in the SiC semiconductor device 101, the outer region 107 is formed in a region closer to the second main surface 104 than the active region 106. This allows the position of the bottom of the outer deep well region 172 to be appropriately brought closer to the position of the bottom of the deep well region 155. In other words, when forming the outer deep well region 172, it is no longer necessary to introduce p-type impurities into a relatively deep position in the surface layer of the first main surface 103. This makes it possible to appropriately prevent the position of the bottom of the outer deep well region 172 from being significantly shifted from the position of the bottom of the deep well region 155.

[0525] Moreover, in SiC semiconductor device 101, outer main surface 162 is located on approximately the same plane as the bottom wall of source trench 145. This allows deep well region 155 and outer deep well region 172 to be formed at approximately the same depth when p-type impurities are introduced into the bottom wall of source trench 145 and outer main surface 162 with equal energy. As a result, it is possible to more appropriately prevent the bottom of outer deep well region 172 from being significantly misaligned with the bottom of deep well region 155.

[0526] Furthermore, according to the SiC semiconductor device 101, the field limit structure 173 is formed in the outer region 107. This makes it possible to obtain an electric field relaxation effect due to the field limit structure 173 in the outer region 107. This makes it possible to appropriately improve the breakdown voltage of the SiC semiconductor layer 102.

[0527] Furthermore, according to the SiC semiconductor device 101, the active region 106 is formed as a plateau-shaped active plateau 163. The active plateau 163 includes an active sidewall 164 connecting the active main surface 161 and the outer main surface 162 of the active region 106. A step reduction structure that reduces the step between the active main surface 161 and the outer main surface 162 is formed in the region between the active main surface 161 and the outer main surface 162. The step reduction structure includes a sidewall structure 182.

[0528] This makes it possible to appropriately reduce the step between the active main surface 161 and the outer main surface 162. This makes it possible to appropriately improve the flatness of the upper layer structure formed on the sidewall structure 182. In the SiC semiconductor device 101, an interlayer insulating layer 191, a source main surface electrode layer 114, a passivation layer 198, and a resin layer 118 are formed as examples of the upper layer structure.

[0529] Furthermore, according to SiC semiconductor device 101, an anchor structure for increasing the connection strength of resin layer 118 is formed in outer region 107. The anchor structure includes an uneven structure formed on first main surface 103 in outer region 107. More specifically, the anchor structure (uneven structure) includes unevenness formed by utilizing interlayer insulating layer 191 formed on first main surface 103 in outer region 107. More specifically, the anchor structure (uneven structure) includes anchor holes 195 formed in interlayer insulating layer 191.

[0530] The resin layer 118 is engaged with the anchor hole 195. In this embodiment, the resin layer 118 is engaged with the anchor hole 195 via the passivation layer 198. This increases the connection strength of the resin layer 118 to the first main surface 103, thereby appropriately suppressing peeling of the resin layer 118.

[0531] Furthermore, according to the SiC semiconductor device 101, a trench gate structure 151 is formed in which a gate electrode layer 139 is embedded in the gate trench 132 with a gate insulating layer 138 sandwiched therebetween. In this trench gate structure 151, the gate electrode layer 139 is covered with a low-resistance electrode layer 157 in the limited space of the gate trench 132. Such a structure can achieve the same effects as those described with reference to FIG.

[0532] Fig. 30 is a graph for explaining the sheet resistance in the gate trench 132. In Fig. 30, the vertical axis represents the sheet resistance [Ω / □], and the horizontal axis represents the item. Fig. 30 shows a first bar graph BL1, a second bar graph BL2, and a third bar graph BL3.

[0533] The first bar graph BL1 represents the sheet resistance in the gate trench 132 filled with n-type polysilicon. The second bar graph BL2 represents the sheet resistance in the gate trench 132 filled with p-type polysilicon.

[0534] A third bar graph BL3 represents the sheet resistance in the gate trench 132 in which the gate electrode layer 139 (p-type polysilicon) and the low-resistance electrode layer 157 are buried. Here, a case will be described in which the low-resistance electrode layer 157 is formed from TiSi2 (p-type titanium silicide) as an example of polycide (silicide).

[0535] Referring to the first bar graph BL1, the sheet resistance in the gate trench 132 filled with n-type polysilicon was 10 Ω / □. Referring to the second bar graph BL2, the sheet resistance in the gate trench 132 filled with p-type polysilicon was 200 Ω / □. Referring to the third bar graph BL3, the sheet resistance in the gate trench 132 filled with the gate electrode layer 139 (p-type polysilicon) and the low resistance electrode layer 157 was 2 Ω / □.

[0536] P-type polysilicon has a work function different from that of n-type polysilicon. A structure in which p-type polysilicon is buried in the gate trench 132 can increase the gate threshold voltage Vth by about 1 V. However, p-type polysilicon has a sheet resistance that is several tens of times (here, 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material for the gate electrode layer 139, energy loss increases significantly as the parasitic resistance in the gate trench 132 (hereinafter simply referred to as "gate resistance") increases.

[0537] In contrast, with a structure having a low resistance electrode layer 157 on the gate electrode layer 139 (p-type polysilicon), the sheet resistance can be reduced to one hundredth or less compared to a case in which the low resistance electrode layer 157 is not formed. Furthermore, with a structure having the low resistance electrode layer 157, the sheet resistance can be reduced to one fifth or less compared to a gate electrode layer 139 including n-type polysilicon.

[0538] In this way, the structure having the low-resistance electrode layer 157 can reduce the sheet resistance in the gate trench 132 while increasing the gate threshold voltage Vth (for example, by about 1 V). This reduces the gate resistance, allowing current to be efficiently diffused along the trench gate structure 151. As a result, switching delay can be reduced.

[0539] Furthermore, the structure having the low-resistance electrode layer 157 eliminates the need to increase the p-type impurity concentration in the body region 131. This allows the gate threshold voltage Vth to be appropriately increased while suppressing an increase in channel resistance. Furthermore, the structure having the low-resistance electrode layer 157 eliminates the need to increase the p-type impurity concentration in the contact region 154. This allows the gate threshold voltage Vth to be appropriately increased while suppressing deterioration of the gate threshold voltage Vth over time and an increase in channel resistance.

[0540] The low-resistance electrode layer 157 may contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. Of these materials, NiSi, CoSi2, and TiSi2 are particularly suitable as a polycide layer for forming the low-resistance electrode layer 157 because they have relatively small resistivity and temperature dependence.

[0541] Further testing by the inventors of the present application revealed that when TiSi2 was used as the material for the low-resistance electrode layer 157, an increase in the leakage current between the gate and source was observed when a low electric field was applied. In contrast, when CoSi2 was used, no increase in the leakage current between the gate and source was observed when a low electric field was applied. Considering this, CoSi2 is considered to be the most preferable polycide layer for forming the low-resistance electrode layer 157.

[0542] Furthermore, in the SiC semiconductor device 101, the gate wiring layer 140 is covered with the low-resistance electrode layer 157. This also reduces the gate resistance of the gate wiring layer 140. In particular, in a structure in which the gate electrode layer 139 and the gate wiring layer 140 are covered with the low-resistance electrode layer 157, current can be efficiently diffused along the trench gate structure 151. This makes it possible to appropriately reduce switching delay.

[0543] Fig. 31 is an enlarged view of a region corresponding to Fig. 24, showing a SiC semiconductor device 211 according to a ninth embodiment of the present invention. Fig. 32 is a cross-sectional view taken along line XXXII-XXXII shown in Fig. 31. In the following, structures corresponding to those described with respect to SiC semiconductor device 101 will be given the same reference numerals and will not be described again.

[0544] 31 and 32 , a SiC semiconductor device 211 includes an outer gate trench 212 formed in the first main surface 103 in the active region 106. The outer gate trench 212 extends in a strip shape along the periphery of the active region 106. The outer gate trench 212 is formed in a region directly below the outer gate finger 110 in the first main surface 103. The outer gate trench 212 extends along the outer gate finger 110.

[0545] More specifically, the outer gate trench 212 is formed along the three side surfaces 105A, 105B, and 105D, and defines the inner region of the active region 106 from three directions. The outer gate trench 212 may be formed in an endless shape (for example, a rectangular ring shape) surrounding the inner region of the active region 106.

[0546] The outer gate trench 212 communicates with the contact trench portion 134 of each gate trench 132. As a result, the outer gate trench 212 and the gate trench 132 are formed by a single trench.

[0547] A gate wiring layer 140 is buried in the outer gate trench 212. The gate wiring layer 140 is connected to the gate electrode layer 139 at the communicating portion between the gate trench 132 and the outer gate trench 212.

[0548] A low-resistance electrode layer 157 covering the gate wiring layer 140 is formed in the outer gate trench 212. In this case, the low-resistance electrode layer 157 covering the gate electrode layer 139 and the low-resistance electrode layer 157 covering the gate wiring layer 140 are located within one trench.

[0549] As described above, the SiC semiconductor device 211 can also achieve the same effects as those described for the SiC semiconductor device 101. Furthermore, the SiC semiconductor device 211 does not require the gate wiring layer 140 to be extended onto the first main surface 103. This makes it possible to prevent the gate wiring layer 140 from facing the SiC semiconductor layer 102 across the gate insulating layer 138 at the opening edge 136 of the gate trench 132 (outer gate trench 212). As a result, it is possible to prevent electric field concentration at the opening edge 136 of the gate trench 132 (outer gate trench 212).

[0550] Fig. 33 is an enlarged view of a region corresponding to Fig. 27, showing a SiC semiconductor device 221 according to a tenth embodiment of the present invention. In the following, structures corresponding to those described for the SiC semiconductor device 101 are given the same reference numerals, and descriptions thereof will be omitted.

[0551] 33 , in this embodiment, the SiC epitaxial layer 122 includes a high concentration region 123, a low concentration region 124, and a concentration gradient region 222 interposed between the high concentration region 123 and the low concentration region 124. The concentration gradient region 222 is formed in the SiC epitaxial layer 122 not only in the active region 106 but also in the outer region 107. The concentration gradient region 222 is formed throughout the entire SiC epitaxial layer 122.

[0552] The concentration gradient region 222 has a concentration gradient in which the n-type impurity concentration gradually decreases from the high-concentration region 123 to the low-concentration region 124. In other words, the concentration gradient region 222 has a concentration gradient in which the n-type impurity concentration gradually increases from the low-concentration region 124 to the high-concentration region 123. The concentration gradient region 222 suppresses abrupt fluctuations in the n-type impurity concentration in the region between the high-concentration region 123 and the low-concentration region 124.

[0553] When the SiC epitaxial layer 122 includes the concentration gradient region 222, the n-type impurity concentration of the high-concentration region 123 is preferably 1.5 to 5 times the n-type impurity concentration of the low-concentration region 124. The n-type impurity concentration of the high-concentration region 123 may be 3 to 5 times the n-type impurity concentration of the low-concentration region 124.

[0554] The thickness of the concentration gradient region 222 may be 0.5 μm or more and 2.0 μm or less, 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2.0 μm or less.

[0555] Although a detailed description will be omitted, the aforementioned gate trench 132, source trench 145, deep well region 155, outer deep well region 172, etc. are formed in the high concentration region 123. In other words, the aforementioned gate trench 132, source trench 145, deep well region 155, outer deep well region 172, etc. are formed in a region on the first main surface 103 side of the boundary region between the high concentration region 123 and the concentration gradient region 222 in the SiC semiconductor layer 102.

[0556] As described above, the SiC semiconductor device 221 can also achieve the same effects as those described for the SiC semiconductor device 101.

[0557] Fig. 34 is an enlarged view of a region corresponding to Fig. 24, showing a SiC semiconductor device 231 according to an eleventh embodiment of the present invention. In the following, structures corresponding to those described with respect to the SiC semiconductor device 101 are given the same reference numerals, and descriptions thereof will be omitted.

[0558] 34, in this embodiment, the gate trenches 132 are formed in a lattice shape in plan view. More specifically, the gate trenches 132 include a plurality of first gate trenches 232 and a plurality of second gate trenches 233. The plurality of first gate trenches 232 and the plurality of second gate trenches 233 form an active trench portion 133.

[0559] The multiple first gate trenches 232 are each formed in a strip shape extending along a first direction X (the m-axis of the SiC single crystal) and are formed at intervals in a second direction Y (the a-axis of the SiC single crystal). The multiple first gate trenches 232 are formed in a stripe shape extending along the first direction X in a plan view. The sidewalls forming the long sides of each first gate trench 232 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of each first gate trench 232 are formed by the m-plane of the SiC single crystal.

[0560] The second gate trenches 233 are each formed in a strip shape extending along the second direction Y (the a-axis of the SiC single crystal) and are formed at intervals in the first direction X (the m-axis of the SiC single crystal). The second gate trenches 233 are formed in a stripe shape extending along the second direction Y in a plan view. The sidewalls forming the long sides of each second gate trench 233 are formed by the m-plane of the SiC single crystal. The sidewalls forming the short sides of each second gate trench 233 are formed by the a-plane of the SiC single crystal.

[0561] The multiple second gate trenches 233 intersect with the multiple first gate trenches 232. This forms one gate trench 132 in a lattice shape in plan view. In the area surrounded by the gate trench 132, multiple cell regions 234 are defined.

[0562] The multiple cell regions 234 are arranged in a matrix at intervals in the first direction X and the second direction Y in a plan view. The multiple cell regions 234 are formed in a quadrangular shape in a plan view. The gate trench 132 may be formed in a honeycomb shape, which is one aspect of a lattice shape, in a plan view. In this case, the multiple cell regions 234 may be formed in a hexagonal shape in a plan view. Furthermore, in this case, the multiple cell regions 234 may be arranged in a staggered manner at intervals in the first direction X and the second direction Y.

[0563] In each cell region 234, the body region 131 is exposed from the sidewall of the gate trench 132. In the gate trench 132, the body region 131 is exposed from the sidewall formed by the m-plane and a-plane of the SiC single crystal.

[0564] Each source trench 145 is formed in the center of each cell region 234 in a plan view. Each source trench 145 is formed in a pattern that appears alone on a cross section of each cell region 234 taken along the first direction X. Each source trench 145 is also formed in a pattern that appears alone on a cross section of each cell region 234 taken along the second direction Y. The sidewalls of each source trench 145 are formed by the m-plane and a-plane of the SiC single crystal.

[0565] More specifically, each source trench 145 is formed in a quadrangular shape in plan view. The planar shape of each source trench 145 is arbitrary. Each source trench 145 may be formed in a polygonal shape such as a triangular shape, a pentagonal shape, or a hexagonal shape, or may be formed in a circular or elliptical shape in plan view.

[0566] The cross-sectional view taken along line XXV-XXV in Fig. 34 corresponds to the cross-sectional view shown in Fig. 25. The cross-sectional view taken along line XXVI-XXVI in Fig. 34 corresponds to the cross-sectional view shown in Fig. 26.

[0567] As described above, the SiC semiconductor device 231 can also achieve the same effects as those described for the SiC semiconductor device 101.

[0568] The present invention may be embodied in other forms.

[0569] In the above-described embodiments, examples have been described in which the SiC semiconductor layer 2, 102 has a layered structure including the SiC semiconductor substrate 21, 121 and the SiC epitaxial layer 122. However, the SiC semiconductor layer 2, 102 may have a single-layer structure made of the SiC semiconductor substrate 21, 121. The SiC semiconductor layer 2, 102 may have a single-layer structure made of the SiC epitaxial layer 22, 122.

[0570] In the above-described embodiments, examples have been described in which a plurality of gate trenches 32, 132 (first gate trenches 33, 232) extending along the m-axis direction ([1-100] direction) of the SiC single crystal are formed. However, a plurality of gate trenches 32, 132 (first gate trenches 33, 232) extending along the a-axis direction ([11-20] direction) of the SiC single crystal may also be formed. In this case, a plurality of source trenches 63, 145 extending along the a-axis direction ([11-20] direction) of the SiC single crystal are formed.

[0571] In the above-described embodiments, examples have been described in which the source electrode layers 67, 147 are embedded in the source trenches 63, 145 with the source insulating layers 66, 146 sandwiched therebetween. However, the source electrode layers 67, 147 may be embedded directly in the source trenches 63, 145 without the source insulating layers 66, 146 interposed therebetween.

[0572] In the above-described embodiments, examples have been described in which the source insulating layers 66, 146 are formed along the sidewalls and bottom walls of the source trenches 63, 145. However, the source insulating layers 66, 146 may expose the bottom walls of the source trenches 63, 145. In this case, the source insulating layers 66, 146 may be formed along the sidewalls and bottom walls of the source trenches 63, 145 so as to expose part of the bottom walls of the source trenches 63, 145.

[0573] The source insulating layers 66, 146 may also expose the sidewalls of the source trenches 63, 145. In this case, the source insulating layers 66, 146 may be formed along the sidewalls and bottom walls of the source trenches 63, 145 so as to expose part of the sidewalls of the source trenches 63, 145.

[0574] In the eighth to eleventh embodiments described above, examples have been described in which the gate electrode layer 139 and the gate wiring layer 140 contain p-type polysilicon. However, when increasing the gate threshold voltage Vth is not a priority, the gate electrode layer 139 and the gate wiring layer 140 may contain n-type polysilicon doped with n-type impurities instead of or in addition to p-type polysilicon.

[0575] In this case, the low-resistance electrode layer 157 may be formed by silicidating a surface portion of the gate electrode layer 139 (n-type polysilicon) with a metal material. That is, the low-resistance electrode layer 157 may include n-type polycide. With such a structure, it is possible to reduce the gate resistance.

[0576] In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted, i.e., a p-type portion may be made n-type, and an n-type portion may be made p-type.

[0577] In each of the above embodiments, n + Instead of the SiC semiconductor substrate 21, 121, + Alternatively, a SiC semiconductor substrate (21, 121) of the type described above may be employed. With this structure, an IGBT (Insulated Gate Bipolar Transistor) can be provided instead of the MISFET. In this case, in each of the above-described embodiments, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT.

[0578] The above-described embodiments can also be applied to semiconductor devices using semiconductor materials other than SiC. For example, the above-described embodiments can also be applied to a compound semiconductor device including a vertical compound semiconductor MISFET in which a compound semiconductor material is used instead of SiC. The compound semiconductor material may be either or both of gallium nitride (GaN) and gallium oxide (Ga2O3).

[0579] In the compound semiconductor MISFET, magnesium may be used as a p-type impurity (acceptor), and germanium (Ge), oxygen (O), or silicon (Si) may be used as an n-type impurity (donor).

[0580] This specification does not limit any combination of the features shown in the first to eleventh embodiments. The first to eleventh embodiments can be combined in any manner and in any form. In other words, a SiC semiconductor device in which the features shown in the first to eleventh embodiments are combined in any manner and in any form may be employed.

[0581] Examples of features extracted from this specification and drawings are given below. The following examples all show SiC semiconductor devices that contribute to suppressing degradation of the gate threshold voltage Vth over time.

[0582] [A1] A SiC semiconductor layer having a first main surface on one side and a second main surface on the other side, the SiC semiconductor layer including an active region and an outer region outside the active region; a trench formed in the first main surface in the active region; a gate insulating layer formed on an inner wall of the trench; a gate electrode embedded in the trench with the gate insulating layer sandwiched between the trench and the source region; a first conductivity type source region formed in a surface layer portion of the first main surface in the active region and located on a side of the trench; a second conductivity type body region formed in a surface layer portion of the first main surface in the active region and located in a region on the second main surface side with respect to the source region; a first conductivity type drift region formed in a surface layer portion of the first main surface in the active region and the outer region, the first conductivity type drift region including a portion located in a region on the second main surface side with respect to the body region; 20 cm -3and a second conductivity type contact region having the following second conductivity type impurity concentration:

[0583] [A2] The second conductivity type impurity concentration in the contact region is 1.0×10 17 cm -3 The SiC semiconductor device according to A1 is as described above.

[0584] [A3] The second conductivity type impurity concentration in the contact region is 1.0×10 20 cm -3 The SiC semiconductor device according to A1 or A2, wherein the SiC semiconductor device has a thickness of less than 100 μm.

[0585] [A4] The impurity region is 1.0×10 20 cm -3 The SiC semiconductor device according to any one of A1 to A3, having the following second conductivity type impurity concentration:

[0586] [A5] The impurity region is 1.0×10 17 cm -3 The SiC semiconductor device according to A4, having the above second conductivity type impurity concentration.

[0587] [A6] The impurity region is 1.0×10 20 cm -3 The SiC semiconductor device according to any one of A1 to A3, having a second conductivity type impurity concentration exceeding:

[0588] [A7] The impurity region is 1.0×10 21 cm -3 The SiC semiconductor device according to A6, having the following second conductivity type impurity concentration:

[0589] [A8] The SiC semiconductor device according to any one of A1 to A3, wherein the impurity region has the same second conductivity type impurity concentration as the contact region.

[0590] [A9] The SiC semiconductor device according to any one of A1 to A8, wherein the impurity region has a thickness equal to that of the contact region.

[0591] [A10] The SiC semiconductor device according to any one of A1 to A9, wherein the impurity region extends in a strip shape along the active region.

[0592] [A11] The SiC semiconductor device according to any one of A1 to A10, wherein the impurity region surrounds the active region.

[0593] [A12] The SiC semiconductor device according to any one of A1 to A11, further including an electrode layer formed on the first main surface, forming an ohmic contact with the source region, and forming a Schottky junction with the contact region.

[0594] [A13] The SiC semiconductor device according to A1, further including an electrode layer formed on the first main surface, forming an ohmic contact with the source region, forming a Schottky junction with the contact region, and forming an ohmic contact with the impurity region.

[0595] [A14] The SiC semiconductor device according to A1, further including an electrode layer formed on the first main surface, forming an ohmic contact with the source region, forming a Schottky junction with the contact region, and forming a Schottky junction with the impurity region.

[0596] [A15] The SiC semiconductor device according to any one of A1 to A14, wherein the SiC semiconductor layer includes a SiC single crystal made of a hexagonal system.

[0597] [A16] The SiC semiconductor device according to A15, wherein the SiC semiconductor layer includes a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, or a 6H-SiC single crystal.

[0598] [A17] The SiC semiconductor device according to A15 or A16, wherein the first main surface faces the c-plane of the SiC single crystal.

[0599] [A18] The SiC semiconductor device according to any one of A15 to A17, wherein the trench has a sidewall facing an m-plane of the SiC single crystal, a sidewall facing an a-plane of the SiC single crystal, and a bottom wall facing a c-plane of the SiC single crystal.

[0600] [A19] The SiC semiconductor device according to A18, wherein the source region is exposed from a sidewall of the trench facing the a-plane of the SiC single crystal, and the body region is exposed from a sidewall of the trench facing the a-plane of the SiC single crystal.

[0601] [A20] The SiC semiconductor device according to any one of A15 to A19, wherein the first main surface has an off-angle inclined at an angle of 0° or more and 10° or less with respect to a c-plane of the SiC single crystal.

[0602] [A21] The SiC semiconductor device according to A20, wherein the off angle is an angle of 5° or less.

[0603] [A22] The SiC semiconductor device according to A20 or A21, wherein the off angle is an angle exceeding 0° and less than 4°.

[0604] [A23] The SiC semiconductor device according to any one of A1 to A22, further comprising a second trench formed in the first main surface at a distance from the trench in the active region, and the contact region is formed on the side of the second trench.

[0605] [A24] The SiC semiconductor device according to A23, further comprising a source electrode layer buried in the second trench.

[0606] [A25] The SiC semiconductor device according to A23 or A24, wherein the contact region is exposed from a sidewall of the second trench.

[0607] [A26] The SiC semiconductor device according to any one of A23 to A25, wherein the contact region is exposed from a sidewall and a bottom wall of the second trench.

[0608] [A27] The SiC semiconductor device according to any one of A23 to A26, wherein the trenches are formed in a lattice pattern in a planar view, and the second trenches are formed in a region surrounded by the trenches in a planar view.

[0609] [A28] The SiC semiconductor device according to any one of A23 to A27, wherein the trench extends in a band shape in plan view, and the second trench extends in a band shape along the trench in plan view.

[0610] [A29] The SiC semiconductor device according to any one of A23 to A28, wherein the second trench is deeper than the first trench.

[0611] [B1] A SiC semiconductor layer having a first main surface on one side and a second main surface on the other side, the SiC semiconductor layer including an active region and an outer region outside the active region, a trench formed in the first main surface in the active region, a gate insulating layer formed on an inner wall of the trench, a gate electrode embedded in the trench with the gate insulating layer sandwiched therebetween, a first conductivity type source region formed in a surface layer portion of the first main surface in the active region and located on a side of the trench, a second conductivity type body region formed in a surface layer portion of the first main surface in the active region and located in a region on the second main surface side with respect to the source region, and a first conductivity type drift region formed in a surface layer portion of the first main surface in the outer region and including a portion located in a region on the second main surface side with respect to the body region; a second conductivity type impurity region formed in a surface layer portion of the first main surface in the outer region and forming a pn junction diode between the drift region and the drift region; and a second conductivity type contact region formed in a surface layer portion of the first main surface in the active region and located in a region on the opposite side of the source region from the trench, the contact region containing first conductivity type impurities and second conductivity type impurities, wherein a portion of the second conductivity type impurities is offset and compensated by the first conductivity type impurities.

[0612] [B2] The SiC semiconductor device according to B1, wherein the contact region has a second conductivity type impurity concentration that exceeds a first conductivity type impurity concentration of the source region.

[0613] [B3] The SiC semiconductor device according to B1 or B2, wherein the contact region has a second conductivity type impurity concentration that is lower than the second conductivity type impurity concentration of the impurity region.

[0614] [B4] The contact area is 1.0×10 20 cm -3 The SiC semiconductor device according to any one of B1 to B3, having the above second conductivity type impurity concentration.

[0615] [B5] The contact area is 1.0×10 21 cm-3 The SiC semiconductor device according to B4, having the following second conductivity type impurity concentration:

[0616] [B6] The impurity region is 1.0×10 20 cm -3 The SiC semiconductor device according to any one of B1 to B5, having the above second conductivity type impurity concentration.

[0617] [B7] The contact area is 1.0×10 21 cm -3 The SiC semiconductor device according to B6, having the following second conductivity type impurity concentration:

[0618] [B8] The SiC semiconductor device according to any one of B1 to B7, wherein the contact region has a thickness greater than a thickness of the source region.

[0619] [B9] The SiC semiconductor device according to B8, wherein the contact region includes a surface region located in a region on the first main surface side relative to a bottom of the source region, in which a portion of the second conductivity type impurities are offset and compensated by the first conductivity type impurities, and a bottom region located in a region on the second main surface side of the SiC semiconductor layer relative to the bottom of the source region, in which the second conductivity type impurities are not offset and compensated by the first conductivity type impurities.

[0620] [B10] The SiC semiconductor device according to any one of B1 to B9, wherein the impurity region extends in a strip shape along the active region.

[0621] [B11] The SiC semiconductor device according to any one of B1 to B10, wherein the impurity region surrounds the active region.

[0622] [B12] The SiC semiconductor device according to any one of B1 to B11, wherein the SiC semiconductor layer includes a SiC single crystal made of a hexagonal system.

[0623] [B13] The SiC semiconductor device according to B12, wherein the SiC semiconductor layer includes a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, or a 6H-SiC single crystal.

[0624] [B14] The SiC semiconductor device according to B12 or B13, wherein the first main surface faces the c-plane of the SiC single crystal.

[0625] [B15] The SiC semiconductor device according to any one of B12 to B14, wherein the trench has a sidewall facing an m-plane of the SiC single crystal, a sidewall facing an a-plane of the SiC single crystal, and a bottom wall facing a c-plane of the SiC single crystal.

[0626] [B16] The SiC semiconductor device according to B15, wherein the source region is exposed from a sidewall of the trench facing the a-plane of the SiC single crystal, and the body region is exposed from a sidewall of the trench facing the a-plane of the SiC single crystal.

[0627] [B17] The SiC semiconductor device according to any one of B12 to B16, wherein the first main surface has an off-angle inclined at an angle of 0° or more and 10° or less with respect to a c-plane of the SiC single crystal.

[0628] [B18] The SiC semiconductor device according to B17, wherein the off angle is an angle of 5° or less.

[0629] [B19] The SiC semiconductor device according to B17 or B18, wherein the off angle is an angle exceeding 0° and less than 4°.

[0630] [B20] The SiC semiconductor device according to any one of B1 to B19, further comprising a second trench formed in the first main surface at a distance from the trench in the active region, and the contact region is formed on the side of the second trench.

[0631] [B21] The SiC semiconductor device according to B20, further comprising a source electrode layer buried in the second trench.

[0632] [B22] The SiC semiconductor device according to B20 or B21, wherein the contact region is exposed from a sidewall of the second trench.

[0633] [B23] The SiC semiconductor device according to any one of B20 to B22, wherein the contact region is exposed from a sidewall and a bottom wall of the second trench.

[0634] [B24] The SiC semiconductor device according to any one of B20 to B23, wherein the trenches are formed in a lattice pattern in a planar view, and the second trenches are formed in a region surrounded by the trenches in a planar view.

[0635] [B25] The SiC semiconductor device according to any one of B20 to B24, wherein the trench extends in a band shape in plan view, and the second trench extends in a band shape along the trench in plan view.

[0636] [B26] The SiC semiconductor device according to any one of B20 to B25, wherein the second trench is deeper than the first trench.

[0637] [C1] A SiC semiconductor layer having a first main surface on one side and a second main surface on the other side, the SiC semiconductor layer including an active region and an outer region outside the active region, a trench formed in the first main surface in the active region, a gate insulating layer formed on an inner wall of the trench, a gate electrode embedded in the trench with the gate insulating layer sandwiched therebetween, a first conductivity type source region formed in a surface layer portion of the first main surface in the active region and positioned on a side of the trench, a second conductivity type body region formed in a surface layer portion of the first main surface in the active region and positioned in a region on the second main surface side with respect to the source region, and a first conductivity type drift region formed in a surface layer portion of the first main surface in a side region and including a portion located in a region on the second main surface side with respect to the body region; a second conductivity type impurity region formed in a surface layer portion of the first main surface in the outer region and forming a pn junction diode with the drift region; a second conductivity type contact region formed in a surface layer portion of the first main surface in the active region and located in a region on the opposite side of the source region from the trench; and an electrode layer formed on the first main surface and forming an ohmic contact with the source region and a Schottky junction with the contact region.

[0638] [C2] The SiC semiconductor device according to C1, wherein the electrode layer forms a Schottky junction with the impurity region.

[0639] [C3] The impurity region is 1.0×10 20 cm -3 The SiC semiconductor device according to C2, having the following second conductivity type impurity concentration:

[0640] [C4] The impurity region is 1.0×10 17 cm -3 The SiC semiconductor device according to C3, having the above second conductivity type impurity concentration.

[0641] [C5] The SiC semiconductor device according to C1, wherein the electrode layer forms an ohmic contact with the impurity region.

[0642] [C6] The impurity region is 1.0×10 20 cm -3 The SiC semiconductor device according to C5, wherein the SiC semiconductor device has a second conductivity type impurity concentration of more than

[0643] [C7] The impurity region is 1.0×10 21 cm -3 The SiC semiconductor device according to C6, having the following second conductivity type impurity concentration:

[0644] [C8] The SiC semiconductor device according to any one of C1 to C7, wherein the impurity region extends in a strip shape along the active region.

[0645] [C9] The SiC semiconductor device according to any one of C1 to C8, wherein the impurity region surrounds the active region.

[0646] [C10] The SiC semiconductor device according to any one of C1 to C9, wherein the SiC semiconductor layer includes a SiC single crystal made of a hexagonal system.

[0647] [C11] The SiC semiconductor device according to C10, wherein the SiC semiconductor layer includes a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, or a 6H-SiC single crystal.

[0648] [C12] The SiC semiconductor device according to C10 or C11, wherein the first main surface faces a c-plane of the SiC single crystal.

[0649] [C13] The SiC semiconductor device according to any one of C10 to C12, wherein the trench has a sidewall facing an m-plane of the SiC single crystal, a sidewall facing an a-plane of the SiC single crystal, and a bottom wall facing a c-plane of the SiC single crystal.

[0650] [C14] The SiC semiconductor device according to C13, wherein the source region is exposed from a sidewall of the trench facing the a-plane of the SiC single crystal, and the body region is exposed from a sidewall of the trench facing the a-plane of the SiC single crystal.

[0651] [C15] The SiC semiconductor device according to any one of C10 to C14, wherein the first main surface has an off-angle inclined at an angle of 0° or more and 10° or less with respect to a c-plane of the SiC single crystal.

[0652] [C16] The SiC semiconductor device according to C15, wherein the off angle is an angle of 5° or less.

[0653] [C17] The SiC semiconductor device according to C15 or C16, wherein the off angle is greater than 0° and less than 4°.

[0654] [C18] The SiC semiconductor device according to any one of C1 to C17, further comprising a second trench formed in the first main surface at a distance from the trench in the active region, and the contact region is formed on the side of the second trench.

[0655] [C19] The SiC semiconductor device according to C18, further comprising a source electrode layer buried in the second trench.

[0656] [C20] The SiC semiconductor device according to C18 or C19, wherein the contact region is exposed from a sidewall of the second trench.

[0657] [C21] The SiC semiconductor device according to any one of C18 to C20, wherein the contact region is exposed from a sidewall and a bottom wall of the second trench.

[0658] [C22] The SiC semiconductor device according to any one of C18 to C21, wherein the trenches are formed in a lattice pattern in a planar view, and the second trenches are formed in a region surrounded by the trenches in a planar view.

[0659] [C23] The SiC semiconductor device according to any one of C18 to C22, wherein the trench extends in a band shape in plan view, and the second trench extends in a band shape along the trench in plan view.

[0660] [C24] The SiC semiconductor device according to any one of C18 to C23, wherein the second trench is deeper than the first trench.

[0661] [D1] A SiC semiconductor device comprising: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a trench formed in the first main surface; a gate insulating layer formed on an inner wall of the trench; a gate electrode embedded in the trench with the gate insulating layer sandwiched between them; a first conductivity type source region formed on a side of the trench in a surface layer portion of the first main surface; a second conductivity type body region formed in a region on the second main surface side of the source region in the surface layer portion of the first main surface; a first conductivity type drift region formed in a region on the second main surface side of the body region in the SiC semiconductor layer; and a second conductivity type contact region having a second conductivity type impurity concentration that is greater than a second conductivity type impurity concentration of the body region and less than a first conductivity type impurity concentration of the source region.

[0662] [E1] A SiC semiconductor layer having a first main surface on one side and a second main surface on the other side, a trench formed in the first main surface, a gate insulating layer formed on an inner wall of the trench, a gate electrode embedded in the trench with the gate insulating layer sandwiched therebetween, a first conductivity type source region formed on a side of the trench in a surface layer portion of the first main surface, a second conductivity type body region formed in a region on the second main surface side with respect to the source region in the surface layer portion of the first main surface, a first conductivity type drift region formed in a region on the second main surface side with respect to the body region in the SiC semiconductor layer, a contact region of a second conductivity type formed in a surface layer portion of the main surface in a region on the opposite side of the trench with respect to the source region, and having a thickness greater than a thickness of the source region in a direction normal to the first main surface, wherein the contact region includes a surface layer region located on the first main surface side with respect to a bottom of the source region, in which some of the second conductivity type impurities are offset and compensated by first conductivity type impurities, and a bottom region located on the second main surface side of the SiC semiconductor layer with respect to the bottom of the source region, in which the second conductivity type impurities are not offset and compensated by the first conductivity type impurities.

[0663] [F1] A SiC semiconductor layer having a first main surface on one side and a second main surface on the other side, a trench formed in the first main surface, a second trench formed in the first main surface at a distance from the trench, a gate insulating layer formed on an inner wall of the trench, a gate electrode embedded in the trench with the gate insulating layer sandwiched therebetween, a first conductivity type source region formed on a side of the trench in a surface layer portion of the first main surface, a second conductivity type body region formed in a region on the second main surface side with respect to the source region in the surface layer portion of the first main surface, a first conductivity type drift region formed in the SiC semiconductor layer in a region on the second main surface side with respect to the body region, and a gate electrode formed along the second trench in the surface layer portion of the first main surface, the gate electrode having a capacitance of 1.0×10 20 cm -3 and a second conductivity type contact region having the following second conductivity type impurity concentration:

[0664] [F2] The SiC semiconductor device according to F1, further including a deep well region of a second conductivity type formed along the second trench so as to cover the contact region in a surface portion of the first main surface.

[0665] [F3] The SiC semiconductor device according to F2, wherein the deep well region has a second conductivity type impurity concentration that is lower than the second conductivity type impurity concentration of the contact region.

[0666] [F4] The SiC semiconductor device according to any one of F1 to F3, wherein the second trench is deeper than the first trench.

[0667] a gate electrode embedded in the trench with the gate insulating layer sandwiched between it and the source region; a first conductivity type source region formed on a side of the trench in a surface layer portion of the first surface; a second conductivity type body region formed in a region on the second main surface side of the source region in a surface layer portion of the first main surface; a first conductivity type drift region formed in a region on the second main surface side of the body region in the SiC semiconductor layer; and a second conductivity type contact region formed along the second trench in the surface layer portion of the first main surface, the contact region containing first conductivity type impurities and second conductivity type impurities, wherein the second conductivity type impurities are offset by the first conductivity type impurities.

[0668] [G2] The SiC semiconductor device described in G1, wherein the contact region includes a surface region located in a region on the first main surface side relative to the bottom of the source region, and a bottom region located in a region on the second main surface side of the SiC semiconductor layer relative to the bottom of the source region.

[0669] [G3] The SiC semiconductor device according to G2, wherein the surface region of the contact region has a portion of the second conductivity type impurities offset and compensated by the first conductivity type impurities.

[0670] [G4] The SiC semiconductor device according to G2 or G3, wherein the bottom region of the contact region does not contain first conductivity type impurities.

[0671] [G5] The SiC semiconductor device according to any one of G1 to G4, further including a deep well region of a second conductivity type formed along the second trench so as to cover the contact region in a surface portion of the first main surface.

[0672] [G6] The SiC semiconductor device according to G5, wherein the deep well region has a second conductivity type impurity concentration that is less than the second conductivity type impurity concentration of the contact region.

[0673] [G7] The SiC semiconductor device according to any one of G1 to G6, wherein the second trench is deeper than the first trench.

[0674] a gate electrode embedded in the trench with the gate insulating layer sandwiched between the source region and the body region; a first conductivity type source region formed on a side of the trench in a surface layer portion of the first surface; a second conductivity type body region formed in a region of the SiC semiconductor layer on the second main surface side with respect to the body region; a second conductivity type contact region formed along the second trench in a surface layer portion of the first main surface; and an electrode layer formed on the first main surface, the electrode layer forming an ohmic contact with the source region and forming a Schottky junction with the contact region.

[0675] [H2] The SiC semiconductor device according to H1, further including a deep well region of a second conductivity type formed along the second trench so as to cover the contact region in a surface layer portion of the first main surface.

[0676] [H3] The SiC semiconductor device according to H2, wherein the deep well region has a second conductivity type impurity concentration that is less than the second conductivity type impurity concentration of the contact region.

[0677] [H4] The SiC semiconductor device according to any one of H1 to H3, wherein the second trench is deeper than the first trench.

[0678] This application corresponds to Japanese Patent Application No. 2018-148646 filed with the Japan Patent Office on August 7, 2018, the entire disclosure of which is incorporated herein by reference. Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these specific examples, and the scope of the present invention is limited only by the appended claims. [Explanation of symbols]

[0679] DESCRIPTION OF SYMBOLS 1...SiC semiconductor device, 2...SiC semiconductor layer, 3...first main surface, 4...second main surface, 6...active region, 7...outer region, 25...drift region, 31...body region, 32...gate trench (trench), 37...gate insulating layer, 38...gate electrode layer (gate electrode), 41...source region, 42...contact region, 45...diode region, 61...SiC semiconductor device, 62...SiC semiconductor device, 67...source electrode layer, 63...source trench (second trench), 71...SiC semiconductor device, 72...SiC semiconductor device, 75...SiC semiconductor device, 85...SiC semiconductor Device, 101...SiC semiconductor device, 102...SiC semiconductor layer, 103...first main surface, 104...second main surface, 106...active region, 107...outer region, 127...drift region, 131...body region, 132...gate trench (trench), 138...gate insulating layer, 139...gate electrode layer (gate electrode), 145...source trench (second trench), 147...source electrode layer, 153...source region, 154...contact region, 171...diode region, 211...SiC semiconductor device, 221...SiC semiconductor device, 231...SiC semiconductor device, θ...off angle

Claims

1. a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side, the SiC semiconductor layer including an active region and an outer region outside the active region; a trench formed in the first main surface in the active region; a gate insulating layer formed on an inner wall of the trench; a gate electrode embedded in the trench with the gate insulating layer sandwiched between the trench and the source region; a first conductivity type source region formed in a surface layer portion of the first main surface in the active region and located on a side of the trench; a second conductivity type body region formed in a surface layer portion of the first main surface in the active region and located in a region on the second main surface side with respect to the source region; a first conductivity type drift region formed in a surface layer portion of the first main surface in the active region and the outer region, the first conductivity type drift region including a portion located in a region on the second main surface side with respect to the body region; ２０ cm －３ and a second conductivity type contact region having the following second conductivity type impurity concentration:

2. The second conductivity type impurity concentration in the contact region is 1.0×10 １７ cm －３ The SiC semiconductor device according to claim 1 .

3. The second conductivity type impurity concentration in the contact region is 1.0×10 ２０ cm －３ The SiC semiconductor device according to claim 1 or 2, wherein the SiC semiconductor device has a thickness of less than 100 μm.

4. The impurity region is 1.0×10 ２０ cm －３ The SiC semiconductor device according to any one of claims 1 to 3, having the following second conductivity type impurity concentration:

5. The impurity region is 1.0×10 １７ cm －３ 5. The SiC semiconductor device according to claim 4, wherein the SiC semiconductor device has a second conductivity type impurity concentration of at least 1000 .mu.m.sup.- ...

6. The impurity region is 1.0×10 ２０ cm －３ The SiC semiconductor device according to any one of claims 1 to 3, wherein the SiC semiconductor device has a second conductivity type impurity concentration exceeding

7. The impurity region is 1.0×10 ２１ cm －３ 7. The SiC semiconductor device according to claim 6, having the following second conductivity type impurity concentration:

8. 4. The SiC semiconductor device according to claim 1, wherein the impurity region has the same second conductivity type impurity concentration as that of the contact region.

9. 9. The SiC semiconductor device according to claim 1, wherein the impurity region has a thickness equal to a thickness of the contact region.

10. 10. The SiC semiconductor device according to claim 1, wherein the impurity region extends in a strip shape along the active region.

11. 11. The SiC semiconductor device according to claim 1, wherein the impurity region surrounds the active region.

12. The SiC semiconductor device according to any one of claims 1 to 11, further comprising an electrode layer formed on the first main surface, forming an ohmic contact with the source region, and forming a Schottky junction with the contact region.

13. 2. The SiC semiconductor device according to claim 1, further comprising an electrode layer formed on the first main surface, forming an ohmic contact with the source region, forming a Schottky junction with the contact region, and forming an ohmic contact with the impurity region.

14. 2. The SiC semiconductor device according to claim 1, further comprising an electrode layer formed on the first main surface, forming an ohmic contact with the source region, forming a Schottky junction with the contact region, and forming a Schottky junction with the impurity region.

15. The SiC semiconductor device according to any one of claims 1 to 14, wherein the SiC semiconductor layer includes a SiC single crystal made of a hexagonal system.

16. 16. The SiC semiconductor device according to claim 15, wherein the SiC semiconductor layer includes 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, or 6H-SiC single crystal.

17. 17. The SiC semiconductor device according to claim 15, wherein the first main surface faces a c-plane of the SiC single crystal.

18. The SiC semiconductor device according to any one of claims 15 to 17, wherein the trench has a sidewall facing an m-plane of the SiC single crystal, a sidewall facing an a-plane of the SiC single crystal, and a bottom wall facing a c-plane of the SiC single crystal.

19. 19. The SiC semiconductor device according to claim 18, wherein the source region is exposed from a sidewall of the trench facing an a-plane of the SiC single crystal, and the body region is exposed from a sidewall of the trench facing an a-plane of the SiC single crystal.

20. 20. The SiC semiconductor device according to claim 15, wherein the first main surface has an off-angle inclined at an angle of 0° or more and 10° or less with respect to a c-plane of the SiC single crystal.

21. The SiC semiconductor device according to claim 20 , wherein the off angle is an angle of 5° or less.

22. 22. The SiC semiconductor device according to claim 20, wherein the off angle is greater than 0° and less than 4°.

23. The SiC semiconductor device according to any one of claims 1 to 22, further comprising a second trench formed in the first main surface at a distance from the trench in the active region, the contact region being formed on a side of the second trench.

24. The SiC semiconductor device of claim 23 , further comprising a source electrode layer buried in the second trench.

25. The SiC semiconductor device according to claim 23 or 24, wherein the contact region is exposed from a sidewall of the second trench.

26. The SiC semiconductor device according to any one of claims 23 to 25, wherein the contact region is exposed from a sidewall and a bottom wall of the second trench.

27. The SiC semiconductor device according to any one of claims 23 to 26, wherein the trenches are formed in a lattice pattern in a planar view, and the second trenches are formed in a region surrounded by the trenches in a planar view.

28. The SiC semiconductor device according to any one of claims 23 to 27, wherein the trench extends in a band shape in a planar view, and the second trench extends in a band shape along the trench in a planar view.

29. The SiC semiconductor device according to any one of claims 23 to 28, wherein the second trench is deeper than the first trench.

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