Semiconductor element
The semiconductor device addresses stress-related issues in nitride semiconductor devices by using a buried layer with a lower thermal expansion coefficient or voids in the dummy gate trench, enhancing reliability and performance stability.
Patent Information
- Application Number
- JP2024071057
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-04-25
- Publication Date
- 2025-11-07
AI Technical Summary
Filling the dummy gate trench in nitride semiconductor devices with metal generates stress due to thermal expansion, leading to cracks, defects, and fluctuations in device characteristics, particularly in GaN devices.
A semiconductor device design that includes a dummy gate trench with a buried layer having a smaller thermal expansion coefficient than the dummy gate electrode, or leaving the dummy gate trench void, to mitigate stress and piezoelectric charge generation.
Reduces stress in the dummy gate trench, suppressing cracks and defects, and stabilizing device performance by minimizing thermal expansion-induced strain and piezoelectric charge effects.
Smart Images
Figure 2025166885000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to semiconductor devices. [Background technology]
[0002] In a semiconductor device having a gate trench structure, a structure is known in which a dummy gate trench is formed near the gate trench, a dummy gate insulating film is formed on the bottom and side surfaces of the dummy gate trench, and a dummy gate electrode is formed to fill the dummy gate trench via the dummy gate insulating film (see Patent Document 1). By providing such a dummy gate trench structure, it is possible to suppress breakdown of the gate trench when a high voltage is applied. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-179373 Summary of the Invention [Problem to be solved by the invention]
[0004] However, in the case of nitride semiconductors, particularly GaN, the inventors have found through their research that filling the inside of the dummy gate trench with metal as in Patent Document 1 generates stress in the dummy gate trench during temperature changes, resulting in various problems. For example, they have found that cracks and defects occur in the semiconductor layer, and polarization charges caused by stress cause fluctuations in device characteristics, current leakage, reduced reliability, and other degradation of device performance.
[0005] The present invention has been made in view of the above background, and aims to provide a semiconductor device in which stress generated in a dummy gate trench is suppressed. [Means for solving the problem]
[0006] One aspect of the present invention is a substrate that is a semiconductor of a first conductivity type; a first semiconductor layer provided on a substrate and made of a first conductivity type nitride semiconductor; a second semiconductor layer located on the first semiconductor layer and made of a second conductivity type nitride semiconductor; a third semiconductor layer of the first conductivity type located on the second semiconductor layer; a gate trench that penetrates the third semiconductor layer and the second semiconductor layer and reaches the first semiconductor layer; a gate insulating film provided in a film shape along the bottom surface and side surfaces of the gate trench; a gate electrode provided in the form of a film along the bottom and side surfaces of the gate trench via the gate insulating film; a dummy gate trench that is provided at a distance from the gate trench, penetrates the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer, and is deeper than the gate trench; a dummy gate insulating film provided in a film shape along the bottom surface and side surface of the dummy gate trench; a dummy gate electrode provided in a film shape along the bottom surface and side surface of the dummy gate trench via the dummy gate insulating film; a buried layer made of a material having a smaller thermal expansion coefficient than the dummy gate electrode, provided on the dummy gate electrode, and filling the inside of the dummy gate trench.
[0007] Another aspect of the present invention is a substrate that is a semiconductor of a first conductivity type; a first semiconductor layer provided on a substrate and made of a first conductivity type nitride semiconductor; a second semiconductor layer located on the first semiconductor layer and made of a second conductivity type nitride semiconductor; a third semiconductor layer of the first conductivity type located on the second semiconductor layer; a gate trench that penetrates the third semiconductor layer and the second semiconductor layer and reaches the first semiconductor layer; a gate insulating film provided in a film shape along the bottom surface and side surfaces of the gate trench; a gate electrode provided in the form of a film along the bottom and side surfaces of the gate trench via the gate insulating film; a dummy gate trench provided at a distance from the gate trench, passing through the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer; a dummy gate insulating film provided in a film shape along the bottom surface and side surface of the dummy gate trench; a dummy gate electrode provided in a film shape along the bottom surface and side surface of the dummy gate trench via the dummy gate insulating film, In the semiconductor device, the inner bottom surface of the dummy gate trench is not filled and a void is formed. [Effects of the Invention]
[0008] In the above embodiment, the interior of the dummy gate trench is filled with a material having a smaller thermal expansion coefficient than the dummy gate electrode via the dummy gate electrode. Alternatively, the interior of the dummy gate trench is not filled, but a void is formed. This reduces stress generated in the dummy gate trench due to the difference in thermal expansion coefficients during temperature changes. As a result, cracks and defects in the semiconductor layer can be suppressed. Furthermore, the generation of piezoelectric charges due to stress can be suppressed, thereby suppressing degradation of device performance.
[0009] As described above, in the above aspect, it is possible to provide a semiconductor element in which stress generated in the dummy gate trench is suppressed. [Brief explanation of the drawings]
[0010] [Figure 1] 1 is a cross-sectional view showing the configuration of a semiconductor element according to Embodiment 1, taken along a plane perpendicular to the main surface of a substrate. [Figure 2] FIG. 1 is a diagram showing a planar pattern of a trench. [Figure 3] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 4] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 5]2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 6] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 7] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 8] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 9] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 10] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 11] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 12] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor element according to a second embodiment, taken along a plane perpendicular to the main surface of the substrate. [Figure 13] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor element according to a third embodiment, taken along a plane perpendicular to the main surface of the substrate. DETAILED DESCRIPTION OF THE INVENTION
[0011] The first semiconductor element includes a substrate that is a semiconductor of a first conductivity type, a first semiconductor layer that is provided on the substrate and is a nitride semiconductor of the first conductivity type, a second semiconductor layer that is located on the first semiconductor layer and is a nitride semiconductor of a second conductivity type, a third semiconductor layer that is located on the second semiconductor layer and is of the first conductivity type, a gate trench that passes through the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer, a gate insulating film that is provided in the form of a film along the bottom and side surfaces of the gate trench, and a gate electrode that is provided in the form of a film along the bottom and side surfaces of the gate trench via the gate insulating film. a dummy gate trench provided at a distance from the gate trench, penetrating the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer and being deeper than the gate trench; a dummy gate insulating film provided in the form of a film along the bottom and side surfaces of the dummy gate trench; a dummy gate electrode provided in the form of a film along the bottom and side surfaces of the dummy gate trench with the dummy gate insulating film interposed therebetween; and a buried layer made of a material having a smaller thermal expansion coefficient than the dummy gate electrode, provided on the dummy gate electrode, and filling the inside of the dummy gate trench.
[0012] In the first semiconductor element, the buried layer may have voids, which can further reduce stress generated in the dummy gate trench.
[0013] In the first semiconductor element, the buried layer may be formed to a position higher than the second semiconductor layer, thereby further reducing stress generated in the dummy gate trench.
[0014] In the first semiconductor element, the width of the dummy gate trench may be 0.5 to 3 μm.
[0015] the second semiconductor element has a substrate which is a semiconductor of a first conductivity type, a first semiconductor layer which is provided on the substrate and is a nitride semiconductor of the first conductivity type, a second semiconductor layer which is located on the first semiconductor layer and is a nitride semiconductor of a second conductivity type, a third semiconductor layer which is located on the second semiconductor layer and is of the first conductivity type, a gate trench which passes through the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer, a gate insulating film which is provided in the form of a film along a bottom surface and side surfaces of the gate trench, a gate electrode which is provided in the form of a film along the bottom surface and side surfaces of the gate trench via the gate insulating film, a dummy gate trench which is provided at a distance from the gate trench and passes through the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer, a dummy gate insulating film which is provided in the form of a film along the bottom surface and side surfaces of the dummy gate trench, and a dummy gate electrode which is provided in the form of a film along the bottom surface and side surfaces of the dummy gate trench via the dummy gate insulating film, and
[0016] In the second semiconductor element, the void may be formed up to a position higher than the second semiconductor layer, which can further reduce stress generated in the dummy gate trench.
[0017] In the second semiconductor element, the width of the dummy gate trench may be 0.5 to 1.5 μm.
[0018] The first and second semiconductor elements may further have a recess spaced apart from the gate trench, penetrating the third semiconductor layer and reaching the second semiconductor layer, and the dummy gate trench may be formed inside the recess in a planar view.
[0019] (Embodiment 1) 1. Structure of semiconductor elements FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to embodiment 1, taken perpendicular to the main surface of a substrate. The semiconductor device according to embodiment 1 is a MISFET having a gate trench structure and a dummy gate trench structure. By providing the dummy gate trench structure near the gate trench structure, it is possible to suppress breakdown of the gate trench structure when a high drain voltage is applied. Furthermore, the semiconductor device according to embodiment 1 has a structure in which, in a plan view, regular hexagonal unit cells are arranged in a honeycomb pattern, and the unit cells are connected in parallel.
[0020] 1, the semiconductor device of the first embodiment includes a substrate 10, a drift layer 11, a p-type layer 12, an n-type layer 13, a gate trench T1, a dummy gate trench T2, a recess T3, a gate insulating film 14, a dummy gate insulating film 15, a gate electrode GM1, a dummy gate electrode GM2, a source electrode SM, a drain electrode DM, a wiring electrode M, a buried layer 16, a void 17, and an interlayer insulating film 18. The gate trench T1, the gate insulating film 14, and the gate electrode GM1 form a gate trench structure. The dummy gate trench T2, the dummy gate insulating film 15, and the dummy gate electrode GM2 form a dummy gate trench structure. Both the gate trench structure and the dummy gate trench structure are MIS structures.
[0021] The substrate 10 is a Si-doped n-type semiconductor having a c-plane as its principal surface. + The substrate 10 is made of GaN. The Si concentration is 1×10 18 / cm 3 That's all. The material of the substrate 10 may be other than GaN, and any material can be used as long as it is conductive and can grow a nitride semiconductor. For example, Si, SiC, ZnO, etc. can be used. However, it is preferable to use a nitride semiconductor, particularly GaN as in the first embodiment.
[0022] The drift layer 11 is provided on the substrate 10. The drift layer 11 is a Si-doped n -The drift layer 11 is made of GaN. The thickness of the drift layer 11 is 8 to 15 μm for a device with a breakdown voltage of 600 V or more, and 0.5 to 3 μm for a device with a low breakdown voltage of 100 V or less. The Si concentration of the drift layer 11 is 1×10 15 ~5×10 16 / cm 3 is.
[0023] The p-type layer 12 is provided on the drift layer 11. The p-type layer 12 is made of Mg-doped p-GaN. The thickness of the p-type layer 12 is 0.3 to 1.5 μm. The Mg concentration of the p-type layer 12 is 1×10 18 ~2×10 19 / cm 3 Preferably, 1 × 10 18 ~6×10 18 / cm 3 is.
[0024] The n-type layer 13 is provided on the p-type layer 12. The n-type layer 13 is a Si-doped n + The n-type layer 13 is made of GaN. The thickness of the n-type layer 13 is 0.1 to 0.5 μm. The Si concentration of the n-type layer 13 is 1×10 18 ~5×10 19 / cm 3 is.
[0025] The interlayer insulating film 18 is provided on the gate insulating film 14, the gate electrode GM1, the n-type layer 13, and the p-type layer 12 at the bottom of the recess T3. The interlayer insulating film 18 is made of, for example, SiO2.
[0026] A gate trench T1 and a recess T3 are provided in predetermined regions on the surface of the n-type layer 13. A dummy gate trench T2 is provided in a predetermined region on the interlayer insulating film .
[0027] FIG. 2 is a diagram showing the planar patterns of the gate trench T1, the dummy gate trench T2, and the recess T3. As shown in FIG. 2, the planar pattern of the recess T3 is a pattern in which regular hexagons are arranged in a honeycomb shape. The planar pattern of the gate trench T1 is a honeycomb pattern provided between the regular hexagons of the recess T3. The planar pattern of the dummy gate trench T2 is a regular hexagonal pattern contained within the regular hexagon of the recess T3 and concentric with the regular hexagon of the recess T3. In the first embodiment, the element area per unit cell increases due to the provision of the dummy gate trench T2. However, by forming the dummy gate trench T2 within the recess T3 in a planar view, the increase in the element area per unit cell can be suppressed. The sides of the regular hexagons of the recess T3 and the dummy gate trench T2 preferably coincide with the m-plane of the GaN.
[0028] In the first embodiment, the pattern of the unit cell is not limited to a regular hexagon, and the planar patterns of the gate trenches T1, dummy gate trenches T2, and recesses T3 are not limited to those described above. They may be striped, square lattice, or other patterns.
[0029] The gate trench T1 is a recess that penetrates the n-type layer 13 and the p-type layer 12 and reaches the drift layer 11. The drift layer 11 is exposed at the bottom of the gate trench T1. The drift layer 11, the p-type layer 12, and the n-type layer 13 are exposed at the side of the gate trench T1, in that order from the bottom side. The p-type layer 12 exposed at the side of the gate trench T1 acts as a channel.
[0030] The dummy gate trench T2 is a recess that penetrates the interlayer insulating film 18, the n-type layer 13, and the p-type layer 12 and reaches the drift layer 11. The depth of the dummy gate trench T2 is deeper than the gate trench T1. In other words, the height from the surface of the substrate 10 to the bottom of the dummy gate trench T2 is smaller than the height from the surface of the substrate 10 to the bottom of the gate trench T1. By making the dummy gate trench T2 deeper than the gate trench T1 in this way, the electric field at the corners of the gate trench T1 can be alleviated. For example, the dummy gate trench T2 is preferably 0.5 to 2 μm deeper than the gate trench T1.
[0031] The width of the dummy gate trench T2 is preferably 0.5 to 3 μm. By setting the width of the dummy gate trench T2 in this range, voids 17 are easily formed in the buried layer 16. The width is preferably 1 to 3 μm.
[0032] The recess T3 is a recess that penetrates the n-type layer 13 and has a depth that reaches the p-type layer 12. The recess T3 is provided to bring the source electrode SM into contact with the p-type layer 12.
[0033] The gate insulating film 14 is provided continuously in the form of a film along the bottom, side, and top surface (on the n-type layer 13 near the gate trench T1) of the gate trench T1. The gate insulating film 14 is made of a material such as SiO2, SiN, SiON, or Al2O3, and has a thickness of, for example, 50 nm.
[0034] The gate electrode GM1 is provided in the form of a continuous film along the bottom, side, and top surfaces of the gate trench T1, with a gate insulating film 14 interposed therebetween. The gate electrode GM1 is made of a material such as TiN and has a thickness of, for example, 600 nm. An interlayer insulating film 18 is provided on the gate electrode GM1.
[0035] The source electrode SM is continuously formed on the p-type layer 12 exposed at the bottom of the recess T3 and on the n-type layer 13. The source electrode SM may be formed of, for example, Ti / Al, Ti / Al / Ti, V / Al / Ti, or Pd / Al / Ti. The source electrode SM may also be formed of a first layer formed on the p-type layer 12 and a second layer formed on the n-type layer 13 and continuously on the first layer. By using different materials for the first and second layers, the contact with the p-type layer 12 and the contact with the n-type layer 13 can be optimized, respectively. In this case, it is recommended to use Pd or Ni as the material for the first layer and Ti / Al as the material for the second layer.
[0036] The drain electrode DM is provided over the entire rear surface of the substrate 10. The material of the drain electrode DM is, for example, Ti / Al, Ti / Al / Ti, V / Al / Ti, or Pd / Al / Ti.
[0037] The dummy gate insulating film 15 is provided continuously in the form of a film along the bottom, side, and top surfaces of the dummy gate trench T2 (on the interlayer insulating film 18 near the dummy gate trench T2). In the first embodiment, the electric field applied to the corners of the gate trench T1 is alleviated by providing the dummy gate trench structure near the gate trench structure, and therefore a strong electric field is applied to the corners of the dummy gate trench T2. For this reason, the dummy gate trench structure is an MIS structure with high breakdown voltage.
[0038] To obtain an MIS structure with a high breakdown voltage, the dummy gate insulating film 15 may be made thicker than the gate insulating film 14. For example, the thickness of the dummy gate insulating film 15 may be set to 2 to 10 times that of the gate insulating film 14. Alternatively, the dummy gate insulating film 15 may be made of a material having a higher critical electric field than the gate insulating film 14. For example, Al2O3, SiO2 / Al2O3, or the like may be preferably used as the material for the dummy gate insulating film 15. Furthermore, using SiN or Al2O3, which has a higher dielectric constant than SiO2, is preferable because the electric field in the insulating film is lowered and the insulating film is less likely to be broken down.
[0039] In the first embodiment, the n-type layer 13 is removed and the p-type layer 12 is exposed in the region from the region where the source electrode SM is provided to the dummy gate trench T2, but the n-type layer 13 may be left.
[0040] Further, the dummy gate insulating film 15 is located on the p-type layer 12 near the dummy gate trench T2 via the interlayer insulating film 18, but may be located directly on the p-type layer 12 without forming the interlayer insulating film 18. However, providing the interlayer insulating film 18 makes it easier to form voids 17, which will be described later.
[0041] The dummy gate electrode GM2 is provided in the form of a continuous film along the bottom, side, and top surfaces of the dummy gate trench T2 via the dummy gate insulating film 15, and is also provided continuously on the source electrode SM at the bottom of the recess T3. By connecting the dummy gate electrode GM2 to the source electrode SM, the potential of the dummy gate electrode GM2 is stabilized. The material of the dummy gate electrode GM2 is a metal such as TiN, and may be the same material as the gate electrode GM1. The dummy gate electrode GM2 is formed so as not to fill the dummy gate trench T2. For example, the dummy gate electrode GM2 is formed to a thickness of 100 to 600 nm.
[0042] The buried layer 16 is provided on the dummy gate electrode GM2 in the dummy gate trench T2 and is provided so as to fill the interior of the dummy gate trench T2 via the dummy gate electrode GM2. The material of the buried layer 16 is a material with a smaller thermal expansion coefficient than the dummy gate electrode GM2, such as a nonmetallic material such as polysilicon or SiO2. Using n-type polysilicon for the buried layer 16 can reduce the electrical resistance to the dummy gate electrode GM2. However, during the heating process, when Si and Ti react, silicide is formed, which reduces the volume and generates stress. Therefore, when polysilicon is used as the material for the buried layer 16, it is preferable to have voids 17. This can suppress the application of stress.
[0043] The difference in thermal expansion coefficient between the buried layer 16 and the semiconductor layer is smaller than the difference in thermal expansion coefficient between the dummy gate electrode GM2 and the semiconductor layer. Therefore, when the inside of the dummy gate trench T2 is filled with the buried layer 16, strain due to the difference in thermal expansion coefficient can be reduced more than when the inside of the dummy gate trench T2 is filled with the dummy gate electrode GM2. In the case of GaN, when stress occurs, unintended piezoelectric charges are generated, resulting in characteristic fluctuations and deterioration. In the structure of embodiment 1, the difference in thermal expansion coefficient is small, so that it is possible to reduce stress generated in the dummy gate trench T2 due to temperature changes such as those during the heating process when forming the semiconductor device and the temperature during device operation, and to suppress the generation of piezoelectric charges.
[0044] The buried layer 16 has a void 17, i.e., a space where air is trapped. As will be described later, the void 17 is formed by not filling the buried layer 16 sufficiently when forming the buried layer 16, and is located approximately at the center of the dummy gate trench T2 in plan view. By providing the void 17, the strain caused by the difference in thermal expansion coefficient can be absorbed by the void 17. Therefore, the stress generated in the dummy gate trench T2 can be further reduced.
[0045] The void 17 may be formed by being surrounded by the buried layer 16 and the wiring electrode M as shown in FIG. 1, or may be formed by being surrounded by the buried layer 16 only.
[0046] The buried layer 16 does not need to fill the entire inside of the dummy gate trench T2, but only needs to be filled to an extent that can reduce the stress generated in the dummy gate trench T2 compared to when the entire inside of the dummy gate trench T2 is filled with the dummy gate electrode GM2. However, the height of the buried layer 16 (the height from the surface of the dummy gate electrode GM2 to the bottom surface of the dummy gate trench T2) is set to, for example, a height equal to or higher than the top surface of the p-type layer 12. This can reduce the stress applied from the dummy gate trench T2 to the p-type layer 12 and the drift layer 11 made of GaN.
[0047] Furthermore, it is more preferable that the height of the buried layer 16 is equal to or higher than the upper surface of the n-type layer 13. This can further reduce the stress generated in the dummy gate trench T2. The recess T3 is formed near the dummy gate trench T2 so as not to contact the n-type layer 13, and when the n-type layer 13 is close to the dummy gate trench T2, the stress applied from the dummy gate trench T2 to the n-type layer 13 made of GaN can be further reduced.
[0048] The wiring electrode M is provided on the interlayer insulating film 18 and the dummy gate electrode GM2. The source electrodes SM of the unit cells are connected in parallel by the wiring electrode M. The wiring electrode M is also provided so as not to fill the voids 17 in the buried layer 16.
[0049] As described above, in the semiconductor element according to the first embodiment, the inside of the dummy gate trench T2 is filled with the buried layer 16 via the dummy gate insulating film 15 and the dummy gate electrode GM2. Therefore, the difference in thermal expansion coefficient between the dummy gate trench T2 and the semiconductor layers (drift layer 11, p-type layer 12, n-type layer 13) is smaller than when the inside of the dummy gate trench T2 is filled with the dummy gate electrode GM2 via the dummy gate insulating film 15. As a result, strain caused by the difference in thermal expansion coefficient can be reduced, and stress generated in the dummy gate trench T2 can be suppressed. Furthermore, since the voids 17 can absorb the strain caused by the stress, stress can be further suppressed.
[0050] As a result of being able to suppress stress, it is possible to suppress cracks and defects in the semiconductor layer. It is also possible to suppress the generation of piezoelectric charges, which are unique to GaN and are generated by stress. As a result of being able to suppress the generation of piezoelectric charges, it is possible to suppress degradation of device performance, such as unintended characteristic fluctuations, current leakage, and reduced reliability. For example, it is possible to suppress fluctuations in threshold voltage.
[0051] 2. Manufacturing method of semiconductor element Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings.
[0052] First, drift layer 11, p-type layer 12, and n-type layer 13 are stacked on substrate 10 in this order from the substrate 10 side by MOCVD (see FIG. 3). Drift layer 11, p-type layer 12, and n-type layer 13 are formed by, for example, MOCVD.
[0053] Next, a predetermined region of the n-type layer 13 is dry-etched until the p-type layer 12 is exposed, thereby forming a recess T3 (see FIG. 4).
[0054] Next, a predetermined region of the n-type layer 13 is dry-etched until the drift layer 11 is exposed, thereby forming a gate trench T1 (see FIG. 5).
[0055] Next, a gate insulating film 14 is formed over the entire upper surface of the device. The gate insulating film 14 is formed by a method such as ALD or CVD. Thereafter, a gate electrode GM1 is formed on the gate insulating film 14. The gate electrode GM1 is formed by a method such as sputtering or vapor deposition. Next, the gate electrode GM1 is patterned to leave the gate electrode GM1 on the bottom, side, and top of the gate trench T1, and to remove other regions to expose the gate insulating film 14. Next, the gate insulating film 14 is patterned to leave the gate insulating film 14 on the bottom, side, and top of the gate trench T1, and to remove other regions. In this way, the gate insulating film 14 and the gate electrode GM1 are formed (see Figure 6).
[0056] Next, the source electrode SM is formed continuously over the region of the bottom surface of the recess T3 near the side surface, the side surface, and the surface of the n-type layer 13 (see FIG. 7). The source electrode SM is formed by evaporation or the like.
[0057] Next, the interlayer insulating film 18 is formed on the entire upper surface of the device, and a predetermined region of the interlayer insulating film 18 is dry-etched until the drift layer 11 is exposed, thereby forming a dummy gate trench T2 (see FIG. 8).
[0058] Next, a dummy gate insulating film 15 is formed on the entire upper surface of the device (see FIG. 9). The method for forming the dummy gate insulating film 15 is the same as that for the gate insulating film .
[0059] Next, a region of the dummy gate insulating film 15 above the source electrode SM is dry-etched until the source electrode SM is exposed, thereby forming a through-hole. Then, a dummy gate electrode GM2 is formed in a film shape continuously on the source electrode SM on the bottom, side, and top surfaces of the dummy gate trench T2 and the bottom surface of the through-hole (see FIG. 10).
[0060] Next, a buried layer 16 is formed over the entire upper surface of the device by a CVD method or the like. The buried layer 16 is formed so as to fill the dummy gate trench T2. Also, voids 17 are formed in the buried layer 16 inside the dummy gate trench T2.
[0061] To form the voids 17, it is preferable to narrow the width of the dummy gate trench T2. For example, it is preferable to set the width to 0.5 to 3 μm. With such a width, the insulating film grows from the upper corners of the dummy gate trench T2 so as to protrude into the inside of the dummy gate trench T2, making it difficult for the source gas to enter the interior of the dummy gate trench T2, and thus the voids 17 are formed.
[0062] Next, the buried layer 16 is removed by dry etching except for the portion inside the dummy gate trench T2, thereby forming the buried layer 16 inside the dummy gate trench T2 (see FIG. 11).
[0063] Next, wiring electrodes M having a predetermined pattern are formed on the gate electrode GM1 and the interlayer insulating film 18. In this manner, the semiconductor element according to the first embodiment shown in FIG.
[0064] (Embodiment 2) 12 is a cross-sectional view showing the configuration of a semiconductor element according to embodiment 2, taken perpendicular to the main surface of the substrate. As shown in FIG. 12, the semiconductor element according to embodiment 2 has a structure in which the voids 17 in embodiment 1 are eliminated and filled with a buried layer 16. Other than that, the semiconductor element according to embodiment 2 is the same as embodiment 1. In embodiment 2, the inside of the dummy gate trench T2 is not filled with a dummy gate electrode GM2, so that stress generated in the dummy gate trench T2 can be reduced. In embodiment 2 as well, the height of the buried layer 16 is preferably the same as in embodiment 1.
[0065] (Embodiment 3) FIG. 13 is a cross-sectional view showing the configuration of a semiconductor element according to embodiment 3, taken perpendicular to the main surface of the substrate. As shown in FIG. 13, the semiconductor element according to embodiment 3 has a structure similar to that of embodiment 1, except that the buried layer 16 is not provided and the entire interior of the dummy gate trench T2 is filled with voids 17. Other than that, the semiconductor element according to embodiment 3 is similar to embodiment 1. In embodiment 3, the entire interior of the dummy gate trench T2 is filled with voids 17, which can largely absorb strain due to differences in thermal expansion coefficients. The height of the voids 17 in embodiment 3 is preferably the same as the height of the buried layer 16 in embodiments 1 and 2. Furthermore, in embodiment 3, the width of the dummy gate trench T2 is preferably 0.5 to 1.5 μm. Within this range, it is easy to fill the entire interior of the dummy gate trench T2 with voids 17.
[0066] (Other variations) Although the first to third embodiments are directed to MISFETs, the present invention can be applied to any field effect transistor having a gate trench structure and a dummy gate trench structure, such as IGBTs and HFETs.
[0067] Furthermore, although GaN is used for the drift layer 11 and the p-type layer 12 in the first to third embodiments, any nitride semiconductor may be used. However, GaN is preferred. When the drift layer 11 and the p-type layer 12 are made of a nitride semiconductor, stress generates piezoelectric charges, resulting in characteristic fluctuations and deterioration, and therefore the dummy trench structure of the present invention functions effectively. Furthermore, the substrate 10 and the n-type layer 13 may be made of a semiconductor other than a nitride semiconductor.
[0068] Furthermore, in the first to third embodiments, the n-type and p-type may be interchanged. [Explanation of symbols]
[0069] 10: Circuit board 11: Drift layer 12:p-type layer 13:N-type layer 14: Gate insulating film 15: Dummy gate insulating film 16: Embedding layer 17: Void 18: Interlayer insulating film GM1: gate electrode GM2: dummy gate electrode SM: Source electrode DM: drain electrode M: Wiring electrode T1: Gate trench T2: Dummy gate trench T3: Recess
Claims
1. a substrate that is a semiconductor of a first conductivity type; a first semiconductor layer provided on a substrate and made of a first conductivity type nitride semiconductor; a second semiconductor layer located on the first semiconductor layer and made of a second conductivity type nitride semiconductor; a third semiconductor layer of the first conductivity type located on the second semiconductor layer; a gate trench that penetrates the third semiconductor layer and the second semiconductor layer and reaches the first semiconductor layer; a gate insulating film provided in a film shape along the bottom surface and side surfaces of the gate trench; a gate electrode provided in the form of a film along the bottom and side surfaces of the gate trench via the gate insulating film; a dummy gate trench that is provided at a distance from the gate trench, penetrates the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer, and is deeper than the gate trench; a dummy gate insulating film provided in a film shape along the bottom surface and side surface of the dummy gate trench; a dummy gate electrode provided in a film shape along the bottom surface and side surface of the dummy gate trench via the dummy gate insulating film; a buried layer made of a material having a smaller thermal expansion coefficient than the dummy gate electrode, the buried layer being provided on the dummy gate electrode and filling the inside of the dummy gate trench.
2. The semiconductor device of claim 1 , wherein the buried layer has voids.
3. 3. The semiconductor element according to claim 1, wherein the buried layer is formed to a position higher than the second semiconductor layer.
4. 3. The semiconductor device according to claim 1, wherein the width of the dummy gate trench is 0.5 to 3 μm.
5. a substrate that is a semiconductor of a first conductivity type; a first semiconductor layer provided on a substrate and made of a first conductivity type nitride semiconductor; a second semiconductor layer located on the first semiconductor layer and made of a second conductivity type nitride semiconductor; a third semiconductor layer of the first conductivity type located on the second semiconductor layer; a gate trench that penetrates the third semiconductor layer and the second semiconductor layer and reaches the first semiconductor layer; a gate insulating film provided in a film shape along the bottom surface and side surfaces of the gate trench; a gate electrode provided in the form of a film along the bottom and side surfaces of the gate trench via the gate insulating film; a dummy gate trench provided at a distance from the gate trench, passing through the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer; a dummy gate insulating film provided in a film shape along the bottom surface and side surface of the dummy gate trench; a dummy gate electrode provided in a film shape along the bottom surface and side surface of the dummy gate trench via the dummy gate insulating film, A semiconductor device, wherein a portion of the dummy gate trench near its bottom is not filled and a void is formed.
6. The semiconductor element according to claim 5 , wherein the voids are formed up to a position higher than the second semiconductor layer.
7. 7. The semiconductor device according to claim 5, wherein the width of the dummy gate trench is 0.5 to 1.5 μm.
8. a recess provided at a distance from the gate trench and penetrating the third semiconductor layer to reach the second semiconductor layer; The semiconductor element according to claim 1 , wherein the dummy gate trench is formed inside the recess in a plan view.
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Semiconductor device and manufacturing method of the same
JP2014179373A