Semiconductor device and manufacturing method for the same

Abstract

To provide a semiconductor device that can be suppressed from peeling off, and a manufacturing method for the semiconductor device.SOLUTION: A semiconductor device A10 comprises: a first lead 11; a semiconductor element 30; a junction sheet 60 intervened between the first lead 11 and the semiconductor element 30, in a first direction (z); and sealing resin 50 covering a portion of the first lead 11, the semiconductor element 30 and the junction sheet 60. The junction sheet 60 has a first surface 61 pointing to a first side z1 in the first direction (z), at least a portion of which is joined to the semiconductor element 30. The first surface 61 includes a first region 611 and a second region 612. At least a portion of the first region 611 overlaps with the semiconductor element 30 when viewed in the first direction (z). The second region 612 is larger in surface-roughness than that in the first region 611, and at least a portion thereof is in contact with the sealing resin 50.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes a support substrate, a semiconductor element, and a sealing resin. The semiconductor element is bonded by solid-state diffusion bonding via an intermediate metal layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2022-63488

[0004] [overview] If delamination occurs between the intermediate metal layer and the encapsulation resin, the semiconductor device may not function properly.

[0005] The present disclosure has been made in light of the above circumstances, and an object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that are capable of suppressing peeling.

[0006] The semiconductor device of the present disclosure comprises a first lead, a semiconductor element, a bonding sheet interposed between the first lead and the semiconductor element in a first direction, and a sealing resin covering a portion of the first lead, the semiconductor element, and the bonding sheet, wherein the bonding sheet has a first surface facing a first side in the first direction and at least a portion of which is bonded to the semiconductor element, the first surface including a first region and a second region, wherein at least a portion of the first region overlaps with the semiconductor element when viewed in the first direction, and the second region has a surface roughness greater than that of the first region and at least a portion of which is in contact with the sealing resin.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 3] FIG. 3 is a partial plan view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a bottom view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 5] FIG. 5 is a side view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a front view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a partially enlarged plan view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 12] 12 is a partially enlarged cross-sectional view taken along line XII-XII in FIG. [Figure 13] FIG. 13 is a partially enlarged cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. [Figure 14] FIG. 14 is a partially enlarged cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. [Figure 15] FIG. 15 is a partially enlarged cross-sectional view showing a first modification of the semiconductor device according to the first embodiment of the present disclosure. [Figure 16] FIG. 16 is a partial enlarged plan view showing a second modified example of the semiconductor device according to the first embodiment of the present disclosure. [Figure 17] FIG. 17 is a partially enlarged cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. [Figure 18] FIG. 18 is a partially enlarged cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 19] FIG. 19 is a partially enlarged cross-sectional view showing a semiconductor device according to a fourth embodiment of the present disclosure.

[0009] [Detailed explanation] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0010] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0011] In this disclosure, unless otherwise specified, the terms "a certain object A is formed on an object B" and "a certain object A is formed on an object B" include "a certain object A is formed directly on an object B" and "a certain object A is formed on an object B with another object interposed between the objects A and B." Similarly, the terms "a certain object A is disposed on an object B" and "a certain object A is disposed on an object B" include "a certain object A is disposed directly on an object B" and "a certain object A is disposed on an object B with another object interposed between the objects A and B," unless otherwise specified. Similarly, the term "a certain object A is located on an object B" includes "a certain object A is located on an object B in contact with the object B" and "a certain object A is located on an object B with another object interposed between the objects A and B," unless otherwise specified. Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in this disclosure, "a surface A faces (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0012] 1 to 12 show a semiconductor device according to a first embodiment of the present disclosure. The application of the semiconductor device A10 of this embodiment is not limited in any way, and it may be used in electronic devices equipped with a power conversion circuit, such as a DC-DC converter. The semiconductor device A10 includes a first lead 11, a second lead 12, a third lead 13, a fourth lead 14, a semiconductor element 30, a plurality of wires 41, 42, and 43, a bonding sheet 60, and a sealing resin 50.

[0013] FIG. 1 is a perspective view showing the semiconductor device A10. FIG. 2 is a plan view showing the semiconductor device A10. FIG. 3 is a partial plan view showing the semiconductor device A10. FIG. 4 is a bottom view showing the semiconductor device A10. FIG. 5 is a side view showing the semiconductor device A10. FIG. 6 is a front view showing the semiconductor device A10. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 3. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 3. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 3. FIG. 10 is a cross-sectional view taken along line XX in FIG. 3. FIG. 11 is a partially enlarged plan view showing the semiconductor device A10. FIG. 12 is a partially enlarged cross-sectional view taken along line XII-XII in FIG. 11.

[0014] In these figures, the first direction z, the second direction x, and the third direction y are perpendicular to each other. One side of the second direction x is the x1 side, the other side is the x2 side. One side of the third direction y is the y1 side, the other side is the y2 side. One side of the first direction z is the z1 side, the other side is the z2 side.

[0015] 1 to 4 and 6 to 11, the first lead 11 has a die pad portion 111 and a terminal portion 112. The first lead 11 is a conductive member on which the semiconductor element 30 is mounted and which forms part of a conductive path between the semiconductor element 30 and a wiring board (not shown) or the like on which the semiconductor device A10 is mounted.

[0016] The first lead 11 includes, for example, copper (Cu) or a copper alloy. The first lead 11 may also have a surface metal layer (not shown). The surface metal layer includes, for example, Ag (silver), Ni (nickel), or the like.

[0017] The die pad portion 111 has a first main surface 111A, a first back surface 111B, and a through hole 111C. The first main surface 111A faces the z1 side in the first direction z. The first back surface 111B faces the z2 side in the first direction z. The through hole 111C penetrates the die pad portion 111 in the first direction z. The shape of the through hole 111C is not limited in any way, and in the illustrated example, it is circular when viewed along the first direction z.

[0018] The terminal portion 112 is connected to the die pad portion 111 and includes a portion extending toward the x2 side in the second direction x. The die pad portion 111 and the terminal portion 112 are electrically connected to each other. A portion of the terminal portion 112 is covered with the sealing resin 50. The portion of the terminal portion 112 covered with the sealing resin 50 is bent when viewed along the third direction y. The surface of the portion of the terminal portion 112 exposed from the sealing resin 50 may be plated with, for example, tin (Sn).

[0019] As shown in FIGS. 1 to 4, 6, and 8, the second lead 12 is spaced apart from the first lead 11 and is located on the y1 side of the first lead 11 in the third direction y. The first lead 11 is electrically connected to the semiconductor element 30 via a wire 41. The second lead 12 has a wire pad portion 121 and a terminal portion 122. The wire pad portion 121 is covered with a sealing resin 50. The wire pad portion 121 may be plated with, for example, silver (Ag) or tin (Sn). The terminal portion 122 is connected to the wire pad portion 121. A portion of the terminal portion 122 is covered with the sealing resin 50, and another portion is exposed from the sealing resin 50. The terminal portion 122 extends in the second direction x, for example, parallel to the terminal portion 112. The surface of the terminal portion 122 may be plated with, for example, tin (Sn).

[0020] As shown in FIGS. 1 to 4, 6, and 9, the third lead 13 is spaced apart from the first lead 11 and the second lead 12 and is located on the y1 side of the second lead 12 in the third direction y. The third lead 13 is electrically connected to the semiconductor element 30 via a wire 42. The third lead 13 has a wire pad portion 131 and a terminal portion 132. The wire pad portion 131 is covered with a sealing resin 50. The wire pad portion 131 may be plated with, for example, silver (Ag) or tin (Sn). The terminal portion 132 is connected to the wire pad portion 131. A portion of the terminal portion 132 is covered with the sealing resin 50, and another portion is exposed from the sealing resin 50. The terminal portion 132 extends in the second direction x, for example, parallel to the terminal portions 112 and 122. The surface of the terminal portion 132 may be plated with, for example, tin (Sn).

[0021] As shown in FIGS. 1 to 4, 6, and 10, the fourth lead 14 is spaced apart from the first lead 11, the second lead 12, and the third lead 13 and is located on the y1 side of the third lead 13 in the third direction y. The fourth lead 14 is electrically connected to the semiconductor element 30 via a wire 43. The fourth lead 14 has a wire pad portion 141 and a terminal portion 142. The wire pad portion 141 is covered with a sealing resin 50. The wire pad portion 141 may be plated with, for example, silver (Ag) or tin (Sn). The terminal portion 142 is connected to the wire pad portion 141. A portion of the terminal portion 142 is covered with the sealing resin 50, and another portion is exposed from the sealing resin 50. The terminal portion 142 extends in the second direction x, for example, parallel to the terminal portions 112, 122, and 132. The surface of the terminal portion 142 may be plated with, for example, tin (Sn).

[0022] As shown in FIGS. 2, 3, and 8 to 12, the semiconductor element 30 is mounted on the first main surface 111A of the die pad portion 111. In the semiconductor device A10, the specific configuration of the semiconductor element 30 is not limited in any way. In this embodiment, the semiconductor element 30 is a switching element, for example, an n-channel, vertical-structure metal-oxide-semiconductor field-effect transistor (MOSFET). The semiconductor element 30 is not limited to a MOSFET. The semiconductor element 30 may be another transistor, such as an insulated gate bipolar transistor (IGBT). Furthermore, the semiconductor element 30 may be an LSI (large-scale integration) or a diode. The semiconductor element 30 has a semiconductor layer 35, a first electrode 31, a second electrode 32, a third electrode 33, and a fourth electrode 34. The thickness of the semiconductor element 30 in the first direction z is, for example, not less than 100 μm and not more than 1000 μm.

[0023] The semiconductor layer 35 includes a compound semiconductor substrate. The main material of the compound semiconductor substrate is silicon carbide (SiC). Alternatively, silicon (Si) may be used as the main material of the compound semiconductor substrate.

[0024] The first electrode 31 is disposed on a portion of the semiconductor layer 35 on the z1 side in the first direction z. A current corresponding to the power converted by the semiconductor element 30 flows through the first electrode 31. In this embodiment, the first electrode 31 is a source electrode.

[0025] The second electrode 32 is disposed on a portion of the semiconductor layer 35 on the z1 side in the first direction z. The second electrode 32 is located away from the first electrode 31. A voltage for driving the semiconductor element 30 is applied to the second electrode 32. In this embodiment, the third electrode 33 is a gate electrode. When viewed along the first direction z, the area of ​​the second electrode 32 is smaller than the area of ​​the first electrode 31.

[0026] The third electrode 33 is disposed on a portion of the semiconductor layer 35 on the z1 side in the first direction z. The third electrode 33 is located away from the first electrode 31 and the second electrode 32. In this embodiment, the third electrode 33 is electrically connected to the first electrode 31 and is a so-called source sense electrode. When viewed along the first direction z, the area of ​​the third electrode 33 is smaller than the area of ​​the first electrode 31. The third electrode 33 may be connected to the second electrode 32.

[0027] The fourth electrode 34 is disposed on a portion of the semiconductor layer 35 on the z2 side in the first direction z. A current corresponding to the power before being converted by the semiconductor element 30 flows through the second electrode 32. In this embodiment, the second electrode 32 is a drain electrode. The fourth electrode 34 is conductively joined to the first main surface 111A via a joining sheet 60. The fourth electrode 34 may contain a metal such as Ag (silver) or Cu (copper), and may have a plating layer containing such a metal.

[0028] The first lead 11 is electrically connected to the fourth electrode 34 of the semiconductor element 30. Therefore, the terminal 112 is the drain terminal of the semiconductor device A10. The second lead 12 is electrically connected to the first electrode 31 of the semiconductor element 30. Therefore, the terminal 122 is the source terminal of the semiconductor device A10. The third lead 13 is electrically connected to the second electrode 32 of the semiconductor element 30. Therefore, the terminal 132 is the gate terminal of the semiconductor device A10. The fourth lead 14 is electrically connected to the third electrode 33 of the semiconductor element 30. Therefore, the terminal 142 is the source sense terminal of the semiconductor device A10. In the illustrated example, the distance in the third direction y between the terminals 112 and 122 is greater than both the distance in the third direction y between the terminals 122 and 132 and the distance in the third direction y between the terminals 132 and 142.

[0029] The bonding sheet 60 is interposed between the first main surface 111A and the fourth electrode 34. The bonding sheet 60 is bonded to both the first main surface 111A and the fourth electrode 34. The method for bonding the bonding sheet 60 to the first main surface 111A and the fourth electrode 34 is not limited, and examples include solid-state diffusion bonding and sintering bonding. The shape of the bonding sheet 60 is not limited, and in the illustrated example, it may be rectangular.

[0030] As shown in FIGS. 11 and 12 , the bonding sheet 60 has a first surface 61, a second surface 62, and a third surface 63. The first surface 61 faces a first side z1 in the first direction z, and at least a portion of the first surface 61 is bonded to the fourth electrode 34. The second surface 62 faces a second side z2 in the first direction z, and at least a portion of the second surface 62 is bonded to the first main surface 111A. The third surface 63 is located between the first surface 61 and the second surface 62 in the first direction and faces a direction intersecting the first direction z. In the illustrated example, the bonding sheet 60 has four third surfaces 63. Two third surfaces 63 face the second direction x, and the other two third surfaces 63 face the third direction y.

[0031] The first surface 61 includes a first region 611 and a second region 612. The second region 612 has a surface roughness greater than that of the first region 611. Indices of the surface roughness of the first region 611 and the second region 612 include, for example, the arithmetic mean height (Ra), maximum peak height (Rp), maximum peak height (Rv), maximum peak height (Rz), and root mean square height (Rq) specified in ISO 25178 and JIS B 0601-2001 (ISO 13565-1). For example, when the surface roughness of the first region 611 and the second region 612 is expressed as the arithmetic mean roughness (Ra), the surface roughness of the first region 611 is less than 0.1 μm, and the surface roughness of the second region 612 is 0.1 μm or more and 5 μm or less.

[0032] At least a portion of the first region 611 overlaps with the semiconductor element 30 when viewed in the first direction z. In the illustrated example, the entire semiconductor element 30 overlaps with the first region 611 when viewed in the first direction z. In addition, in the illustrated example, the first region 611 protrudes from the semiconductor element 30 when viewed in the first direction z.

[0033] At least a portion of the second region 612 is in contact with the sealing resin 50. In the illustrated example, the second region 612 is separated from the semiconductor element 30 as viewed in the first direction z. Furthermore, the second region 612 is in contact with at least a portion of the periphery of the first surface 61 as viewed in the first direction z. In the illustrated example, the second region 612 is in contact with the entire periphery of the first surface 61 as viewed in the first direction z. In this example, the first surface 61 has a rectangular shape as viewed in the first direction z, and the second region 612 is in contact with corners of the first surface 61 as viewed in the first direction z.

[0034] The surface roughness of the second surface 62 in this example may be equal to the surface roughness of the first region 611. The surface roughness of the third surface 63 may be smaller than the surface roughness of the second region 612, for example.

[0035] The specific configuration of the bonding sheet 60 is not limited in any way, and it may be composed of a single layer or multiple layers. In the illustrated example, the bonding sheet 60 has a base layer 600, a first layer 601, a second layer 602, and a third layer 603. The base layer 600 includes a metal such as Al (aluminum), Zn (zinc), or an alloy thereof.

[0036] The first layer 601 is laminated on a first side z1 in the first direction z of the base layer 600. The first layer 601 includes a metal such as Ag (silver) or Cu (copper), or an alloy thereof. At least a portion of the first surface 61 is made up of the first layer 601. In the illustrated example, the entire first region 611 is made up of the first layer 601. Furthermore, the entire second region 612 is made up of the first layer 601. Such a configuration is preferable when the first surface 61 and the fourth electrode 34 are bonded by solid-state diffusion bonding.

[0037] The second layer 602 is laminated on the second side z2 in the first direction z of the base layer 600. The second layer 602 includes a metal such as Ag (silver) or Cu (copper) or an alloy thereof. At least a portion of the second surface 62 is formed by the second layer 602. In the illustrated example, the entire second surface 62 is formed by the second layer 602. This configuration is preferable when the second surface 62 and the first main surface 111A are bonded by solid-state diffusion bonding. In the illustrated example, the surface roughness of the second surface 62 is smaller than the surface roughness of the second region 612 and is approximately the same as the surface roughness of the first region 611.

[0038] The third layer 603 is a layer that constitutes the third surface 63. The third layer 603 includes, for example, a metal such as Ag (silver) or Cu (copper), or an alloy thereof.

[0039] The thickness of base layer 600 is, for example, 10 μm or more and 200 μm or less. The thickness of first layer 601 is, for example, 0.1 μm or more and 5 μm or less. The thickness of second layer 602 is, for example, 0.1 μm or more and 5 μm or less. The thickness of third layer 603 is, for example, 0.1 μm or more and 5 μm or less.

[0040] As shown in FIGS. 3, 8, 11, and 12, the multiple wires 41 are electrically connected to the first electrode 31 of the semiconductor element 30 and are connected to the wire pad portion 121 of the second lead 12. The specific configuration of the wires 41 is not limited, and includes configurations in which the cross-sectional shape is circular, elliptical, flattened rectangular, etc. In the illustrated example, the wires 41 have a circular cross-sectional shape. The wires 41 are connected by wedge bonding, for example. The material of the wires 41 is not limited, and includes, for example, Cu (copper), Al (aluminum), etc. In this embodiment, two wires 41 are individually connected to the first electrode 31 and the wire pad portion 121. Instead of the multiple wires 41, a member formed of, for example, a metal plate material may be used.

[0041] As shown in FIGS. 3, 9, and 11, the wire 42 is connected to the second electrode 32 of the semiconductor element 30 and the wire pad portion 131 of the third lead 13. The specific configuration of the wire 42 is not limited in any way, and includes configurations in which the cross-sectional shape is circular, elliptical, flattened rectangular, etc. The wire 42 is connected by wedge bonding, for example. The cross-sectional size of the wire 42 is smaller than the cross-sectional size of the wire 41. The material of the wire 42 is not limited in any way, and includes, for example, Cu (copper), Al (aluminum), etc.

[0042] As shown in FIGS. 3, 10, and 11, the wire 43 is connected to the third electrode 33 of the semiconductor element 30 and the wire pad portion 141 of the fourth lead 14. The specific configuration of the wire 43 is not limited in any way, and includes configurations in which the cross-sectional shape is circular, elliptical, flattened rectangular, etc. The wire 43 is connected by wedge bonding, for example. The cross-sectional size of the wire 43 is smaller than the cross-sectional size of the wire 41. The material of the wire 43 is not limited in any way, and includes, for example, Cu (copper), Al (aluminum), etc.

[0043] As shown in FIGS. 1 to 10 , the sealing resin 50 covers the semiconductor element 30, the wires 41, 42, and 43, the bonding sheet 60, and portions of the first lead 11, the second lead 12, the third lead 13, and the fourth lead 14. The sealing resin 50 has electrical insulation properties. The sealing resin 50 is made of a material containing, for example, black epoxy resin. The sealing resin 50 has a resin main surface 51, a resin back surface 52, a pair of first side surfaces 53, a pair of second side surfaces 54, a pair of openings 55, a mounting hole 56, and a recess 57.

[0044] The resin main surface 51 faces the z1 side in the first direction z. The resin back surface 52 faces the z2 side in the first direction z. A first back surface 111B of the die pad portion 111 is exposed from the resin back surface 52. The first back surface 111B and the resin back surface 52 are flush with each other.

[0045] The pair of first side surfaces 53 are spaced apart from each other in the second direction x. The pair of first side surfaces 53 are connected to the resin main surface 51 and the resin back surface 52. A terminal portion 112 of the first lead 11, a terminal portion 122 of the second lead 12, a terminal portion 132 of the third lead 13, and a terminal portion 142 of the fourth lead 14 protrude from the first side surfaces 53 facing the x2 side in the second direction x.

[0046] The pair of second side surfaces 54 are spaced apart from each other in the third direction y. The pair of second side surfaces 54 are connected to the resin main surface 51 and the resin rear surface 52.

[0047] The pair of openings 55 are positioned apart from each other in the third direction y. Each of the pair of openings 55 is recessed inward into the sealing resin 50 from the resin main surface 51 and one of the pair of second side surfaces 54. A part of the first main surface 111A of the die pad portion 111 of the first lead 11 is exposed from the pair of openings 55.

[0048] The mounting hole 56 penetrates the sealing resin 50 from the resin main surface 51 to the resin back surface 52 in the first direction z. When viewed from the first direction z, the mounting hole 56 is contained within the through hole 111C of the die pad portion 111 of the first lead 11. The inner peripheral surface of the die pad portion 111 that defines the through hole 111C is covered with the sealing resin 50. As a result, when viewed along the first direction z, the maximum dimension of the mounting hole 56 is smaller than the dimension of the through hole 111C.

[0049] The recess 57 is located between the terminal portion 112 and the terminal portion 122 in the third direction y. The recess 57 is recessed from the first side surface 53 located on the x2 side in the second direction x to the x1 side in the second direction x.

[0050] 13 and 14 show an example of a manufacturing method for the semiconductor device A10. In this manufacturing method, first, a bonding sheet 60 is prepared. The step of preparing the bonding sheet 60 includes a step of forming the second region 612. The method for forming the second region 612 is not limited in any way. The second region 612 may be formed by, for example, a blasting process, an etching process, or a beam sputtering process. In the illustrated example, the first layer 601, the second layer 602, and the third layer 603 are formed by, for example, plating the first layer 601. Next, after forming a mask layer as needed, the second region 612 is formed by, for example, a blasting process, an etching process, a beam sputtering process, or the like. Unlike this example, the first layer 601, the second layer 602, and the third layer 603 may be formed after performing, for example, a blasting process, an etching process, a beam sputtering process, or the like on the base layer 600 to form the second region 612.

[0051] The first lead 11, the second lead 12, the third lead 13, and the fourth lead 14 may be parts included in, for example, the same lead frame (not shown). As shown in Figure 13, a bonding sheet 60 is placed on the first main surface 111A of the die pad portion 111 of the first lead 11.

[0052] 14, the first main surface 111A and the fourth electrode 34 are bonded via the bonding sheet 60. The bonding method is not limited to any particular method, and may be, for example, solid-phase diffusion bonding, sintering bonding, etc. When performing solid-phase diffusion bonding, a predetermined pressure is applied to the first lead 11, the bonding sheet 60, and the semiconductor element 30, and the temperature is raised to a predetermined temperature.

[0053] Thereafter, for example, a plurality of wires 41, 42, and 43 are bonded, and a sealing resin 50 is formed, whereby the semiconductor device A10 is obtained.

[0054] Next, the operation of the semiconductor device A10 will be described.

[0055] The first surface 61 includes a first region 611 and a second region 612. At least a portion of the first region 611, which has a relatively small surface roughness, is bonded to the fourth electrode 34. This allows the semiconductor element 30 and the bonding sheet 60 to be bonded appropriately. At least a portion of the second region 612, which has a relatively large surface roughness, is in contact with the sealing resin 50. This prevents peeling between the bonding sheet 60 and the sealing resin 50.

[0056] In this embodiment, the entire fourth electrode 34 is bonded to the first region 611. This allows the semiconductor element 30 and the bonding sheet 60 to be bonded more firmly.

[0057] When viewed in the first direction z, the first region 611 protrudes from the semiconductor element 30. This has the advantage that even if the semiconductor element 30 is misaligned when placed in the first region 611, the entire fourth electrode 34 can be easily placed on the first region 611.

[0058] The second region 612 is in contact with the periphery of the first surface 61. This makes it possible to prevent peeling from the sealing resin 50 at the periphery of the bonding sheet 60. When the first surface 61 is rectangular, the configuration in which the second region 612 is in contact with the corners of the first surface 61 makes it possible to prevent peeling from the sealing resin 50 at the corners of the first surface 61.

[0059] 15 to 19 show modified examples and other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals. Furthermore, the configurations of the various parts in each modified example and each embodiment can be appropriately combined with each other as long as no technical contradiction occurs.

[0060] 15 shows a first modified example of the semiconductor device A10. In the semiconductor device A11 of this modified example, the size and arrangement of the first region 611 and the second region 612 differ from those of the above-described example. When viewed in the first direction z, the entire first region 611 overlaps with the semiconductor element 30. When viewed in the first direction z, the semiconductor element 30 (fourth electrode 34) is larger than the first region 611. When viewed in the first direction z, the semiconductor element 30 (fourth electrode 34) protrudes from the first region 611. When viewed in the first direction z, the second region 612 overlaps with the semiconductor element 30 (fourth electrode 34).

[0061] This modification can prevent peeling in the semiconductor device A11. As can be seen from this modification, a configuration may be adopted in which a portion of the second region 612 overlaps with the semiconductor element 30 (fourth electrode 34). Even if a portion of the second region 612 overlaps with the semiconductor element 30 (fourth electrode 34), the bonding sheet 60 and the semiconductor element 30 can be bonded appropriately because the first region 611 is properly secured.

[0062] 16 shows a second modified example of the semiconductor device A10. In the semiconductor device A12 of this modified example, the second region 612 is in contact with a part of the periphery of the first surface 61 and is separated from another part. The first region 611 is in contact with a part of the periphery of the first surface 61. The second region 612 is divided into multiple regions. The second region 612 is in contact with a corner of the first surface 61.

[0063] This modification can prevent peeling in the semiconductor device A12. As can be seen from this modification, the second region 612 may be configured to contact only a portion of the periphery of the first surface 61. By having the second region 612 contact the corners of the first surface 61, peeling at the corners of the first surface 61 can be prevented.

[0064] 17 shows a semiconductor device according to a second embodiment of the present disclosure. In the semiconductor device A20 of this embodiment, the second surface 62 includes a third region 621 and a fourth region 622.

[0065] The third region 621 is in contact with the first main surface 111A and is bonded to the first main surface 111A. The fourth region 622 has a surface roughness greater than that of the third region 621. The fourth region 622 is in contact with the periphery of the second surface 62. The surface roughness of the second region 612 and the fourth region 622 may be equivalent to the surface roughness of the first region 611 and the second region 612, for example.

[0066] In the illustrated example, a portion of the sealing resin 50 is interposed between the fourth region 622 and the first main surface 111A. The fourth region 622 is in contact with the sealing resin 50. For example, when the first lead 11, the semiconductor element 30, and the bonding sheet 60 are formed by solid-state diffusion bonding, if significant pressure is not applied to the portion of the bonding sheet 60 that protrudes from the semiconductor element 30, a gap may be formed between the fourth region 622 and the first main surface 111A. If the liquid resin material used to form the sealing resin 50 seeps into this gap, the illustrated configuration may result.

[0067] In this embodiment, the third surface 63 includes a fifth region 631. The fifth region 631 has a surface roughness greater than that of the first region 611 and the third region 621.

[0068] This embodiment can prevent peeling in the semiconductor device A20. By providing the fourth region 622 and the fifth region 631, peeling between the bonding sheet 60 and the sealing resin 50 can be more reliably prevented.

[0069] 18 shows a semiconductor device according to a third embodiment of the present disclosure. In a semiconductor device A30 of this embodiment, the bonding sheet 60 does not have the third layer 603 described above.

[0070] The bonding sheet 60 of this embodiment can be formed, for example, by forming plating layers that can become multiple first layers 601 and multiple second layers 602 on a material sheet that can form multiple base layers 600, forming a portion that will become the second region 612, and then cutting this material sheet.

[0071] This embodiment can prevent peeling in the semiconductor device A30. As can be understood from this embodiment, the end surface of the base layer 600 facing the second direction x or the third direction y may be configured to be in contact with the sealing resin 50.

[0072] 19 shows a semiconductor device according to a fourth embodiment of the present disclosure. A semiconductor device A40 of this embodiment differs from the above-described embodiments in the configuration of a second region 612.

[0073] In this embodiment, the second region 612 is formed by the base layer 600. In the bonding sheet 60 of this example, the second region 612 is formed by, for example, performing blasting, etching, beam sputtering, or the like on appropriate locations of the base layer 600, and the first layer 601 and the second layer 602 are formed by performing plating, or the like on areas avoiding the second region 612. The first region 611 is formed by the first layer 601.

[0074] This embodiment can prevent peeling in the semiconductor device A 40. As can be understood from this embodiment, the second region 612 may be composed of the base layer 600, the first layer 601, and the like.

[0075] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0076] [Appendix 1] First lead (11) and A semiconductor element (30); a bonding sheet (60) interposed between the first lead (11) and the semiconductor element (30) in a first direction (z); a sealing resin (50) that covers a portion of the first lead (11), the semiconductor element (30), and the bonding sheet (60); the bonding sheet (60) has a first surface (61) facing a first side (z1) in the first direction (z) and at least a portion of which is bonded to the semiconductor element (30); The first surface (61) includes a first region (611) and a second region (612), The first region (611) at least partially overlaps with the semiconductor element (30) when viewed in the first direction (z), The second region (612) has a surface roughness greater than that of the first region (611), and at least a portion of the second region (612) is in contact with the sealing resin (50). [Appendix 2] The semiconductor device (A10) according to Appendix 1, wherein the entire semiconductor element (30) overlaps with the first region (611) when viewed in the first direction (z). [Appendix 3] The semiconductor device (A10) according to appendix 1 or 2, wherein the first region (611) protrudes from the semiconductor element (30) when viewed in the first direction (z). [Appendix 4] The semiconductor device (A10) according to appendix 3, wherein the second region (612) is spaced apart from the semiconductor element (30) when viewed in the first direction (z). [Appendix 5] A semiconductor device (A10) according to any one of appendices 1 to 4, wherein, when viewed in the first direction (z), the second region (612) is in contact with at least a portion of the periphery of the first surface (61). [Appendix 6] The semiconductor device (A10) according to any one of appendices 1 to 4, wherein, when viewed in the first direction (z), the second region (612) contacts the entire periphery of the first surface (61). [Appendix 7] The first surface (61) is rectangular when viewed in the first direction (z), The semiconductor device (A10) according to Appendix 5, wherein the second region (612) is in contact with a corner of the first surface (61) when viewed in the first direction (z). [Appendix 8] The joining sheet (60) includes a base layer (600) and a first layer (601) laminated on the first side (z1) of the base layer (600) in the first direction (z), The semiconductor device (A10) according to any one of appendices 1 to 7, wherein the first region (611) is constituted by the first layer (601). [Appendix 9] The semiconductor device (A10) according to appendix 8, wherein at least a portion of the second region (612) is constituted by the first layer (601). [Appendix 10] the base layer (60) has a second surface (62) facing a second side z2 in the first direction (z) and at least a portion of which is joined to the first lead (11); the second surface (62) includes a third region (621) and a fourth region (622); The third region (621) is in contact with the first lead (11), The semiconductor device (A10) according to appendix 8 or 9, wherein the fourth region (622) has a surface roughness greater than that of the third region (621). [Appendix 11] the sealing resin (50) is interposed between the fourth region (622) and the first lead (11); The semiconductor device (A20) according to appendix 10, wherein the fourth region (622) is in contact with the sealing resin (50). [Appendix 12] The joining sheet (60) includes a second layer (602) laminated on the second side (z2) of the base material layer (600) in the first direction (z), The semiconductor device (A20) according to appendix 10 or 11, wherein the third region (621) is constituted by the second layer (602). [Appendix 13] The joining sheet (60) has a third surface (63) located between the first surface (61) and the second surface (62) in the first direction (z) and facing a direction intersecting the first direction (z), The semiconductor device (A20) according to appendix 12, wherein the third surface (63) includes a fifth region (631) having a surface roughness greater than that of the first region (611). [Appendix 14] The semiconductor device (A20) according to appendix 13, wherein the bonding sheet (60) further includes a third layer (603) that constitutes the third surface (63). [Appendix 15] providing a bonding sheet (60) having a first surface (61) and a second surface (62); a step of joining the first lead (11) and the semiconductor element (30) via the joining sheet (60); and forming a sealing resin (50) that covers the semiconductor element (30), the bonding sheet (60), and at least a portion of the first lead (11), The first surface (61) includes a first region (611) and a second region (612), The second region (612) has a surface roughness greater than that of the first region (611), In the bonding step, at least a part of the first region (611) is bonded to the semiconductor element (30), In the step of forming the sealing resin, at least a part of the second region is covered with the sealing resin. [Appendix 16] The method for manufacturing a semiconductor device (A10) according to Appendix 15, wherein in the step of preparing the bonding sheet, the second region (612) is formed by any one of blasting, etching, and beam sputtering. [Appendix 17] A method for manufacturing a semiconductor device (A10) described in Appendix 16, wherein in the step of forming the bonding sheet (60), a base material layer (600) and a first layer (601) covering one side of the previous base material layer (600) are formed, and then the second region (612) is formed. [Explanation of symbols]

[0077] A10, A11, A12, A20, A30, A40: Semiconductor device 11: First lead 12: Second lead 13: Third lead 14: 4th lead 30: Semiconductor element 31: 1st electrode 32: 2nd electrode 33:Third electrode 34: 4th electrode 35: Semiconductor layer 41, 42, 43: Wire 50: Sealing resin 51: Resin main surface 52: Resin back 53 :1st side 54:Second side 55 :Aperture 56: Mounting hole 57: Recess 60: Bonding sheet 61: 1st page 62: 2nd side 63:Side 3 111: Die pad section 111A: 1st main surface 111B: 1st back side 111C: Through hole 112:Terminal section 121: Wire pad section 122:Terminal section 131: Wire pad section 132:Terminal section 141: Wire pad section 142:Terminal section 600: Base material layer 601 :1st layer 602 :2nd layer 603: 3rd layer 611: 1st area 612:Second area 621: Third area 622: 4th area 631: 5th area x :Second direction y: third direction z: first direction

Claims

1. The first lead and A semiconductor element; a bonding sheet interposed between the first lead and the semiconductor element in a first direction; a sealing resin that covers a portion of the first lead, the semiconductor element, and the bonding sheet, the bonding sheet has a first surface facing a first side in the first direction and at least a portion of which is bonded to the semiconductor element; the first surface includes a first region and a second region; the first region at least partially overlaps with the semiconductor element when viewed in the first direction; The second region has a surface roughness greater than that of the first region, and at least a portion of the second region is in contact with the sealing resin.

2. The semiconductor device according to claim 1 , wherein the entire semiconductor element overlaps the first region when viewed in the first direction.

3. The semiconductor device according to claim 1 , wherein the first region protrudes from the semiconductor element when viewed in the first direction.

4. The semiconductor device according to claim 3 , wherein the second region is spaced apart from the semiconductor element when viewed in the first direction.

5. The semiconductor device according to claim 1 , wherein the second region is in contact with at least a portion of a periphery of the first surface when viewed in the first direction.

6. The semiconductor device according to claim 1 , wherein the second region is in contact with an entire periphery of the first surface when viewed in the first direction.

7. the first surface has a rectangular shape when viewed in the first direction, The semiconductor device according to claim 5 , wherein the second region is in contact with a corner of the first surface when viewed in the first direction.

8. the bonding sheet includes a base layer and a first layer laminated on the first side of the base layer in the first direction, 8. The semiconductor device according to claim 1, wherein said first region is formed by said first layer.

9. 9. The semiconductor device according to claim 8, wherein at least a portion of said second region is formed by said first layer.

10. the base layer has a second surface facing a second side z2 in the first direction and at least a portion of which is joined to the first lead; the second surface includes a third region and a fourth region; the third region is in contact with the first lead, The semiconductor device according to claim 8 , wherein the fourth region has a surface roughness greater than that of the third region.

11. the sealing resin is interposed between the fourth region and the first lead; The semiconductor device according to claim 10 , wherein the fourth region is in contact with the sealing resin.

12. the bonding sheet includes a second layer laminated on the second side of the base material layer in the first direction, The semiconductor device according to claim 10 , wherein the third region is formed by the second layer.

13. the bonding sheet has a third surface located between the first surface and the second surface in the first direction and facing a direction intersecting the first direction, The semiconductor device according to claim 12 , wherein said third surface includes a fifth region having a surface roughness greater than that of said first region.

14. The semiconductor device according to claim 13 , wherein the bonding sheet further includes a third layer that constitutes the third surface.

15. providing a bonding sheet having a first surface and a second surface; a step of joining a first lead and a semiconductor element via the joining sheet; forming a sealing resin that covers the semiconductor element, the bonding sheet, and at least a portion of the first lead; the first surface includes a first region and a second region; The second region has a surface roughness greater than that of the first region, In the bonding step, at least a portion of the first region and the semiconductor element are bonded to each other, In the step of forming the sealing resin, at least a portion of the second region is covered with the sealing resin.

16. The method for manufacturing a semiconductor device according to claim 15, wherein in the step of preparing the bonding sheet, the second region is formed by any one of blasting, etching, and beam sputtering.

17. 17. The method for manufacturing a semiconductor device according to claim 16, wherein in the step of forming the bonding sheet, the second region is formed after forming a first layer that covers one surface of the base material layer and the former base material layer.

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