Photoelectric conversion device and photoelectric conversion system

Abstract

To improve the reading speed of signals from pixels, in a photoelectric conversion device in which a plurality of signal output lines are arranged in each column of a pixel array part.SOLUTION: A photoelectric conversion device has: a plurality of pixels arranged to include first and second pixel groups and form a column; a plurality of signal lines including a first signal line connected to the first pixel group and a second signal line connected to the second pixel group; and a column circuit having a voltage control part controlling supply of voltage to the plurality of signal lines and a switch circuit controlling electrical connection and separation between the plurality of signal lines. The voltage control part outputs signals from the first pixel group, supplies predetermined voltage to the second signal line in a first period during which it does not output signals from the second pixel group, outputs signals from the second pixel group, and supplies predetermined voltage to the first signal line in a second period during which it does not output the signals from the first pixel group. The switch circuit separates the first signal line and the second signal line from each other in the first and second periods, and connects the first signal line and the second signal line to each other in a third period between the first period and the second period.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system. [Background technology]

[0002] Patent Document 1 describes a photoelectric conversion device configured such that the signal line used to read out signals from pixels is alternately selected from two signal output lines arranged in each column of a pixel array section. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-072534 Summary of the Invention [Problem to be solved by the invention]

[0004] However, with the technology described in Patent Document 1, the speed at which signals are read out from pixels is not necessarily sufficient, and there is a demand for an improvement in the readout speed.

[0005] An object of the present invention is to provide a technique for improving the speed at which signals are read out from pixels in a photoelectric conversion device in which a plurality of signal output lines are arranged for each column of a pixel array section. [Means for solving the problem]

[0006] According to one disclosure of the present specification, a pixel circuit includes a plurality of pixels including a first pixel group and a second pixel group arranged in a column, a plurality of signal lines including a first signal line connected to the first pixel group and a second signal line connected to the second pixel group, a voltage control unit connected to the plurality of signal lines and controlling the supply of a predetermined voltage to each of the plurality of signal lines, and a switch circuit controlling electrical connection and separation between the plurality of signal lines, wherein the voltage control unit outputs a signal from the first pixel group to the first signal line, and a photoelectric conversion device that supplies the predetermined voltage to the second signal line during a first period in which signals from two pixel groups are not output to the second signal line, outputs signals from the second pixel group to the second signal line, and supplies the predetermined voltage to the first signal line during a second period in which signals from the first pixel group are not output to the first signal line, and the switch circuit separates the first signal line and the second signal line during the first period and the second period, and connects the first signal line and the second signal line during a third period between the first period and the second period.

[0007] According to another disclosure of the present specification, there is provided a method for driving a photoelectric conversion device having a plurality of pixels arranged in a column, including a first pixel group and a second pixel group, and a plurality of signal lines, including a first signal line connected to the first pixel group and a second signal line connected to the second pixel group, wherein the method includes: during a first period in which a signal from the first pixel group is output to the first signal line and a signal from the second pixel group is not output to the second signal line, electrically separating the first signal line from the second signal line and supplying a predetermined voltage to the second signal line; during a second period in which a signal from the second pixel group is output to the second signal line and a signal from the first pixel group is not output to the first signal line, electrically separating the first signal line from the second signal line and supplying a predetermined voltage to the first signal line; and during a third period between the first period and the second period, electrically connecting the first signal line and the second signal line. [Effects of the Invention]

[0008] According to the present invention, in a photoelectric conversion device in which a plurality of signal output lines are arranged for each column of a pixel array section, it is possible to improve the speed at which signals are read out from pixels. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment. [Figure 2] 1 is a circuit diagram showing an example of the configuration of a pixel in a photoelectric conversion device according to a first embodiment. [Figure 3] 2 is a circuit diagram showing an example of the configuration of a column circuit in the photoelectric conversion device according to the first embodiment. FIG. [Figure 4] 1 is a schematic diagram illustrating an example of the configuration of a photoelectric conversion device according to a first embodiment. [Figure 5] FIG. 3 is a timing chart (part 1) showing a method for driving the photoelectric conversion device according to the first embodiment. [Figure 6] FIG. 4 is a timing chart (part 2) showing the method of driving the photoelectric conversion device according to the first embodiment. [Figure 7] FIG. 10 is a schematic diagram illustrating an example of the configuration of a photoelectric conversion device according to a second embodiment. [Figure 8] FIG. 10 is a schematic diagram illustrating an example of the configuration of a photoelectric conversion device according to a third embodiment. [Figure 9] FIG. 10 is a schematic diagram illustrating an example of the configuration of a photoelectric conversion device according to a fourth embodiment. [Figure 10] FIG. 10 is a timing chart showing a method for driving a photoelectric conversion device according to a fourth embodiment. [Figure 11] FIG. 10 is a block diagram showing a schematic configuration of a photoelectric conversion system according to a fifth embodiment. [Figure 12] FIG. 13 is a diagram illustrating an example of the configuration of a photoelectric conversion system and a moving object according to a sixth embodiment. [Figure 13] FIG. 13 is a block diagram showing a schematic configuration of a device according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, an apparatus for image capture will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to this apparatus for image capture, and can also be applied to other examples of photoelectric conversion devices. For example, there are distance measurement devices (devices for measuring distance using focus detection or TOF (Time Of Flight)), photometry devices (devices for measuring the amount of incident light, etc.), etc.

[0011] The conductivity types of the transistors described in the following embodiments are merely examples and are not limited to the conductivity types described in the embodiments. The conductivity types described in the embodiments can be changed as appropriate, and the potentials of the gate, source, and drain of the transistors are accordingly changed accordingly.

[0012] For example, in the case of a transistor operated as a switch, the low level and high level of the potential supplied to the gate may be reversed in accordance with the change in the conductivity type compared to the description in the embodiment. The conductivity types of the semiconductor regions described in the following embodiments are also merely examples and are not limited to the conductivity types described in the embodiments. The conductivity types described in the embodiments can be changed as appropriate, and the potential of the semiconductor regions is changed accordingly.

[0013] In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being connected to each other unless otherwise specified.

[0014] [First embodiment] A photoelectric conversion device and a method for driving the same according to a first embodiment of the present invention will be described with reference to FIGS.

[0015] Fig. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to this embodiment. As shown in Fig. 1, the photoelectric conversion device 100 according to this embodiment includes a pixel array section 10, a vertical scanning circuit 20, readout circuits 40A and 40B, reference signal output circuits 48A and 48B, and counter circuits 58A and 58B. The photoelectric conversion device 100 also includes horizontal scanning circuits 70A and 70B, processing circuits 80A and 80B, output circuits 82A and 82B, and a control circuit 90.

[0016] The pixel array unit 10 has a plurality of pixels 12 arranged in a matrix across a plurality of rows and a plurality of columns. Each pixel 12 includes a photoelectric conversion unit formed of a photoelectric conversion element such as a photodiode, and outputs a pixel signal corresponding to the amount of incident light. The number of rows and columns of the pixel array arranged in the pixel array unit 10 is not particularly limited. In addition to effective pixels that output pixel signals corresponding to the amount of incident light, the pixel array unit 10 may also include optical black pixels whose photoelectric conversion units are shielded from light, dummy pixels that do not output signals, and the like. The specific configuration of the pixels 12 will be described later.

[0017] Control lines 14 are arranged in each row of the pixel array section 10, extending in a first direction (the horizontal direction in FIG. 1). Each of the control lines 14 is connected to the pixels 12 aligned in the first direction and serves as a signal line common to these pixels 12. Each of the control lines 14 may include multiple signal lines. The first direction in which the control lines 14 extend may be referred to as the row direction or horizontal direction. The control lines 14 are connected to a vertical scanning circuit 20.

[0018] In each column of the pixel array section 10, a signal output line 16A or a signal output line 16B is arranged, extending in a second direction (vertical direction in FIG. 1 ) intersecting the first direction. The signal output lines 16A and 16B are arranged alternately in each column. For example, the signal output lines 16A are arranged in odd-numbered columns, and the signal output lines 16B are arranged in even-numbered columns. The signal output line 16A is connected to a readout circuit 40A. The signal output line 16B is connected to a readout circuit 40B. The signal output lines 16A and 16B do not necessarily have to be arranged in different columns, and may be arranged in the same column.

[0019] Each of the signal output lines 16 arranged in each column includes a plurality of signal lines. The pixels 12 arranged in each column are connected to one of the plurality of signal lines arranged in the corresponding column. In this embodiment, each of the signal output lines 16A and 16B includes two signal lines (signal lines 161 and 162 described below). In this case, the plurality of pixels 12 arranged in each column includes a first pixel group connected to the signal line 161 and a second pixel group connected to the signal line 162.

[0020] The vertical scanning circuit 20 has a function of generating control signals for driving the pixels 12 in response to control signals from the control circuit 90 and outputting the generated control signals to the pixel array unit 10. The vertical scanning circuit 20 may use logic circuits such as a shift register and an address decoder. The vertical scanning circuit 20 sequentially outputs control signals to the control lines 14 of each row, and performs an operation known as vertical scanning, which sequentially drives the pixels 12 of the pixel array unit 10 row by row. The signals read out from the pixels 12 row by row are input to a readout circuit 40A or a readout circuit 40B via a signal output line 16A or a signal output line 16B arranged in each column of the pixel array unit 10.

[0021] The readout circuit 40A has a plurality of column circuits 42 corresponding to the number of columns on which the signal output lines 16A are arranged. Each of the column circuits 42 of the readout circuit 40A is connected to the signal output line 16A of the corresponding column. Similarly, the readout circuit 40B has a plurality of column circuits 42 corresponding to the number of columns on which the signal output lines 16B are arranged. Each of the column circuits 42 of the readout circuit 40B is connected to the signal output line 16B of the corresponding column. The column circuits 42 are signal processing circuits that perform predetermined processing on pixel signals read out from the pixels 12 of the corresponding column. Examples of processing performed by the column circuits 42 include signal processing such as amplification and analog-to-digital conversion (AD conversion). The column circuits 42 have a signal holding circuit (memory) for holding the processed pixel signals.

[0022] The reference signal output circuit 48A is connected to the readout circuit 40A. The reference signal output circuit 48A has a function of outputting a reference signal used for AD conversion to the readout circuit 40A in response to a control signal from the control circuit 90. Similarly, the reference signal output circuit 48B is connected to the readout circuit 40B. The reference signal output circuit 48B has a function of outputting a reference signal used for AD conversion to the readout circuit 40B in response to a control signal from the control circuit 90. Note that the reference signal output circuits 48A and 48B may be configured to generate and output a reference signal, or may be configured to buffer and output a reference signal generated outside the photoelectric conversion device.

[0023] The reference signal used in AD conversion may be a signal having a predetermined amplitude according to the range of the pixel signal and whose signal level changes over time. The reference signal is not particularly limited, but for example, a ramp signal whose signal level monotonically increases or decreases over time may be applied. Note that the change in signal level does not necessarily have to be continuous, but may be step-like. Furthermore, the change in signal level does not necessarily have to be linear with respect to time, but may be curved with respect to time (for example, a sine wave or cosine wave).

[0024] The counter circuit 58A is connected to the readout circuit 40A. The counter circuit 58A performs a counting operation in response to a control signal from the control circuit 90 and has the function of outputting a count signal indicating the count value to the readout circuit 40A. The counter circuit 58A starts its counting operation in synchronization with the timing at which the signal level of the reference signal supplied from the reference signal output circuit 48A starts to change. Similarly, the counter circuit 58B is connected to the readout circuit 40B. The counter circuit 58B performs a counting operation in response to a control signal from the control circuit 90 and has the function of outputting a count signal indicating the count value to the readout circuit 40B. The counter circuit 58B starts its counting operation in synchronization with the timing at which the signal level of the reference signal supplied from the reference signal output circuit 48B starts to change. Note that the functions of the counter circuits 58A and 58B may be provided in each of the column circuits 42.

[0025] The horizontal scanning circuit 70A has a function of generating control signals for reading out pixel signals from the column circuits 42 of the readout circuit 40A in response to control signals from the control circuit 90 and outputting the generated control signals to the readout circuit 40A. The horizontal scanning circuit 70A sequentially scans the column circuits 42 of the readout circuit 40A and outputs the pixel signals held therein to the processing circuit 80A via horizontal output lines 72A, a so-called horizontal scanning operation. Similarly, the horizontal scanning circuit 70B has a function of generating control signals for reading out pixel signals from the column circuits 42 of the readout circuit 40B in response to control signals from the control circuit 90 and outputting the generated control signals to the readout circuit 40B. The horizontal scanning circuit 70B performs horizontal scanning on the column circuits 42 of the readout circuit 40B in the same manner as the horizontal scanning circuit 70A. Logic circuits such as shift registers and address decoders may be used in the horizontal scanning circuits 70A and 70B.

[0026] The processing circuit 80A is composed of a buffer amplifier, a differential amplifier, etc., and has the function of performing predetermined signal processing on pixel signals of a column selected by the horizontal scanning circuit 70A and outputting the processed pixel data to the output circuit 82A. Similarly, the processing circuit 80B is composed of a buffer amplifier, a differential amplifier, etc., and has the function of performing predetermined signal processing on pixel signals of a column selected by the horizontal scanning circuit 70B and outputting the processed pixel data to the output circuit 82B. Examples of signal processing performed by the processing circuits 80A and 80B include correction processing using correlated double sampling (CDS) and amplification processing.

[0027] The output circuit 82A has an external interface circuit and has a function of outputting image data input from the processing circuit 80A to the outside of the photoelectric conversion device 100. Similarly, the output circuit 82B has an external interface circuit and has a function of outputting image data input from the processing circuit 80B to the outside of the photoelectric conversion device 100. The external interface circuits provided in the output circuits 82A and 82B are not particularly limited. For example, a SerDes (SERializer / DESerializer) transmission circuit such as an LVDS (Low Voltage Differential Signaling) circuit or an SLVS (Scalable Low Voltage Signaling) circuit can be used as the external interface circuit.

[0028] The control circuit 90 has a function of generating control signals for controlling the operation of each of the above-mentioned functional blocks and outputting the generated control signals to these functional blocks. Note that at least some of the control signals for controlling the operation of these functional blocks may be configured to be supplied from outside the photoelectric conversion device 100.

[0029] 1 shows an example in which two readout circuit blocks are provided: a readout circuit block including a readout circuit 40A, a horizontal scanning circuit 70A, a processing circuit 80A, etc., and a readout circuit block including a readout circuit 40B, a horizontal scanning circuit 70B, a processing circuit 80B, etc. However, the number of readout circuit blocks does not necessarily have to be two, and one readout circuit block may also be provided.

[0030] 2 is a circuit diagram showing an example of the configuration of a pixel in the photoelectric conversion device according to this embodiment. Each of the pixels 12 constituting the pixel array unit 10 can be configured with a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4, for example, as shown in FIG.

[0031] The photoelectric conversion element PD is, for example, a photodiode, and has an anode connected to a ground voltage line and a cathode connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. A node FD, to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected, is a so-called floating diffusion. The floating diffusion includes a capacitance component (floating diffusion capacitance) and functions as a charge storage portion. The floating diffusion capacitance may include transistor gate capacitance, pn junction capacitance, wiring capacitance, etc. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a node to which a power supply voltage (voltage VDD) is supplied. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the signal output line 16A (or signal output line 16B).

[0032] In the pixel configuration of FIG. 2, the control line 14 for each row includes three signal lines connected to the gate of the transfer transistor M1, the gate of the reset transistor M2, and the gate of the selection transistor M4. A control signal PTX is supplied to the gate of the transfer transistor M1 from the vertical scanning circuit 20. A control signal PRES is supplied to the gate of the reset transistor M2 from the vertical scanning circuit 20. A control signal PSEL is supplied to the gate of the selection transistor M4 from the vertical scanning circuit 20. When each transistor is an N-type transistor, the corresponding transistor turns on when a high-level control signal is supplied from the vertical scanning circuit 20. On the other hand, the corresponding transistor turns off when a low-level control signal is supplied from the vertical scanning circuit 20.

[0033] In this embodiment, the description will be given assuming that electrons, among electron-hole pairs generated in the photoelectric conversion element PD by incident light, are used as signal charges. When electrons are used as signal charges, each transistor constituting the pixel 12 may be configured as an N-type transistor. However, the signal charges are not limited to electrons; holes may also be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor will be the opposite conductivity type to that described in this embodiment. Furthermore, the names of the source and drain of a MOS transistor may vary depending on the transistor's conductivity type and the focused function. Some or all of the names of the source and drain used in this embodiment may be reversed. In this specification, one of the source and drain may be referred to as a first main node, the other of the source and drain as a second main node, and the gate as a control node.

[0034] The photoelectric conversion element PD converts incident light into an electric charge in an amount corresponding to the amount of light (photoelectric conversion) and accumulates the generated electric charge. When the transfer transistor M1 is turned on, it transfers the electric charge held by the photoelectric conversion element PD to the node FD. The electric charge transferred from the photoelectric conversion element PD is held in the capacitance (floating diffusion capacitance) of the node FD. As a result, the node FD has a potential corresponding to the amount of electric charge transferred from the photoelectric conversion element PD due to charge-voltage conversion by the floating diffusion capacitance.

[0035] When the selection transistor M4 is turned on, it connects the amplification transistor M3 to the signal output line 16A (or signal output line 16B). The amplification transistor M3 is configured so that a voltage VDD is supplied to its drain and a bias current is supplied to its source from a current source (current sources 441 and 442, described below) (not shown) via the selection transistor M4. This causes the amplification transistor M3 to form an amplifier (source follower circuit) with its gate as an input node, and outputs a signal based on the potential of node FD to the signal output line 16A (or signal output line 16B) via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 form an output unit that outputs a pixel signal according to the amount of charge held at node FD.

[0036] The reset transistor M2 has a function of controlling the supply of a voltage (voltage VDD) to the FD node for resetting the node FD as a charge storage unit. When the reset transistor M2 is turned on, it resets the node FD to a voltage corresponding to the voltage VDD.

[0037] FIG. 3 is a circuit diagram showing an example of the configuration of a column circuit in a photoelectric conversion device according to this embodiment. FIG. 3 shows two of the multiple column circuits 42 that make up the readout circuit 40A. Two signal lines 161, 162 that make up the signal output line 16A of each column are connected to the column circuit 42 of the corresponding column. Each column circuit 42 may be configured, for example, as shown in FIG. 3 , with P-type transistors M51, M52, current sources 441, 442, a switch S1, comparison circuits 521, 522, and memories 621, 622, 641, 642. As described above, the current sources 441, 442 function as load current sources for the amplification transistor M3 of the pixel 12.

[0038] The source of the transistor M51 is connected to a node to which the power supply voltage (voltage VDD) is supplied. The drain of the transistor M51 is connected to a signal line 161, one terminal of the switch S1, and one terminal of the current source 441. The other terminal of the current source 441 is connected to a ground voltage node. A control signal VLRES1 is supplied to the gate of the transistor M51 from the control circuit 90. The source of the transistor M52 is connected to the node to which the power supply voltage (voltage VDD) is supplied. The drain of the transistor M52 is connected to the signal line 162, the other terminal of the switch S1, and one terminal of the current source 442. The other terminal of the current source 442 is connected to the ground voltage node. A control signal VLRES2 is supplied to the gate of the transistor M52 from the control circuit 90. A control signal is supplied to the control node of the switch S1 from the control circuit 90. The control signals VLRES1, VLRES2, and VLSHT are signals common to the column circuits 42 of each column. The voltage supplied to the sources of the transistors M51 and M52 may be a fixed voltage other than the power supply voltage.

[0039] The transistor M51 is turned off when a high-level control signal VLRES1 is supplied from the control circuit 90, and is turned on when a low-level control signal VLRES1 is supplied from the control circuit 90. Similarly, the transistor M52 is turned off when a high-level control signal VLRES2 is supplied from the control circuit 90, and is turned on when a low-level control signal VLRES2 is supplied from the control circuit 90. The transistors M51 and M52 function as a voltage control unit that controls the supply of voltage to the signal lines 161 and 162.

[0040] The switch S1 is turned on when a high-level control signal VLSHT is supplied from the control circuit 90, and is turned off when a low-level control signal VLSHT is supplied from the control circuit 90. The switch S1 serves as a switch circuit that controls electrical connection and separation between the signal lines 161 and 162.

[0041] The comparison circuit 521 has two input nodes (a non-inverting input node (+) and an inverting input node (-)) to which two signals to be compared are input, and one output node to which a signal indicating the comparison result is output, and can be configured by, for example, a differential amplifier circuit. One input node (an inverting input node) of the comparison circuit 521 is connected to a signal line 161, and a voltage VOUT1 that is an output signal of the pixel 12 is input via the signal line 161. The other input node (a non-inverting input node) of the comparison circuit 521 is connected to a reference signal line 50. A reference signal VRAMP is input to the other input node of the comparison circuit 521 from the reference signal output circuit 48A via the reference signal line 50.

[0042] Similarly, the comparison circuit 522 has two input nodes (a non-inverting input node (+) and an inverting input node (-)) to which two signals to be compared are input, and one output node to which a signal indicating the comparison result is output, and may be configured by, for example, a differential amplifier circuit. One input node (an inverting input node) of the comparison circuit 522 is connected to the signal line 162, and a voltage VOUT2 that is an output signal of the pixel 12 is input via the signal line 162. The other input node (a non-inverting input node) of the comparison circuit 522 is connected to the reference signal line 50. A reference signal VRAMP is input to the other input node of the comparison circuit 522 from the reference signal output circuit 48A via the reference signal line 50.

[0043] The memory 621 has two input nodes and one output node. The memory 641 has two input nodes and one output node. One input node of the memory 621 is connected to the output node of the comparison circuit 521. The other input node of the memory 621 is connected to the count signal line 60. A count signal COUNT is input to the other input node of the memory 621 from the counter circuit 58A via the count signal line 60. One input node of the memory 641 is connected to the output node of the memory 621. The other input node of the memory 641 is connected to the horizontal scanning circuit 70A. The output node of the memory 641 is connected to the horizontal output line 72A.

[0044] Similarly, the memory 622 has two input nodes and one output node. The memory 642 has two input nodes and one output node. One input node of the memory 622 is connected to the output node of the comparison circuit 522. The other input node of the memory 622 is connected to the count signal line 60. The count signal COUNT is input to the other input node of the memory 622 from the counter circuit 58A via the count signal line 60. One input node of the memory 642 is connected to the output node of the memory 622. The other input node of the memory 642 is connected to the horizontal scanning circuit 70A. The output node of the memory 642 is connected to the horizontal output line 72A.

[0045] The comparison circuit 521 compares the level of the voltage VOUT1 output from the signal line 161 with the level of the reference signal VRAMP supplied from the reference signal line 50, and outputs a signal according to the comparison result. For example, the comparison circuit 521 outputs a high-level signal when the level of the reference signal VRAMP is lower than the level of the voltage VOUT1. On the other hand, the comparison circuit 521 outputs a low-level signal when the level of the reference signal VRAMP is higher than the level of the voltage VOUT1. Note that the relationship between the magnitude of the input signal and the level of the output signal may be reversed.

[0046] The memory 621 holds, as digital data of the pixel signal, the count value indicated by the count signal COUNT supplied from the counter circuit 58A at the timing when the level of the output node of the comparison circuit 521 is inverted. That is, the comparison circuit 521 and the counter circuit 58A function as an analog-to-digital conversion circuit that converts the analog signal output to the signal line 161 into a digital signal. The memory 641 holds the digital data of the pixel signal transferred from the memory 621. The digital data held in the memory 641 is transferred to the processing circuit 80A via the horizontal output line 72A sequentially for each column in response to a control signal supplied from the horizontal scanning circuit 70A. By providing the memory 641 subsequent to the memory 621, it is possible to perform an analog-to-digital conversion operation in parallel with the transfer operation to the processing circuit 80A.

[0047] Instead of providing the counter circuit 58A, the memory 621 of the column circuit 42 may have the function of a counter circuit. In this case, the memory 621 of the column circuit 42 of each column receives a common clock signal output from the control circuit 90 and counts pulses of the clock signal. The count value at the timing when the level of the output signal of the comparison circuit 521 is inverted becomes digital data held by the memory 621.

[0048] The configurations and operations of the comparison circuit 522, memory 622, and memory 642 are the same as those of the comparison circuit 521, memory 621, and memory 641, except that one input node (inverting input node) of the comparison circuit 521 is connected to the signal line 162.

[0049] The column circuits 42 of the readout circuit 40B are the same as the column circuits 42 of the readout circuit 40A except that they are arranged in a different column from the column circuits 42 of the readout circuit 40A, and therefore will not be described again. Hereinafter, the description will focus on the column circuits 42 of the readout circuit 40A, but the same applies to the column circuits 42 of the readout circuit 40B. In the following description, when the signal output lines 16A, 16B, readout circuits 40A, 40B, etc. are commonly described, the distinction between A and B may be omitted and they may be referred to as signal output lines 16, readout circuits 40, etc. When a plurality of similar components is provided, consecutive numbers such as 1, 2, 3, etc. may be added to each reference numeral to distinguish them from one another.

[0050] The photoelectric conversion device 100 of this embodiment may be configured so that all of the above-mentioned functional blocks are arranged on a single substrate, or may be configured so that multiple substrates are stacked together and functional blocks are created on each substrate.

[0051] FIG. 4 is a schematic diagram showing an example of the configuration of a photoelectric conversion device according to this embodiment. FIG. 4(a) is a schematic diagram showing a case where a pixel substrate 110 on which a pixel array section 10 is arranged and a circuit substrate 120 on which other functional blocks are arranged are stacked. By arranging the pixel substrate 110 and the circuit substrate 120 on separate substrates, it is possible to reduce the size of the photoelectric conversion device 100 without sacrificing the area of ​​the pixel array section 10. FIG. 4(b) is a schematic diagram showing a case where the pixel substrate 110 on which the pixel array section 10 is arranged and circuit substrates 120, 130 on which other functional blocks are arranged are stacked. In this case as well, it is possible to reduce the size of the photoelectric conversion device 100 without sacrificing the area of ​​the pixel array section 10.

[0052] Furthermore, if the pixel array section 10 and the P-type transistors M51 and M52 that constitute the column circuit 42 are provided on separate substrates, the transistors that constitute the pixel substrate 110 will be only N-type pixel transistors. This allows the manufacturing process for the P-type transistors on the pixel substrate 110 to be omitted, thereby simplifying the manufacturing process.

[0053] It should be noted that the circuit elements that make up one functional block do not necessarily have to be arranged on the same substrate, and may be arranged on separate substrates.

[0054] Next, as an example of the operation of the photoelectric conversion device 100 according to this embodiment, an operation mode in which the two signal lines 161, 162 constituting the signal output lines 16A, 16B of each column are alternately used to sequentially read out signals from the pixels 12 for one row will be described.

[0055] First, the operation when reading out a signal from a pixel 12 connected to a signal line 161 will be described with reference to Fig. 5. Fig. 5 is a timing diagram showing a method for driving a photoelectric conversion device according to this embodiment. The timing diagram in Fig. 5 shows waveforms of control signals PTX and PRES, a reference signal VRAMP, and a voltage VOUT1 on the signal line 161.

[0056] When reading a signal from a pixel 12 connected to the signal line 161, the current source 441 and the comparator circuit 521 are set to an operating state, while the current source 442 and the comparator circuit 522 are set to a power-saving state, thereby reducing power consumption during operation. In this case, to prevent the potential of the unused signal line 162 from floating, the transistor M52 is turned on to fix the voltage of the signal line 162 to the power supply voltage. Examples of the power-saving state include stopping the supply of the power supply voltage and preventing a through current from flowing from the power supply voltage node to the ground node. Note that the power-saving state referred to in this specification includes, but is not limited to, a state in which the power consumption of the circuit subject to control is set to zero. In other words, it also includes a state in which the power consumption of the circuit subject to control is reduced compared to the normal operating state. When power consumption is reduced to zero, it may take some time to return to the operating state. However, by not setting power consumption to zero but setting it to a state where it is reduced compared to the normal operating state, the return to the operating state can be speeded up. The power saving state, which is a state where the power consumption is lower than the normal operating state, can be 50% or less of the power consumption in the normal operating state. To further reduce power consumption, the power consumption in the power saving state can be 20% or less of the power consumption in the normal operating state.

[0057] Just before time t0, the control signal PSEL (not shown) of the row to be read, which includes the pixels 12 connected to the signal line 161, is at a high level. This turns on the selection transistors M4 of the pixels 12 in that row, and each of these pixels 12 is ready to output a pixel signal to the signal output line 16A of the corresponding column. Also, just before time t0, the control signals PTX and PRES of the row to be read are at a low level, and the reference signal VRAMP is at a predetermined reference voltage.

[0058] During the period from time t0 to time t1, the vertical scanning circuit 20 controls the control signal PRES of the row to be readout to a high level. This turns on the reset transistor M2 of the pixels 12 belonging to that row, and resets the node FD to a voltage corresponding to the voltage VDD. A voltage VOUT1 (a pixel signal at the reset level of the pixels 12) corresponding to the reset voltage of the node FD is output to the signal line 161 connected to the pixels 12 of the row to be readout.

[0059] When the control signal PRES changes from low to high at time t0, the voltage at node FD increases due to capacitive coupling between the gate and source of the reset transistor M2, and the voltage VOUT1 also increases accordingly. Also, when the control signal PRES changes from high to low at time t1, the voltage at node FD decreases due to capacitive coupling between the gate and source of the reset transistor M2, and the voltage VOUT1 also decreases accordingly.

[0060] At the next time t2, the reference signal output circuit 48A starts a slope operation in which the voltage of the reference signal VRAMP is gradually decreased over time. At the same time as the slope operation starts, the counter circuit 58A starts counting up and outputs a count signal COUNT indicating the count value to the column circuit 42 of each column via the count signal line 60.

[0061] The comparison circuit 521 of the column circuit 42 compares the level of the voltage VOUT1 with the level of the reference signal VRAMP. The level of the output signal of the comparison circuit 521 is inverted at a timing when the magnitude relationship between the level of the voltage VOUT1 and the level of the reference signal VRAMP changes, for example, at time t3 in FIG.

[0062] The memory 621 of the column circuit 42 holds the count value indicated by the count signal COUNT output from the counter circuit 58A at the timing when the level of the output signal of the comparison circuit 521 is inverted, as digital data of the pixel signal of the reset level of the pixel 12. In this way, AD conversion is performed on the pixel signal of the reset level of the pixel 12. The digital data held in the memory 621 is transferred to the memory 641, and then transferred to the processing circuit 80A in response to a control signal from the horizontal scanning circuit 70A.

[0063] At the following time t4, the reference signal output circuit 48A resets the reference signal VRAMP to the level of the reference voltage.

[0064] During the subsequent period from time t5 to time t6, the vertical scanning circuit 20 controls the control signal PTX for the row to be readout to a high level. This turns on the transfer transistor M1 of the pixel 12 belonging to that row, and the charge accumulated in the photoelectric conversion element PD during the predetermined exposure period is transferred to the node FD. This causes the voltage of the node FD to decrease in accordance with the amount of charge transferred from the photoelectric conversion element PD, and the voltage VOUT1 of the signal line 161 also decreases. A voltage VOUT1 (a pixel signal at the optical signal level of the pixel 12) corresponding to the voltage of the node FD is output to the signal line 161. Note that FIG. 5 shows a waveform equivalent to a dark state, and it is assumed that the reset level remains constant at approximately the same level as at time t2 even after time t6.

[0065] When the control signal PTX changes from low to high at time t5, the voltage at node FD increases due to capacitive coupling between the gate and drain of the transfer transistor M1, and the voltage VOUT1 also increases accordingly. Also, when the control signal PTX changes from high to low at time t6, the voltage at node FD decreases due to capacitive coupling between the gate and drain of the transfer transistor M1, and the voltage VOUT1 also decreases accordingly.

[0066] At the next time t7, the reference signal output circuit 48A starts a slope operation in which the voltage of the reference signal VRAMP changes over time. At the same time as the slope operation starts, the counter circuit 58A starts counting up and outputs a count signal COUNT indicating the count value to the column circuit 42 of each column via the count signal line 60.

[0067] The comparison circuit 521 of the column circuit 42 compares the level of the voltage VOUT1 with the level of the reference signal VRAMP. The level of the output signal of the comparison circuit 521 is inverted at a timing when the magnitude relationship between the level of the voltage VOUT1 and the level of the reference signal VRAMP changes, for example, at time t8 in FIG.

[0068] The memory 621 of the column circuit 42 holds the count value indicated by the count signal COUNT output from the counter circuit 58A at the timing when the level of the output signal of the comparison circuit 521 is inverted, as digital data of the pixel signal of the optical signal level of the pixel 12. In this way, AD conversion is performed on the pixel signal of the optical signal level of the pixel 12. The digital data held in the memory 621 is transferred to the memory 641, and then transferred to the processing circuit 80A in response to a control signal from the horizontal scanning circuit 70A.

[0069] The digital data of the pixel signals acquired in this way is subjected to correction processing using digital CDS (Correlated Double Sampling) in a subsequent processing circuit 80A. In the correction processing using digital CDS, the digital data of the pixel signals at the reset level is subtracted from the digital data of the pixel signals at the optical signal level, and noise components superimposed on the pixel signals at the optical signal level are removed.

[0070] At the following time t9, the reference signal output circuit 48A resets the reference signal VRAMP to the level of the reference voltage.

[0071] In this way, during a predetermined unit period (from time t10 to time t20), pixel signals of the pixels 12 connected to the signal line 161 are read out via the signal line 161. Note that the operation of reading out pixel signals of the pixels 12 connected to the signal line 162 is performed in a similar procedure, with the current source 442 and the comparison circuit 522 in the operating state, the current source 441 and the comparison circuit 521 in the power saving state, the transistor M52 turned off, and the transistor M51 turned on.

[0072] Next, the switching operation between the readout operation of the pixel signal output to the signal line 161 and the readout operation of the pixel signal output to the signal line 162 will be described with reference to Fig. 6. Fig. 6 is a timing diagram showing a method for driving the photoelectric conversion device according to this embodiment. The timing diagram in Fig. 6 shows waveforms of control signals VLRES1, VLRES2, VLSHT, voltage VOUT1 of signal line 161, and voltage VOUT2 of signal line 162. In Fig. 6, the solid line represents voltage VOUT1, and the dashed line represents voltage VOUT2.

[0073] 6, the periods from time t10 to time t20 and from time t50 to time t60 correspond to periods during which a readout operation of pixel signals from pixels 12 connected to signal line 161 is performed. Also, the period from time t30 to time t40 corresponds to a period during which a readout operation of pixel signals from pixels 12 connected to signal line 162 is performed.

[0074] During the period from time t0 to time t10, the control circuit 90 controls the control signals VLRES1, VLRES2, and VLSHT to a high level, which turns off the transistors M51 and M52 and turns on the switch S1, connecting the signal line 161 and the signal line 162 via the switch S1 and setting them to the same potential.

[0075] At the next time t10, the control circuit 90 changes the control signals VLRES2 and VLSHT from high to low to turn on the transistor M52 and turn off the switch S1, thereby fixing the voltage of the signal line 162 to the power supply voltage via the transistor M52 and electrically isolating the signal line 161 from the signal line 162, enabling pixel signals to be read out.

[0076] The operations of the pixel 12 and the column circuit 42 during the period from time t10 to time t20 are as described with reference to Fig. 5. That is, during the period from time t10 to time t20, the operation of reading out pixel signals from the pixel 12 via the signal line 161 is performed.

[0077] At the next time t20, the control circuit 90 changes the control signal VLRES2 from low to high to turn off the transistor M52, thereby cutting off the voltage supply from the power supply voltage node to the signal line 162, and the charge accumulated in the parasitic capacitance associated with the signal line 162 is discharged via the current source 442, causing the potential of the signal line 162 to start decreasing from the power supply voltage.

[0078] Also, at time t20, the control circuit 90 changes the control signal VLSHT from low level to high level to turn on the switch S1, thereby short-circuiting the signal line 161 and the signal line 162 via the switch S1.

[0079] When pixel signals are read from the signal line 162 during the subsequent period from time t30 to time t40, the potential of the signal line 162 needs to be reduced from the power supply voltage to the reset level (corresponding to the level of voltage VOUT1 during the period from time t10 to time t11 in FIG. 5). However, because it takes a certain amount of time for voltage VOUT2 to settle, there is a concern that the readout speed may decrease.

[0080] In this regard, in this embodiment, the above-described short-circuiting operation is performed during the period from time t20 to time t30, thereby distributing the charge between the signal line 161 and the signal line 162 and promoting an increase in the potential of the signal line 161 and a decrease in the potential of the signal line 162. By additionally performing such an operation, it is possible to shorten the length of the period until the potential of the signal line 162 is stabilized at the reset level.

[0081] At the next time t30, the control circuit 90 changes the control signals VLRES1 and VLSHT from high to low to turn on the transistor M51 and turn off the switch S1, thereby fixing the voltage of the signal line 161 to the power supply voltage via the transistor M51 and electrically isolating the signal line 162 from the signal line 161, enabling pixel signals to be read out.

[0082] During the period from time t30 to time t40, a pixel signal is read from the pixel 12 via the signal line 162. As described above, the operations of the pixel 12 and the column circuit 42 during the period from time t30 to time t40 are performed in the same procedure as during the period from time t10 to time t20.

[0083] At the next time t40, the control circuit 90 changes the control signal VLRES1 from low to high to turn off the transistor M51, thereby cutting off the voltage supply from the power supply voltage node to the signal line 161, and the charge accumulated in the parasitic capacitance associated with the signal line 161 is discharged via the current source 441, causing the potential of the signal line 161 to start decreasing from the power supply voltage.

[0084] Also, at time t40, the control circuit 90 changes the control signal VLSHT from low level to high level to turn on the switch S1, thereby short-circuiting the signal line 161 and the signal line 162 via the switch S1.

[0085] When pixel signals are read from the signal line 161 during the subsequent period from time t50 to time t60, the potential of the signal line 161 needs to be reduced from the power supply voltage to the reset level. However, since it takes a certain amount of time for the voltage VOUT1 to settle, there is a concern that the readout speed may decrease.

[0086] In this regard, in this embodiment, the above-described short-circuiting operation is performed during the period from time t40 to time t50, thereby distributing the charge between the signal line 161 and the signal line 162 and promoting a decrease in the potential of the signal line 161 and an increase in the potential of the signal line 162. By additionally performing such an operation, it is possible to shorten the length of the period until the potential of the signal line 161 is stabilized at the reset level. The subsequent operations from time t50 onwards are similar to those from time t10 onwards.

[0087] As described above, in this embodiment, when pixel signals are read out to the signal line 161, a predetermined voltage is applied to the signal line 162 of the same column. Furthermore, when pixel signals are read out to the signal line 162, a predetermined voltage is applied to the signal line 161 of the same column. Then, the signal lines 161 and 162 are short-circuited between the period when pixel signals are read out to the signal line 161 and the period when pixel signals are read out to the signal line 162. This shortens the length of the period until the potentials of the signal lines 161 and 162 are statically settled to the reset level, thereby speeding up the readout operation. In particular, when the readout operation of pixel signals to the signal line 161 and the readout operation of pixel signals to the signal line 162 are alternately switched, the effect of speeding up the readout operation is significant.

[0088] The photoelectric conversion device 100 according to this embodiment can also simultaneously use the two signal lines 161 and 162 that make up the signal output lines 16A and 16B of each column to read out signals from two rows of pixels 12 in parallel. In an operation mode in which the two signal lines 161 and 162 are simultaneously used, the switch S1 and the transistors M51 and M52 are set to the off state. In this state, the signals from the pixels 12 are output in parallel to the signal lines 161 and 162, and these signals are then read out in parallel to the comparison circuits 521 and 522.

[0089] As described above, according to this embodiment, in a photoelectric conversion device in which a plurality of signal output lines are arranged for each column of a pixel array, the speed at which signals are read out from pixels can be improved.

[0090] Although the present embodiment describes a case in which each column's signal output line 16 includes two signal lines, a configuration similar to this embodiment can also be applied when each column's signal output line 16 includes three or more signal lines. For example, if each column's signal output line 16 includes three signal lines (first, second, and third signal lines), signals are read from the first, second, and third signal lines, respectively, during the first, second, and third periods. Between each period, at least the signal lines that are read during the preceding and following periods are short-circuited. In this case, it is preferable to have the same number of switches S1 connected to each signal line. This configuration allows the effect of turning off the switch S1 to be uniform across the signal lines, thereby suppressing image quality degradation.

[0091] [Second embodiment] A photoelectric conversion device and a driving method thereof according to a second embodiment of the present invention will be described with reference to Fig. 7. Components similar to those of the photoelectric conversion device according to the first embodiment will be given the same reference numerals, and descriptions thereof will be omitted or simplified. In this embodiment, differences from the photoelectric conversion device according to the first embodiment will be mainly described, and descriptions of similarities between the photoelectric conversion device according to the first embodiment will be omitted as appropriate.

[0092] FIG. 7 is a schematic diagram showing an example of the configuration of a photoelectric conversion device according to this embodiment. FIG. 7 shows a portion of a pixel array unit 10 and a portion of a column circuit 42, which are components of the photoelectric conversion device according to this embodiment. In this embodiment, the pixel array unit 10 is assumed to have color filters in a so-called Bayer array. FIG. 7 shows one column out of the multiple columns constituting the pixel array unit 10, in which pixels 12R sensitive to red light and pixels 12G sensitive to green light are alternately arranged. Furthermore, the column circuit 42 shows only the components corresponding to the transistors M51 and M52 and switch S1 in the first embodiment, among the components of the column circuit 42 corresponding to this one column.

[0093] 7, in the photoelectric conversion device according to this embodiment, the signal output line 16 arranged in each column of the pixel array unit 10 has four signal lines 161, 162, 163, and 164. The column circuit 42 has a transistor M51 connected to the signal line 161, a transistor M52 connected to the signal line 162, a transistor M53 connected to the signal line 163, and a transistor M54 connected to the signal line 164. The column circuit 42 also has a switch S11 connected between the signal lines 161 and 162, and a switch S12 connected between the signal lines 163 and 164. The transistors M51, M52, M53, and M54 correspond to the transistors M51 and M52 of the first embodiment, and when turned on, fix the voltage of the corresponding signal line to the power supply voltage. The switches S11 and S12 correspond to the switch S1 in the first embodiment, and when turned on, short-circuit the corresponding signal lines.

[0094] The plurality of pixels 12R constituting the pixel array unit 10 are divided into pixels 12R connected to signal line 161 and pixels 12R connected to signal line 162 in row units. Similarly, the plurality of pixels 12G constituting the pixel array unit 10 are divided into pixels 12G connected to signal line 163 and pixels 12G connected to signal line 164 in row units.

[0095] The switches S11 and S12 are connected between signal lines to which pixels 12 of the same color are connected. That is, the switch S11 is connected between a signal line 161 to which the pixel 12R is connected and a signal line 162 to which the pixel 12R is connected. The switch S12 is connected between a signal line 163 to which the pixel 12G is connected and a signal line 164 to which the pixel 12G is connected.

[0096] Although not shown in Figure 7, a column (not shown) in which pixels 12B sensitive to blue light and pixels 12G sensitive to green light are arranged alternately is similar to the column in which pixels 12R and pixels 12G are arranged alternately.

[0097] When the operation of the first embodiment is applied to the photoelectric conversion device of this embodiment, a readout operation from pixel 12R to signal line 161 and a readout operation from pixel 12R to signal line 162 are alternately performed. In parallel with this, a readout operation from pixel 12G to signal line 163 and a readout operation from pixel 12G to signal line 164 are alternately performed. For example, the control signals VLRES1_1 and VLRES2_1 in FIG. 7 may be controlled by a waveform similar to that of the control signal VLRES1 in FIG. 6, and the control signals VLRES1_2 and VLRES2_2 may be controlled by a waveform similar to that of the control signal VLRES2 in FIG. 6. Then, at a predetermined timing for switching between the readout operation to signal line 161 and the readout operation to signal line 162, switch S11 is turned on to short-circuit signal line 161 and signal line 162. At a predetermined timing for switching between the readout operation to signal line 163 and the readout operation to signal line 164, switch S12 is turned on to short-circuit signal line 163 and signal line 164.

[0098] This enables the speed of the pixel signal readout operation to be increased, as in the case of the first embodiment. Furthermore, when switching the readout operation, color mixing can be prevented by independently short-circuiting each signal line that outputs signals from pixels 12 of the same color.

[0099] As described above, according to this embodiment, in a photoelectric conversion device in which a plurality of signal output lines are arranged for each column of a pixel array, the speed at which signals are read out from pixels can be improved.

[0100] [Third embodiment] A photoelectric conversion device and a driving method thereof according to a third embodiment of the present invention will be described with reference to Fig. 8. Components similar to those of the photoelectric conversion device according to the first or second embodiment will be given the same reference numerals, and descriptions thereof will be omitted or simplified. In this embodiment, differences from the photoelectric conversion device according to the first or second embodiment will be mainly described, and descriptions of similarities with the photoelectric conversion device according to the first or second embodiment will be omitted as appropriate.

[0101] FIG. 8 is a schematic diagram showing an example of the configuration of a photoelectric conversion device according to this embodiment. FIG. 8 shows a portion of the pixel array unit 10 and a portion of the column circuit 42, which are components of the photoelectric conversion device according to this embodiment. In this embodiment, as in the second embodiment, the pixel array unit 10 is assumed to have color filters in a Bayer array. FIG. 8 shows one column, in which pixels 12R and pixels 12G are alternately arranged, out of the multiple columns that make up the pixel array unit 10. Furthermore, the column circuit 42 shows only the components corresponding to the transistors M51 and M52 and switch S1 in the first embodiment, among the components of the column circuit 42 corresponding to this one column.

[0102] 8 , in the photoelectric conversion device according to this embodiment, the signal output line 16 arranged in each column of the pixel array unit 10 includes eight signal lines 161, 162, 163, 164, 165, 166, 167, and 168. The column circuit 42 includes a column circuit 421 connected to the signal lines 161, 162, 163, and 164, and a column circuit 422 connected to the signal lines 165, 166, 167, and 168. The column circuit 421 includes a transistor M51 connected to the signal line 161, a transistor M52 connected to the signal line 162, a transistor M53 connected to the signal line 163, and a transistor M54 connected to the signal line 164. The column circuit 421 also includes a switch S11 connected between the signal lines 161 and 162, and a switch S12 connected between the signal lines 162 and 163. The column circuit 421 further includes a switch S13 connected between the signal line 163 and the signal line 164, and a switch S14 connected between the signal line 164 and the signal line 161.

[0103] Transistors M51, M52, M53, and M54 correspond to the transistors M51 and M52 in the first embodiment, and when turned on, fix the voltage of the corresponding signal line to the power supply voltage. Switches S11, S12, S13, and S14 correspond to the switch S1 in the first embodiment, and when turned on, short-circuit the corresponding signal lines.

[0104] The plurality of pixels 12R constituting the pixel array unit 10 are divided into pixels 12R connected to signal line 161, pixels 12R connected to signal line 162, pixels 12R connected to signal line 163, and pixels 12R connected to signal line 164, on a row basis. Similarly, the plurality of pixels 12G constituting the pixel array unit 10 are divided into pixels 12G connected to signal line 165, pixels 12G connected to signal line 166, pixels 12G connected to signal line 167, and pixels 12G connected to signal line 168, on a row basis.

[0105] The switches S11, S12, S13, and S14 are connected between signal lines to which pixels 12 of the same color are connected. That is, the switch S11 is connected between the signal line 161 to which the pixel 12R is connected and the signal line 162 to which the pixel 12R is connected. The switch S12 is connected between the signal line 162 to which the pixel 12R is connected and the signal line 163 to which the pixel 12R is connected. The switch S13 is connected between the signal line 163 to which the pixel 12R is connected and the signal line 164 to which the pixel 12R is connected. The switch S14 is connected between the signal line 164 to which the pixel 12R is connected and the signal line 161 to which the pixel 12R is connected.

[0106] The column circuit 422 is similar to the column circuit 421 except for the connected signal lines, and therefore illustration and description of the components will be omitted. Also, although not shown in Fig. 7, a column in which pixels 12B sensitive to blue light and pixels 12G sensitive to green light are alternately arranged is similar to the column in which pixels 12R and pixels 12G are alternately arranged.

[0107] When the operation of the first embodiment is applied to the photoelectric conversion device of this embodiment, a read operation from pixel 12R to signal lines 161 and 162 and a read operation from pixel 12R to signal lines 163 and 164 are alternately performed. In parallel with this, a read operation from pixel 12G to signal lines 165 and 166 and a read operation from pixel 12G to signal lines 167 and 168 are alternately performed. For example, the control signals VLRES1_1 and VLRES2_1 in FIG. 8 may be controlled by a waveform similar to the control signal VLRES1 in FIG. 6, and the control signals VLRES1_2 and VLRES2_2 may be controlled by a waveform similar to the control signal VLRES2 in FIG. 6. Then, at a predetermined timing for switching between the read operation to signal lines 161 and 162 and the read operation to signal lines 163 and 164, switches S11, S12, S13, and S14 are turned on to short-circuit the signal lines 161, 162, 163, and 164. Furthermore, at a predetermined timing when the read operation to the signal lines 165 and 166 and the read operation to the signal lines 167 and 168 are switched, the signal lines 165, 166, 167, and 168 are short-circuited.

[0108] This enables the speed of the pixel signal readout operation to be increased, as in the case of the first embodiment. Also, by using the signal lines that output signals from pixels 12 of the same color as the signal lines that are short-circuited when switching the readout operation, it is possible to prevent color mixing.

[0109] Furthermore, in this embodiment, the number of signal lines to be short-circuited (for example, four signal lines 161, 162, 163, and 164) is equal to the number of switches used therefor (for example, four switches S11, S12, S13, and S14). This configuration makes it possible to equalize the effects of turning off the switches among the signal lines. For example, the signal lines 161, 162, 163, and 164 can be short-circuited without switch S14, but the signal lines 161 and 164 and the signal lines 162 and 163 are affected differently when the switch is turned off, which could cause degradation of image quality. By providing the same number of switches as the signal lines to be short-circuited, as in this embodiment, degradation of image quality can be suppressed.

[0110] As described above, according to this embodiment, in a photoelectric conversion device in which a plurality of signal output lines are arranged for each column of a pixel array, the speed at which signals are read out from pixels can be improved.

[0111] [Fourth embodiment] A photoelectric conversion device and a driving method thereof according to a fourth embodiment of the present invention will be described with reference to Figures 9 and 10. Components similar to those in the photoelectric conversion devices according to the first to third embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. In this embodiment, differences from the photoelectric conversion devices according to the first to third embodiments will be mainly described, and descriptions of similarities with the photoelectric conversion devices according to the first to third embodiments will be omitted as appropriate.

[0112] This embodiment shows an example of connections between the pixel array unit 10 and column circuits when the photoelectric conversion device is composed of multiple substrates. In this embodiment, differences from the photoelectric conversion device of the first embodiment will be mainly described, and descriptions of parts that are the same as those in the photoelectric conversion device of the first embodiment will be omitted as appropriate.

[0113] The photoelectric conversion device of this embodiment is a stacked-type photoelectric conversion device including a pixel substrate 110 on which a pixel array section 10 is arranged and a circuit substrate 120 on which other circuit blocks are arranged. FIG. 9 is a schematic diagram showing a configuration example of the photoelectric conversion device according to this embodiment. FIG. 9(a) shows a plan view of the pixel substrate 110, and FIG. 9(b) shows a plan view of the circuit substrate 120. These substrates are stacked so that they overlap in a planar manner to form the photoelectric conversion device of this embodiment. FIG. 9 shows a plurality of pixels 12 arranged in one of the multiple columns constituting the pixel array section 10 and some components of a column circuit 42 corresponding to the plurality of pixels 12. In the configuration example of FIG. 9, the plurality of pixels 12 are divided into two groups in the column direction, and these two groups are connected to signal lines 161 and 162, respectively. The signal lines 161 and 162 are connected to the column circuit 42 provided on the circuit substrate 120 via electrical connection parts 112 and 114 between the pixel substrate 110 and the circuit substrate 120. The signal lines 161 and 162 are connected to a common inverting input node of a comparison circuit 52 via a multiplexer 116 (selection circuit) provided on a circuit board 120. The connection relationship between the transistors M51 and M52 and the switch S1 and the signal lines 161 and 162 is the same as in the first embodiment.

[0114] Next, the switching operation between the readout operation of the pixel signal output to the signal line 161 and the readout operation of the pixel signal of the pixel 12 output to the signal line 162 will be described with reference to Fig. 10. Fig. 10 is a timing diagram showing a method for driving the photoelectric conversion device according to this embodiment. The timing diagram in Fig. 10 shows the waveforms of control signals VLRES1, VLRES2, and VLSHT.

[0115] In Figure 10, the period from time t10 to time t20 corresponds to the period during which the pixel signal readout operation to signal line 161 is performed, and the period from time t30 to time t40 corresponds to the period during which the pixel signal readout operation to signal line 162 is performed.

[0116] During the period before time t0, the control signal VLRES1 is at a high level, the control signals VLRES2 and VLSHT are at a low level, the transistor M51 and switch S1 are off, and the transistor M52 is on. In other words, the potential of the signal line 162 is fixed to the power supply voltage, and the signal line 161 is electrically isolated from the signal line 162. The multiplexer 116 selects the signal line 161, enabling the signals of the pixels 12 connected to the signal line 161 to be output to the comparison circuit 52. This makes it possible to read out the pixel signals output to the signal line 161. The control circuit 90 reads out the signals of the pixels 12 connected to the signal line 161 to the signal line 161 in row-sequential order via the vertical scanning circuit 20.

[0117] At the next time t0, the control circuit 90 changes the control signals VLRES2 and VLSHT from low to high to turn off the transistor M52 and turn on the switch S1, thereby shorting the signal lines 161 and 162 via the switch S1 while disconnecting the signal lines 161 and 162 from the power supply voltage.

[0118] At the next time t10, the control circuit 90 changes the control signals VLRES1 and VLSHT from high to low to turn on the transistor M51 and turn off the switch S1, thereby disconnecting the signal line 161 from the signal line 162 and fixing the voltage of the signal line 161 to the power supply voltage.

[0119] During the subsequent period from time t10 to time t20, the multiplexer 116 selects the signal line 162, enabling the signals of the pixels 12 connected to the signal line 162 to be output to the comparison circuit 52. This makes it possible to read out the pixel signals output to the signal line 162. The control circuit 90 reads out the signals of the pixels 12 connected to the signal line 162 to the signal line 162 in row sequence via the vertical scanning circuit 20.

[0120] At subsequent time t20, the control circuit 90 changes the control signals VLRES1 and VLSHT from low to high to turn off the transistor M51 and turn on the switch S1, thereby shorting the signal lines 161 and 162 via the switch S1 while disconnecting the signal lines 161 and 162 from the power supply voltage.

[0121] At the next time t30, the control circuit 90 changes the control signals VLRES2 and VLSHT from high to low to turn on the transistor M52 and turn off the switch S1, thereby disconnecting the signal line 162 from the signal line 161 and fixing the voltage of the signal line 162 to the power supply voltage.

[0122] During the subsequent period from time t30 to time t40, the multiplexer 116 selects the signal line 161, enabling the signals of the pixels 12 connected to the signal line 161 to be output to the comparison circuit 52. This makes it possible to read out the pixel signals output to the signal line 161. The control circuit 90 reads out the signals of the pixels 12 connected to the signal line 161 to the signal line 161 in row sequence via the vertical scanning circuit 20.

[0123] In this manner, in this embodiment as well, the signal lines are short-circuited at the timing when the signal lines are switched from the read state to the power supply voltage reset state, thereby enabling the read operation to be performed at a higher speed, as in the first embodiment.

[0124] As described above, according to this embodiment, in a photoelectric conversion device in which a plurality of signal output lines are arranged for each column of a pixel array, the speed at which signals are read out from pixels can be improved.

[0125] [Fifth embodiment] A photoelectric conversion system according to a fifth embodiment of the present invention will be described with reference to Fig. 11. Fig. 11 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0126] The photoelectric conversion device 100 described in the first to fourth embodiments can be applied to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photoelectric conversion system. Fig. 11 illustrates a block diagram of a digital still camera as an example of such systems.

[0127] 11 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that adjusts the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any one of the first to fourth embodiments, and converts the optical image formed by the lens 202 into image data.

[0128] The photoelectric conversion system 200 also has a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from a digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compressions as necessary and outputs the image data. The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 201 is formed, or may be formed on a semiconductor substrate different from the semiconductor layer on which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed in the same semiconductor layer as the imaging device 201.

[0129] The photoelectric conversion system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The photoelectric conversion system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out imaging data from the recording medium 214. The recording medium 214 may be built into the photoelectric conversion system 200 or may be detachable.

[0130] Furthermore, the photoelectric conversion system 200 has an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the image capture device 201 and the signal processing unit 208. Here, timing signals and the like may be input from outside, and the photoelectric conversion system 200 only needs to have at least the image capture device 201 and the signal processing unit 208 that processes the output signal output from the image capture device 201.

[0131] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0132] As described above, according to this embodiment, a photoelectric conversion system can be realized to which the photoelectric conversion device 100 according to the first to fourth embodiments is applied.

[0133] [Sixth embodiment] A photoelectric conversion system and a moving object according to a sixth embodiment of the present invention will be described with reference to Fig. 12. Fig. 12 is a diagram showing the configuration of the photoelectric conversion system and a moving object according to this embodiment.

[0134] FIG. 12(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 includes an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to fourth embodiments. The photoelectric conversion system 300 includes an image processing unit 312 that performs image processing on multiple pieces of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 300. The photoelectric conversion system 300 also includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to the object. In other words, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0135] The photoelectric conversion system 300 is connected to a vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 318. The photoelectric conversion system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination unit 318. For example, if the determination result of the collision determination unit 318 indicates a high possibility of a collision, the control ECU 330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0136] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 300. Fig. 12(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0137] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0138] [Seventh embodiment] An apparatus according to a seventh embodiment of the present invention will be described with reference to Fig. 13. Fig. 13 is a block diagram showing a schematic configuration of the apparatus according to this embodiment.

[0139] FIG. 13 is a schematic diagram showing equipment EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device 100 of any one of the first to fourth embodiments. All or part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometry sensor, or a distance measurement sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC, each including a photoelectric conversion unit, are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0140] The photoelectric conversion device APR may have a structure (chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may also be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected by through-silicon vias (TSVs), inter-chip wiring formed by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

[0141] The photoelectric conversion device APR may include, in addition to the semiconductor device IC, a package PKG that houses the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connecting members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device IC.

[0142] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes signals output from the photoelectric conversion device APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. The device EQP displays the signal output from the photoelectric conversion device APR on a display device DSPL and transmits the signal to the outside using a communication device (not shown) provided in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and arithmetic circuit unit provided in the photoelectric conversion device APR.

[0143] The device EQP shown in FIG. 13 can be an electronic device such as an information terminal with a photographing function (e.g., a smartphone or a wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP can also be transportation equipment (mobile object) such as a vehicle, a ship, or an aircraft. The device EQP can also be medical equipment such as an endoscope or a CT scanner. The device EQP can also be medical equipment such as an endoscope or a CT scanner.

[0144] The mechanical device MCHN in the transportation equipment can be used as a moving device. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device APR and for assisting and / or automating driving (piloting) using a photographing function. The processing device PRCS for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

[0145] The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser, and / or user. Therefore, if the photoelectric conversion device APR is installed in a device EQP, the value of the device EQP can also be increased. Therefore, when manufacturing and selling the device EQP, deciding to install the photoelectric conversion device APR according to this embodiment in the device EQP is advantageous in increasing the value of the device EQP.

[0146] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0147] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0148] Furthermore, the circuit configuration of the pixel 12 shown in FIG. 2 is an example and can be modified as appropriate. For example, each pixel 12 may have two or more photoelectric conversion elements. In this case, a configuration in which multiple photoelectric conversion elements share one FD node may be used. Also, a configuration in which multiple photoelectric conversion elements share one microlens, making it possible to detect a phase difference, may be used as a pupil-splitting pixel. Also, the pixel 12 does not necessarily have to have a selection transistor M4. Also, a configuration in which the capacitance value of the node FD is switchable may be used.

[0149] 3, the column circuit 42 can be modified as appropriate. For example, the comparison circuit 52 may further include a capacitor or switch for auto-zero operation.

[0150] In addition, in the above embodiment, an example has been shown in which a slope-type AD conversion circuit is used for AD conversion of pixel signals, but the AD conversion circuit used for AD conversion of pixel signals is not limited to a slope-type AD conversion circuit. In addition to a slope-type AD conversion circuit, for example, a SAR (Successive Approximation Register) type AD conversion circuit, a ΔΣ type AD conversion circuit, or a pipeline type AD conversion circuit can also be used for AD conversion of pixel signals.

[0151] Furthermore, the photoelectric conversion systems shown in the fifth and sixth embodiments are examples of photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied, and photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 11 and 12(a).

[0152] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0153] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features.

[0154] The disclosure of the above embodiments includes the following configurations and methods. (Configuration 1) a plurality of pixels arranged in a row, the pixels including a first pixel group and a second pixel group; a plurality of signal lines including a first signal line connected to the first pixel group and a second signal line connected to the second pixel group; a column circuit including a voltage control unit connected to the plurality of signal lines and controlling the supply of a predetermined voltage to each of the plurality of signal lines, and a switch circuit controlling electrical connection and separation between the plurality of signal lines; the voltage control unit supplies the predetermined voltage to the second signal line during a first period in which signals from the first pixel group are output to the first signal line and signals from the second pixel group are not output to the second signal line, and supplies the predetermined voltage to the first signal line during a second period in which signals from the second pixel group are output to the second signal line and signals from the first pixel group are not output to the first signal line; The switch circuit separates the first signal line and the second signal line during the first period and the second period, and connects the first signal line and the second signal line during a third period between the first period and the second period. A photoelectric conversion device characterized by: (Configuration 2) The processing in the first period and the processing in the second period are executed alternately. 2. The photoelectric conversion device according to configuration 1, (Configuration 3) The voltage control unit has a plurality of switches provided between a node to which a fixed voltage is supplied and each of the plurality of signal lines. 3. The photoelectric conversion device according to configuration 1 or 2. (Configuration 4) The fixed voltage is the power supply voltage 4. The photoelectric conversion device according to configuration 3. (Configuration 5) Each of the plurality of switches is a P-type transistor. 5. The photoelectric conversion device according to configuration 3 or 4. (Configuration 6) each of the plurality of pixels includes an N-type transistor; the N-type transistor is disposed on a first substrate; The P-type transistor is disposed on a second substrate stacked on the first substrate. 6. The photoelectric conversion device according to configuration 5. (Configuration 7) The column circuit includes a first signal processing circuit that processes a signal output from the first signal line, and a second signal processing circuit that processes a signal output from the second signal line. 7. The photoelectric conversion device according to any one of configurations 1 to 6. (Configuration 8) The second signal processing circuit is set to a power saving state during the first period, and the first signal processing circuit is set to a power saving state during the second period. 8. The photoelectric conversion device according to configuration 7. (Configuration 9) The column circuit includes a selection circuit that selects and outputs one of the signals output from the first signal line and the signals output from the second signal line, and a signal processing circuit that processes the signal output from the selection circuit. 7. The photoelectric conversion device according to any one of configurations 1 to 6. (Configuration 10) The first signal processing circuit and the second signal processing circuit each have an analog-to-digital conversion circuit that converts analog signals output to the plurality of signal lines into digital signals. 9. The photoelectric conversion device according to configuration 7 or 8. (Configuration 11) the plurality of signal lines includes three or more signal lines, The switch circuit has a plurality of switches each connected between any two of the plurality of signal lines, and the number of the switches connected to each of the plurality of signal lines is the same. 11. The photoelectric conversion device according to any one of configurations 1 to 10. (Configuration 12) the plurality of pixels further includes a third pixel group and a fourth pixel group; the plurality of signal lines further include a third signal line connected to the third pixel group and a fourth signal line connected to the fourth pixel group; the voltage control unit supplies the predetermined voltage to the fourth signal line during the first period in which signals from the third pixel group are output to the third signal line and signals from the fourth pixel group are not output to the fourth signal line, and supplies the predetermined voltage to the third signal line during the second period in which signals from the fourth pixel group are output to the fourth signal line and signals from the third pixel group are not output to the third signal line; The switch circuit separates the third signal line and the fourth signal line during the first period and the second period, and connects the third signal line and the fourth signal line during the third period. 12. The photoelectric conversion device according to any one of configurations 1 to 11. (Configuration 13) the pixels of the first pixel group and the second pixel group are sensitive to light of a first color; the pixels of the third pixel group and the fourth pixel group are sensitive to light of a second color different from the first color; The switch circuit connects the first signal line and the second signal line and the third signal line and the fourth signal line independently of each other during the third period. 13. The photoelectric conversion device according to configuration 12. (Configuration 14) the pixels of the first pixel group, the second pixel group, the third pixel group, and the fourth pixel group are sensitive to light of the same color; The switch circuit connects the first signal line, the second signal line, the third signal line, and the fourth signal line during the third period. 13. The photoelectric conversion device according to configuration 12. (Configuration 15) a plurality of pixels arranged in a row, the pixels including a first pixel group and a second pixel group; a plurality of signal lines including a first signal line connected to the first pixel group and a second signal line connected to the second pixel group; a column circuit including: a voltage control unit connected to the plurality of signal lines and controlling the supply of a predetermined voltage to each of the plurality of signal lines; and a switch circuit controlling electrical connection and separation between the plurality of signal lines; a control circuit for controlling the column circuit; The control circuit when executing a first period in which signals from the first pixel group are output to the first signal lines and signals from the second pixel group are not output to the second signal lines, the first signal lines and the second signal lines are separated by the switch circuit, and the predetermined voltage is supplied to the second signal lines by a voltage control unit; when executing a second period in which signals from the second pixel group are output to the second signal lines and signals from the first pixel group are not output to the first signal lines, separating the first signal lines and the second signal lines by the switch circuit, and supplying the predetermined voltage to the first signal lines by a voltage control unit; During a third period between the first period and the second period, the first signal line and the second signal line are connected by the switch circuit. A photoelectric conversion device characterized by: (Configuration 16) When an operation of outputting a signal from the first pixel group to the first signal line and an operation of outputting a signal from the second pixel group to the second signal line are performed in parallel, the control circuit separates the first signal line and the second signal line using the switch circuit, and stops the supply of the predetermined voltage to the first signal line and the second signal line by the voltage control unit. 16. The photoelectric conversion device according to configuration 15. (Configuration 17) The photoelectric conversion device according to any one of structures 1 to 16, a signal processing device that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising: (Configuration 18) A mobile object, The photoelectric conversion device according to any one of structures 1 to 16, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object characterized by having: (Configuration 19) The photoelectric conversion device according to any one of structures 1 to 16, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on the information obtained by the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; and a storage device that stores information obtained by the photoelectric conversion device; An apparatus characterized by comprising: (Method 1) A method for driving a photoelectric conversion device having a plurality of pixels arranged in a column, the pixels including a first pixel group and a second pixel group, and a plurality of signal lines including a first signal line connected to the first pixel group and a second signal line connected to the second pixel group, during a first period in which signals from the first pixel group are output to the first signal lines and signals from the second pixel group are not output to the second signal lines, the first signal lines and the second signal lines are electrically separated and a predetermined voltage is supplied to the second signal lines; during a second period in which signals from the second pixel group are output to the second signal lines and signals from the first pixel group are not output to the first signal lines, the first signal lines and the second signal lines are electrically separated and a predetermined voltage is supplied to the first signal lines; During a third period between the first period and the second period, the first signal line and the second signal line are electrically connected. A method for driving a photoelectric conversion device. [Explanation of symbols]

[0155] M51, M52, M53, M54...Transistors S1, S11, S12, S13, S14...Switches 10...Pixel array section 12...pixels 14...Control line 16, 16A, 16B...Signal output lines 161, 162, 163, 164, 165, 166, 167, 168...Signal lines 42,421,422…Column circuit 441,442…Current source 90...Control circuit 100...Photoelectric conversion device

Claims

1. a plurality of pixels arranged in a row, the pixels including a first pixel group and a second pixel group; a plurality of signal lines including a first signal line connected to the first pixel group and a second signal line connected to the second pixel group; a column circuit including a voltage control unit connected to the plurality of signal lines and controlling the supply of a predetermined voltage to each of the plurality of signal lines, and a switch circuit controlling electrical connection and separation between the plurality of signal lines; the voltage control unit supplies the predetermined voltage to the second signal line during a first period in which signals from the first pixel group are output to the first signal line and signals from the second pixel group are not output to the second signal line, and supplies the predetermined voltage to the first signal line during a second period in which signals from the second pixel group are output to the second signal line and signals from the first pixel group are not output to the first signal line; The switch circuit separates the first signal line and the second signal line during the first period and the second period, and connects the first signal line and the second signal line during a third period between the first period and the second period. A photoelectric conversion device characterized by:

2. The processing in the first period and the processing in the second period are alternately switched.

2. The photoelectric conversion device according to claim 1.

3. The voltage control unit has a plurality of switches provided between a node to which a fixed voltage is supplied and each of the plurality of signal lines.

2. The photoelectric conversion device according to claim 1.

4. The fixed voltage is the power supply voltage 4. The photoelectric conversion device according to claim 3.

5. Each of the plurality of switches is a P-type transistor.

4. The photoelectric conversion device according to claim 3.

6. each of the plurality of pixels includes an N-type transistor; the N-type transistor is disposed on a first substrate; The P-type transistor is disposed on a second substrate stacked on the first substrate.

6. The photoelectric conversion device according to claim 5.

7. The column circuit includes a first signal processing circuit that processes a signal output from the first signal line, and a second signal processing circuit that processes a signal output from the second signal line.

7. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

8. The second signal processing circuit is set to a power saving state during the first period, and the first signal processing circuit is set to a power saving state during the second period.

8. The photoelectric conversion device according to claim 7.

9. The column circuit includes a selection circuit that selects and outputs one of the signals output from the first signal line and the signals output from the second signal line, and a signal processing circuit that processes the signal output from the selection circuit.

7. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

10. The first signal processing circuit and the second signal processing circuit each have an analog-to-digital conversion circuit that converts analog signals output to the plurality of signal lines into digital signals.

8. The photoelectric conversion device according to claim 7.

11. the plurality of signal lines includes three or more signal lines, The switch circuit has a plurality of switches each connected between any two of the plurality of signal lines, and the number of the switches connected to each of the plurality of signal lines is the same.

7. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

12. the plurality of pixels further includes a third pixel group and a fourth pixel group; the plurality of signal lines further include a third signal line connected to the third pixel group and a fourth signal line connected to the fourth pixel group; the voltage control unit supplies the predetermined voltage to the fourth signal line during the first period in which signals from the third pixel group are output to the third signal line and signals from the fourth pixel group are not output to the fourth signal line, and supplies the predetermined voltage to the third signal line during the second period in which signals from the fourth pixel group are output to the fourth signal line and signals from the third pixel group are not output to the third signal line; The switch circuit separates the third signal line and the fourth signal line during the first period and the second period, and connects the third signal line and the fourth signal line during the third period.

7. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

13. the pixels of the first pixel group and the second pixel group are sensitive to light of a first color; the pixels of the third pixel group and the fourth pixel group are sensitive to light of a second color different from the first color; The switch circuit connects the first signal line and the second signal line and the third signal line and the fourth signal line independently of each other during the third period.

13. The photoelectric conversion device according to claim 12.

14. the pixels of the first pixel group, the second pixel group, the third pixel group, and the fourth pixel group are sensitive to light of the same color; The switch circuit connects the first signal line, the second signal line, the third signal line, and the fourth signal line during the third period.

13. The photoelectric conversion device according to claim 12.

15. a plurality of pixels arranged in a row, the pixels including a first pixel group and a second pixel group; a plurality of signal lines including a first signal line connected to the first pixel group and a second signal line connected to the second pixel group; a column circuit including: a voltage control unit connected to the plurality of signal lines and controlling the supply of a predetermined voltage to each of the plurality of signal lines; and a switch circuit controlling electrical connection and separation between the plurality of signal lines; a control circuit for controlling the column circuit; The control circuit when executing a first period in which signals from the first pixel group are output to the first signal lines and signals from the second pixel group are not output to the second signal lines, the first signal lines and the second signal lines are separated by the switch circuit, and the predetermined voltage is supplied to the second signal lines by a voltage control unit; when executing a second period in which signals from the second pixel group are output to the second signal lines and signals from the first pixel group are not output to the first signal lines, the first signal lines and the second signal lines are separated by the switch circuit, and the predetermined voltage is supplied to the first signal lines by a voltage control unit; During a third period between the first period and the second period, the first signal line and the second signal line are connected by the switch circuit. A photoelectric conversion device characterized by:

16. When an operation of outputting a signal from the first pixel group to the first signal line and an operation of outputting a signal from the second pixel group to the second signal line are performed in parallel, the control circuit separates the first signal line and the second signal line using the switch circuit, and stops the supply of the predetermined voltage to the first signal line and the second signal line by the voltage control unit.

16. The photoelectric conversion device according to claim 15.

17. The photoelectric conversion device according to any one of claims 1 to 6, a signal processing device that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

18. A mobile object, The photoelectric conversion device according to any one of claims 1 to 6, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object characterized by having:

19. The photoelectric conversion device according to any one of claims 1 to 6, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on the information obtained by the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; and a storage device that stores information obtained by the photoelectric conversion device; An apparatus characterized by comprising:

20. A method for driving a photoelectric conversion device having a plurality of pixels arranged in a column, the pixels including a first pixel group and a second pixel group, and a plurality of signal lines including a first signal line connected to the first pixel group and a second signal line connected to the second pixel group, during a first period in which signals from the first pixel group are output to the first signal lines and signals from the second pixel group are not output to the second signal lines, the first signal lines and the second signal lines are electrically separated and a predetermined voltage is supplied to the second signal lines; during a second period in which signals from the second pixel group are output to the second signal lines and signals from the first pixel group are not output to the first signal lines, the first signal lines and the second signal lines are electrically separated and a predetermined voltage is supplied to the first signal lines; During a third period between the first period and the second period, the first signal line and the second signal line are electrically connected. A method for driving a photoelectric conversion device.

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