Semiconductor device

Abstract

To provide a semiconductor device having a novel layout.SOLUTION: A semiconductor device 1 includes a first electrode layer 55, second via electrodes 61 (via electrodes) laid in a mesh pattern on the first electrode layer 55, and a second electrode layer 65 arranged on the second via electrodes 61.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 (US2010 / 109052A1) discloses a semiconductor device having a multilayer wiring structure including a plurality of wirings stacked via a plurality of plugs. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2010 / 0109052 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a semiconductor device having a novel layout.

[0005] The present disclosure provides a semiconductor device including a first electrode layer, via electrodes laid out in a mesh pattern on the first electrode layer, and a second electrode layer disposed on the via electrodes.

[0006] The present disclosure provides a semiconductor device including a first insulating layer, a plurality of first via electrodes embedded in the first insulating layer, a first electrode layer connected to the plurality of first via electrodes on the first insulating layer, a second insulating layer covering the first electrode layer, second via electrodes embedded in the second insulating layer in a mesh pattern and connected to the first electrode layer, and a second electrode layer connected to the second via electrodes on the second insulating layer.

[0007] The present disclosure provides a semiconductor device including a chip, a functional device formed on the chip, a first electrode layer disposed on the chip and covering the functional device in a planar view, via electrodes laid in a mesh pattern on the first electrode layer and covering the functional device in a mesh pattern on the planar view, and a second electrode layer disposed on the via electrodes and covering the functional device in a planar view.

[0008] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. [Figure 3] FIG. 3 is a circuit diagram showing the configuration of the main transistor. [Figure 4] FIG. 4 is a circuit diagram showing the configuration of a system transistor. [Figure 5A] FIG. 5A is a circuit diagram illustrating the turn-off operation of the main transistor. [Figure 5B] FIG. 5B is a circuit diagram illustrating the normal operation of the main transistor. [Figure 5C] FIG. 5C is a circuit diagram illustrating the off transition operation of the main transistor. [Figure 5D] FIG. 5D is a circuit diagram illustrating the active clamp operation of the main transistor. [Figure 6] FIG. 6 is an enlarged plan view showing a main part of the active region. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. [Figure 8] FIG. 8 is a perspective view showing the layout of the active region. [Figure 9] FIG. 9 is a perspective view showing the layout of the main surface insulating film. [Figure 10]FIG. 10 is a perspective view showing the layout of the first insulating layer and the first via electrodes. [Figure 11] FIG. 11 is a perspective view in which the first insulating layer is omitted from FIG. [Figure 12] FIG. 12 is a perspective view showing the layout of the first electrode layer. [Figure 13] FIG. 13 is a perspective view showing the layout of the second insulating layer and the second via electrodes. [Figure 14] FIG. 14 is a perspective view in which the second insulating layer is omitted from FIG. [Figure 15] FIG. 15 is a perspective view showing the layout of the second electrode layer. [Figure 16] FIG. 16 is a perspective view showing the layout of the first pad electrodes. [Figure 17] FIG. 17 is a cross-sectional view showing a main part of the first via electrode, the first electrode layer, the second via electrode, and the second electrode layer. [Figure 18] FIG. 18 is a cross-sectional view showing other main parts of the first via electrode, the first electrode layer, the second via electrode, and the second electrode layer. [Figure 19] FIG. 19 is a plan view showing the layout of the gate structure, the first via electrode, and the second via electrode. [Figure 20A] FIG. 20A is a plan view showing a second via electrode according to a first modified example. [Figure 20B] FIG. 20B is a plan view showing a second via electrode according to a second modified example. [Figure 20C] FIG. 20C is a plan view showing a second via electrode according to a third modified example. [Figure 20D] FIG. 20D is a plan view showing a second via electrode according to the fourth modified example. DETAILED DESCRIPTION OF THE INVENTION

[0010] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0011] In this specification, open language such as "including" and "having" is described as a concept that encompasses closed language such as "consisting of." When the term "substantially" is used in this specification, this term not only includes a numerical value (form) that is equal to the numerical value (form) of the comparison target, but also includes a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target.

[0012] In this specification, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of explanation, and are not intended to limit the names of each structure.

[0013] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type."

[0014] "P-type" is a conductivity type resulting from a trivalent element, while "n-type" is a conductivity type resulting from a pentavalent element. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0015] Fig. 1 is a plan view showing a schematic configuration of a semiconductor device 1 according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a circuit diagram showing a configuration of a main transistor 10. Fig. 4 is a circuit diagram showing a configuration of a system transistor 11.

[0016] 1 and 2, a semiconductor device 1 includes a chip 2 formed in a rectangular parallelepiped shape. In this embodiment, the chip 2 is a Si chip including a Si single crystal. The chip 2 may also be referred to as a "semiconductor chip."

[0017] The chip 2 may be a wide bandgap semiconductor chip including a single crystal of a wide bandgap semiconductor. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of Si. Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). For example, the chip 2 may be a SiC chip including a single crystal of SiC.

[0018] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2. The first main surface 3 is a circuit surface on which various circuit structures that constitute an electronic circuit are formed. The second main surface 4 is a non-circuit surface that does not have any circuit structures.

[0019] The first side surface 5A extends in a first direction X along the first main surface 3. The second side surface 5B is connected to the first side surface 5A and extends in a second direction Y that intersects (specifically, is perpendicular to) the first direction X along the first main surface 3. The third side surface 5C is connected to the second side surface 5B and extends in the first direction X. The fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C and extends in the second direction Y.

[0020] The semiconductor device 1 includes an n-type first region 6 formed in a surface layer portion of the second main surface 4. The first region 6 may also be referred to as a "semiconductor region (layer)" or a "drain region (layer)." The first region 6 extends in a layered form along the second main surface 4 over the entire surface layer portion of the second main surface 4, and forms the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first region 6 is formed by an n-type semiconductor substrate (Si substrate).

[0021] The first region 6 may have a thickness of 10 μm or more and 200 μm or less. The thickness of the first region 6 may have a value belonging to at least one of the ranges of 10 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, and 175 μm or more and 200 μm or less. The thickness of the first region 6 may be 150 μm or less.

[0022] The semiconductor device 1 includes an n-type second region 7 formed in a surface layer portion of the first main surface 3. The second region 7 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or a "drain region (layer)." The first region 6 has an n-type impurity concentration lower than the n-type impurity concentration of the second region 7.

[0023] The second region 7 extends in a layered manner along the first main surface 3 over the entire surface portion of the first main surface 3, forming the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second region 7 is formed by an n-type epitaxial layer (Si epitaxial layer) stacked on the first region 6. The second region 7 has a thickness less than that of the first region 6.

[0024] The thickness of the second region 7 may be 1 μm or more and 20 μm or less. The thickness of the second region 7 may have a value belonging to at least one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, 12.5 μm or more and 15 μm or less, 15 μm or more and 17.5 μm or less, and 17.5 μm or more and 20 μm or less. The thickness of the second region 7 may be 5 μm or more and 15 μm or less. The thickness of the second region 7 may be 10 μm or less.

[0025] The semiconductor device 1 includes an active region 8 defined on the first main surface 3. The active region 8 may also be referred to as a "transistor region," an "output region," or the like. The active region 8 is a region where an output current IO (output signal) is generated.

[0026] In this embodiment, the active region 8 is defined in a region on the first side surface 5A side of the first main surface 3. In plan view, the active region 8 is defined in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the first main surface 3. The active region 8 may be electrically isolated from other regions by a trench-type region isolation structure.

[0027] The position, size, and planar shape of the active region 8 are arbitrary and are not limited to a specific layout. The area ratio of the planar area of ​​the active region 8 to the planar area of ​​the first main surface 3 may be 0.1 or more and 0.8 or less. The area ratio may have a value belonging to at least one of the ranges of 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, and 0.7 or more and 0.8 or less.

[0028] The semiconductor device 1 includes a control region 9 provided in a region on the first main surface 3 that is different from the active region 8. The control region 9 is a region having a plurality of types of electronic circuits (circuit devices) that realize various functions. In this embodiment, the control region 9 is defined in a region on the third side surface 5C side of the active region 8, and faces the active region 8 in the second direction Y.

[0029] In this embodiment, the control region 9 is defined in a polygonal shape (a quadrangle in this embodiment) in plan view, having four sides parallel to the periphery of the first main surface 3. The control region 9 may be electrically isolated from other regions by a trench-type region isolation structure.

[0030] The position, size, planar shape, etc. of the control region 9 are arbitrary and are not limited to a specific layout. The control region 9 may have a planar area approximately equal to the planar area of ​​the active region 8, or may have a planar area different from the planar area of ​​the active region 8. The planar area of ​​the control region 9 may be larger or smaller than the planar area of ​​the active region 8.

[0031] The area ratio of the planar area of ​​the control region 9 to the planar area of ​​the first principal surface 3 may be 0.1 or more and 0.8 or less. The area ratio may have a value belonging to at least one of the ranges of 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, and 0.7 or more and 0.8 or less.

[0032] The area ratio of the planar area of ​​the control region 9 to the planar area of ​​the active region 8 may be 0.1 or more and 4 or less. The area ratio may have a value belonging to at least one of the ranges of 0.1 or more and 0.5 or less, 0.5 or more and 1 or less, 1 or more and 1.5 or less, 1.5 or more and 2 or less, 2 or more and 2.5 or less, 2.5 or more and 3 or less, 3 or more and 3.5 or less, and 3.5 or more and 4 or less.

[0033] 3, the semiconductor device 1 includes a main transistor 10 as an example of a functional device formed in the active region 8. The main transistor 10 may also be referred to as a "transistor (structure)," a "power transistor (structure)," an "output transistor (structure)," etc.

[0034] In this embodiment, the main transistor 10 is a multi-gate field-effect transistor including one main drain MD, one main source MS, and multiple electrically independent main gates MG. The main transistor 10 generates one output current IO in response to multiple gate signals VG, including on signals and off signals. The output current IO is a drain-source current flowing between the main drain MD and the main source MS.

[0035] 4, the main transistor 10 includes a plurality of (two or more) system transistors 11. The system transistors 11 may be referred to as a "system transistor structure" or the like. The plurality of system transistors 11 are formed in a concentrated manner in the active region 8. In this embodiment, the plurality of system transistors 11 includes a first system transistor 11A and a second system transistor 11B.

[0036] Each of the plurality of system transistors 11 includes a system drain SD, a system source SS, and a plurality of system gates SG. The plurality of system drains SD are electrically connected to each other to form one main drain MD. The plurality of system sources SS are electrically connected to each other to form one main source MS. The plurality of system gates SG are provided electrically independent from each other to form a plurality of main gates MG.

[0037] The multiple system transistors 11 each generate a system current IS in response to a corresponding gate signal VG. Each system current IS is a drain-source current flowing between the system drain SD and the system source SS of each system transistor 11. The multiple system currents IS may have different values ​​or may have approximately equal values. The multiple system currents IS are added between the main drain MD and the main source MS. This generates a single output current IO consisting of the added value of the multiple system currents IS.

[0038] The main transistor 10 is driven in a plurality of operating modes in response to a plurality of electrically independent gate signals VG. The plurality of operating modes include an off operation, an on operation, and a sub-on operation. The plurality of gate signals VG include a first gate signal VG1 that controls the on / off state of the first system transistor 11A and a second gate signal VG2 that controls the on / off state of the second system transistor 11B.

[0039] In the OFF operation, both the first system transistor 11A and the second system transistor 11B are simultaneously controlled to the OFF state. In the ON operation, both the first system transistor 11A and the second system transistor 11B are simultaneously controlled to the ON state. In the sub-ON operation, either the first system transistor 11A or the second system transistor 11B is controlled to the ON state, and the other of the first system transistor 11A and the second system transistor 11B is controlled to the OFF state.

[0040] The channel utilization rate during sub-ON operation is lower than that during ON operation. Therefore, the ON resistance during sub-ON operation is higher than that during ON operation. In other words, the main transistor 10 is a variable ON resistance switching device.

[0041] 1, the semiconductor device 1 includes a control circuit 12 formed in a control region 9. The control circuit 12 may be referred to as a "control IC." The control circuit 12 is electrically connected to a main transistor 10. The control circuit 12 generates a plurality of gate signals VG and outputs them to a plurality of main gates MG (a plurality of system gates SG) of the main transistor 10.

[0042] The control circuit 12, together with the main transistor 10, constitutes an IPD (Intelligent Power Device). The IPD may also be called an "IPM (Intelligent Power Module)", an "IPS (Intelligent Power Switch)", a "smart power driver", a "smart MISFET (Smart MOSFET)", or a "protected MISFET (Protected MOSFET)".

[0043] In this embodiment, the control circuit 12 includes a gate drive circuit 13, an active clamp circuit 14, a current monitor circuit 15, an overcurrent protection circuit 16, an overheat protection circuit 17, an undervoltage malfunction avoidance circuit 18, an open load detection circuit 19, a power supply reverse connection protection circuit 20, and a logic circuit 21. The control circuit 12 does not necessarily need to include all of these functional circuits 13 to 21 at the same time, and it is sufficient if it includes at least one of these functional circuits 13 to 21.

[0044] The current monitor circuit 15 may be called a CS circuit (Current Sense circuit), the overcurrent protection circuit 16 may be called an OCP circuit (Over Current Protection circuit), the overheat protection circuit 17 may be called a TSD circuit (Thermal shut down circuit), the low voltage malfunction avoidance circuit 18 may be called a UVLO circuit (Under Voltage Lock Out circuit), the open load detection circuit 19 may be called an OLD circuit (Open Load Detection circuit), and the power supply reverse connection protection circuit 20 may be called an RBP circuit (Reverse Battery Protection circuit).

[0045] The gate drive circuit 13 is formed on the first main surface 3 of the control region 9. The gate drive circuit 13 is electrically connected to a plurality of main gates MG (a plurality of system gates SG). The gate drive circuit 13 generates a plurality of electrically independent gate signals VG that control the on / off of the main transistor 10, and outputs them to the plurality of main gates MG (a plurality of system gates SG).

[0046] The active clamp circuit 14 is formed on the first main surface 3 of the control region 9. The active clamp circuit 14 is electrically connected to the main drain MD (at least one system drain SD) and the main gate MG (at least one system gate SG).

[0047] The active clamp circuit 14 may include a first circuit including a plurality of pn junction diodes connected in series in the forward direction, and a second circuit including a plurality of Zener diodes connected in series in the forward direction. The second circuit may be connected in reverse bias to the first circuit.

[0048] The active clamp circuit 14 shifts the plurality of system transistors 11 to the active clamp operation in cooperation with the gate drive circuit 13. Specifically, after the plurality of system transistors 11 are controlled to change from an on state to an off state, when a back electromotive force generated in the plurality of system transistors 11 exceeds a predetermined threshold voltage, the active clamp circuit 14 controls some of the plurality of system transistors 11 to change from an off state to an on state in cooperation with the gate drive circuit 13.

[0049] As a result, the back electromotive force is limited to a predetermined clamp voltage by some of the system transistors 11, and at the same time, the energy caused by the back electromotive force is consumed by some of the system transistors 11. This improves the active clamp withstand capability of the main transistor 10.

[0050] The current monitor circuit 15 is formed on the first main surface 3 of the control region 9. The current monitor circuit 15 generates a monitor current that monitors the output current IO of the main transistor 10 and outputs the monitor current to another circuit. The current monitor circuit 15 may include one or more monitor transistors electrically connected to the main transistor 10.

[0051] The monitor transistor may be formed using a part of the main transistor 10 (plurality of system transistors 11) in the active region 8. The monitor transistor may be controlled to be turned on and off simultaneously with the main transistor 10, and may generate a monitor current linked to the output current IO.

[0052] The monitor transistor may be electrically connected to any one of the system transistors 11. In this case, the monitor transistor may be controlled to be turned on and off simultaneously with any one of the system transistors 11, and may generate a monitor current linked to any one of the system currents IS.

[0053] The overcurrent protection circuit 16 is formed on the first main surface 3 of the control region 9. The overcurrent protection circuit 16 generates an electrical signal for controlling the gate drive circuit 13 based on the monitor current from the current monitor circuit 15, and cooperates with the gate drive circuit 13 to control the on / off of the main transistor 10.

[0054] For example, the overcurrent protection circuit 16 may determine that the main transistor 10 is in an overcurrent state when the monitor current is equal to or greater than a predetermined threshold, and may cooperate with the gate drive circuit 13 to control some or all of the multiple system transistors 11 to an off state. The overcurrent protection circuit 16 may cooperate with the gate drive circuit 13 to transition the main transistor 10 to normal operation when the monitor current is less than a predetermined threshold.

[0055] The overheat protection circuit 17 is formed on the first main surface 3 of the control region 9. The overheat protection circuit 17 may determine that the main transistor 10 is in an overheated state when the temperature of the main transistor 10 exceeds a predetermined value, and may cooperate with the gate drive circuit 13 to control some or all of the multiple system transistors 11 to an off state.

[0056] The overheat protection circuit 17 may include a first temperature sensing device (e.g., a temperature sensing diode) that detects the temperature of the active region 8 and a second temperature sensing device (e.g., a temperature sensing diode) that detects the temperature of the control region 9. The first temperature sensing device may be disposed in the active region 8 and generate a first temperature sensing signal that monitors the temperature of the active region 8. The second temperature sensing device may be disposed in the control region 9 and generate a first temperature sensing signal that monitors the temperature of the control region 9.

[0057] The overheat protection circuit 17 may determine that the active region 8 is in an overheated state when the difference between the first temperature detection signal and the second temperature detection signal is equal to or greater than a predetermined threshold, and may cooperate with the gate drive circuit 13 to control some or all of the multiple system transistors 11 to an off state. The overheat protection circuit 17 may cooperate with the gate drive circuit 13 to transition the main transistor 10 to normal operation when the difference between the first temperature detection signal and the second temperature detection signal is equal to or greater than a predetermined threshold.

[0058] Low voltage malfunction avoidance circuit 18 is formed on first main surface 3 of control region 9. Low voltage malfunction avoidance circuit 18 prevents various functional circuits in control circuit 12 from malfunctioning when the startup voltage for starting control circuit 12 is less than a predetermined value. Low voltage malfunction avoidance circuit 18 may be configured to start control circuit 12 when the startup voltage is equal to or greater than a predetermined threshold voltage, and to stop control circuit 12 when the startup voltage is less than the threshold voltage.

[0059] The open load detection circuit 19 is formed on the first main surface 3 of the control region 9. The open load detection circuit 19 determines the electrical connection state of a load (for example, an inductive load). The open load detection circuit 19 may be configured to monitor the voltage between the terminals of the main transistor 10, and determine that the load is in an open state when the voltage between the terminals is equal to or greater than a predetermined threshold.

[0060] The power supply reverse connection protection circuit 20 is formed on the first main surface 3 of the control region 9. The power supply reverse connection protection circuit 20 detects reverse voltage when the power supply is connected in reverse, and protects the control circuit 12 and the main transistor 10 from the reverse voltage (reverse current). The logic circuit 21 is formed on the first main surface 3 of the control region 9. The logic circuit 21 generates electrical signals to be supplied to various circuits in the control circuit 12.

[0061] Fig. 5A is a circuit diagram illustrating the off operation of the main transistor 10. Fig. 5B is a circuit diagram illustrating the normal operation of the main transistor 10. Fig. 5C is a circuit diagram illustrating the off transition operation of the main transistor 10. Fig. 5D is a circuit diagram illustrating the active clamp operation of the main transistor 10.

[0062] 5A to 5D show an example in which an inductive load L as an example of a load is electrically connected to the main drain MD to illustrate an operation example of the semiconductor device 1. The inductive load L is not a component of the semiconductor device 1. Therefore, a configuration including the semiconductor device 1 and the inductive load L may be referred to as an "inductive load driving device" or an "inductive load control device." Examples of the inductive load L include a relay, a solenoid, a lamp, and a motor. The inductive load L may be for use in a vehicle. That is, the semiconductor device 1 may be an in-vehicle semiconductor device.

[0063] 5A, during an off operation, the control circuit 12 (gate drive circuit 13) outputs a first gate signal VG1 consisting of an off signal to the first system transistor 11A, and outputs a second gate signal VG2 consisting of an off signal to the second system transistor 11B, thereby controlling the first system transistor 11A to an off state, and controlling the second system transistor 11B to an off state.

[0064] 5B, during normal operation, the control circuit 12 (gate drive circuit 13) outputs a first gate signal VG1 consisting of an on signal to the first system transistor 11A, and outputs a second gate signal VG2 consisting of an on signal to the second system transistor 11B. As a result, the first system transistor 11A is controlled to change from an off state to an on state, and the second system transistor 11B is controlled to change from an off state to an on state. The main transistor 10 generates an output current IO including both the system current IS of the first system transistor 11A and the system current IS of the second system transistor 11B.

[0065] 5C, during an OFF transition operation, the control circuit 12 (gate drive circuit 13) outputs a first gate signal VG1 consisting of an OFF signal to the first system transistor 11A in the ON state, and outputs a second gate signal VG2 consisting of an OFF signal to the second system transistor 11B in the ON state. As a result, the first system transistor 11A is controlled to change from the ON state to the OFF state, and the second system transistor 11B is controlled to change from the ON state to the OFF state.

[0066] 5D, when the main transistor 10 is controlled to be in the off state, a back electromotive force caused by the inductive load L occurs between the main drain MD and the main source MS of the main transistor 10. The control circuit 12 (active clamp circuit 14) operates in response to the rise in the back electromotive force caused by the inductive load L, and causes the main transistor 10 to enter active clamp operation.

[0067] During the active clamp operation, the control circuit 12 (active clamp circuit 14) generates a first gate signal VG1 consisting of an ON signal in response to an increase in the back electromotive force of the inductive load L and outputs it to the first system transistor 11A. As a result, the first system transistor 11A is controlled to change from an OFF state to an ON state, and at the same time, the second system transistor 11B is controlled (maintained) in an OFF state.

[0068] The first system transistor 11A consumes the back electromotive force of the inductive load L and at the same time clamps the voltage between the main drain MD and the main source MS of the main transistor 10. Because the second system transistor 11B is in the off state, the entire main transistor 10 is prevented from turning on due to the back electromotive force. This prevents a sudden temperature rise in the main transistor 10 during active clamp operation, improving the active clamp withstand capability.

[0069] The channel utilization rate of the main transistor 10 during active clamp operation is lower than the channel utilization rate of the main transistor 10 during normal operation. Therefore, the on-resistance of the main transistor 10 during active clamp operation is higher than the on-resistance of the main transistor 10 during normal operation.

[0070] Fig. 6 is an enlarged plan view showing a main part of the active region 8. Fig. 7 is a cross-sectional view taken along line VII-VII shown in Fig. 6. Fig. 8 is a perspective view showing the layout of the active region 8. Fig. 9 is a perspective view showing the layout of the main surface insulating film 45. Fig. 10 is a perspective view showing the layout of the first insulating layer 50 and the first via electrode 51.

[0071] FIG. 11 is a perspective view in which the first insulating layer 50 is omitted from FIG. 10. FIG. 12 is a perspective view showing the layout of the first electrode layer 55. FIG. 13 is a perspective view showing the layout of the second insulating layer 60 and the second via electrode 61. FIG. 14 is a perspective view in which the second insulating layer 60 is omitted from FIG. 13. FIG. 15 is a perspective view showing the layout of the second electrode layer 65. FIG. 16 is a perspective view showing the layout of the first pad electrode 75.

[0072] Fig. 17 is a cross-sectional view showing a main portion of the first via electrode 51, the first electrode layer 55, the second via electrode 61, and the second electrode layer 65. Fig. 18 is a cross-sectional view showing another main portion of the first via electrode 51, the first electrode layer 55, the second via electrode 61, and the second electrode layer 65. Fig. 19 is a plan view showing the layout of the gate structure 30, the first via electrode 51, and the second via electrode 61.

[0073] 6 to 19, semiconductor device 1 includes p-type body region 25 formed in a surface layer portion of first main surface 3 in active region 8. Body region 25 is formed at a distance from the bottom of second region 7 toward first main surface 3, and faces first region 6 with part of second region 7 interposed therebetween. Body region 25 extends in a layered manner along first main surface 3.

[0074] The semiconductor device 1 includes a plurality of trench-type (trench electrode-type) gate structures 30 formed on the first main surface 3 in the active region 8. The gate structures 30 may also be referred to as "trench gate structures," "trench structures," or the like. The plurality of gate structures 30 are arranged at intervals in the first direction X and extend in stripes in the second direction Y. In other words, the plurality of gate structures 30 are arranged in stripes in the second direction Y.

[0075] The plurality of gate structures 30 penetrate the body region 25. The plurality of gate structures 30 are formed at intervals from the bottom of the second region 7 toward the first main surface 3, and face the first region 6 across a part of the second region 7. The plurality of gate structures 30 may be located closer to the first main surface 3 than the depth position of the intermediate portion of the second region 7, or may be located closer to the bottom of the second region 7 than the depth position of the intermediate portion of the second region 7.

[0076] The width of the gate structure 30 may be greater than 0 μm and less than or equal to 2 μm. The width of the gate structure 30 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0077] In this embodiment, the spacing between the gate structures 30 is less than the width of the gate structures 30. Of course, the spacing between the gate structures 30 may be greater than the width of the gate structures 30. The spacing between the gate structures 30 may be greater than 0 μm and equal to or less than 2 μm.

[0078] The spacing of the gate structures 30 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0079] The gate pitch of the multiple gate structures 30 may be greater than 0 μm and less than or equal to 4 μm. The gate pitch is the distance between the centers of the multiple gate structures 30. The gate pitch may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, and 3.5 μm to 4 μm. The gate pitch is preferably greater than or equal to 1 μm and less than or equal to 2.5 μm.

[0080] The depth of the gate structure 30 may be greater than 0 μm and less than or equal to 6 μm. The depth of the gate structure 30 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, and 5 μm to 6 μm. The depth of the gate structure 30 is preferably greater than or equal to 2.5 μm and less than or equal to 4.5 μm.

[0081] The plurality of gate structures 30 each include a trench 31, an insulating film 32, and a buried electrode 33. The trench 31 is formed in the first main surface 3, and defines the wall surfaces (sidewalls and bottom wall) of the gate structure 30.

[0082] The insulating film 32 includes a first insulating film 34 and a second insulating film 35. The first insulating film 34 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first insulating film 34 has a relatively large thickness and covers the wall surface on the bottom wall side of the trench 31. Specifically, the first insulating film 34 covers the wall surface on the bottom wall side of the trench 31 relative to the bottom of the body region 25 in a film-like manner.

[0083] The thickness of the first insulating film 34 may be greater than 0 nm and less than or equal to 500 nm. The thickness of the first insulating film 34 may have a value belonging to at least one of the ranges of greater than 0 nm and less than or equal to 100 nm, 100 nm to 200 nm, 200 nm to 300 nm, 300 nm to 400 nm, and 400 nm to 500 nm. The thickness of the first insulating film 34 may be greater than or equal to 200 nm and less than or equal to 300 nm.

[0084] The second insulating film 35 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second insulating film 35 includes the same type of insulating material as the first insulating film 34 and is connected to the first insulating film 34. The second insulating film 35 has a thickness less than that of the first insulating film 34 and covers the wall surface on the opening side of the trench 31. Specifically, the second insulating film 35 covers the wall surface on the opening side of the trench 31 relative to the bottom of the body region 25 in a film-like manner.

[0085] The thickness of the second insulating film 35 may be greater than 0 nm and less than or equal to 50 nm. The thickness of the second insulating film 35 may have a value belonging to at least one of the ranges of greater than 0 nm and less than or equal to 10 nm, 10 nm to 20 nm, 20 nm to 30 nm, 30 nm to 40 nm, and 40 nm to 50 nm.

[0086] The buried electrode 33 is buried in the trench 31 via an insulating film 32. The buried electrode 33 has a multi-electrode structure including a plurality of electrodes buried in a stacked manner in the depth direction of the trench 31. Specifically, the buried electrode 33 has a stacked structure including a first buried electrode 36, a second buried electrode 37, and an intermediate insulating film 38.

[0087] The first buried electrode 36 includes conductive polysilicon. The first buried electrode 36 is buried in the bottom wall side of the trench 31 via the first insulating film 34, and faces the second region 7 via the first insulating film 34. The first buried electrode 36 may have an upper end portion facing the body region 25 via the first insulating film 34. The first buried electrode 36 is drawn out from the bottom wall side of the trench 31 to the opening side of the trench 31 at the end of the trench 31.

[0088] The second buried electrode 37 includes conductive polysilicon. The second buried electrode 37 is buried in the opening side of the trench 31 via the second insulating film 35 and faces the body region 25 via the second insulating film 35. In this embodiment, the second buried electrode 37 has a lower end that engages with the gap between the upper end of the first buried electrode 36 and the sidewall of the trench 31. The lower end of the second buried electrode 37 may face the second region 7 via the second insulating film 35.

[0089] The second buried electrode 37 has an electrode surface exposed from the trench 31. The electrode surface is formed at a distance from the height position of the first main surface 3 to the bottom wall side of the trench 31. The electrode surface may be recessed toward the bottom wall side of the trench 31.

[0090] The intermediate insulating film 38 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the intermediate insulating film 38 includes the same type of insulating material as the first insulating film 34, and is connected to the first insulating film 34 and the second insulating film 35. The intermediate insulating film 38 may include an oxide of the first buried electrode 36.

[0091] The intermediate insulating film 38 is interposed in the trench 31 between the upper end of the first buried electrode 36 and the lower end of the second buried electrode 37, and separates the first buried electrode 36 from the second buried electrode 37. The intermediate insulating film 38 is connected to the insulating film 32 (the first insulating film 34 and the second insulating film 35).

[0092] The multiple gate structures 30 include multiple first gate structures 30A for the first system transistors 11A and multiple second gate structures 30B for the second system transistors 11B. In this embodiment, a first gate group including multiple (two in this embodiment) first gate structures 30A adjacent to each other in the first direction X and a second gate group including multiple (two in this embodiment) second gate structures 30B adjacent to each other in the first direction X are alternately arranged in the first direction X.

[0093] The first gate group may include 3 to 10 first gate structures 30A. The second gate group may include 3 to 10 second gate structures 30B. The number of second gate structures 30B in the second gate group may be the same as or different from the number of first gate structures 30A in the first gate group.

[0094] Of course, one first gate structure 30A and one second gate structure 30B may be arranged alternately in the first direction X. This configuration is effective in dispersing the first gate structures 30A and second gate structures 30B as heat generation origins and improving the active clamping resistance.

[0095] In this configuration, the same first gate signal VG1 is simultaneously applied to both the first buried electrode 36 and the second buried electrode 37 of the first gate structure 30A, thereby suppressing a voltage drop across the first buried electrode 36 and the second buried electrode 37 of the first gate structure 30A, and thus suppressing undesired electric field concentration due to the voltage drop.

[0096] Similarly, the same second gate signal VG2 is simultaneously applied to both the first buried electrode 36 and the second buried electrode 37 of the second gate structure 30B, thereby suppressing a voltage drop across the first buried electrode 36 and the second buried electrode 37 of the second gate structure 30B and preventing undesired electric field concentration due to the voltage drop.

[0097] The semiconductor device 1 includes a plurality of mesas 40 in the active region 8, which are partitioned into chips 2 by a plurality of gate structures 30. The mesas 40 are partitioned at intervals in the first direction X in accordance with the layout of the gate structures 30, and each extend in a strip shape in the second direction Y. In other words, the mesas 40 are arranged alternately with the gate structures 30 in the first direction X. The width of the mesas 40 corresponds to the spacing between the gate structures 30.

[0098] The semiconductor device 1 includes a plurality of n-type source regions 41 formed in regions along the plurality of gate structures 30 in the plurality of mesa portions 40. The plurality of source regions 41 are formed on both sides of the plurality of gate structures 30, respectively, and are arranged at intervals in the second direction Y. The plurality of source regions 41 are formed at intervals from the bottom of the body region 25 toward the first main surface 3.

[0099] The plurality of source regions 41 are formed in a region on one side in the first direction X with respect to the corresponding gate structure 30 and a region on the other side in the first direction X with respect to the corresponding gate structure 30. The plurality of source regions 41 face the corresponding second buried electrodes 37 with the corresponding second insulating films 35 interposed therebetween.

[0100] The plurality of source regions 41 on one side face the plurality of source regions 41 on the other side across the corresponding gate structure 30. Of course, the plurality of source regions 41 on one side may face the region between the plurality of source regions 41 on the other side across the corresponding gate structure 30.

[0101] In each mesa portion 40, the plurality of source regions 41 along the gate structure 30 on one side face regions between the plurality of source regions 41 along the gate structure 30 on the other side in the first direction X. Of course, the plurality of source regions 41 along the gate structure 30 on one side may be connected to the plurality of source regions 41 along the gate structure 30 on the other side in the first direction X.

[0102] The plurality of source regions 41 define channels along corresponding gate structures 30 in the body region 25. Specifically, the plurality of source regions 41 along the plurality of first gate structures 30A define first channels of the first system transistors 11A, and the plurality of source regions 41 along the plurality of second gate structures 30B define second channels of the second system transistors 11B.

[0103] The first channels have a first channel area, and the second channels have a second channel area. The first channel area is the total planar area of ​​the source regions 41 along the first gate structures 30A. The second channel area is the total planar area of ​​the source regions 41 along the second gate structures 30B.

[0104] The second channel area may be smaller than the first channel area. The second channel area may be larger than the first channel area. The second channel area may be approximately equal to the first channel area. During normal operation, the main transistor 10 is driven by the first channel area and the second channel area, and during active clamp operation, the main transistor 10 is driven by the first channel area.

[0105] That is, during active clamp operation, the main transistor 10 is driven by the first channel area which is less than the total channel area, which is the sum of the first channel area and the second channel area.

[0106] The channel ratio of the first channel area to the total channel area may have a value belonging to at least one of the ranges of greater than 0% and less than 10%, 10% to 20%, 20% to 30%, 30% to 40%, 40% to 50%, 50% to 60%, 60% to 70%, 70% to 80%, 80% to 90%, and 90% to less than 100%.

[0107] The semiconductor device 1 includes a plurality of p-type contact regions 42 formed in regions along the plurality of gate structures 30 in the plurality of mesa portions 40. The plurality of contact regions 42 are formed on both sides of the plurality of gate structures 30, respectively, and are arranged at intervals in the second direction Y. Specifically, the plurality of contact regions 42 are arranged alternately with the plurality of source regions 41 in the second direction Y. The plurality of contact regions 42 are formed at intervals from the bottom of the body region 25 toward the first main surface 3.

[0108] The plurality of contact regions 42 are formed in a region on one side in the first direction X with respect to the corresponding gate structure 30, and in a region on the other side in the first direction X with respect to the corresponding gate structure 30. The plurality of contact regions 42 face the corresponding second buried electrodes 37 with the corresponding second insulating films 35 interposed therebetween.

[0109] The plurality of contact regions 42 on one side face the plurality of contact regions 42 on the other side across the corresponding gate structure 30. Of course, the plurality of contact regions 42 on one side may face the region (i.e., the plurality of source regions 41) between the plurality of contact regions 42 on the other side across the corresponding gate structure 30.

[0110] In each mesa portion 40, the plurality of contact regions 42 along the gate structure 30 on one side face regions (i.e., the plurality of source regions 41) between the plurality of contact regions 42 along the gate structure 30 on the other side in the first direction X. Of course, the plurality of contact regions 42 along the gate structure 30 on one side may be connected to the plurality of contact regions 42 along the gate structure 30 on the other side in the first direction X.

[0111] The semiconductor device 1 includes a main surface insulating film 45 that selectively covers the first main surface 3 in the active region 8. The main surface insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main surface insulating film 45 includes a silicon nitride film. The main surface insulating film 45 covers the main transistor 10 in the active region 8 and the control circuit 12 in the control region 9.

[0112] The main surface insulating film 45 coats the first main surface 3 in a film-like manner. The main surface insulating film 45 coats the plurality of gate structures 30 on the first main surface 3 in a film-like manner. Specifically, the main surface insulating film 45 extends from above the first main surface 3 into the trench 31 and coats the electrode surface of the second buried electrode 37 (buried electrode 33) and the second insulating film 35 (insulating film 32) in a film-like manner.

[0113] The main surface insulating film 45 may have a thickness greater than 0 μm and equal to or less than 1 μm. The thickness of the main surface insulating film 45 may have a value belonging to at least one of the ranges of greater than 0 μm and equal to or less than 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, 0.4 μm to 0.5 μm, 0.5 μm to 0.6 μm, 0.6 μm to 0.7 μm, 0.7 μm to 0.8 μm, 0.8 μm to 0.9 μm, and 0.9 μm to 1 μm.

[0114] The semiconductor device 1 includes a plurality of contact openings 46 formed in a main surface insulating film 45. The plurality of contact openings 46 are formed in portions of the main surface insulating film 45 that cover the plurality of mesa portions 40 and are spaced apart from the plurality of gate structures 30, exposing the plurality of mesa portions 40. The plurality of contact openings 46 expose the plurality of source regions 41 and the plurality of contact regions 42. In this embodiment, the plurality of contact openings 46 extend in a strip shape in the second direction Y in accordance with the extension direction of the plurality of gate structures 30 (the plurality of mesa portions 40).

[0115] The semiconductor device 1 includes a first insulating layer 50 covering the first main surface 3. The first insulating layer 50 may be referred to as a "first insulating interlayer film." The first insulating layer 50 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first insulating layer 50 may include an insulating material different from the insulating material of the main surface insulating film 45. The first insulating layer 50 includes a silicon oxide film.

[0116] The first insulating layer 50 covers the main transistor 10 in the active region 8, and covers the control circuit 12 in the control region 9. In this embodiment, the first insulating layer 50 covers the main transistor 10 and the control circuit 12 via the main surface insulating film 45. The first insulating layer 50 collectively covers the multiple gate structures 30 via the main surface insulating film 45.

[0117] The first insulating layer 50 extends from above the main surface insulating film 45 into the plurality of contact openings 46, and has portions that cover the first main surface 3 (the plurality of mesa portions 40) within the plurality of contact openings 46. The first insulating layer 50 covers the plurality of source regions 41 and the plurality of contact regions 42 within the plurality of contact openings 46.

[0118] The first insulating layer 50 has a thickness greater than that of the main surface insulating film 45. The thickness of the first insulating layer 50 may be greater than 0 μm and less than or equal to 3 μm. The thickness of the first insulating layer 50 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm.

[0119] The semiconductor device 1 includes a plurality of first via electrodes 51 embedded in the first insulating layer 50 in the active region 8. The first via electrodes 51 may also be referred to as "lower via electrodes." The plurality of first via electrodes 51 are mechanically, electrically, and thermally connected to the main transistor 10. Specifically, the plurality of first via electrodes 51 are mechanically, electrically, and thermally connected to a plurality of first channels of the first system transistors 11A and a plurality of second channels of the second system transistors 11B.

[0120] The multiple first via electrodes 51 are arranged at intervals in the first direction X and extend linearly in the second direction Y. In this embodiment, the multiple first via electrodes 51 are formed in a one-to-one correspondence with the multiple mesa portions 40. That is, the multiple first via electrodes 51 extend linearly in the second direction Y following the extension direction of the corresponding mesa portions 40.

[0121] The plurality of first via electrodes 51 penetrate the first insulating layer 50 at intervals from the plurality of gate structures 30, and are mechanically, electrically, and thermally connected to the corresponding mesa portions 40. The plurality of first via electrodes 51 are mechanically, electrically, and thermally connected to the plurality of source regions 41 and the plurality of contact regions 42 in the corresponding mesa portions 40.

[0122] In this embodiment, the multiple first via electrodes 51 are formed at a distance from the wall surface of the corresponding contact opening 46, and each has a lower end that faces the wall surface of the corresponding contact opening 46 through a portion of the first insulating layer 50.

[0123] The multiple first via electrodes 51 have electrode surfaces exposed from the first insulating layer 50. The electrode surfaces are recessed toward the first main surface 3 with respect to the height position of the insulating surface of the first insulating layer 50. Of course, the electrode surfaces may form a single flat surface together with the insulating surface. The multiple first via electrodes 51 each have a height (greater than 0 μm and equal to or less than 3 μm) corresponding to the thickness of the first insulating layer 50.

[0124] The plurality of first via electrodes 51 may be formed in a one-to-many correspondence with each corresponding mesa portion 40. In this case, the plurality of first via electrodes 51 may extend linearly in the second direction Y along the corresponding mesa portion 40, and may be formed at intervals in the second direction Y.

[0125] The multiple first via electrodes 51 are arranged at a first pitch P1. The first pitch P1 is the distance in the first direction X between the centers of the multiple first via electrodes 51. The first pitch P1 is also the distance between the centers of the multiple mesa portions 40. The first pitch P1 may be greater than 0 μm and equal to or less than 4 μm.

[0126] The first pitch P1 may have a value belonging to at least one of the ranges of greater than 0 μm and equal to or less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, and 3.5 μm to 4 μm. The first pitch P1 is preferably equal to or greater than 1 μm and equal to or less than 2.5 μm.

[0127] The multiple first via electrodes 51 each have a first width W1 that is less than the width of the mesa portion 40. The first width W1 is less than the width of the gate structure 30. The first width W1 may be greater than 0 μm and equal to or less than 1 μm.

[0128] The first width W1 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, 0.4 μm to 0.5 μm, 0.5 μm to 0.6 μm, 0.6 μm to 0.7 μm, 0.7 μm to 0.8 μm, 0.8 μm to 0.9 μm, and 0.9 μm to 1 μm. The first width W1 is preferably 0.5 μm or less. The first width W1 is preferably 0.1 μm to 0.3 μm.

[0129] The multiple first via electrodes 51 are respectively embedded in multiple first via holes 52 formed in the first insulating layer 50. In this embodiment, the multiple first via electrodes 51 each include a first barrier film 53 and a first via body electrode 54.

[0130] The first barrier film 53 may include either or both of a titanium film and a titanium alloy film (e.g., a titanium nitride film). The first barrier film 53 may have a single-layer structure made of a titanium film or a titanium alloy film. The first barrier film 53 may have a multilayer structure including a titanium film and a titanium alloy film stacked in this order from the wall surface side of the first via hole 52.

[0131] The first barrier film 53 may have a thickness greater than 0 nm and less than 200 nm. The thickness of the first barrier film 53 may have a value belonging to at least one of the ranges of greater than 0 nm and less than 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm.

[0132] The first barrier film 53 covers the first main surface 3 (mesa portion 40) and the wall surface of the first via hole 52 in a film-like manner, and is mechanically, electrically, and thermally connected to the first main surface 3 (mesa portion 40). The first barrier film 53 is mechanically, electrically, and thermally connected to the plurality of source regions 41 and the plurality of contact regions 42.

[0133] The first via body electrode 54 includes at least one of aluminum, aluminum alloy, copper, copper alloy, molybdenum, molybdenum alloy, tungsten, and tungsten alloy. The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy. The first via body electrode 54 may have a thermal conductivity of 100 W / m·K or more and 500 W / m·K or less.

[0134] The thermal conductivity of the first via body electrode 54 may have a value belonging to at least one of the ranges of 100 W / m·K to 150 W / m·K, 150 W / m·K to 200 W / m·K, 200 W / m·K to 250 W / m·K, 250 W / m·K to 300 W / m·K, 300 W / m·K to 350 W / m·K, 350 W / m·K to 400 W / m·K, 400 W / m·K to 450 W / m·K, and 450 W / m·K to 500 W / m·K.

[0135] For example, the thermal conductivity of copper is 386 W / m·K, that of aluminum is 237 W / m·K, that of tungsten is 178 W / m·K, and that of molybdenum is 137 W / m·K. The first via body electrode 54 preferably has a thermal conductivity higher than that of the chip 2 (silicon) (=148 W / m·K). In this embodiment, the first via body electrode 54 is made of tungsten, which has excellent embedding properties in the first via hole 52.

[0136] The first via body electrode 54 is embedded in the first via hole 52 via the first barrier film 53, and is electrically and thermally connected to the first main surface 3 (mesa portion 40). The first via body electrode 54 is mechanically, electrically, and thermally connected to the plurality of source regions 41 and the plurality of contact regions 42.

[0137] The first via body electrode 54 forms the electrode surface of the first via electrode 51. The multiple first via electrodes 51 do not necessarily have to have the first barrier film 53, and may have the first via body electrode 54 directly embedded in the first via hole 52.

[0138] The semiconductor device 1 includes a first electrode layer 55 disposed on the first insulating layer 50 in the active region 8. The first electrode layer 55 covers the main transistor 10 via the first insulating layer 50. Specifically, the first electrode layer 55 collectively covers the multiple gate structures 30 and the multiple mesa portions 40 via the first insulating layer 50.

[0139] Although specific illustration is omitted, the first electrode layer 55 collectively covers the plurality of gate structures 30 and the plurality of mesa portions 40 in a region inward from both end portions of the plurality of gate structures 30. The first electrode layer 55 collectively covers the plurality of first via electrodes 51 on the first insulating layer 50, and is mechanically, electrically, and thermally connected to the plurality of first via electrodes 51.

[0140] That is, the first electrode layer 55 is electrically and thermally connected to the main transistor 10 through the plurality of first via electrodes 51. Specifically, the first electrode layer 55 is mechanically, electrically, and thermally connected to the plurality of first channels of the first system transistors 11A and the plurality of second channels of the second system transistors 11B through the plurality of first via electrodes 51.

[0141] The first electrode layer 55 has an electrode surface that extends along the insulating surface of the first insulating layer 50. The electrode surface of the first electrode layer 55 has a plurality of recesses 56 that are recessed toward the first via electrodes 51 in the portion that covers the first via electrodes 51. The recesses 56 are formed at intervals in the first direction X, following the layout of the first via electrodes 51, and extend linearly in the second direction Y.

[0142] In this embodiment, the first electrode layer 55 has a laminated structure including a first lower barrier film 57, a first electrode main film 58, and a first upper barrier film 59, which are laminated in this order from the first insulating layer 50 side.

[0143] The first lower barrier film 57 may include either or both of a titanium film and a titanium alloy film (e.g., a titanium nitride film). The first lower barrier film 57 may have a single-layer structure made of a titanium film or a titanium alloy film. The first lower barrier film 57 may have a multilayer structure including a titanium film and a titanium alloy film stacked in this order from the first insulating layer 50 side.

[0144] The first lower barrier film 57 may have a thickness greater than 0 nm and less than 200 nm. The thickness of the first lower barrier film 57 may have a value belonging to at least one of the ranges of greater than 0 nm and less than 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm.

[0145] The first lower barrier film 57 coats the first insulating layer 50 in a film-like manner. The first lower barrier film 57 collectively coats the plurality of first via electrodes 51 in a film-like manner on the first insulating layer 50. The first lower barrier film 57 penetrates the plurality of first via holes 52 from above the first insulating layer 50, and is mechanically, electrically, and thermally connected to the first barrier film 53 and the first via body electrode 54.

[0146] The first electrode body film 58 includes at least one of aluminum, aluminum alloy, copper, copper alloy, molybdenum, molybdenum alloy, tungsten, and tungsten alloy. The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy. The first electrode body film 58 may have a thermal conductivity of 100 W / m·K or more and 500 W / m·K or less.

[0147] The thermal conductivity of the first electrode main film 58 may have a value belonging to at least one of the ranges of 100 W / m·K to 150 W / m·K, 150 W / m·K to 200 W / m·K, 200 W / m·K to 250 W / m·K, 250 W / m·K to 300 W / m·K, 300 W / m·K to 350 W / m·K, 350 W / m·K to 400 W / m·K, 400 W / m·K to 450 W / m·K, and 450 W / m·K to 500 W / m·K. In this embodiment, the first electrode main film 58 is made of an aluminum alloy.

[0148] The first electrode main film 58 has a thickness greater than that of the first lower barrier film 57. The thickness of the first electrode main film 58 may be greater than 0 μm and less than 2 μm. The thickness of the first electrode main film 58 may have a value belonging to at least one of the ranges of greater than 0 nm and less than 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0149] The first electrode main film 58 is laminated on the first lower barrier film 57 and coats the first lower barrier film 57 in a film form. The first electrode main film 58 coats the plurality of first via electrodes 51 collectively in a film form via the first lower barrier film 57, and is electrically and thermally connected to the plurality of first via electrodes 51.

[0150] The first upper barrier film 59 may include either or both of a titanium film and a titanium alloy film (e.g., a titanium nitride film). The first upper barrier film 59 may have a single-layer structure made of a titanium film or a titanium alloy film. The first upper barrier film 59 may have a multilayer structure including a titanium film and a titanium alloy film stacked in this order from the first insulating layer 50 side.

[0151] The first upper barrier film 59 has a thickness less than the thickness of the first electrode main film 58. The thickness of the first upper barrier film 59 may be greater than 0 nm and less than 200 nm. The thickness of the first upper barrier film 59 may have a value belonging to at least one of the ranges of greater than 0 nm and less than 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm.

[0152] The first upper barrier film 59 is laminated on the first electrode main film 58 and coats the first electrode main film 58 in a film-like manner. The first upper barrier film 59 coats the first via electrodes 51 collectively in a film-like manner via the first lower barrier film 57 and the first electrode main film 58, and is electrically and thermally connected to the first via electrodes 51.

[0153] The semiconductor device 1 includes a second insulating layer 60 covering the first insulating layer 50. The second insulating layer 60 may be referred to as an "insulating second interlayer film." The second insulating layer 60 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second insulating layer 60 includes a silicon oxide film.

[0154] The second insulating layer 60 covers the first insulating layer 50 in the active region 8 and the control region 9. The second insulating layer 60 covers the first electrode layer 55 in the active region 8 in the form of a film. Specifically, the second insulating layer 60 covers the main transistor 10 via the first insulating layer 50 and the first electrode layer 55. The second insulating layer 60 collectively covers the multiple gate structures 30 and the multiple mesa portions 40 via the first insulating layer 50 and the first electrode layer 55.

[0155] In this embodiment, the second insulating layer 60 has a thickness less than that of the first insulating layer 50. The thickness of the second insulating layer 60 may be greater than that of the first insulating layer 50. In this embodiment, the thickness of the second insulating layer 60 is greater than the thickness (total thickness) of the first electrode layer 55. The thickness of the second insulating layer 60 may be less than the thickness (total thickness) of the first electrode layer 55.

[0156] The thickness of the second insulating layer 60 may be greater than 0 μm and less than or equal to 3 μm. The thickness of the second insulating layer 60 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm.

[0157] The semiconductor device 1 includes a second via electrode 61 embedded in the second insulating layer 60 in the active region 8. The second via electrode 61 may also be referred to as an "upper via electrode." The second via electrode 61 is embedded in the second insulating layer 60 in a layout different from the layout of the multiple first via electrodes 51.

[0158] Specifically, the second via electrode 61 is embedded in the second insulating layer 60 in a mesh (lattice) pattern in a plan view, and overlaps the main transistor 10 in a mesh-like pattern. The second via electrode 61 is formed at a distance from the control region 9 in a plan view, and does not cover the control region 9 (control circuit 12). The second via electrode 61 overlaps the plurality of gate structures 30 and the plurality of mesa portions 40 in a mesh-like pattern in a plan view. The second via electrode 61 overlaps the plurality of first via electrodes 51 in a mesh-like pattern in a plan view.

[0159] The second via electrode 61 is mechanically, electrically, and thermally connected to the first electrode layer 55. The second via electrode 61 is electrically and thermally connected to the main transistor 10 via the plurality of first via electrodes 51 and the first electrode layer 55. The second via electrode 61 is electrically and thermally connected to the plurality of first channels of the first system transistors 11A and the plurality of second channels of the second system transistors 11B via the plurality of first via electrodes 51 and the first electrode layer 55.

[0160] The second via electrode 61 has an electrode surface exposed from the second insulating layer 60. The electrode surface is recessed toward the first electrode layer 55 from the height position of the insulating surface of the second insulating layer 60. Of course, the electrode surface may form one flat surface together with the insulating surface.

[0161] The second via electrodes 61 each have a height (greater than 0 μm and equal to or less than 3 μm) corresponding to the thickness of the second insulating layer 60. In this embodiment, the height of the second via electrodes 61 is less than the height of the first via electrodes 51. Of course, if the thickness of the second insulating layer 60 is greater than the thickness of the first insulating layer 50, the height of the second via electrodes 61 may be greater than the height of the first via electrodes 51.

[0162] The second via electrode 61 has a second width W2 that is less than the width of the mesa portion 40. The second width W2 may be greater than the width of the mesa portion 40. The second width W2 is less than the width of the gate structure 30. The second width W2 may be greater than the width of the gate structure 30. The second width W2 may be approximately equal to the first width W1 of the first via electrode 51. The second width W2 may be greater or smaller than the first width W1. The second width W2 may be greater than 0 μm and equal to or less than 1 μm.

[0163] The second width W2 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, 0.4 μm to 0.5 μm, 0.5 μm to 0.6 μm, 0.6 μm to 0.7 μm, 0.7 μm to 0.8 μm, 0.8 μm to 0.9 μm, and 0.9 μm to 1 μm. The second width W2 is preferably 0.5 μm or less. The second width W2 is preferably 0.1 μm to 0.3 μm.

[0164] The second via electrode 61 integrally includes a plurality of first line portions 61a and a plurality of second line portions 61b. The plurality of first line portions 61a are arranged at intervals in the first direction X and extend linearly in the second direction Y. In other words, the plurality of first line portions 61a extend in the second direction Y in the form of stripes.

[0165] The multiple first line portions 61a are each arranged in the region between the multiple first via electrodes 51 at intervals in the first direction X from the multiple first via electrodes 51 in a plan view. Therefore, the multiple first line portions 61a do not overlap the multiple first via electrodes 51 in a plan view. The multiple first line portions 61a are each arranged in the middle of the region between the multiple first via electrodes 51 in a plan view, and extend parallel to the multiple first via electrodes 51.

[0166] The multiple first line portions 61a are each arranged in the region between the multiple mesa portions 40 at intervals in the first direction X from the multiple mesa portions 40 in a plan view. Therefore, the multiple first line portions 61a do not overlap the multiple mesa portions 40 in a plan view. The multiple first line portions 61a are each arranged in the middle of the region between the multiple mesa portions 40 and extend parallel to the multiple mesa portions 40.

[0167] In this embodiment, the multiple first line portions 61a overlap with the multiple gate structures 30 in a one-to-one correspondence. The multiple first line portions 61a extend linearly in the second direction Y following the extension direction of the corresponding gate structures 30. The multiple first line portions 61a are each disposed in the center of the multiple gate structures 30 in a plan view, and extend parallel to the multiple gate structures 30.

[0168] In this embodiment, the multiple first line portions 61a face the multiple gate structures 30 via the main surface insulating film 45. The multiple first line portions 61a face the buried electrodes 33 of the gate structures 30 corresponding to them in the stacking direction. Specifically, the multiple first line portions 61a face both the first buried electrodes 36 and the second buried electrodes 37 in the stacking direction.

[0169] The multiple first line portions 61a are each disposed in an area between the multiple recesses 56 of the first electrode layer 55 at intervals in the first direction X from the multiple recesses 56 in the plan view. Therefore, the multiple first line portions 61a do not overlap the multiple recesses 56. The multiple first line portions 61a are each disposed in the middle of the area between the multiple recesses 56 in the plan view, and extend parallel to the multiple recesses 56 in the plan view. This prevents the multiple first line portions 61a from being deformed due to the multiple recesses 56.

[0170] The multiple first line portions 61a have a second pitch P2. The second pitch P2 is the distance in the first direction X between the centers of the multiple first line portions 61a. The second pitch P2 is also the distance between the centers of the multiple gate structures 30. In this embodiment, the second pitch P2 is approximately equal to the first pitch P1 of the multiple first via electrodes 51. The second pitch P2 may be larger or smaller than the first pitch P1.

[0171] The second pitch P2 may be greater than 0 μm and equal to or less than 4 μm. The second pitch P2 may have a value belonging to at least one of the following ranges: greater than 0 μm and equal to or less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, and 3.5 μm to 4 μm. The second pitch P2 is preferably greater than 1 μm and equal to or less than 2.5 μm.

[0172] In this embodiment, the second width W2 of the first line portion 61a is approximately equal to the first width W1 of the plurality of first via electrodes 51. Of course, the second width W2 of the first line portion 61a may be different from the first width W1. The second width W2 of the first line portion 61a may be larger or smaller than the first width W1.

[0173] The second line portions 61b are each disposed in an area between the first line portions 61a, and extend linearly in a direction different from the direction in which the first line portions 61a extend. Specifically, the second line portions 61b extend linearly in the first direction X in the area between the first line portions 61a, and are arranged at intervals in the second direction Y. In other words, the second line portions 61b extend in stripes in the first direction X.

[0174] The second line portions 61b are connected to the first line portions 61a in a T-shape. The second line portions 61b include a plurality of second line portions 61b arranged on one side of the first line portions 61a in the first direction X, and a plurality of second line portions 61b arranged on the other side of the first line portions 61a in the first direction X.

[0175] The multiple second line portions 61b on one side are arranged offset in the second direction Y with respect to the multiple second line portions 61b on the other side, and each face a region between the multiple second line portions 61b on the other side in the first direction X. As a result, the multiple second line portions 61b, together with the multiple first line portions 61a, form a lattice-shaped second via electrode 61.

[0176] Of course, the second line portions 61b may be connected to the first line portions 61a in a cross shape. In this case, the second line portions 61b on one side face the second line portions 61b on the other side in the first direction X. However, a T-junction has a better ability to embed an electrode material into the connection portion than a cross.

[0177] The multiple second line portions 61b cross the multiple first via electrodes 51 in the first direction X in a plan view and are connected to the multiple first line portions 61a, respectively. That is, the multiple second line portions 61b form multiple intersections that cross (specifically, are perpendicular to) the multiple first via electrodes 51 in a plan view. The multiple second line portions 61b cross the multiple mesa portions 40 in the first direction X in a plan view. That is, the multiple second line portions 61b form multiple intersections that cross (specifically, are perpendicular to) the multiple mesa portions 40.

[0178] The second line portions 61b cross the recesses 56 of the first electrode layer 55 in the first direction X. That is, the second line portions 61b form multiple intersections where they intersect (specifically, are perpendicular to) the recesses 56. The second line portions 61b may have recesses that extend along the recesses 56 at the intersections. The second line portions 61b are arranged at intervals along the extension direction of the recesses 56. Therefore, defects in the shape of the second line portions 61b caused by the recesses 56 are suppressed.

[0179] In this embodiment, the multiple second line portions 61b straddle multiple gate structures 30 in a plan view. As a result, the multiple second line portions 61b face the multiple gate structures 30 in the stacking direction. The multiple second line portions 61b face the buried electrodes 33 of the gate structures 30 corresponding to them in the stacking direction. Specifically, the multiple second line portions 61b face both the first buried electrode 36 and the second buried electrode 37 in the stacking direction.

[0180] The second line portions 61b have a third pitch P3. The third pitch P3 is the distance in the second direction Y between the centers of the second line portions 61b. In this embodiment, the third pitch P3 is less than the first pitch P1. The third pitch P3 may be approximately equal to the first pitch P1. The third pitch P3 may be greater than the first pitch P1.

[0181] In this embodiment, the third pitch P3 is less than the second pitch P2. The third pitch P3 may be approximately equal to the second pitch P2. The third pitch P3 may be greater than the second pitch P2. The third pitch P3 may be greater than 0 μm and equal to or less than 4 μm.

[0182] The third pitch P3 may have a value belonging to at least one of the ranges of greater than 0 μm and equal to or less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, and 3.5 μm to 4 μm. The third pitch P3 is preferably equal to or greater than 0.5 μm and equal to or less than 1.5 μm.

[0183] In this embodiment, the second width W2 of the second line portion 61b is approximately equal to the first width W1 of the plurality of first via electrodes 51. Of course, the second width W2 of the second line portion 61b may be different from the first width W1. The second width W2 of the second line portion 61b may be larger or smaller than the first width W1.

[0184] In this embodiment, the second width W2 of the second line portion 61b is approximately equal to the second width W2 of the plurality of first line portions 61a, but of course the second width W2 of the second line portion 61b may be different from the second width W2 of the plurality of first line portions 61a. The second width W2 of the second line portion 61b may be larger than the second width W2 of the plurality of first line portions 61a. The second width W2 of the second line portion 61b may be smaller than the second width W2 of the plurality of first line portions 61a.

[0185] The second via electrodes 61 (including the first line portion 61a and the second line portion 61b) are embedded in mesh-like second via holes 62 formed in the second insulating layer 60. In this embodiment, the second via electrodes 61 each include a second barrier film 63 and a second via body electrode 64.

[0186] The second barrier film 63 may include either or both of a titanium film and a titanium alloy film (e.g., a titanium nitride film). The second barrier film 63 may have a single-layer structure made of a titanium film or a titanium alloy film. The second barrier film 63 may have a multilayer structure including a titanium film and a titanium alloy film stacked in this order from the wall surface side of the second via hole 62. It is preferable that the second barrier film 63 has the same configuration as the first barrier film 53.

[0187] The second barrier film 63 may have a thickness greater than 0 nm and less than or equal to 200 nm. The thickness of the second barrier film 63 may have a value belonging to at least one of the ranges of greater than 0 nm and less than or equal to 25 nm, 25 to 50 nm, 50 to 75 nm, 75 to 100 nm, 100 to 125 nm, 125 to 150 nm, 150 to 175 nm, and 175 to 200 nm.

[0188] The second barrier film 63 covers the electrode surface of the first electrode layer 55 and the wall surface of the second via hole 62 in a film-like manner, and is mechanically, electrically, and thermally connected to the first electrode layer 55. In this embodiment, the second barrier film 63 is connected to the first upper barrier film 59 of the first electrode layer 55.

[0189] The second via body electrode 64 includes at least one of aluminum, aluminum alloy, copper, copper alloy, molybdenum, molybdenum alloy, tungsten, and tungsten alloy. The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy. The second via body electrode 64 may have a thermal conductivity of 100 W / m·K or more and 500 W / m·K or less.

[0190] The thermal conductivity of the second via body electrode 64 may have a value belonging to at least one of the ranges of 100 W / m·K to 150 W / m·K, 150 W / m·K to 200 W / m·K, 200 W / m·K to 250 W / m·K, 250 W / m·K to 300 W / m·K, 300 W / m·K to 350 W / m·K, 350 W / m·K to 400 W / m·K, 400 W / m·K to 450 W / m·K, and 450 W / m·K to 500 W / m·K.

[0191] The second via body electrode 64 preferably has a thermal conductivity higher than that of the chip 2 (silicon) (=148 W / m·K). The second via body electrode 64 preferably has the same configuration as the first via body electrode 54. In this embodiment, the second via body electrode 64 is made of tungsten, which has excellent embedding properties in the second via hole 62.

[0192] The second via body electrode 64 is embedded in the second via hole 62 via the second barrier film 63, and is electrically and thermally connected to the first electrode layer 55. The second via body electrode 64 forms the electrode surface of the second via electrode 61. The second via electrode 61 does not necessarily have to have the second barrier film 63, and may have the second via body electrode 64 embedded directly in the second via hole 62.

[0193] The semiconductor device 1 includes a second electrode layer 65 disposed on the second insulating layer 60 in the active region 8. The second electrode layer 65 covers the main transistor 10 via the first insulating layer 50, the plurality of first via electrodes 51, the second insulating layer 60, and the second via electrode 61. Specifically, the second electrode layer 65 collectively covers the plurality of gate structures 30 and the plurality of mesa portions 40 via the first insulating layer 50, the plurality of first via electrodes 51, the second insulating layer 60, and the second via electrode 61.

[0194] The second electrode layer 65 may cover the entire areas of the plurality of gate structures 30 and the entire areas of the plurality of mesa portions 40. The second electrode layer 65 may cover the entire area of ​​the active region 8. The second electrode layer 65 may cover the plurality of gate structures 30 and the plurality of mesa portions 40 collectively in areas inward from both end portions of the plurality of gate structures 30.

[0195] The second electrode layer 65 collectively covers the second via electrodes 61 on the second insulating layer 60 and is mechanically, electrically, and thermally connected to the second via electrodes 61. Specifically, the second electrode layer 65 covers the entire areas of the multiple first line portions 61a and the entire areas of the multiple second line portions 61b and is mechanically, electrically, and thermally connected to the multiple first line portions 61a and the multiple second line portions 61b.

[0196] The second electrode layer 65 is electrically and thermally connected to the main transistor 10 via the plurality of first via electrodes 51, the first electrode layer 55, and the second via electrode 61. Specifically, the second electrode layer 65 is electrically and thermally connected to the plurality of second channels of the second system transistors 11B and the plurality of second channels of the second system transistors 11B via the second via electrode 61.

[0197] The second electrode layer 65 has an electrode surface that extends along the insulating surface of the second insulating layer 60. The electrode surface of the second electrode layer 65 has recesses 66 that are recessed toward the second via electrodes 61 in the portions that cover the second via electrodes 61. The recesses 66 extend in a mesh pattern following the layout of the second via electrodes 61.

[0198] In this embodiment, the second electrode layer 65 has a laminated structure including a second lower barrier film 67, a second electrode main film 68, and a second upper barrier film 69, which are laminated in this order from the second insulating layer 60 side.

[0199] The second lower barrier film 67 may include either or both of a titanium film and a titanium alloy film (e.g., a titanium nitride film). The second lower barrier film 67 may have a single-layer structure made of a titanium film or a titanium alloy film. The second lower barrier film 67 may have a multilayer structure including a titanium film and a titanium alloy film stacked in this order from the second insulating layer 60 side. The second lower barrier film 67 preferably has the same structure as the first lower barrier film 57 of the first electrode layer 55.

[0200] The second lower barrier film 67 may have a thickness greater than 0 nm and less than 200 nm. The thickness of the second lower barrier film 67 may have a value belonging to at least one of the ranges greater than 0 nm and less than 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm.

[0201] The second lower barrier film 67 coats the second insulating layer 60 in a film-like manner. The second lower barrier film 67 collectively coats the second via electrode 61 in a film-like manner. The second lower barrier film 67 penetrates into the second via hole 62 from above the second insulating layer 60, and is mechanically, electrically, and thermally connected to the second barrier film 63 and the second via body electrode 64.

[0202] The second electrode main body film 68 includes at least one of aluminum, aluminum alloy, copper, copper alloy, molybdenum, molybdenum alloy, tungsten, and tungsten alloy. The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy. The second electrode main body film 68 preferably has the same configuration as the first electrode main body film 58 of the first electrode layer 55. The second electrode main body film 68 may have a thermal conductivity of 100 W / m·K or more and 500 W / m·K or less.

[0203] The thermal conductivity of the second electrode main body film 68 may have a value belonging to at least one of the ranges of 100 W / m·K to 150 W / m·K, 150 W / m·K to 200 W / m·K, 200 W / m·K to 250 W / m·K, 250 W / m·K to 300 W / m·K, 300 W / m·K to 350 W / m·K, 350 W / m·K to 400 W / m·K, 400 W / m·K to 450 W / m·K, and 450 W / m·K to 500 W / m·K. In this embodiment, the second electrode main body film 68 is made of an aluminum alloy.

[0204] The second electrode main body film 68 has a thickness greater than that of the second lower barrier film 67. The second electrode main body film 68 may have a thickness greater than 0 μm and less than or equal to 2 μm. The thickness of the second electrode main body film 68 may have a value belonging to at least one of the ranges of greater than 0 nm and less than or equal to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0205] The second electrode main film 68 is laminated on the second lower barrier film 67 and coats the second lower barrier film 67 in a film form. The second electrode main film 68 coats the second via electrode 61 collectively in a film form via the second lower barrier film 67, and is electrically and thermally connected to the second via electrode 61.

[0206] The second upper barrier film 69 may include either or both of a titanium film and a titanium alloy film (e.g., a titanium nitride film). The second upper barrier film 69 may have a single-layer structure made of a titanium film or a titanium alloy film. The second upper barrier film 69 may have a multilayer structure including a titanium film and a titanium alloy film stacked in this order from the second insulating layer 60 side. The second upper barrier film 69 preferably has the same configuration as the first upper barrier film 59 of the first electrode layer 55.

[0207] The second upper barrier film 69 has a thickness less than the thickness of the second electrode main film 68. The thickness of the second upper barrier film 69 may be greater than 0 nm and less than 200 nm. The thickness of the second upper barrier film 69 may have a value belonging to at least one of the ranges of greater than 0 nm and less than 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm.

[0208] The second upper barrier film 69 is laminated on the second electrode main body film 68 and coats the second electrode main body film 68 in a film-like manner. The second upper barrier film 69 coats the second via electrode 61 collectively in a film-like manner via the second lower barrier film 67 and the second electrode main body film 68, and is electrically and thermally connected to the second via electrode 61.

[0209] The thickness (total thickness) of the second electrode layer 65 may be greater or smaller than the thickness (total thickness) of the first electrode layer 55. The thickness (total thickness) of the second electrode layer 65 may be approximately equal to the thickness (total thickness) of the first electrode layer 55.

[0210] The semiconductor device 1 includes a third insulating layer 70 that covers the second insulating layer 60 (see FIG. 2). The third insulating layer 70 may be referred to as a "third interlayer film." The third insulating layer 70 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the third insulating layer 70 includes a silicon oxide film.

[0211] The third insulating layer 70 covers the second insulating layer 60 in the active region 8 and the control region 9. The third insulating layer 70 covers the second electrode layer 65 in the active region 8 in the form of a film. Specifically, the third insulating layer 70 covers the main transistor 10 via the first insulating layer 50, the first electrode layer 55, the second insulating layer 60, and the second electrode layer 65. The third insulating layer 70 collectively covers the multiple gate structures 30 and the multiple mesa portions 40 via the first insulating layer 50, the first electrode layer 55, the second insulating layer 60, and the second electrode layer 65.

[0212] In this embodiment, the third insulating layer 70 has a thickness less than that of the first insulating layer 50. The thickness of the third insulating layer 70 may be greater than that of the first insulating layer 50. The thickness of the third insulating layer 70 may be greater or less than that of the second insulating layer 60. The thickness of the third insulating layer 70 may be greater or less than the thickness (total thickness) of the first electrode layer 55. The thickness of the third insulating layer 70 may be greater or less than the thickness (total thickness) of the second electrode layer 65.

[0213] The thickness of the third insulating layer 70 may be greater than 0 μm and less than or equal to 3 μm. The thickness of the third insulating layer 70 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm.

[0214] The semiconductor device 1 includes a pad opening 71 that exposes the second electrode layer 65 in the third insulating layer 70. The pad opening 71 exposes an inner portion of the second electrode layer 65 at a distance from the periphery of the second electrode layer 65.

[0215] In a cross-sectional view, the pad opening 71 exposes an area of ​​50% or more and less than 100% of the second electrode layer 65. The ratio of the pad opening 71 to the second electrode layer 65 may have a value belonging to at least one of the ranges of 50% or more and 60% or less, 60% or more and 70% or less, 70% or more and 80% or less, 80% or more and 90% or less, and 90% or more and less than 100%.

[0216] The semiconductor device 1 includes a first pad electrode 75 disposed on the third insulating layer 70 (second electrode layer 65) in the active region 8. The first pad electrode 75 may also be referred to as a "source pad electrode." The first pad electrode 75 is a terminal electrode to which one or more conductive connection members are connected.

[0217] For example, the conductive connecting member may be one or more metal clips. The conductive connecting member may be one or more bonding wires. The bonding wires may include at least one of gold wires, copper wires, and aluminum wires.

[0218] The first pad electrode 75 includes at least one of aluminum, aluminum alloy, copper, copper alloy, molybdenum, molybdenum alloy, tungsten, and tungsten alloy. The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy. The first pad electrode 75 may have a thermal conductivity of 100 W / m·K or more and 500 W / m·K or less.

[0219] The thermal conductivity of the first pad electrode 75 may have a value belonging to at least one of the ranges of 100 W / m·K to 150 W / m·K, 150 W / m·K to 200 W / m·K, 200 W / m·K to 250 W / m·K, 250 W / m·K to 300 W / m·K, 300 W / m·K to 350 W / m·K, 350 W / m·K to 400 W / m·K, 400 W / m·K to 450 W / m·K, and 450 W / m·K to 500 W / m·K. In this embodiment, the first pad electrode 75 is made of an aluminum alloy.

[0220] The first pad electrode 75 covers the main transistor 10 via the first insulating layer 50, the plurality of first via electrodes 51, the second insulating layer 60, the second via electrode 61, and the second electrode layer 65. Specifically, the first pad electrode 75 collectively covers the plurality of gate structures 30 and the plurality of mesa portions 40 via the first insulating layer 50, the plurality of first via electrodes 51, the second insulating layer 60, the second via electrode 61, and the second electrode layer 65.

[0221] The first pad electrode 75 may have a planar area larger than the planar area of ​​the first electrode layer 55. Of course, the planar area of ​​the first pad electrode 75 may be smaller than the planar area of ​​the first electrode layer 55. The first pad electrode 75 may have a planar area larger than the planar area of ​​the second electrode layer 65. Of course, the planar area of ​​the first pad electrode 75 may be smaller than the planar area of ​​the second electrode layer 65.

[0222] The first pad electrode 75 may cover the entire areas of the plurality of gate structures 30 and the entire areas of the plurality of mesa portions 40. The first pad electrode 75 may cover the entire area of ​​the active region 8. The first pad electrode 75 may cover the plurality of gate structures 30 and the plurality of mesa portions 40 collectively in areas inward from both end portions of the plurality of gate structures 30.

[0223] The first pad electrode 75 enters the pad opening 71 from above the third insulating layer 70 and is mechanically, electrically, and thermally connected to the second electrode layer 65 within the pad opening 71. The first pad electrode 75 is electrically and thermally connected to the main transistor 10 via a plurality of first via electrodes 51, the first electrode layer 55, the second via electrodes 61, and the second electrode layer 65.

[0224] Specifically, the first pad electrode 75 is electrically and thermally connected to the plurality of second channels of the second system transistor 11B and the plurality of second channels of the second system transistor 11B via the plurality of first via electrodes 51, the first electrode layer 55, the second via electrode 61 and the second electrode layer 65.

[0225] The first pad electrode 75 has an electrode surface that extends along the electrode surface of the second electrode layer 65 and the insulating surface of the third insulating layer 70. The electrode surface of the first pad electrode 75 may have depressions 76 that are depressed toward the depressions 66 of the second electrode layer 65 in the portions that cover the depressions 66 of the second electrode layer 65. The multiple depressions 76 may extend in a mesh pattern following the layout of the second via electrodes 61.

[0226] The first pad electrode 75 has a thickness greater than the thickness (total thickness) of the first electrode layer 55. The thickness of the first pad electrode 75 is greater than the thickness (total thickness) of the second electrode layer 65. In this embodiment, the thickness of the first pad electrode 75 is greater than the total thickness of the thickness (total thickness) of the first electrode layer 55 and the thickness (total thickness) of the second electrode layer 65. The thickness of the first pad electrode 75 may be smaller than the total thickness of the thickness (total thickness) of the first electrode layer 55 and the thickness (total thickness) of the second electrode layer 65.

[0227] The thickness of the first pad electrode 75 may be greater than 0 μm and less than 10 μm. The thickness of the first pad electrode 75 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm. The thickness of the first pad electrode 75 is preferably greater than or equal to 3 μm.

[0228] The semiconductor device 1 includes a plurality of second pad electrodes 80 disposed on the third insulating layer 70 in the control region 9. The second pad electrodes 80 may also be referred to as "control pad electrodes." The second pad electrodes 80 are terminal electrodes to which one or more conductive connection members are connected.

[0229] For example, the conductive connecting member may be one or more metal clips. The conductive connecting member may be one or more bonding wires. The bonding wires may include at least one of gold wires, copper wires, and aluminum wires.

[0230] The second pad electrode 80 includes at least one of aluminum, aluminum alloy, copper, copper alloy, molybdenum, molybdenum alloy, tungsten, and tungsten alloy. The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy. The second pad electrode 80 may have a thermal conductivity of 100 W / m·K or more and 500 W / m·K or less.

[0231] The thermal conductivity of the second pad electrode 80 may have a value belonging to at least one of the ranges of 100 W / m·K to 150 W / m·K, 150 W / m·K to 200 W / m·K, 200 W / m·K to 250 W / m·K, 250 W / m·K to 300 W / m·K, 300 W / m·K to 350 W / m·K, 350 W / m·K to 400 W / m·K, 400 W / m·K to 450 W / m·K, and 450 W / m·K to 500 W / m·K. In this embodiment, the second pad electrode 80 is made of an aluminum alloy.

[0232] The multiple second pad electrodes 80 each have a planar area smaller than the planar area of ​​the first pad electrode 75, and are arranged at intervals along the periphery of the control region 9 (the periphery of the first main surface 3). The planar area of ​​each second pad electrode 80 may be 1 / 10 or less of the planar area of ​​the first pad electrode 75.

[0233] The second pad electrode 80 is electrically connected to various functional circuits 13 to 21 in the control region 9. The second pad electrodes 80 are electrically connected to the control circuit 12 (any of the functional circuits 13 to 21) through a plurality of control wirings 81 and a plurality of control via electrodes 82 selectively routed on the first main surface 3.

[0234] The plurality of control wirings 81 may be selectively routed on either or both of the first insulating layer 50 and the second insulating layer 60. The control wirings 81 routed on the first insulating layer 50 may have a configuration similar to that of the first electrode layer 55. The control wirings 81 routed on the second insulating layer 60 may have a configuration similar to that of the second electrode layer 65.

[0235] The control via electrode 82 embedded in the first insulating layer 50 may have a configuration similar to that of the first via electrode 51 embedded in the first insulating layer 50. The control via electrode 82 embedded in the second insulating layer 60 may have a configuration similar to that of the second via electrode 61 embedded in the second insulating layer 60.

[0236] The control wiring 81 includes a plurality of gate wirings 83 that electrically connect the control circuit 12 and the plurality of gate structures 30 (see FIG. 2). The plurality of gate wirings 83 may be selectively routed on either or both of the first insulating layer 50 and the second insulating layer 60.

[0237] The plurality of gate wirings 83 are electrically connected to any of the functional circuits 13 to 21 (at least the gate drive circuit 13) of the control circuit 12 through the plurality of control via electrodes 82 in the control region 9, and are electrically connected to the plurality of gate structures 30 through the plurality of control via electrodes 82 in the active region 8. In this embodiment, the plurality of gate wirings 83 are electrically connected to both the first buried electrode 36 and the second buried electrode 37.

[0238] The semiconductor device 1 includes a third pad electrode 85 covering the second main surface 4. The third pad electrode 85 may also be referred to as a "drain pad electrode." The third pad electrode 85 is mechanically and electrically connected to the first region 6 on the second main surface 4. The third pad electrode 85 is electrically connected to the main drain MD of the main transistor 10 and the control circuit 12.

[0239] The third pad electrode 85 covers the entire second main surface 4 and is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The third pad electrode 85 may be formed at a distance inward from the periphery of the second main surface 4, leaving the periphery of the second main surface 4 exposed.

[0240] As described above, the semiconductor device 1 includes the first electrode layer 55, the second via electrodes 61 (via electrodes), and the second electrode layer 65. The second via electrodes 61 are laid in a mesh-like pattern on the first electrode layer 55. The second electrode layer 65 is disposed on the mesh-like second via electrodes 61.

[0241] This configuration provides a semiconductor device 1 with a novel layout. For example, in this semiconductor device 1, the heat transfer efficiency between the first electrode layer 55 and the second electrode layer 65 is improved by the second via electrodes 61 arranged in a mesh pattern. This improves heat dissipation. This configuration is also effective in reducing the resistance (on-resistance) between the first electrode layer 55 and the second electrode layer 65 and improving the active clamping resistance.

[0242] The first electrode layer 55 may have recesses 56 extending linearly in one direction (second direction Y). With this configuration, the mesh-like second via electrodes 61 can avoid design rule limitations caused by the recesses 56, while the volume of the second via electrodes 61 can be increased.

[0243] In this case, the second via electrode 61 may include a first line portion 61a extending linearly along the recess 56 at a distance from the recess 56. The second via electrode 61 may include a second line portion 61b extending linearly from the first line portion 61a toward the recess 56 and intersecting the recess 56.

[0244] From another perspective, the semiconductor device 1 includes a first insulating layer 50, a plurality of first via electrodes 51, a first electrode layer 55, a second insulating layer 60, a second via electrode 61, and a second electrode layer 65. The plurality of first via electrodes 51 are embedded in the first insulating layer 50.

[0245] The first electrode layer 55 is connected to a plurality of first via electrodes 51 on the first insulating layer 50. The second insulating layer 60 covers the first electrode layer 55. The second via electrodes 61 are embedded in the second insulating layer 60 in a mesh pattern and connected to the first electrode layer 55. The second electrode layer 65 is connected to the second via electrodes 61 on the second insulating layer 60.

[0246] This configuration provides the semiconductor device 1 having a novel layout. For example, in this semiconductor device 1, the heat transfer efficiency between the first electrode layer 55 and the second electrode layer 65 is improved by the second via electrodes 61 arranged in a mesh pattern.

[0247] Furthermore, this configuration makes it possible to increase the volume of the second via electrode 61 while avoiding design rule limitations imposed by the underlying structure (layout of the plurality of first via electrodes 51) by using the mesh-like second via electrode 61. Therefore, the volume of the second insulating layer 60 interposed between the first electrode layer 55 and the second electrode layer 65 is reduced by the second via electrode 61.

[0248] This appropriately improves heat dissipation. Such a configuration is also effective in reducing the resistance (on-resistance) between the first electrode layer 55 and the second electrode layer 65 and improving the active clamp withstand capability.

[0249] The second via electrode 61 may intersect with the plurality of first via electrodes 51 in a plan view. The first via electrodes 51 may be arranged at intervals in a first direction X in a plan view, and may each extend in a line shape in a second direction Y intersecting the first direction X.

[0250] The second via electrode 61 may have a plurality of first line portions 61a and a plurality of second line portions 61b. The plurality of first line portions 61a may be arranged at intervals in the first direction X in a plan view, and may each extend linearly in the second direction Y. The plurality of second line portions 61b may be arranged at intervals in the second direction Y in regions between the plurality of first line portions 61a in a plan view, and may each extend linearly in the first direction X.

[0251] The multiple first line portions 61a may be arranged in regions between the multiple first via electrodes 51 in a plan view. The multiple second line portions 61b may intersect with the multiple first via electrodes 51 in a plan view. The multiple second line portions 61b may be connected to the multiple first line portions 61a in a T-shape. The interval between the multiple second line portions 61b in the second direction Y may be less than the interval between the multiple first line portions 61a in the first direction X.

[0252] The multiple first via electrodes 51 may be arranged at a pitch of 4 μm or less. The multiple first line portions 61a may be arranged at a pitch of 4 μm or less. The multiple second line portions 61b may be arranged in the second direction Y at a pitch of 4 μm or less. Each of the multiple first via electrodes 51 may have a width of 1 μm or less. The second via electrode 61 may have a width of 1 μm or less.

[0253] The semiconductor device 1 may include a chip 2 and a main transistor 10 (functional device). The main transistor 10 may be formed on the chip 2. In this case, a first insulating layer 50 may cover the functional device on the chip 2. A plurality of first via electrodes 51 may be electrically connected to the main transistor 10.

[0254] According to this configuration, the volume of the second via electrode 61 can be increased while avoiding design rule restrictions imposed by the underlying structure (layout of the main transistor 10) by using the mesh-like second via electrode 61. Furthermore, according to this configuration, heat generated in the main transistor 10 is transferred to the second electrode layer 65 via the multiple first via electrodes 51, the first electrode layer 55, and the mesh-like second via electrode 61. This appropriately suppresses a temperature rise in the main transistor 10.

[0255] The main transistor 10 may include a plurality of gate structures 30 and a plurality of channels. The plurality of gate structures 30 may be formed in the chip 2. The plurality of channels may be formed in regions along the plurality of gate structures 30 within the chip 2, respectively. In this case, the plurality of first via electrodes 51 may be electrically connected to the plurality of channels.

[0256] From another perspective, the semiconductor device 1 includes a chip 2, a main transistor 10 (functional device), a first electrode layer 55, a second insulating layer 60, a second via electrode 61 (via electrode), and a second electrode layer 65. The main transistor 10 is formed on the chip 2.

[0257] The first electrode layer 55 is disposed on the chip 2 and covers the main transistor 10 in a planar view. The second via electrodes 61 are laid in a mesh-like pattern on the first electrode layer 55 and cover the main transistor 10 in a mesh-like pattern in a planar view. The second electrode layer 65 is disposed on the second via electrodes 61 and covers the main transistor 10 in a planar view.

[0258] This configuration provides the semiconductor device 1 having a novel layout. For example, in this semiconductor device 1, the heat transfer efficiency between the first electrode layer 55 and the second electrode layer 65 is improved by the second via electrodes 61 arranged in a mesh pattern.

[0259] Furthermore, with this configuration, the volume of the second via electrode 61 can be increased while avoiding design rule limitations imposed by the underlying structure (layout of the main transistor 10) by using the mesh-like second via electrode 61. This appropriately improves heat dissipation. Such a configuration is also effective in reducing the resistance value (on-resistance value) between the first electrode layer 55 and the second electrode layer 65 and improving the active clamp withstand capability.

[0260] The main transistor 10 may have a plurality of gate structures 30 formed on the chip 2. In this case, the second via electrode 61 may overlap the plurality of gate structures 30 in a planar view. The plurality of gate structures 30 may be arranged at intervals in a first direction X in a planar view, and may each extend linearly in a second direction Y intersecting the first direction X.

[0261] The second via electrode 61 may have a plurality of first line portions 61a and a plurality of second line portions 61b. The plurality of first line portions 61a may be arranged at intervals in the first direction X in a plan view, and may each extend linearly in the second direction Y. The plurality of second line portions 61b may be arranged at intervals in the second direction Y in regions between the plurality of first line portions 61a in a plan view, and may each extend linearly in the first direction X.

[0262] The plurality of gate structures 30 may define a mesa portion 40 in the chip 2. The plurality of first line portions 61a may be arranged directly above the plurality of gate structures 30 in a planar view. The plurality of second line portions 61b may intersect with the mesa portion 40 in a planar view. The width of the mesa portion 40 may be less than the width of the plurality of gate structures 30. The plurality of second line portions 61b may be connected to the plurality of first line portions 61a in a T-shape.

[0263] The semiconductor device 1 may include a plurality of first via electrodes 51 (lower via electrodes). The plurality of first via electrodes 51 may be embedded in the first insulating layer 50 and electrically connected to the main transistor 10. In this case, the first electrode layer 55 may be connected to the plurality of first via electrodes 51 on the first insulating layer 50. The second via electrode 61 may intersect with the plurality of first via electrodes 51 in a plan view.

[0264] The second via electrodes 61 according to the first to fourth modified examples will be described below. Figures 20A to 20D are plan views showing the layouts of the second via electrodes 61 according to the first to fourth modified examples.

[0265] 20A (first modified example), the second via electrode 61 includes a plurality of sub-via portions 61c in addition to a plurality of first line portions 61a and a plurality of second line portions 61b. The sub-via portions 61c are respectively arranged in a plurality of via spaces S partitioned by the plurality of first line portions 61a and the plurality of second line portions 61b. That is, in this embodiment, the volume of the second via electrode 61 is increased by the plurality of sub-via portions 61c.

[0266] In this embodiment, the multiple sub-via parts 61c are each arranged in a one-to-many correspondence with one corresponding via space S. Of course, the multiple sub-via parts 61c may also be arranged in a one-to-one correspondence with one corresponding via space S. The layout of the multiple sub-via parts 61c in one via space S will be described below.

[0267] In this embodiment, the sub-via portions 61c are respectively arranged in the via space S at intervals from the first line portions 61a and the second line portions 61b. Of course, at least one or all of the sub-via portions 61c may be connected to either one or both of the first line portion 61a and the second line portion 61b.

[0268] In this embodiment, the sub-via portions 61c are arranged at intervals in the first direction X and extend in a line shape (rectangular shape) in the second direction Y. That is, the sub-via portions 61c extend in a stripe shape in the second direction Y in a plan view. The planar shape of the sub-via portions 61c is arbitrary. The sub-via portions 61c may be formed in a triangular shape, a quadrangular shape, a pentagonal shape, a hexagonal shape, a circular shape, an elliptical shape, or the like in a plan view.

[0269] The multiple sub-via portions 61c are each arranged at intervals in the first direction X from the first via electrode 51 in a plan view. Specifically, the multiple first line portions 61a are each arranged in a region between the first via electrode 51 and the first line portions 61a in a plan view, and do not overlap the multiple first via electrodes 51. The multiple first line portions 61a are each arranged in an intermediate portion of the region between the first via electrode 51 and the first line portions 61a in a plan view, and extend parallel to the first via electrode 51 and the first line portions 61a.

[0270] In this embodiment, the sub-via portions 61c overlap both the gate structure 30 and the mesa portion 40 in plan view. In this embodiment, the sub-via portions 61c face the gate structures 30 via the main surface insulating film 45. The sub-via portions 61c face the buried electrodes 33 of the gate structures 30 corresponding to them in the stacking direction. Specifically, the sub-via portions 61c face both the first buried electrode 36 and the second buried electrode 37 in the stacking direction.

[0271] The sub-via portions 61c may be arranged at intervals from the mesa portion 40 in the first direction X in a plan view, and may overlap only the gate structure 30. The sub-via portions 61c may be arranged at intervals from the gate structure 30 in the first direction X in a plan view, and may overlap only the mesa portion 40.

[0272] The sub-via portions 61c are arranged at intervals in the first direction X from the depression 56 of the first electrode layer 55. This prevents the sub-via portions 61c from being deformed due to the depression 56. The sub-via portions 61c extend parallel to the depression 56. Of course, the sub-via portions 61c may have portions that overlap the first via electrode 51 (depression 56) in a plan view.

[0273] 20B (second modified example), the second via electrode 61 includes a plurality of sub-via portions 61c, as in the first modified example. In this embodiment, the plurality of sub-via portions 61c are arranged in a one-to-many correspondence with one corresponding via space S spaced apart from the plurality of first line portions 61a and the plurality of second line portions 61b. At least one or all of the sub-via portions 61c may be connected to either one or both of the first line portion 61a and the second line portion 61b.

[0274] In this embodiment, the sub-via portions 61c are arranged in a matrix at intervals in the first direction X and the second direction Y in the corresponding via spaces S. In this embodiment, the sub-via electrodes are formed in a rectangular shape in a plan view. The planar shape of the sub-via portions 61c is arbitrary. The sub-via portions 61c may be formed in a triangular, quadrangular, pentagonal, hexagonal, circular, elliptical, or other shape in a plan view.

[0275] The multiple sub-via portions 61c are each arranged at intervals in the first direction X from the first via electrode 51 in a plan view. Specifically, the multiple first line portions 61a are each arranged in a region between the first via electrode 51 and the first line portions 61a in a plan view, and do not overlap the multiple first via electrodes 51. The multiple first line portions 61a are each arranged in an intermediate portion of the region between the first via electrode 51 and the first line portions 61a in a plan view, and extend parallel to the first via electrode 51 and the first line portions 61a.

[0276] In this embodiment, the sub-via portions 61c overlap both the gate structure 30 and the mesa portion 40 in plan view. In this embodiment, the sub-via portions 61c face the gate structures 30 via the main surface insulating film 45. The sub-via portions 61c face the buried electrodes 33 of the gate structures 30 corresponding to them in the stacking direction. Specifically, the sub-via portions 61c face both the first buried electrode 36 and the second buried electrode 37 in the stacking direction.

[0277] The sub-via portions 61c may be arranged at intervals from the mesa portion 40 in the first direction X in a plan view, and may overlap only the gate structure 30. The sub-via portions 61c may be arranged at intervals from the gate structure 30 in the first direction X in a plan view, and may overlap only the mesa portion 40.

[0278] The sub-via portions 61c are arranged at intervals in the first direction X from the depression 56 of the first electrode layer 55. This prevents the sub-via portions 61c from being deformed due to the depression 56. The sub-via portions 61c extend parallel to the depression 56. Of course, the sub-via portions 61c may have portions that overlap the first via electrode 51 (depression 56) in a plan view.

[0279] 20C (third modified example), the second via electrode 61 includes a plurality of sub-via portions 61c, as in the first modified example. In this embodiment, the plurality of sub-via portions 61c are each arranged in a one-to-many correspondence with one corresponding via space S spaced apart from the plurality of first line portions 61a and the plurality of second line portions 61b. At least one or all of the sub-via portions 61c may be connected to either one or both of the first line portion 61a and the second line portion 61b.

[0280] In this embodiment, the sub-via portions 61c extend linearly (rectangularly) in the first direction X in the corresponding via spaces S, and are arranged at intervals in the second direction Y. In other words, the sub-via portions 61c extend in stripes in the first direction X.

[0281] The sub-via portions 61c cross the first via electrode 51 in the first direction X in a planar view. That is, the sub-via portions 61c form a plurality of intersections that cross (specifically, orthogonal to) the first via electrode 51 in a planar view. The sub-via portions 61c cross the mesa portion 40 in the first direction X in a planar view. That is, the sub-via portions 61c form a plurality of intersections that cross (specifically, orthogonal to) the mesa portion 40.

[0282] The sub-via portions 61c cross the depressions 56 of the first electrode layer 55 in the first direction X. That is, the sub-via portions 61c form a plurality of intersections that intersect (specifically, perpendicular to) the depressions 56. The sub-via portions 61c are arranged at intervals along the extension direction of the depressions 56. Therefore, shape defects of the sub-via portions 61c caused by the depressions 56 are suppressed.

[0283] In this embodiment, the sub-via portions 61c straddle the gate structures 30 in a plan view. As a result, the sub-via portions 61c face the gate structures 30 in the stacking direction. The sub-via portions 61c face the buried electrodes 33 of the gate structures 30 corresponding to the sub-via portions 61c in the stacking direction. Specifically, the sub-via portions 61c face both the first buried electrode 36 and the second buried electrode 37 in the stacking direction.

[0284] The sub-via portions 61c may be arranged at intervals in the first direction X from the gate structure 30 in a plan view, and may overlap only with the mesa portion 40. In other words, the sub-via portions 61c may partially intersect with the mesa portion 40.

[0285] 20D (fourth modified example), the second via electrode 61 includes a plurality of sub-via portions 61c, as in the first modified example. In this embodiment, the plurality of sub-via portions 61c are arranged in a one-to-one correspondence with one corresponding via space S spaced apart from the plurality of first line portions 61a and the plurality of second line portions 61b. At least one or all of the sub-via portions 61c may be connected to either one or both of the first line portion 61a and the second line portion 61b.

[0286] The configuration of one sub-via portion 61c will be described below. In this embodiment, the sub-via portion 61c is formed in a ring shape in a plan view. In this embodiment, the sub-via portion 61c is formed in a polygonal ring shape (quadratic ring shape) having four sides extending parallel to the plurality of first line portions 61a and the plurality of second line portions 61b. The sub-via portion 61c may be formed in a circular ring shape or an elliptical ring shape.

[0287] The sub-via portion 61c includes a plurality of first portions 61c1 extending in the first direction X and a plurality of second portions 61c2 extending in the second direction Y. In this embodiment, the plurality of first portions 61c1 extend in a linear (rectangular) shape in the first direction X and are arranged at intervals in the second direction Y. In other words, the plurality of first portions 61c1 extend in a stripe shape in the first direction X in a plan view.

[0288] The multiple first portions 61c1 cross the first via electrode 51 in the first direction X in a plan view. That is, the multiple first portions 61c1 form multiple intersections that cross (specifically, orthogonal to) the first via electrode 51 in a plan view. The multiple first portions 61c1 cross the mesa portion 40 in the first direction X in a plan view. That is, the multiple first portions 61c1 form multiple intersections that cross (specifically, orthogonal to) the mesa portion 40.

[0289] The multiple first portions 61c1 cross the recess 56 of the first electrode layer 55 in the first direction X. That is, the multiple first portions 61c1 form multiple intersections that intersect (specifically, perpendicular to) the recess 56. The multiple first portions 61c1 are arranged at intervals along the extension direction of the recess 56. Therefore, shape defects of the multiple first portions 61c1 caused by the recess 56 are suppressed.

[0290] In this embodiment, the multiple first portions 61c1 straddle multiple gate structures 30 in a plan view. As a result, the multiple first portions 61c1 face the multiple gate structures 30 in the stacking direction. The multiple first portions 61c1 face the buried electrodes 33 of the gate structures 30 corresponding to the stacking direction. Specifically, the multiple first portions 61c1 face both the first buried electrode 36 and the second buried electrode 37 in the stacking direction.

[0291] The multiple first portions 61c1 may be arranged at intervals in the first direction X from the gate structure 30 in a plan view and may overlap only with the mesa portion 40. In other words, the multiple first portions 61c1 may partially intersect with the mesa portion 40.

[0292] In this embodiment, the second portions 61c2 are arranged at intervals in the first direction X and extend in lines (rectangular shapes) in the second direction Y. That is, the second portions 61c2 extend in stripes in the second direction Y in a plan view.

[0293] The multiple second portions 61c2 are each arranged at intervals in the first direction X from the first via electrode 51 in a plan view. Specifically, the multiple first line portions 61a are each arranged in a region between the first via electrode 51 and the first line portions 61a in a plan view, and do not overlap the multiple first via electrodes 51. The multiple first line portions 61a are each arranged in an intermediate portion of the region between the first via electrode 51 and the first line portions 61a in a plan view, and extend parallel to the first via electrode 51 and the first line portions 61a.

[0294] In this embodiment, the multiple second portions 61c2 overlap both the gate structure 30 and the mesa portion 40 in plan view. In this embodiment, the multiple second portions 61c2 face the multiple gate structures 30 via the main surface insulating film 45. The multiple second portions 61c2 face the buried electrodes 33 of the gate structures 30 corresponding to them in the stacking direction. Specifically, the multiple second portions 61c2 face both the first buried electrode 36 and the second buried electrode 37 in the stacking direction.

[0295] The second portions 61c2 may be spaced apart from the mesa portion 40 in the first direction X in a plan view, and may overlap only with the gate structure 30. The second portions 61c2 may be spaced apart from the gate structure 30 in the first direction X in a plan view, and may overlap only with the mesa portion 40.

[0296] The second portions 61c2 are arranged at intervals in the first direction X from the depression 56 of the first electrode layer 55. This prevents the second portions 61c2 from being deformed due to the depression 56. The second portions 61c2 extend parallel to the depression 56. Of course, the second portions 61c2 may have portions that overlap the first via electrode 51 (depression 56) in a plan view.

[0297] Although specific embodiments have been described above, the specific embodiments may be embodied in other forms. For example, in the above-described embodiment, an example has been shown in which the gate signal VG is applied to the first buried electrode 36. However, the first electrode layer 55 may be electrically connected to the first buried electrode 36 (the lead-out portion) through the first via electrode 51. In this case, the first buried electrode 36 is formed as a field plate.

[0298] For example, in the above-described embodiment, the semiconductor device 1 includes the active region 8 (main transistor 10) and the control region 9 (control circuit 12). However, the semiconductor device 1 does not necessarily have to include the control region 9 (control circuit 12), and may include only the active region 8 (main transistor 10).

[0299] Below are examples of features extracted from this specification and the accompanying drawings. Below, alphanumeric characters in parentheses represent corresponding components in the specific embodiments described above, but are not intended to limit the scope of each clause to the specific embodiments described above. The "semiconductor device" in the following clauses may be replaced with "semiconductor switching device," "semiconductor control device," "semiconductor module," "electronic circuit," "semiconductor circuit," "intelligent power device," "intelligent power module," "intelligent power switch," etc., as necessary.

[0300] [A1] A semiconductor device (1) including a first electrode layer (55), via electrodes (61) laid in a mesh pattern on the first electrode layer (55), and a second electrode layer (65) arranged on the via electrodes (61).

[0301] [A2] The semiconductor device (1) described in A1, wherein the via electrode (61) is mechanically, electrically, and thermally connected to the first electrode layer (55), and the second electrode layer (65) is mechanically, electrically, and thermally connected to the via electrode (61).

[0302] [A3] The semiconductor device (1) according to A1 or A2, wherein the first electrode layer (55) includes an electrode surface having depressions (56) extending linearly in one direction.

[0303] [A4] The semiconductor device (1) according to A3, wherein the via electrode (61) includes a first line portion (61a) extending in a line along the recess (56) at a distance from the recess (56).

[0304] [A5] The semiconductor device (1) described in A4, wherein the via electrode (61) includes a second line portion (61b) that is drawn out in a line shape from the first line portion (61a) toward the recess (56) and intersects with the recess (56).

[0305] [A6] The semiconductor device (1) described in A1 or A2, wherein the via electrode (61) includes a plurality of first line portions (61a) arranged at intervals in a first direction (X) in a planar view and each extending in a line in a second direction (Y) intersecting the first direction (X), and a plurality of second line portions (61b) arranged at intervals in the second direction (Y) in a region between the plurality of first line portions (61a) in a planar view and each extending in a line in the first direction (X).

[0306] [A7] The semiconductor device (1) described in A6, wherein the plurality of first line portions (61a) are arranged in the first direction (X) in a planar view at a first pitch (P1), and the plurality of second line portions (61b) are arranged in the second direction (Y) in a planar view at a second pitch (P2) narrower than the first pitch (P1).

[0307] [A8] The semiconductor device (1) according to A7, wherein the first pitch (P1) is 4 μm or less.

[0308] [A9] The semiconductor device (1) according to A8, wherein the first pitch (P1) is 2.5 μm or less.

[0309] [A10] The semiconductor device (1) according to any one of A6 to A9, wherein the plurality of first line portions (61a) each have a first width (W1) of 1 μm or less, and the plurality of second line portions (61b) each have a second width (W2) of 1 μm or less.

[0310] [A11] The semiconductor device (1) according to A10, wherein the first width (W1) is 0.3 μm or less, and the second width (W2) is 0.3 μm or less.

[0311] [A12] A semiconductor device (1) described in any one of A6 to A11, wherein the first electrode layer (55) includes an electrode surface having a depression (56) extending linearly in the second direction (Y), the plurality of first line portions (61a) are arranged at intervals from the depression (56) in the first direction (X), and the plurality of second line portions (61b) intersect the depression (56).

[0312] [A13] The semiconductor device (1) according to A12, wherein the plurality of recesses (56) are formed at intervals in the first direction (X).

[0313] [A14] The semiconductor device (1) according to any one of A1 to A13, wherein the first electrode layer (55) contains aluminum, the via electrode (61) contains tungsten, and the second electrode layer (65) contains aluminum.

[0314] [A15] The semiconductor device (1) according to any one of A1 to A14, further including a pad electrode (75) arranged on the second electrode layer (65).

[0315] [A16] The semiconductor device (1) according to A15, wherein the pad electrode (75) has a thickness greater than either or both of the thickness of the first electrode layer (55) and the thickness of the second electrode layer (65).

[0316] [A17] The semiconductor device (1) according to A15 or A16, wherein the pad electrode (75) contains aluminum.

[0317] [A18] A semiconductor device (1) according to any one of A1 to A17, further comprising a lower via electrode (51), the first electrode layer (55) being arranged on the lower via electrode (51), and the via electrode (61) intersecting the lower via electrode (51) in a planar view.

[0318] [A19] The semiconductor device (1) according to A18, wherein the via electrode (61) has a plurality of intersections with the lower via electrode (51) in a plan view.

[0319] [A20] A semiconductor device (1) described in any one of A1 to A19, further including a chip 2 and a functional device (10, 11) formed on the chip 2, wherein the first electrode layer (55) overlaps the functional device (10, 11) in a planar view, and the via electrode (61) overlaps the functional device (10, 11) in a mesh-like pattern in a planar view.

[0320] [A21] The semiconductor device (1) according to A20, wherein the functional device (10, 11) includes a transistor (10, 11).

[0321] [A22] The semiconductor device (1) according to A21, wherein the transistors (10, 11) include a first system transistor (11A) and a second system transistor (11B) that are electrically independent from each other.

[0322] [A23] The semiconductor device (1) according to A22, wherein both the first system transistor (11A) and the second system transistor (11B) are controlled to be simultaneously turned on in response to a plurality of gate signals (VG, VG1, VG2) during normal operation.

[0323] [A24] The semiconductor device (1) according to A23, wherein either the first system transistor (11A) or the second system transistor (11B) is controlled to change from an off state to an on state in response to a plurality of gate signals (VG, VG1, VG2) during active clamp operation.

[0324] [B1] A semiconductor device (1) including a first insulating layer (50), a plurality of first via electrodes (51) embedded in the first insulating layer (50), a first electrode layer (55) connected to the plurality of first via electrodes (51) on the first insulating layer (50), a second insulating layer (60) covering the first electrode layer (55), second via electrodes (61) embedded in the second insulating layer (60) in a mesh pattern and connected to the first electrode layer (55), and a second electrode layer (65) connected to the second via electrodes (61) on the second insulating layer (60).

[0325] [B2] The semiconductor device (1) according to B1, wherein the second via electrode (61) intersects with a plurality of the first via electrodes (51) in a plan view.

[0326] [B3] The semiconductor device (1) described in B1 or B2, wherein the plurality of first via electrodes (51) are arranged at intervals in a first direction (X) in a planar view and extend in a line shape in a second direction (Y) intersecting the first direction (X).

[0327] [B4] The semiconductor device (1) described in B3, wherein the second via electrode (61) includes a plurality of first line portions (61a) arranged at intervals in the first direction (X) in a planar view and each extending in a line in the second direction (Y), and a plurality of second line portions (61b) arranged at intervals in the second direction (Y) in a region between the plurality of first line portions (61a) in a planar view and each extending in a line in the first direction (X).

[0328] [B5] The semiconductor device (1) described in B4, wherein the plurality of first line portions (61a) are respectively arranged in areas between the plurality of first via electrodes (51) in a planar view, and the plurality of second line portions (61b) intersect the plurality of first via electrodes (51) in a planar view.

[0329] [B6] The semiconductor device (1) according to B4 or B5, wherein the second line portions (61b) are connected to the first line portions (61a) in a T-shape.

[0330] [B7] The semiconductor device (1) according to any one of B4 to B6, wherein the pitch (P3) of the plurality of second line portions (61b) in the second direction (Y) is less than the pitch (P2) of the plurality of first line portions (61a) in the first direction (X).

[0331] [B8] A semiconductor device (1) according to any one of B4 to B7, wherein the plurality of first via electrodes (51) are arranged at a pitch (P1) of 4 μm or less, and the plurality of first line portions (61a) are arranged at a pitch (P2) of 4 μm or less.

[0332] [B9] The semiconductor device (1) according to any one of B4 to B8, wherein the second line portions (61b) are arranged in the second direction (Y) at a pitch (P3) of 4 μm or less.

[0333] [B10] A semiconductor device (1) according to any one of B1 to B9, wherein the plurality of first via electrodes (51) each have a width (W1) of 1 μm or less, and the second via electrode (61) has a width (W2) of 1 μm or less.

[0334] [B11] A semiconductor device (1) according to any one of B1 to B10, further comprising a chip (2) and a functional device (10, 11) formed on the chip (2), wherein the first insulating layer (50) covers the functional device (10, 11) on the chip (2), and the first via electrode (51) is electrically connected to the functional device (10, 11).

[0335] [B12] The semiconductor device (1) described in B11, wherein the functional device (10, 11) includes a plurality of gate structures (30) formed in the chip (2) and a plurality of channels formed in regions along the plurality of gate structures (30) within the chip (2), and the plurality of first via electrodes (51) are electrically connected to the plurality of channels.

[0336] [B13] A semiconductor device (1) including: a chip (2); functional devices (10, 11) formed on the chip (2); a first electrode layer (55) arranged on the chip (2) and covering the functional devices (10, 11) in a planar view; via electrodes (61) laid in a mesh-like pattern on the first electrode layer (55) and covering the functional devices (10, 11) in a mesh-like pattern in a planar view; and a second electrode layer (65) arranged on the via electrodes (61) and covering the functional devices (10, 11) in a planar view.

[0337] [B14] The semiconductor device (1) described in B13, wherein the functional device (10, 11) has a plurality of gate structures (30) formed on the chip (2), and the via electrode covers the plurality of gate structures (30) in a planar view.

[0338] [B15] The semiconductor device (1) according to B14, wherein the plurality of gate structures (30) are arranged at intervals in a first direction (X) in a planar view and extend in a line shape in a second direction (Y) intersecting the first direction (X).

[0339] [B16] The semiconductor device (1) described in B15, wherein the via electrode includes a plurality of first line portions (61a) arranged at intervals in the first direction (X) in a planar view and each extending in a line in the second direction (Y), and a plurality of second line portions (61b) arranged at intervals in the second direction (Y) in a region between the plurality of first line portions (61a) in a planar view and each extending in a line in the first direction (X).

[0340] [B17] The semiconductor device (1) described in B16, wherein the plurality of gate structures (30) define a mesa portion (40) on the chip (2), the plurality of first line portions (61a) are arranged directly above the plurality of gate structures (30) in a planar view, and the plurality of second line portions (61b) are arranged directly above the mesa portion (40) in a planar view.

[0341] [B18] The semiconductor device (1) according to B17, wherein the mesa portion (40) has a width less than the width of the plurality of gate structures (30).

[0342] [B19] The semiconductor device (1) according to any one of B16 to B18, wherein the second line portions (61b) are connected to the first line portions (61a) in a T-shape.

[0343] [B20] A semiconductor device (1) described in any one of B13 to B19, further including a plurality of lower via electrodes (51) electrically connected to the functional devices (10, 11), the first electrode layer (55) being connected to the plurality of lower via electrodes (51), and the via electrode intersecting the plurality of lower via electrodes (51) in a planar view.

[0344] The above [A1] to [A24] and the above [B1] to [B20] can be appropriately combined with each other. Specific embodiments have been described in detail above, but these are merely examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined with each other without being limited by the order of explanation in the specification, the order of embodiment examples, the order of modified examples, etc. [Explanation of symbols]

[0345] 1. Semiconductor device 2 chips 10 Main Transistor 11 transistors 11A 1st system transistor 11B Second system transistor 30 Gate Structure 40 Mesa 50 First insulating layer 51 First via electrode 55 1st electrode layer 56 Depression 60 Second insulating layer 61 Second via electrode 61a 1st Line Section 61b 2nd Line Section 65 Second electrode layer 75 First pad electrode P1 First pitch P2 2nd pitch P3 3rd pitch VG Gate signal VG1 First gate signal VG2 Second gate signal W1 1st width W2 Second width X 1st direction Y Second direction

Claims

1. a first insulating layer; a plurality of first via electrodes embedded in the first insulating layer; a first electrode layer on the first insulating layer and connected to the plurality of first via electrodes; a second insulating layer covering the first electrode layer; a second via electrode embedded in the second insulating layer in a mesh pattern and connected to the first electrode layer; a second electrode layer on the second insulating layer and connected to the second via electrode.

2. The semiconductor device according to claim 1 , wherein the second via electrode intersects a plurality of the first via electrodes in a plan view.

3. 2 . The semiconductor device according to claim 1 , wherein the plurality of first via electrodes are arranged at intervals in a first direction X in a plan view, and extend linearly in a second direction Y intersecting the first direction X.

4. The second via electrode is a plurality of first line portions that are arranged at intervals in the first direction X in a plan view and extend linearly in the second direction Y; 4. The semiconductor device according to claim 3, further comprising: a plurality of second line portions arranged in a region between the plurality of first line portions in a plan view at intervals in the second direction Y, each extending in a line shape in the first direction X.

5. the first line portions are arranged in regions between the first via electrodes in a plan view, The semiconductor device according to claim 4 , wherein the second line portions intersect with the first via electrodes in a plan view.

6. The semiconductor device according to claim 4 , wherein the second line portions are connected to the first line portions in a T-shape.

7. The semiconductor device according to claim 4 , wherein a pitch between the plurality of second line portions in the second direction Y is less than a pitch between the plurality of first line portions in the first direction X.

8. The plurality of first via electrodes are arranged at a pitch of 4 μm or less, The semiconductor device according to claim 4 , wherein the plurality of first line portions are arranged at a pitch of 4 μm or less.

9. The semiconductor device according to claim 4 , wherein the second line portions are arranged in the second direction Y at a pitch of 4 μm or less.

10. each of the plurality of first via electrodes has a width of 1 μm or less; The semiconductor device according to claim 1 , wherein the second via electrode has a width of 1 μm or less.

11. Chips and a functional device formed on the chip, the first insulating layer covers the functional device on the chip; 11. The semiconductor device according to claim 1, wherein the first via electrode is electrically connected to the functional device.

12. the functional device includes a plurality of gate structures formed on the chip, and a plurality of channels formed in regions along the plurality of gate structures within the chip, respectively; The semiconductor device according to claim 11 , wherein the plurality of first via electrodes are electrically connected to the plurality of channels.

13. Chips and a functional device formed on the chip; a first electrode layer disposed on the chip and covering the functional device in a plan view; a via electrode laid on the first electrode layer in a mesh pattern so as to cover the functional device in a mesh pattern in a plan view; a second electrode layer disposed on the via electrode and covering the functional device in a plan view.

14. the functional device has a plurality of gate structures formed on the chip; The semiconductor device according to claim 13 , wherein the via electrodes cover the plurality of gate structures in a mesh pattern in a plan view.

15. 15. The semiconductor device according to claim 14, wherein the plurality of gate structures are arranged at intervals in a first direction X in a plan view, and extend linearly in a second direction Y intersecting the first direction X.

16. The via electrode is a plurality of first line portions that are arranged at intervals in the first direction X in a plan view and extend linearly in the second direction Y; 16. The semiconductor device according to claim 15, further comprising: a plurality of second line portions arranged in a region between the plurality of first line portions in a plan view at intervals in the second direction Y, and each extending in a line shape in the first direction X.

17. the plurality of gate structures define mesas in the chip; the first line portions are arranged directly above the gate structures in a plan view, The semiconductor device according to claim 16 , wherein the second line portions are arranged directly above the mesa portion in a plan view.

18. The semiconductor device according to claim 17 , wherein the mesa portion has a width less than a width of a plurality of the gate structures.

19. The semiconductor device according to claim 16 , wherein the second line portions are connected to the first line portions in a T-shape.

20. further comprising a plurality of lower via electrodes electrically connected to the functional device; the first electrode layer is connected to the plurality of lower via electrodes; 20. The semiconductor device according to claim 13, wherein the via electrode intersects with a plurality of the lower via electrodes in a plan view.

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