Power factor correction circuit, control device, and electronic device

Abstract

To provide a power factor correction circuit capable of reducing standby power consumption.SOLUTION: A power factor correction circuit (7) includes: at least one of first voltage-dividing resistors (Rd1, Rd2) and a first switch (SW1) connected to an end to which a first voltage (Vh) having a full-wave rectified waveform is applied, and second voltage-dividing resistors (Rd3, Rd4) and a second switch (SW2) connected to an end to which an output voltage (Vdc) of a DC / DC converter is applied; and a control device (700A) configured to control the power factor correction circuit. The on / off state of at least one of the first switch and the second switch is controlled based on a control signal (Poff) input from an external device to the control device for switching between the normal state and the standby state.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to power factor correction circuits. [Background technology]

[0002] A power factor correction circuit brings the power factor close to 1 (that is, 100%) by matching the phases of an AC input voltage and an AC input current (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-60692

[0004] [overview] Power factor correction circuits are used in, for example, AC adapters, and in recent years there has been a demand for reducing standby power consumption.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a power factor correction circuit that makes it possible to reduce standby power consumption.

[0006] One aspect of the present disclosure is a power factor correction circuit having a DC / DC converter, at least one of a first voltage dividing resistor and a first switch connected to an application terminal of a first voltage having a full-wave rectified waveform, and a second voltage dividing resistor and a second switch connected to an application terminal of an output voltage of the DC / DC converter; a controller configured to control the power factor correction circuit; Equipped with The control device is configured such that the on / off of at least one of the first switch and the second switch is controlled based on a control signal that is input from the outside to the control device and that switches between a normal state and a standby state.

[0007] Another aspect of the present disclosure is a control device configured to control a power factor correction circuit having a DC / DC converter, at least one of a first external terminal configured to receive a first voltage having a full-wave rectified waveform and a second external terminal configured to receive an output voltage of the DC / DC converter; at least one of a first voltage dividing resistor and a first switch connected to the first external terminal and a second voltage dividing resistor and a second switch connected to the second external terminal; a third external terminal configured to receive a control signal for switching between a normal state and a standby state; Equipped with At least one of the first switch and the second switch is controlled to be turned on or off based on the control signal. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram showing the configuration of an electronic device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing the configuration of a PFC circuit according to an embodiment. [Figure 3] FIG. 3 is a diagram illustrating an example of an offset voltage generating circuit. [Figure 4] FIG. 4 is a diagram illustrating an example of the first arithmetic circuit. [Figure 5] FIG. 5 is a diagram illustrating an example of the first conversion circuit. [Figure 6] FIG. 6 is a diagram illustrating an example of the second conversion circuit. [Figure 7] FIG. 7 is a diagram illustrating an example of the second arithmetic circuit. [Figure 8] FIG. 8 is a diagram showing an example of waveforms of an AC voltage and an input current. [Figure 9] FIG. 9 is a diagram showing the configuration of the control device according to the first embodiment. [Figure 10] FIG. 10 is a diagram showing the configuration of a control device according to the second embodiment. [Figure 11] FIG. 11 is a timing chart showing an example of operation in the second embodiment. [Figure 12]FIG. 12 is a diagram showing the configuration of a control device according to the third embodiment. [Figure 13] FIG. 13 is a diagram showing the configuration of a control device according to the fourth embodiment.

[0009] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0010] <Electronic equipment> 1 is a circuit diagram showing the configuration of an electronic device 1 according to an embodiment. Examples of the electronic device 1 include home appliances such as televisions, refrigerators, and air conditioners, as well as computers. The electronic device 1 includes a fuse 2, a capacitor 3, a filter 4, a rectifier circuit 5, a capacitor 6, and a power factor correction (PFC) circuit 7. The electronic device 1 further includes a DC / DC converter 8, a microcomputer 9, and a signal processing circuit 10. The electronic device 1 is divided into a primary side and a secondary side that are insulated from each other, with an isolation transformer (not shown) of the DC / DC converter 8 as the boundary.

[0011] The rectifier circuit 5 is, for example, a diode bridge. An AC voltage Vac, such as a commercial AC voltage, is supplied to the rectifier circuit 5 via a fuse 2, a capacitor 3, and a filter 4. The rectifier circuit 5 full-wave rectifies the AC voltage Vac to generate a first voltage Vh. Therefore, the first voltage Vh has a full-wave rectified waveform.

[0012] The first voltage Vh is supplied to a PFC circuit 7 via a capacitor 6. The PFC circuit 7 has a step-up DC / DC converter (switching regulator) that generates an output voltage Vdc from the first voltage Vh. The PFC circuit 7 improves the power factor by approximately matching the phases of the first voltage Vh and the input current Iac.

[0013] The DC / DC converter 8 receives the output voltage Vdc of the PFC circuit 7, steps it down, and supplies it to the microcomputer 9 and the signal processing circuit 10, which are the loads.

[0014] The microcontroller 9 integrally controls the entire electronic device 1. The signal processing circuit 10 is a block that performs specific signal processing, and examples thereof include an interface circuit for communicating with an external device, an image processing circuit, an audio processing circuit, and the like. In a real electronic device 1, it is needless to say that a plurality of signal processing circuits 10 are provided according to its functions.

[0015] The above is the description of the configuration of the electronic device 1. Thus, AC / DC conversion is performed by an electronic device including a rectifier circuit 5 that full-wave rectifies the AC voltage Vac and a PFC circuit 7 that boosts the first voltage Vh after full-wave rectification to generate the output voltage Vdc. Next, details of the PFC circuit 7 mounted on the electronic device 1 will be described.

[0016] <PFC Circuit> FIG. 2 is a circuit diagram showing the configuration of the PFC circuit 7 according to an embodiment. The PFC circuit 7 has a boost-type DC / DC converter (switching regulator) as described above. Note that, different from this embodiment, the PFC circuit 7 may have a DC / DC converter other than the boost type.

[0017] The PFC circuit 7 includes a control device 700, resistors R1 to R9, capacitors C1 to C6, diodes D1 and D2, inductors L1 and L2, and a switching transistor M1. In this embodiment, the switching transistor M1 is an NMOS transistor (N-channel MOSFET (metal-oxide-semiconductor field-effect transistor)). Note that, although the switching transistor is provided outside the control device in the configuration shown in FIG. 9, it is not limited thereto and may be built in the control device.

[0018] The control device 700 is a device that controls the PFC circuit 7 and has an IC in which the internal configuration shown in FIG. 2 is integrated. The control device 700 includes, as external terminals for establishing electrical connection with the outside, a terminal VCC, a terminal GND, a terminal ZCD, a terminal OUT, a terminal CS, a terminal MULT, a terminal EO, and a terminal VS.

[0019] A first voltage Vh is applied to one end of resistor R1. The other end of resistor R1 is connected to one end of resistor R2, one end of capacitor C5, and terminal MULT. The other end of resistor R2 and the other end of capacitor C5 are connected to the ground end (the end to which the ground potential is applied). With this configuration, a voltage Vmult, which is the first voltage Vh divided by resistors R1 and R2, is supplied to terminal MULT.

[0020] One end of resistor R1 is connected to one end of inductor L1 and the anode of diode D1. The other end of inductor L1 is connected to the anode of diode D2 and the drain of switching transistor M1. The cathodes of diodes D1 and D2 are connected to one end of capacitor C1. The other end of capacitor C1 is connected to ground, and the gate of switching transistor M1 is connected to terminal OUT via resistor R8, and the source of switching transistor M1 is connected to ground via resistor R9. With this configuration, PFC circuit 7 is equipped with a step-up DC / DC converter (switching regulator). Voltage Vdc, which is the output voltage of the step-up DC / DC converter (switching regulator), is output from one end of capacitor C1.

[0021] Inductor L1 and inductor L2 are magnetically coupled. One end of inductor L2 is connected to terminal ZCD via resistor R7. The other end of inductor L2 is connected to ground. With this configuration, the control device 700 can detect the zero crossing of the current flowing through inductor L1 by monitoring the voltage supplied to terminal ZCD.

[0022] The output voltage Vdc is applied to one end of resistor R3. The other end of resistor R3 is connected to one end of resistor R4, one end of capacitor C2, and terminal VS. The other end of resistor R4 and the other end of capacitor C2 are connected to ground. With this configuration, a detection voltage Vs, which is the output voltage Vdc divided by resistors R3 and R4, is supplied to terminal VS.

[0023] One end of resistor R9 is connected to the source of switching transistor M1, and the other end of resistor R9 is connected to ground. A voltage proportional to the current flowing through switching transistor M1 (the drain current of switching transistor M1) is generated across resistor R9. Resistor R6 and capacitor C6 form an RC circuit (low-pass filter) that removes high-frequency components from the voltage (current detection signal) generated across resistor R9 to generate a detection voltage Vcs, which is supplied to terminal CS. The detection voltage Vcs is a voltage proportional to the current flowing through the switching transistor.

[0024] One end of resistor R5 and one end of capacitor C3 are connected to terminal EO. The other end of resistor R5 is connected to one end of capacitor C4. The other end of capacitor C3 and the other end of capacitor C4 are connected to ground. A power supply voltage Vcc is supplied to terminal VCC, and terminal GND is connected to ground.

[0025] <Control device> The specific configuration of the control device 700 will be described below.

[0026] The control device 700 includes a Zener diode 701, a comparator 702, a bandgap reference voltage circuit 703, a constant voltage circuit 704, and an overheat protection circuit 705. The anode of the Zener diode 701 is connected to the ground terminal, and the cathode of the Zener diode 701 is connected to the terminal VCC.

[0027] The Zener diode 701 clamps the power supply voltage Vcc to a Zener voltage. The inverting input terminal (-) of the comparator 702, the bandgap reference voltage circuit 703, and the constant voltage circuit 704 are connected to the terminal VCC.

[0028] The comparator 702 is a hysteresis comparator that compares the power supply voltage Vcc with a threshold voltage and outputs an undervoltage lockout signal UVLO indicating the comparison result. If the power supply voltage Vcc is equal to or greater than the threshold voltage, the undervoltage lockout signal UVLO goes low (indicating a normal state), and if the power supply voltage Vcc is less than the threshold voltage, the undervoltage lockout signal UVLO goes high (indicating an abnormal state). The threshold voltage used by the comparator 702 transitions between a first threshold voltage Vth1 (e.g., 8 V) and a second threshold voltage Vth2 (e.g., 13 V) depending on the level of the undervoltage lockout signal UVLO.

[0029] The bandgap reference voltage circuit 703 generates a reference voltage using the power supply voltage Vcc and supplies it to the constant voltage circuit 704 .

[0030] The constant voltage circuit 704 generates a constant voltage using the power supply voltage Vcc and a reference voltage, and supplies the constant voltage to each part of the control device 700 .

[0031] The overheat protection circuit 705 detects the ambient temperature, and if the ambient temperature is equal to or higher than the threshold temperature, outputs a high-level overheat protection signal TSD (a level indicating an abnormal state), and if the ambient temperature is lower than the threshold temperature, outputs a low-level overheat protection signal TSD (a level indicating a normal state).

[0032] The control device 700 further includes a comparator 706 , a startup excessive boost reducing circuit 707 , a comparator 708 , and a comparator 709 .

[0033] The comparator 706 compares the detection voltage Vs with a threshold voltage Vth3 (for example, 2.25 [V]) and outputs the comparison result to the startup overboost reduction circuit 707. If the detection voltage Vs is equal to or greater than the threshold voltage Vth3, the output signal of the comparator 706 becomes high level (a level indicating an abnormal state), and if the detection voltage Vs is less than the threshold voltage Vth3, the output signal of the comparator 706 becomes low level (a level indicating a normal state).

[0034] The startup overboost reduction circuit 707 outputs a startup overboost reduction signal OVR. Based on the output signal of the comparator 706 and the output voltage Vcomp of a comparator 715 (described later), when the detection voltage Vs rises to a threshold voltage Vth3 at startup, the startup overboost reduction circuit 707 sets the startup overboost reduction signal OVR to a high level (a level indicating an abnormal state) until a second voltage V2 (described later) drops to a constant voltage Vburst (described later), and sets the startup overboost reduction signal OVR to a low level (a level indicating a normal state) at all other times.

[0035] The comparator 708 compares the detection voltage Vs with a threshold voltage Vth4 (e.g., 0.3 V) and outputs the comparison result, a short-circuit protection signal SP. If the detection voltage Vs is equal to or greater than the threshold voltage Vth4, the short-circuit protection signal SP goes low (indicating a normal state), and if the detection voltage Vs is less than the threshold voltage Vth4, the short-circuit protection signal SP goes high (indicating an abnormal state).

[0036] Comparator 709 is a hysteresis comparator that compares detection voltage Vs with a threshold voltage and outputs a static overvoltage protection signal SOVP indicating the comparison result. If detection voltage Vs is equal to or greater than the threshold voltage, static overvoltage protection signal SOVP goes high (indicating an abnormal state), and if detection voltage Vs is less than the threshold voltage, static overvoltage protection signal SOVP goes low (indicating a normal state). The threshold voltage used by comparator 709 transitions between threshold voltage Vth5 (e.g., 2.6 [V]) and threshold voltage Vth6 (e.g., 2.7 [V]) depending on the level of static overvoltage protection signal SOVP.

[0037] The control device 700 further includes an error amplifier circuit 710, an OR gate 711, an NMOS transistor 712, an arithmetic circuit 713, a Zener diode 714, a comparator 715, and a drive circuit DRV1.

[0038] The error amplifier circuit 710 amplifies the error between the reference voltage Vref1 and the detection voltage Vs, which corresponds to the output voltage Vdc of a step-up DC / DC converter (switching regulator) provided in the PFC circuit 7, to generate a second voltage V2. The amplification factor of the error amplifier circuit 710 may be 1. The error amplifier circuit 710 supplies the second voltage V2 to a terminal EO and an arithmetic circuit 713.

[0039] The OR gate 711 outputs the logical sum of the undervoltage lockout signal UVLO and the startup overboost reduction signal OVR to the gate of the NMOS transistor 712. The drain of the NMOS transistor 712 is connected to the terminal EO, and the source of the NMOS transistor 712 is connected to the ground terminal. The NMOS transistor 712 is a switch for discharging the second voltage applied to the terminal EO. Therefore, when at least one of the undervoltage lockout signal UVLO and the startup overboost reduction signal OVR is at a high level, the NMOS transistor 712 is turned on, and the second voltage V2 drops.

[0040] The arithmetic circuit 713 generates a third voltage by multiplying the AC voltage (first voltage) Vmult by the second voltage V2, and adds an offset voltage Voffset to the third voltage to generate a fourth voltage V4.

[0041] The fourth voltage V4 is connected to the inverting input terminal of the comparator 715. The cathode of the Zener diode 714 is connected to the inverting input terminal of the comparator 715, and the anode of the Zener diode 714 is connected to the ground terminal. The Zener diode 714 clamps the fourth voltage V4 to a Zener voltage.

[0042] The comparator 715 compares the detection voltage Vcs, which corresponds to the current flowing through the switching transistor M1, with the fourth voltage V4, and outputs a voltage Vcomp indicating the comparison result.

[0043] The drive circuit DRV1 drives the switching transistor M1 on and off, and turns off the switching transistor M1 every time the detection voltage Vcs becomes higher than the fourth voltage V4, in accordance with the voltage Vcomp output from the comparator 715. Note that turning off refers to switching from an on state to an off state. That is, the drive circuit DRV1 turns off the switching transistor M1 based on the voltage Vcomp output from the comparator 715. The configuration of the drive circuit DRV1 is not particularly limited, and any known technology may be used.

[0044] 2 shows an example of the drive circuit DRV1. The drive circuit DRV1 includes a comparator 716, a one-shot circuit 717, a timer 718, an OR gate 719, a flip-flop 720, an AND gate 721, a pre-driver 722, a gate clamp circuit 723, a PMOS transistor (P-channel MOSFET) 724, an NMOS transistor 725, and a resistor 726.

[0045] Comparator 716 is a hysteresis comparator that compares the voltage applied to terminal ZCD with a threshold voltage and outputs the comparison result to one-shot circuit 717. If the voltage applied to terminal ZCD is equal to or greater than the threshold voltage, the output signal of comparator 716 becomes low level, and if the voltage applied to terminal ZCD is less than the threshold voltage, the output signal of comparator 716 becomes high level. The threshold voltage used by comparator 716 transitions between threshold voltage Vth7 (e.g., 0.67 [V]) and threshold voltage Vth8 (e.g., 0.9 [V]) depending on the level of the output signal of comparator 716.

[0046] When the output signal of the comparator 716 goes high, the one-shot circuit 717 supplies a one-shot pulse to the first input terminal of the OR gate 719 .

[0047] When the timer 718 has timed out a certain period of time, it supplies a high-level signal to the second input terminal of the OR gate 719. The timer 718 is reset every time the pre-driver 722 receives a high-level signal from the AND gate 721.

[0048] An OR gate 719 supplies the logical sum of the output signal of the one-shot circuit 717 and the output of the timer 718 to a set terminal (S) of an RS flip-flop 720. A voltage Vcomp, which is the output of the comparator 715, is supplied to a reset terminal (R) of the RS flip-flop 720. The output (Q) of the RS flip-flop 720 transitions to a high level at each positive edge of the voltage applied to the set terminal (S), and transitions to a low level at each positive edge of the voltage applied to the reset terminal (R).

[0049] The AND gate 721 supplies the pre-driver 722 with the logical product of the inverted signal of the undervoltage lockout signal UVLO, the output signal of the RS flip-flop 720, the inverted signal of the static overvoltage protection signal SOVP, the inverted signal of the short-circuit protection signal SP, the inverted signal of the overheat protection signal TSD, and the PFC off signal PFCOFF_H, which will be described later.

[0050] The pre-driver 722 complementarily drives the PMOS transistor 724 and the NMOS transistor 725 on / off based on the output of the AND gate 721. Specifically, when the output of the AND gate 721 is high, the pre-driver 722 turns the PMOS transistor 724 on and the NMOS transistor 725 off, thereby setting the voltage at the terminal OUT to a high level and turning the switching transistor M1 on. On the other hand, when the output of the AND gate 721 is low, the pre-driver 722 turns the PMOS transistor 724 off and the NMOS transistor 725 on, thereby setting the voltage at the terminal OUT to a low level and turning the switching transistor M1 off.

[0051] The source of the PMOS transistor 724 is connected to a gate clamp circuit 723, and the drain of the PMOS transistor 724 is connected to the drain of the NMOS transistor 725, the terminal OUT, and one end of a resistor 726. The source of the NMOS transistor 725 is connected to the ground terminal and the other end of the resistor 726. The gate clamp circuit 723 generates a high-level voltage that is applied to the terminal OUT from the power supply voltage Vcc. The gate clamp circuit 723 clamps the high-level voltage applied to the terminal OUT to a constant voltage, so that the high-level voltage applied to the terminal OUT does not exceed the gate-source breakdown voltage of the switching transistor M1 when the power supply voltage Vcc rises.

[0052] The control device 700 has a comparator 727 and a terminal PFCOFF as an external terminal. A non-inverting input terminal of the comparator 727 is connected to the terminal PFCOFF. The comparator 727 compares the control signal Poff input to the terminal PFCOFF with a threshold voltage Vth9, and outputs a PFC off signal PFCOFF_H. The PFC off signal PFCOFF_H is input to an AND gate 721. As a result, when the control signal Poff is at a low level, the PFC off signal PFCOFF_H becomes a low level, and when the control signal Poff is at a high level, the PFC off signal PFCOFF_H becomes a high level. When the control signal Poff is at a low level, the PFC circuit 7 (control device 700) is placed in a standby state.

[0053] <Arithmetic circuit> This concludes the description of the configuration of the PFC circuit 7. Next, we will describe the internal configuration of the arithmetic circuit 713. First, we will describe a specific example configuration of the offset voltage generating circuit 713A provided in the arithmetic circuit 713.

[0054] 3 shows an example of the offset voltage generating circuit 713A. The offset voltage generating circuit 713A includes a constant current generating circuit 713A1, a first current generating circuit 713A2, and a resistor R10.

[0055] The constant current generating circuit 713A1 includes a current mirror circuit formed by PMOS transistors M2 and M3 and a current source IS1. The constant voltage Vdd output from the constant voltage circuit 704 is applied to the source and back gate of the PMOS transistor M2 and the source and back gate of the PMOS transistor M3. The gate and drain of the PMOS transistor M2 and the gate of the PMOS transistor M3 are connected to one end of the current source IS1. The other end of the current source IS1 is connected to ground. The drain of the PMOS transistor M3 and one end of a resistor R10 are connected to a node ND1. The other end of the resistor R10 is connected to ground. The constant current generating circuit 713A1 generates a constant current I0 and supplies it to the node ND1. The value of the constant current I0 is not particularly limited. For example, if the constant current output by the current source IS1 is 1 μA and the current mirror ratio is 6:1, the value of the constant current I0 is 167 nA.

[0056] The first current generating circuit 713A2 includes an operational amplifier OP1, a drain-type current mirror circuit formed by PMOS transistors M4 and M5, an NMOS transistor M6, a resistor R11, and a drain-type current mirror circuit formed by NMOS transistors M7 and M8. The constant voltage Vdd output from the constant voltage circuit 704 is applied to the source and back gate of the PMOS transistor M4 and the source and back gate of the PMOS transistor M5. The gate and drain of the PMOS transistor M4 and the gate of the PMOS transistor M5 are connected to the drain of the NMOS transistor M6.

[0057] The source and back gate of the NMOS transistor M6 are connected to one end of a resistor R11 and the inverting input terminal of an operational amplifier OP1. The other end of the resistor R11 is connected to ground. A voltage Vmult is supplied to a first non-inverting input terminal of the operational amplifier OP1, and a constant voltage of, for example, 2.5 V is supplied to a second non-inverting input terminal of the operational amplifier OP1. The output terminal of the operational amplifier OP1 is connected to the gate of the NMOS transistor M6. The operational amplifier OP1 outputs a signal obtained by amplifying the difference between the voltage supplied to its inverting input terminal and the voltage Vmult plus the constant voltage of, for example, 2.5 V.

[0058] The drain of the PMOS transistor M5 is connected to the drain and gate of the NMOS transistor M7 and the gate of the NMOS transistor M8. The source and back gate of the NMOS transistor M7 and the source and back gate of the NMOS transistor M8 are connected to the ground terminal. The drain of the NMOS transistor M8 is connected to the node ND1. The first current generating circuit 713A2 generates a first current I1 and draws the first current I1 from the node ND1. The first current I1 varies depending on the voltage (AC voltage) Vmult. Specifically, the first current I1 increases as the voltage Vmult increases. In the example shown in FIG. 3, the first current I1 increases linearly as the voltage Vmult increases.

[0059] A current obtained by subtracting the first current I1 from the constant current I0, i.e., a differential current (I0-I1), flows from node ND1 to resistor R10. The product of the differential current (I0-I1) and the resistance value of resistor R10 is the offset voltage Voffset. Therefore, the offset voltage Voffset varies depending on the voltage Vmult. Specifically, the offset voltage Voffset decreases as the voltage Vmult increases. In the example shown in FIG. 3, the offset voltage Voffset decreases linearly as the voltage Vmult increases.

[0060] The range of the offset voltage Voffset is not particularly limited, but in the example shown in FIG. 3, for example, if the value of the constant current I0 is 167 [nA] as described above, the current mirror ratio of the discharge current mirror circuit in the first current generating circuit 713A2 is 10:1, the resistance value of the resistor R11 which is a current source connected to the discharge current mirror circuit is 2 [MΩ], the drain current mirror ratio in the first current generating circuit 713A2 is 1:1, and the resistance value of the resistor R10 is 161.2 [kΩ], then the offset voltage Voffset is variable within a range of 6.9 [mV] to 26.8 [mV].

[0061] If the design value of the minimum value of the offset voltage Voffset is set to, for example, 6.9 [mV] as in the above example, the actual minimum value of the offset voltage Voffset due to variations in the circuit constants can be made equal to or greater than zero.

[0062] 3, if the minimum value of the offset voltage Voffset becomes smaller than zero, the offset voltage generation circuit 713A will not operate normally, and therefore it is desirable that the minimum value of the offset voltage Voffset be equal to or greater than zero. Note that it is also possible to configure the circuit so that no malfunction occurs when the minimum value of the offset voltage Voffset becomes smaller than zero, and therefore it is also possible to set the minimum value of the offset voltage Voffset to be smaller than zero.

[0063] Furthermore, the offset voltage generating circuit 713A may be provided with a trimming element for adjusting the circuit constants, thereby suppressing variations in the circuit constants and setting the minimum design value of the offset voltage Voffset to zero or close to zero. An example of such a trimming element is at least one fuse provided in a parallel circuit of multiple resistors to adjust the resistance of a resistor that serves as a current source connected to the discharge current mirror circuit in the first current generating circuit 713A2. The fuse can be blown, for example, by laser trimming.

[0064] The above is a description of the configuration of the offset voltage generation circuit 713A. Next, a description will be given of a specific configuration example of the circuits other than the offset voltage generation circuit 713A of the arithmetic circuit 713. In addition to the offset voltage generation circuit 713A, the arithmetic circuit 713 includes a first arithmetic circuit 713B, a first conversion circuit 713C, a second conversion circuit 713D, and a second arithmetic circuit 713E.

[0065] FIG. 4 shows an example of the first arithmetic circuit 713B. The first arithmetic circuit 713B includes resistors R12 to R15 and an operational amplifier OP2. A second voltage V2 is applied to one end of the resistor R12. The other end of the resistor R12 and one end of the resistor R13 are connected to the non-inverting input terminal of the operational amplifier OP2. The other end of the resistor R13 is connected to ground. A constant voltage Vburst is applied to one end of the resistor R14. The other end of the resistor R14 and one end of the resistor R15 are connected to the inverting input terminal of the operational amplifier OP2. The other end of the resistor R15 is connected to the output terminal of the operational amplifier OP2. The first arithmetic circuit 713B outputs a voltage (V2-Vburst) obtained by subtracting the constant voltage Vburst from the second voltage V2.

[0066] 5 shows an example of a first conversion circuit 713C. The first conversion circuit 713C includes an operational amplifier OP3, a resistor R16, and an NPN bipolar transistor M9. A voltage (V2-Vburst) is applied to the non-inverting input terminal of the operational amplifier OP3. One end of the resistor R16 is connected to the inverting input terminal and output terminal of the operational amplifier OP3. The other end of the resistor R16 is connected to the ground terminal. The collector and base of the NPN bipolar transistor M9 are connected to the power supply terminal of the operational amplifier OP3. The emitter of the NPN bipolar transistor M9 is connected to the ground terminal. The first conversion circuit 713C converts the voltage (V2-Vburst) into a current (I2-Iburst) and outputs the current (I2-Iburst) as the base current of the NPN bipolar transistor M9.

[0067] FIG. 6 shows an example of a second conversion circuit 713D. The second conversion circuit 713D includes an operational amplifier OP4, a resistor R17, and an NPN bipolar transistor M10. A voltage Vmult is applied to the non-inverting input terminal of the operational amplifier OP4. One end of the resistor R17 is connected to the inverting input terminal and output terminal of the operational amplifier OP4. The other end of the resistor R17 is connected to ground. The collector and base of the NPN bipolar transistor M10 are connected to the power supply terminal of the operational amplifier OP4. The emitter of the NPN bipolar transistor M10 is connected to ground. The second conversion circuit 713D converts the voltage Vmult into a current Imult and outputs the current Imult as the base current of the NPN bipolar transistor M10.

[0068] 7 shows an example of the second arithmetic circuit 713E. The second arithmetic circuit 713E includes resistors R18 to R24, a current source IS2, NPN bipolar transistors M11 to M20, PMOS transistors M21 and M22, NMOS transistors M23 and M24, a PNP bipolar transistor M25, and a NOT gate NG1.

[0069] The constant voltage Vdd output from the constant voltage circuit 704 is applied to one end of each of the resistors R18 to R22, the collector of the NPN bipolar transistor M12, the source and backgate of the PMOS transistor M21, the source and backgate of the PMOS transistor M22, and the emitter of the PNP bipolar transistor M25. The other end of the resistor R18 is connected to the collector of the NPN bipolar transistor M11. The emitter of the NPN bipolar transistor M11 is connected to one end of the current source IS2 and the base of the NPN bipolar transistor M15. The other end of the current source IS2 is connected to ground.

[0070] The base and emitter of NPN bipolar transistor M12 are connected to the base of PNP bipolar transistor M25 and the collector of NPN bipolar transistor M13. The emitter of NPN bipolar transistor M13 is connected to the collector of NPN bipolar transistor M15. The emitter of NPN bipolar transistor M15 is connected to the emitter of NPN bipolar transistor M16. The other end of resistor R19 is connected to the collector of NPN bipolar transistor M14. The emitter of NPN bipolar transistor M14 is connected to the base of NPN bipolar transistor M11 and the collector of NPN bipolar transistor M16.

[0071] The other end of resistor R20 is connected to the collector of NPN bipolar transistor M17. The emitter of NPN bipolar transistor M17 is connected to the base of NPN bipolar transistor M16 and the collector of NPN bipolar transistor M18. The emitter of NPN bipolar transistor M18 is connected to ground. The base of NPN bipolar transistor M18 is connected to the base and collector of NPN bipolar transistor M10 in the second conversion circuit 713D. NPN bipolar transistors M10 and M18 form a current mirror circuit.

[0072] The other end of resistor R21 is connected to the collector of NPN bipolar transistor M19. The emitter of NPN bipolar transistor M19 is connected to the base of NPN bipolar transistor M17 and the collector of NPN bipolar transistor M20. The emitter of NPN bipolar transistor M20 is connected to the ground terminal. The base of NPN bipolar transistor M20 is connected to the base and collector of NPN bipolar transistor M9 in the first conversion circuit 713C. NPN bipolar transistors M9 and M20 form a current mirror circuit.

[0073] The other end of the resistor R22 is connected to one end of a resistor R23, the base of an NPN bipolar transistor M13, the base of an NPN bipolar transistor M14, and the base of an NPN bipolar transistor M19. The other end of the resistor R23 is connected to the ground terminal.

[0074] The gate and drain of the PMOS transistor M21 are connected to the gate of the PMOS transistor M22. The PMOS transistors M21 and M22 form a current mirror circuit. The drain of the PMOS transistor M22 is connected to the drain of the NMOS transistor M23 and the input terminal of the NOT gate. An enable signal EN is supplied to the gate of the NMOS transistor M23. The source and back gate of the NMOS transistor M23 are connected to the ground terminal. The output terminal of the NOT gate is connected to the gate of the NMOS transistor M24. The source and back gate of the NMOS transistor M24 are connected to the ground terminal. The drain of the NMOS transistor M24 is connected to one end of a resistor R24. The other end of the resistor R24 ​​is connected to the collector of a PNP bipolar transistor M25 and one end of a resistor R10. The other end of the resistor R10 is connected to the ground terminal.

[0075] The second arithmetic circuit 713E multiplies the current (I2-Iburst) by the current Imult and outputs the result of this multiplication, an output current Iout, to a resistor R10. The resistor R10 converts the output current Iout into a voltage (K×Vmult(V2-Vburst)). The constant K is determined by the ratio between the resistance value of the resistor R16 in the first conversion circuit 713C and the resistance value of the resistor R10, and the ratio between the resistance value of the resistor R17 in the second conversion circuit 713D and the resistance value of the resistor R10. The current I3 output by the current source IS2 in the second arithmetic circuit 713E is a current proportional to the peak value (maximum value) of the voltage Vmult. The second arithmetic circuit 713E can be switched between an enabled state and a disabled state by an enable signal EN.

[0076] The resistor R10 shown in Fig. 7 is the same as the resistor R10 provided in the offset voltage generating circuit 713A shown in Fig. 3. Therefore, an offset voltage Voffset is also applied to the resistor R10. Therefore, the fourth voltage V4 generated in the resistor R10 as the voltage across the resistor R10 is expressed by the following equation. V4=K×Vmult(V2-Vburst)+Voffset

[0077] Here, in order to explain the effect of the PFC circuit 7, a circuit obtained by removing the offset voltage generating circuit 713A from the PFC circuit 7 will be compared with the PFC circuit 7.

[0078] In a circuit in which the offset voltage generating circuit 713A is removed from the PFC circuit 7, the on-time of the switching transistor M1 is shortened when the first voltage Vh is near 0 [V] due to the operation of the drive circuit DRV1. Therefore, when the first voltage Vh is near 0 [V], the capacitor 6 provided on the output side of the rectifier circuit 5 cannot be sufficiently discharged, and as a result, the current output from the rectifier circuit 5 is temporarily stopped, causing distortion in the input current Iac (see the dotted line in FIG. 8).

[0079] On the other hand, in the PFC circuit 7, when the first voltage Vh is near 0 [V], the offset voltage Voffset increases and the fourth voltage V4 also increases, so that the on-time of the switching transistor M1 is lengthened by the operation of the drive circuit DRV1. Therefore, when the first voltage Vh is near 0 [V], the capacitor 6 provided on the output side of the rectifier circuit 5 can be sufficiently discharged, resulting in a smooth current output from the rectifier circuit 5 and suppressed distortion of the input current Iac (see the solid line in FIG. 8). In other words, the control device 700 can suppress the total harmonic distortion (THD) of the PFC circuit 7.

[0080] Note that since it is not necessary to increase the offset voltage Voffset except near the first voltage Vh of 0 [V], it is desirable that the offset voltage Voffset is variable as in the above-described embodiment. However, the addition of an unnecessary offset voltage Voffset other than near the first voltage Vh of 0 [V] may be allowed, and the offset voltage Voffset may be fixed.

[0081] <Problems of the PFC Circuit> However, in the PFC circuit 7 (FIG. 2) as described above, there were the following problems. By setting the control signal Poff to a low level, the PFC off signal PFCOFF_H becomes a low level, the voltage at the terminal OUT becomes a low level by the pre-driver 722, and the switching transistor M1 becomes an off state. As a result, the PFC circuit 7 enters a standby state, and the power consumption is reduced. However, even in the standby state, power consumption occurs in the resistors R1 and R2 for generating the voltage Vmult, and in the resistors R3 and F4 for generating the detection voltage Vs, and further reduction of the standby power was an issue.

[0082] <First Embodiment> To solve the above problems, the embodiment of the present disclosure described below is implemented. FIG. 9 is a diagram showing the configuration of the control device 700A according to the first embodiment. In FIG. 9, for the sake of convenience, the parts related to the differences from the configuration shown in FIG. 2 described above are shown, and the illustration of the same configuration as that of the control device 700 in the control device 700A is omitted. This also applies to the drawings related to the control devices according to other embodiments described later.

[0083] As shown in FIG. 9, the control device 700A includes voltage dividing resistors Rd1 and Rd2, voltage dividing resistors Rd3 and Rd4, and switches SW1 and SW2 in addition to the comparator 727 and the drive circuit DRV1. That is, the control device 700A incorporates the voltage dividing resistors Rd1 and Rd2, the voltage dividing resistors Rd3 and Rd4, and the switches SW1 and SW2. Further, the control device 700A includes a terminal VH and a terminal VDC as external terminals.

[0084] The terminal VH is connected to the application terminal of the first voltage Vh. One end of the voltage-dividing resistor Rd1 is connected to the terminal VH. The other end of the voltage-dividing resistor Rd1 is connected to one end of the voltage-dividing resistor Rd2. The switch SW1 is an NMOS transistor. The other end of the voltage-dividing resistor Rd2 is connected to the drain of the switch SW1. The source of the switch SW1 is connected to the ground terminal. The output terminal of the comparator 727 is connected to the gate of the switch SW1. That is, the PFC off signal PFCOFF_H output from the comparator 727 is applied to the gate of the switch SW1.

[0085] The terminal VDC is connected to the application terminal of the output voltage Vdc. One end of the voltage-dividing resistor Rd3 is connected to the terminal VDC. The other end of the voltage-dividing resistor Rd3 is connected to one end of the voltage-dividing resistor Rd4. The switch SW2 is an NMOS transistor. The other end of the voltage-dividing resistor Rd4 is connected to the drain of the switch SW2. The source of the switch SW2 is connected to the ground terminal. The output terminal of the comparator 727 is connected to the gate of the switch SW2. That is, the PFC off signal PFCOFF_H output from the comparator 727 is applied to the gate of the switch SW2.

[0086] With this configuration, when the control signal Poff is at a high level, the PFC off signal PFCOFF_H is at a high level, and the drive circuit DRV1 drives the switching transistor M1 on and off. In this normal state, the PFC off signal PFCOFF_H is at a high level, so that both switches SW1 and SW2 are in an on state. Therefore, the first voltage Vh applied to the terminal VH is divided by the voltage-dividing resistors Rd1 and Rd2, and a voltage Vmult is generated at a node Nd1 to which the voltage-dividing resistors Rd1 and Rd2 are connected. The voltage Vmult is supplied to the arithmetic circuit 713 (not shown in FIG. 9) in the control device 700A, as in FIG. 2 described above. Furthermore, the output voltage Vdc applied to the terminal VDC is divided by the voltage-dividing resistors Rd3 and Rd4, and a detection voltage Vs is generated at a node Nd2 to which the voltage-dividing resistors Rd3 and Rd4 are connected. The detected voltage Vs is supplied to the error amplifier circuit 710 (not shown in FIG. 9) in the control device 700A in the same manner as in FIG.

[0087] On the other hand, when the control signal Poff is at a low level, the PFC off signal PFCOFF_H becomes a low level, and the drive circuit DRV1 turns off the switching transistor M1. In this standby state, because the PFC off signal PFCOFF_H is at a low level, both switches SW1 and SW2 are turned off. Therefore, no current flows through the voltage-dividing resistors Rd1, Rd2 and Rd3, Rd4, respectively, reducing power consumption in the standby state. Note that because high voltages Vh and Vdc are applied to the terminals VH and VDC, respectively, the terminals VH and VDC must be high-voltage terminals.

[0088] Second Embodiment In the first embodiment described above, power consumption in the standby state can be reduced, but since the switches SW1 and SW2 are turned off in the standby state, the voltage Vmult becomes the first voltage VH, and the detection voltage Vs becomes the output voltage Vdc, there is a problem that a high voltage is applied to the internal circuit (such as an arithmetic circuit or an error amplifier circuit) to which the voltage Vmult or the detection voltage Vs is applied.

[0089] In view of the above, a second embodiment is implemented. Fig. 10 is a diagram showing the configuration of a control device 700B according to the second embodiment. The control device 700B differs from the first embodiment in that it includes switches SW3 and SW4, diodes D1 and D2, and a delay circuit 728.

[0090] The switch SW3 is an NMOS transistor. The drain of the switch SW3 is connected to the node Nd1. The source of the switch SW3 is connected to the cathode of the diode D1. The anode of the diode D1 is connected to the ground terminal.

[0091] The switch SW4 is an NMOS transistor. The drain of the switch SW4 is connected to the node Nd2. The source of the switch SW4 is connected to the cathode of the diode D2. The anode of the diode D2 is connected to the ground terminal.

[0092] The delay circuit 728 generates PFC off enable signals PFCOFF_EN1 and PFCOFF_EN2 by delaying the PFC off signal PFCOFF_H output from the comparator 727. The PFC off enable signal PFCOFF_EN1 is applied to the gates of the switches SW1 and SW2. The PFC off enable signal PFCOFF_EN2 is applied to the gates of the switches SW3 and SW4.

[0093] The operation of the configuration of the second embodiment will be described using the timing chart shown in Fig. 11. In Fig. 11, from the top to bottom, example waveforms of the PFC off signal PFCOFF_H, the PFC off enable signal PFCOFF_EN1, the PFC off enable signal PFCOFF_EN2, the output voltage Vdc, the detection voltage Vs, and the voltage at the terminal OUT are shown.

[0094] 11, the PFC off signal PFCOFF_H is at a high level indicating a normal state (i.e., the control signal Poff is at a high level), and the PFC off enable signals PFCOFF_EN1 and PFCOFF_EN2 are both at a high level. Therefore, the switches SW1 to SW4 are all in an on state, the voltage Vmult is the value obtained by dividing the first voltage Vh by the voltage-dividing resistors Rd1 and Rd2, and the detection voltage Vs is the value obtained by dividing the output voltage Vdc by the voltage-dividing resistors Rd3 and Rd4. At this time, the drive circuit DRV1 repeatedly switches the voltage at the terminal OUT between high and low levels, the switching transistor M1 is switched, and the output voltage Vdc is controlled to a target value Vout (e.g., 400 V).

[0095] Then, at timing t1, the control signal Poff goes low, causing the PFC off signal PFCOFF_H to go low, indicating a standby state. This causes the drive circuit DRV1 to set the voltage at the terminal OUT to low, turning off the switching transistor M1 and stopping switching. This causes the output voltage Vdc to start decreasing. Accordingly, the detection voltage Vs also starts decreasing.

[0096] After that, at timing t2, the PFC off enable signal PFCOFF_EN2 falls to the low level before PFCOFF_EN1. That is, the delay amount of the PFC off enable signal PFCOFF_EN2 with respect to the falling edge of the PFC off signal PFCOFF_H is smaller than that of PFCOFF_EN1. Therefore, the switches SW3 and SW4 are turned off before the switches SW1 and SW2. As a result, the voltage Vmult and the detection voltage Vs are each in an unstable state, but they are clamped by the diodes D1 and D2, respectively, preventing the voltage Vmult and the detection voltage Vs from becoming high. FIG. 11 shows a state in which the detection voltage Vs is clamped to the clamp voltage Vclp by the diode D2.

[0097] After that, at timing t3, the PFC off enable signal PFCOFF_EN1 goes low, turning off the switches SW1 and SW2. This reduces the power consumption of the voltage-dividing resistors Rd1 and Rd2 or Rd3 and Rd4 in the standby state. In this way, when transitioning to the standby state, the standby power consumption can be reduced while preventing the application of a high voltage due to the voltage Vmult or the detection voltage Vs to the internal circuit.

[0098] At timing t4, the control signal Poff goes high, causing the PFC off signal PFCOFF_H to go high, indicating a normal state, which restarts the switching of the switching transistor M1 by the drive circuit DRV1, causing the output voltage Vdc to rise.

[0099] Then, at timing t5, the PFC off enable signal PFCOFF_EN1 rises to the high level earlier than PFCOFF_EN2. That is, the delay amount of the PFC off enable signal PFCOFF_EN1 with respect to the rising edge of the PFC off signal PFCOFF_H is smaller than that of PFCOFF_EN2. As a result, the switches SW1 and SW2 are turned on earlier than the switches SW3 and SW4, a voltage obtained by dividing the first voltage Vh is generated at the node Nd1, and a voltage obtained by dividing the output voltage Vdc is generated at the node Nd2.

[0100] After that, at timing t6, the PFC off enable signal PFCOFF_EN2 rises to high level, turning on the switches SW3 and SW4. As a result, the voltage Vmult becomes a value obtained by dividing the first voltage Vh, and the detection voltage Vs becomes a value obtained by dividing the output voltage Vdc. In this way, even when transitioning to the normal state, it is possible to prevent a high voltage from being applied to the internal circuit due to the voltage Vmult or the detection voltage Vs.

[0101] <Third embodiment> FIG. 12 is a diagram showing the configuration of a control device 700C according to a third embodiment. In this embodiment, resistors R1, R2 and R3, R4 are connected externally to the control device 700C. The control device 700C has built-in switches SW1 and SW2 and external terminals MULT, VS, DR1, and DR2. That is, the resistors R1 to R4 are provided in a PFC circuit 7 including the control device 700C. Furthermore, diodes D1 and D2 are provided in the PFC circuit 7 externally to the control device 700C.

[0102] One end of resistor R1 is connected to the application terminal of the first voltage Vh. The other end of resistor R1 is connected to one end of resistor R2. The other end of resistor R2 is connected to terminal DR1. Terminal DR1 is connected to the drain of switch SW1. The source of switch SW1 is connected to the ground terminal. Node N1, to which resistors R1 and R2 are connected, is connected to terminal MULT. Terminal MULT is connected to the cathode of diode D1. The anode of diode D1 is connected to the ground terminal.

[0103] One end of resistor R3 is connected to the application terminal of output voltage Vdc. The other end of resistor R3 is connected to one end of resistor R4. The other end of resistor R4 is connected to terminal DR2. Terminal DR2 is connected to the drain of switch SW2. The source of switch SW2 is connected to the ground terminal. Node N2, to which resistors R3 and R4 are connected, is connected to terminal VS. Terminal VS is connected to the cathode of diode D2. The anode of diode D2 is connected to the ground terminal.

[0104] In this configuration, a PFC off signal PFCOFF_H is applied to the gates of the switches SW1 and SW2. When the control signal Poff is at a high level indicating a normal state and the PFC off signal PFCOFF_H is at a high level, both switches SW1 and SW2 are in the on state. As a result, a voltage Vmult obtained by dividing the first voltage Vh using resistors R1 and R2 is generated at the terminal MULT, and a detection voltage Vs obtained by dividing the output voltage Vdc using resistors R3 and R4 is generated at the terminal VS.

[0105] On the other hand, when the control signal Poff is at a low level indicating the standby state and the PFC off signal PFCOFF_H is at a low level, switches SW1 and SW2 are both in the off state. This reduces the power consumption due to resistors R1 and R2 or R3 and R4 in the standby state. At this time, the voltage at terminal MULT or the voltage at terminal VS is clamped by diodes D1 and D2, respectively, preventing a high voltage from being applied to the internal circuitry due to voltage Vmult or detection voltage Vs.

[0106] <Fourth embodiment> 13 is a diagram showing the configuration of a control device 700D according to the fourth embodiment. This embodiment differs from the third embodiment in that the switches SW1 and SW2 are also provided outside the control device 700D. This eliminates the need for external terminals in the control device 700D for connecting the drains of the switches SW1 and SW2.

[0107] In this embodiment, a control signal Poff is applied to the gates of the switches SW1 and SW2. By setting the control signal Poff to a low level, which indicates a standby state, both switches SW1 and SW2 are turned off, reducing power consumption. At this time, the clamping effect of diodes D1 and D2 prevents a high voltage from being applied to the internal circuitry due to the voltage Vmult or the detection voltage Vs.

[0108] <Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0109] <Additional Notes> As described above, one aspect of the present disclosure is a power factor correction circuit (7) having a DC / DC converter, at least one of first voltage dividing resistors (Rd1, Rd2) and a first switch (SW1) connected to an application terminal of a first voltage (Vh) having a full-wave rectified waveform, and second voltage dividing resistors (Rd3, Rd4) and a second switch (SW2) connected to an application terminal of an output voltage (Vdc) of the DC / DC converter; a control device (700A) configured to control the power factor correction circuit; Equipped with The control device is configured so that the on / off of at least one of the first switch and the second switch is controlled based on a control signal (Poff) that is input from outside to the control device to switch between a normal state and a standby state (first configuration).

[0110] In addition, in the first configuration, both the first voltage dividing resistor and the first switch and the second voltage dividing resistor and the second switch may be provided (second configuration).

[0111] In the first or second configuration, the control device (700A) at least one of a first external terminal (VH) for applying the first voltage and a second external terminal (VDC) for applying the output voltage; The configuration may also include at least one of the first voltage dividing resistor and the first switch connected to the first external terminal, and the second voltage dividing resistor and the second switch connected to the second external terminal (third configuration).

[0112] In the third configuration, the control device (700B) includes a third switch (SW3) and a first clamp circuit (D1) connected to a first node (Nd1) at which a divided voltage is generated by the first voltage dividing resistor; at least one of a fourth switch (SW4) and a second clamp circuit (D2) connected to a second node (Nd2) at which a divided voltage is generated by the second voltage dividing resistor; the control device further comprises a delay circuit (728) configured to delay a signal based on the control signal to generate a first enable signal (PFCOFF_EN1) and a second enable signal (PFCOFF_EN2); the first enable signal is applied to at least one of a control end of the first switch and a control end of the second switch; The second enable signal may be applied to at least one of the control terminal of the third switch and the control terminal of the fourth switch (fourth configuration).

[0113] In the first or second configuration, at least one of the first voltage dividing resistors (R1, R2) and the second voltage dividing resistors (R3, R4) is provided outside the control device (700C), At least one of the first switch and the second switch may be provided inside the control device (fifth configuration).

[0114] At least one of the first voltage dividing resistors (R1, R2) and the second voltage dividing resistors (R3, R4) is provided outside the control device (700D), At least one of the first switch (SW1) and the second switch (SW2) may be configured to be provided outside the control device (sixth configuration).

[0115] In the fifth or sixth configuration, the control device has at least one of a third external terminal (MULT) connected to a node (N1) at which a divided voltage is generated by the first voltage dividing resistor, and a fourth external terminal (VS) connected to a node (N2) at which a divided voltage is generated by the second voltage dividing resistor, At least one of a third clamp circuit (D1) connected to the third external terminal and a fourth clamp circuit (D2) connected to the fourth external terminal may be provided outside the control device (seventh configuration).

[0116] Also, an electronic device (1) according to one aspect of the present disclosure includes a rectifier circuit (5) configured to full-wave rectify an AC voltage (Vac); and a power factor correction circuit (7) of any one of the first to seventh configurations configured to receive the output voltage (Vh) of the rectifier circuit (eighth configuration).

[0117] Another aspect of the present disclosure is a control device (700A) configured to control a power factor correction circuit (7) having a DC / DC converter, at least one of a first external terminal (VH) configured to receive a first voltage (Vh) having a full-wave rectified waveform, and a second external terminal (VDC) configured to receive an output voltage (Vdc) of the DC / DC converter; at least one of a first voltage dividing resistor (Rd1, Rd2) and a first switch (SW1) connected to the first external terminal, and a second voltage dividing resistor (Rd3, Rd4) and a second switch (SW2) connected to the second external terminal; a third external terminal (PFCOFF) configured to receive a control signal (Poff) for switching between a normal state and a standby state; Equipped with At least one of the first switch and the second switch is controlled to be turned on or off based on the control signal (ninth configuration).

[0118] In addition, in the ninth configuration, both the first voltage dividing resistor and the first switch and the second voltage dividing resistor and the second switch may be provided (tenth configuration).

[0119] In the ninth or tenth configuration, a third switch (SW3) and a first clamp circuit (D1) connected to a first node (Nd1) at which a divided voltage is generated by the first voltage dividing resistor; at least one of a fourth switch (SW4) and a second clamp circuit (D2) connected to a second node (Nd2) at which a divided voltage is generated by the second voltage dividing resistor; a delay circuit (728) configured to delay a signal based on the control signal to generate a first enable signal (PFCOFFEN_1) and a second enable signal (PFCOFFEN_2); the first enable signal is applied to at least one of a control end of the first switch and a control end of the second switch; The second enable signal may be applied to at least one of the control terminal of the third switch and the control terminal of the fourth switch (eleventh configuration). [Industrial Applicability]

[0120] The present disclosure can be used in AC / DC converters for various applications. [Explanation of symbols]

[0121] 1 Electronic equipment 2 fuses 3. Capacitors 4 Filters 5 Rectifier circuit 6 capacitors 7 PFC circuit 8 DC / DC converters 9 Microcomputer 10 Signal processing circuit 700, 700A-700D control device 701 Zener diode 702 Comparator 702 Control device 703 Bandgap Reference Voltage Circuit 704 Constant Voltage Circuit 705 Overheat protection circuit 706 Comparator 707 Start-up overvoltage reduction circuit 708 Comparator 709 Comparator 710 Error Amplifier Circuit 711 OR Gate 712 NMOS transistor 713 Arithmetic circuit 713A Offset Voltage Generation Circuit 713A1 Constant current generation circuit 713A2 1st current generation circuit 713B 1st calculation circuit 713C 1st conversion circuit 713D Second conversion circuit 713E 2nd arithmetic circuit 714 Zener diode 715 Comparator 716 Comparator 717 One-shot circuit 718 Timer 719 OR Gate 720 flip-flops 720 RS Flip-Flop 721 AND Gate 722 Pre-driver 723 Gate clamp circuit 724 PMOS transistors 725 NMOS transistor 726 Resistance 727 Comparator 728 Delay Circuit C1~C6 capacitors D1, D2 diodes DRV1 drive circuit L1 inductor L2 inductor M1 Switching transistor R1~R4 resistance Rd1~Rd4 Voltage dividing resistors SW1 to SW4 switches

Claims

1. A power factor correction circuit having a DC / DC converter, at least one of a first voltage dividing resistor and a first switch connected to an application terminal of a first voltage having a full-wave rectified waveform, and a second voltage dividing resistor and a second switch connected to an application terminal of an output voltage of the DC / DC converter; a controller configured to control the power factor correction circuit; Equipped with A power factor correction circuit in which the on / off of at least one of the first switch and the second switch is controlled based on a control signal that is input from outside to the control device and that switches between a normal state and a standby state.

2. 2. The power factor correction circuit according to claim 1, comprising both the first voltage dividing resistor and the first switch, and the second voltage dividing resistor and the second switch.

3. The control device at least one of a first external terminal for applying the first voltage and a second external terminal for applying the output voltage; at least one of the first voltage dividing resistor and the first switch connected to the first external terminal, and the second voltage dividing resistor and the second switch connected to the second external terminal; 2. The power factor correction circuit of claim 1, comprising:

4. The control device a third switch and a first clamp circuit connected to a first node at which a divided voltage is generated by the first voltage dividing resistor; a fourth switch and / or a second clamp circuit connected to a second node at which a divided voltage is generated by the second voltage dividing resistor; the control device further includes a delay circuit configured to delay a signal based on the control signal to generate a first enable signal and a second enable signal; the first enable signal is applied to at least one of a control end of the first switch and a control end of the second switch; The power factor correction circuit according to claim 3 , wherein the second enable signal is applied to at least one of a control end of the third switch and a control end of the fourth switch.

5. at least one of the first voltage dividing resistor and the second voltage dividing resistor is provided outside the control device; The power factor correction circuit according to claim 1 , wherein at least one of the first switch and the second switch is provided inside the control device.

6. at least one of the first voltage dividing resistor and the second voltage dividing resistor is provided outside the control device; 2. The power factor correction circuit according to claim 1, wherein at least one of the first switch and the second switch is provided outside the control device.

7. the control device has at least one of a third external terminal connected to a node at which a voltage divided by the first voltage dividing resistor is generated and a fourth external terminal connected to a node at which a voltage divided by the second voltage dividing resistor is generated; 7. The power factor correction circuit according to claim 5, wherein at least one of a third clamp circuit connected to the third external terminal and a fourth clamp circuit connected to the fourth external terminal is provided outside the control device.

8. a rectifier circuit configured to full-wave rectify an AC voltage; An electronic device comprising: the power factor correction circuit according to claim 1 configured to receive the output voltage of the rectifier circuit.

9. 1. A control device configured to control a power factor correction circuit having a DC / DC converter, comprising: at least one of a first external terminal configured to receive a first voltage having a full-wave rectified waveform and a second external terminal configured to receive an output voltage of the DC / DC converter; at least one of a first voltage dividing resistor and a first switch connected to the first external terminal and a second voltage dividing resistor and a second switch connected to the second external terminal; a third external terminal configured to receive a control signal for switching between a normal state and a standby state; Equipped with A control device in which the on / off of at least one of the first switch and the second switch is controlled based on the control signal.

10. The control device according to claim 9 , further comprising both the first voltage dividing resistor and the first switch, and the second voltage dividing resistor and the second switch.

11. a third switch and a first clamp circuit connected to a first node at which a divided voltage is generated by the first voltage dividing resistor; a fourth switch and / or a second clamp circuit connected to a second node at which a divided voltage is generated by the second voltage dividing resistor; a delay circuit configured to delay a signal based on the control signal to generate a first enable signal and a second enable signal; the first enable signal is applied to at least one of a control end of the first switch and a control end of the second switch; 11. The control device according to claim 9, wherein the second enable signal is applied to at least one of a control end of the third switch and a control end of the fourth switch.

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