Photoelectric conversion device and equipment

Abstract

To provide a technique advantageous to improve characteristics of a photoelectric conversion device.SOLUTION: A photoelectric conversion device includes: a pixel circuit in which a plurality of pixels are arranged; a plurality of ramp signal lines to which ramp signals having different gradients are supplied; and an AD conversion part in which a plurality of AD conversion circuits including a first AD conversion circuit and a second AD conversion circuit adjacent to each other are arranged. Each of the plurality of AD conversion circuits includes: a selection circuit which selects a ramp signal line so as to select a ramp signal to be used for AD conversion among the plurality of ramp signals; a comparison circuit which compares the ramp signal selected by the selection circuit and a pixel signal from the pixel; and a supply line which supplies the ramp signal from the selection circuit to the comparison circuit. The supply line includes a first portion extending from the comparison circuit and a second portion for connecting the first portion and the selection circuit. A wiring region in which the supply line is arranged includes a region in which the second portion provided in the first AD conversion circuit or the first portion provided in the second AD conversion circuit is arranged between the first portion provided in the first AD conversion circuit and the second portion provided in the second AD conversion circuit.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and an apparatus. [Background technology]

[0002] As television standards become higher in pixel count and frame rate, photoelectric conversion devices that capture television images are also required to record higher pixel count and frame rate images. To meet this demand, the analog-to-digital converters (ADCs) of photoelectric conversion devices must be made faster. Furthermore, not only higher pixel count and higher frame rate, but also an expanded dynamic range is an important factor in image expression. Patent Document 1 discloses an imaging device that can improve the dynamic range without increasing the time required for AD conversion by supplying a ramp signal with a different slope to the ADC depending on the magnitude of the signal obtained from the pixel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-153291 Summary of the Invention [Problem to be solved by the invention]

[0004] To achieve a high frame rate, it is possible to provide multiple ADCs for each pixel column and simultaneously process signals output from multiple rows of pixels. When multiple ADCs are provided for each pixel column, unintended coupling capacitance may occur between the densely packed ADCs and the wiring patterns used to input signals to the ADCs. When ramp signals with different slopes are supplied to adjacent ADCs, the slopes of the ramp signals change if the different slopes affect each other through the coupling capacitance, resulting in a change in the AD conversion gain. This may result in a degradation of the image quality of the resulting image.

[0005] An object of the present invention is to provide a technique that is advantageous for improving the characteristics of a photoelectric conversion device. [Means for solving the problem]

[0006] In view of the above-described problems, a photoelectric conversion device according to an embodiment of the present invention is a photoelectric conversion device including: a pixel circuit in which a plurality of pixels are arranged to form a plurality of rows and a plurality of columns; a plurality of ramp signal lines to which ramp signals having different slopes are supplied; and an AD conversion unit in which a plurality of AD conversion circuits including a first AD conversion circuit and a second AD conversion circuit adjacent to each other are arranged corresponding to one column, wherein each of the plurality of AD conversion circuits includes a selection circuit that selects a ramp signal line to select a ramp signal to be used for AD conversion from the plurality of ramp signal lines; a comparison circuit that compares a ramp signal selected by the selection circuit with a pixel signal from a pixel; and a supply line that supplies the ramp signal from the selection circuit to the comparison circuit, wherein the supply line includes a first portion extending from the comparison circuit and a second portion connecting the first portion and the selection circuit, and a wiring region in which the supply line is arranged includes a region in which the second portion of the first AD conversion circuit or the first portion of the second AD conversion circuit is arranged between the first portion of the first AD conversion circuit and the second portion of the second AD conversion circuit. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a technique that is advantageous for improving the characteristics of a photoelectric conversion device. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a photoelectric conversion device according to an embodiment of the present invention. [Figure 2] 2 is a diagram showing an example of the configuration of an AD conversion circuit of the photoelectric conversion device of FIG. 1; [Figure 3] 2 is a diagram showing an example of the configuration of an AD conversion circuit of the photoelectric conversion device of FIG. 1; [Figure 4]2 is a diagram showing an example of the operation of an AD conversion circuit of the photoelectric conversion device of FIG. 1; [Figure 5] 2 is a diagram showing an example of the layout of an AD conversion circuit of the photoelectric conversion device of FIG. 1; [Figure 6] 2 is a diagram showing an example of the layout of a wiring pattern that supplies a ramp signal to the AD conversion circuit of the photoelectric conversion device of FIG. 1; [Figure 7] 2 is a diagram showing an example of the configuration of an AD conversion circuit of the photoelectric conversion device of FIG. 1; [Figure 8] 2 is a diagram showing an example of the operation of an AD conversion circuit of the photoelectric conversion device of FIG. 1; [Figure 9] 2 is a diagram showing an example of the configuration of an AD conversion circuit of the photoelectric conversion device of FIG. 1; [Figure 10] FIG. 2 is a diagram showing an example of the configuration of a device incorporating the photoelectric conversion device of FIG. 1. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0010] A photoelectric conversion device according to an embodiment of the present disclosure will be described with reference to Figures 1 to 9. Figure 1 is a block diagram showing an example configuration of an imaging device 1000 including a photoelectric conversion device 1 according to this embodiment. The imaging device 1000 includes a photoelectric conversion device 1 equipped with a parallel AD converter, and an image processing LSI 2. The photoelectric conversion device 1 may also be called a CMOS image sensor, for example.

[0011] The image processing LSI2 performs various processes on image data output from the photoelectric conversion device 1. The processes performed by the image processing LSI2 include white balance processing, gamma processing, high dynamic range synthesis processing, and processing to correct the ratio of two pixel signals with different gains. The image data output from the photoelectric conversion device 1 and image data processed by the image processing LSI2 are recorded on a recording medium such as a memory. The recording medium may be built into the image processing LSI2 or may be arranged separately from the imaging device 1000. The image processing LSI2 may also have a built-in CPU as a computer, and the CPU may communicate (e.g., serial communication) with the photoelectric conversion device 1 and the like based on a computer program stored in the memory, and control the entire imaging device 1000.

[0012] The photoelectric conversion device 1 includes a pixel circuit 110, a vertical scanning circuit 120, a ramp circuit 140, an AD conversion unit 150, a horizontal transfer circuit 160, a signal processing circuit 170, an external output circuit 180, and a controller circuit 300. Furthermore, for example, the photoelectric conversion device 1 may include an amplifier or the like between the pixel circuit 110 and the AD conversion unit 150 that amplifies an analog signal (pixel signal) from the pixel circuit 110.

[0013] The controller circuit 300 is an interface with the image processing LSI 2, and receives control signals from the CPU of the image processing LSI 2 to the photoelectric conversion device 1 using serial communication or the like. The controller circuit 300 controls each component within the photoelectric conversion device 1.

[0014] The pixel circuit 110 has a plurality of pixels 111 arranged in a plurality of rows and a plurality of columns. Each pixel 111 has a photoelectric conversion element (e.g., a photodiode) that performs photoelectric conversion according to the amount of incident light and outputs a voltage signal. The pixel 111 may have a color filter, a microlens, or the like arranged on an incident surface through which light is incident on the photoelectric conversion element. For example, three color filters that transmit red, green, and blue, respectively, may be periodically arranged so as to correspond to the photoelectric conversion elements arranged in the pixel 111. For example, the color filters may be arranged in a Bayer array across the pixel circuit 110 as a whole, but this is not necessarily limited to this.

[0015] The timing control circuit 100 supplies an operation clock CLK or timing signals to each component of the photoelectric conversion device 1. The timing control circuit 100 controls the operation of each component by the operation clock CLK or timing signals.

[0016] The vertical scanning circuit 120 performs timing control to sequentially read out output signals from the pixels 111 arranged two-dimensionally in the pixel circuit 110 for multiple rows during one frame. For example, during one frame, signals are read out from the pixels 111 sequentially for multiple rows from the top row to the bottom row in the pixel circuit 110 shown in FIG.

[0017] The constant voltage circuit 400 can supply a predetermined voltage to each of the signal output lines. Instead of the constant voltage circuit 400, a clipping circuit that clips the signal at a predetermined constant voltage may be used.

[0018] The ramp circuit 140 is a signal generator that generates a ramp-shaped voltage signal (ramp signal) whose voltage changes with a constant slope over time. As will be described later, the ramp circuit 140 can generate multiple ramp signals with different slopes.

[0019] The AD conversion unit 150 includes a comparison circuit that compares the pixel signal read out from the pixel circuit 110 with the ramp signal supplied from the ramp circuit 140. The AD conversion unit 150 also includes a counter / latch circuit that counts the time until the voltage level of the pixel signal matches the voltage level of the ramp signal using the comparison circuit and holds the count value. The detailed configuration of the AD conversion circuit for each pixel column in the AD conversion unit 150 will be described later.

[0020] In this embodiment, the AD conversion unit 150 includes an AD conversion unit 150u and an AD conversion unit 150d. As shown in FIG. 1, the AD conversion unit 150u and the AD conversion unit 150d are provided above and below the pixel circuit 110, respectively. It can also be said that the pixel circuit 110 is arranged between the AD conversion unit 150u and the AD conversion unit 150d. For example, pixel signals output from pixels 111 arranged in odd-numbered rows of the pixel circuit 110 may be converted into time count values ​​by the AD conversion unit 150u arranged above the pixel circuit 110 and then read out. Furthermore, pixel signals output from pixels 111 arranged in even-numbered rows of the pixel circuit 110 may be converted into time count values ​​by the AD conversion unit 150d arranged below the pixel circuit 110 and then read out.

[0021] The count values ​​for each column in one row held in the counter / latch circuit of the AD conversion unit 150 are sequentially read out as AD-converted image data by the horizontal transfer circuit 160, for example, starting from the column corresponding to the right end of the pixel circuit 110. The image data output from the horizontal transfer circuit 160 is input to the signal processing circuit 170. The signal processing circuit 170 is a circuit that performs digital signal processing. For example, the signal processing circuit 170 may add a fixed amount of offset value through digital processing, or may perform shift calculations or multiplications. In other words, the signal processing circuit 170 is capable of performing digital gain calculations.

[0022] The image data output from the signal processing circuit 170 is supplied to the external output circuit 180. The external output circuit 180 has a serializer function and converts the multi-bit parallel signal input from the signal processing circuit 170 into a serial signal. The external output circuit 180 also converts this serial signal into a signal conforming to, for example, the Low Voltage Differential Signaling (LVDS) standard, and outputs it to an external device (for example, the image processing LSI 2) as image data.

[0023] First embodiment Next, the configuration and operation of the AD conversion unit 150 according to the first embodiment of the present disclosure will be described. FIG. 2 is a circuit block diagram showing a detailed configuration of an AD conversion circuit 220 corresponding to one pixel column of the pixel circuits 110 in the AD conversion unit 150. As shown in FIG. 2, two AD conversion units 150u and 150d are provided on either side of the pixel circuit 110. Each of the AD conversion units 150u and 150d has a plurality of AD conversion circuits 220 arranged corresponding to one column. For simplicity of explanation, the configuration shown in FIG. 2 illustrates eight pixels 111 for eight rows arranged in one column, but the number of rows in which the pixels 111 are arranged is not limited to this.

[0024] Each of the multiple AD conversion circuits 220 includes a selection circuit 201, a buffer circuit 202, a comparison circuit 209, and a counter / latch circuit 210. The photoelectric conversion device 1 is provided with multiple ramp signal lines (two ramp signal lines 141 and 142 in the configuration shown in FIG. 2 ) to which ramp signals with different slopes are supplied from the ramp circuit 140. The selection circuit 201 selects the ramp signal lines 141 and 142 to select a ramp signal to be used for AD conversion from the multiple ramp signal lines 141 and 142. In this embodiment, a configuration is shown in which two types of ramp signals are supplied from the ramp circuit 140 via the two ramp signal lines 141 and 142. However, this is not limited thereto, and three or more ramp signal lines may be provided, and the selection circuit 201 may select a ramp signal to be used for AD conversion from three or more types of ramp signals. The buffer circuit 202 corrects the signal voltage of the ramp signal supplied from the selection circuit 201 and outputs the corrected signal to the comparison circuit 209 in the downstream stage. The buffer circuit 202 may be, for example, a source follower circuit. The comparison circuit 209 compares the ramp signal selected by the selection circuit 201 with the pixel signal from the pixel 111. The counter / latch circuit 210 stores a time count value as the AD conversion result and outputs it to the downstream horizontal transfer circuit 160. The AD conversion circuit 220 also includes a supply line SL that supplies a ramp signal from the selection circuit 201 to the comparison circuit 209. The supply line SL connects the output terminal of the selection circuit 201 to one input terminal of the comparison circuit 209 via the buffer circuit 202 and the input capacitor 205. In the configuration shown in FIG. 2 , an example is shown in which a total of eight AD conversion circuits 220 are provided, four on each side of the pixel circuit 110 corresponding to one column. However, the number of AD conversion circuits 220 per column is not limited to this and may be two to seven or less, or eight or more.

[0025] In order to transmit pixel signals from the pixel circuits 110 to the AD conversion units 150u and 150d, a plurality of signal output lines VL are provided corresponding to a plurality of AD conversion circuits 220 provided for each column in which the pixels 111 of the pixel circuits 110 are arranged. The signal output lines VL are connected to a comparison circuit 209 via input capacitors 208. In the configuration shown in FIG. 2, pixel signals output from the pixels 111 arranged in odd-numbered rows of the pixel circuits 110 are read out to the AD conversion circuit 220 of the AD conversion unit 150d via the signal output lines VL. Furthermore, pixel signals output from the pixels 111 arranged in even-numbered rows of the pixel circuits 110 are read out to the AD conversion circuit 220 of the AD conversion unit 150d via the signal output lines VL. An amplifier circuit may be provided between the signal output lines VL and the AD conversion units 150u and 150d, and the signal voltages output from the pixels 111 may be amplified and then input to the comparison circuit 209 of the AD conversion circuit 220. Other configurations of the AD conversion section 150 may be common to the AD conversion section 150u and the AD conversion section 150d.

[0026] Fig. 3 shows a more detailed circuit block diagram of the AD conversion unit 150. Although Fig. 3 shows the AD conversion unit 150d, the AD conversion unit 150u may also have a similar configuration.

[0027] The signal output lines VL1 to VL4 are signal output lines corresponding to one column of pixels arranged in the pixel circuit 110. Pixel signals are input to each signal output line from pixels 111 arranged in the same pixel column of the pixel circuit 110. The signal output line VL includes a portion 206 to which the pixel 111 is connected, a portion 207 connected to a comparison circuit 209, and an input capacitor 208. In FIG. 3, portions 206a to 206d, portions 207a to 207d, and input capacitors 208a to 208d are shown corresponding to the signal output lines VL1 to VL4. Hereinafter, when referring to a specific signal output line among the signal output lines VL, a subscript is added to the reference symbol, such as signal output line VL "1." Similarly, when referring to a specific portion among the portion 206, a subscript is added to the reference symbol, such as portion 206 "a." The same applies to other components below.

[0028] As described above, the selection circuit 201 selects one of the ramp signal lines 141 and 142 so as to select the ramp signal Ramp1 supplied from the ramp circuit 140 to the ramp signal line 141 and the ramp signal Ramp2 supplied to the ramp signal line 142. Then, the selection circuit 201 outputs the ramp signals Ramp1 and Ramp2 to the comparison circuit 209 for each selection circuit 201.

[0029] A supply line SL for supplying ramp signals Ramp1 and Ramp2 from the selection circuit 201 to the comparison circuit 209 includes, with an input capacitance 205 as the boundary, a portion 204 extending from the comparison circuit 209 and a portion 203 connecting the portion 204 and the selection circuit 201. The portion 203 can also be said to be a portion extending from the selection circuit 201 to the input capacitance 205 via the buffer circuit 202. The buffer circuit 202 can also be said to be arranged in the portion 203 of the supply line SL.

[0030] The ramp signals Ramp1 and Ramp2 selected by the selection circuit 201 are input to one of the two input terminals of the comparison circuit 209 via a supply line SL including an input capacitor 205 and a buffer circuit 202. The signal voltage (pixel signal) from the pixel 111 is input to the other of the two input terminals of the comparison circuit 209 via a signal output line VL and an input capacitor. The comparison circuit 209 compares the input pixel signal with the ramp signal and outputs a signal level according to the comparison result. As an example, here, if the voltage level of the ramp signals Ramp1 and Ramp2 is higher than the voltage level of the pixel signal, the comparison circuit 209 outputs an H level, and if the voltage level of the ramp signals Ramp1 and Ramp2 is lower than the voltage level of the pixel signal, the comparison circuit 209 outputs an L level. In this configuration, the signal voltages of the ramp signals Ramp1 and Ramp2 are monotonically increased over time, and the time until the output of the comparison circuit 209 inverts from an H level to an L level is counted. This time count value can then be used as the AD conversion result of the pixel signal.

[0031] Furthermore, a predetermined voltage is input to the comparator circuit 209 instead of the ramp signals Ramp1 and Ramp2, and the comparison circuit 209 compares the input voltage with the pixel signal. This allows the comparator circuit 209 to be used as a level determination circuit that determines whether the signal level of the pixel signal is higher or lower than a predetermined voltage. Details of the operation of using the comparator circuit 209 as a level determination circuit will be described later. As shown in FIG. 3 , the AD conversion circuit 220 may include a determination holding circuit 211 for holding the determination result of the comparator circuit 209 when the comparator circuit 209 is used as a level determination circuit. Furthermore, the comparator circuit 209 may be configured to generate a determination signal in accordance with the held determination result and feed it back to the selection circuit 201. This allows the selection circuit 201 to select the ramp signals Ramp1 and Ramp2 in accordance with the fed-back determination signal.

[0032] Next, the operation timing of the AD conversion circuit 220 related to AD conversion in this embodiment will be described using Figures 4(a) and 4(b). As shown in Figure 4(a), the comparison circuit 209 compares the input voltage Sout with the input voltage VRAMP and outputs a comparison signal PCOMP as the comparison result. In this embodiment, the input voltage Sout is a voltage corresponding to the pixel signal input to the comparison circuit 209 from the pixel 111 via the signal output line VL. The input voltage VRAMP is a voltage corresponding to the ramp signals Ramp1 and Ramp2 selected by the selection circuit 201 and input to the comparison circuit 209 via the buffer circuit 202.

[0033] 4(b) shows the operation timing of the AD conversion circuit 220. In this embodiment, when AD converting the signal of the pixel 111, first, a noise signal (hereinafter sometimes referred to as an N signal) is read from the pixel 111 and AD conversion is performed. Next, a signal photoelectrically converted by the photoelectric conversion element and an S signal containing noise are read from the pixel 111 and AD conversion is performed. For these two digital signals, the signal processing circuit 170 performs subtraction processing to subtract the N signal from the S signal, thereby canceling out the noise component and improving the S / N ratio.

[0034] During the AD conversion period of the N signal, a reset level is read out as the N signal from the pixel 111 of the pixel circuit 110 to the signal output line VL. All selection circuits 201 arranged in the AD conversion unit 150 select the ramp signal line 142 supplied with the ramp signal Ramp1, which has a gentler slope than the ramp signal Ramp2, from among the multiple ramp signals Ramp1 and Ramp2 supplied from the ramp circuit 140. A voltage corresponding to the ramp signal Ramp1 is supplied as the input voltage VRAMP to the comparison circuit 209 via the buffer circuit 202. The counter of the counter / latch circuit 210 starts counting time upon start of supply of the input voltage VRAMP (ramp signal Ramp1). The comparison circuit 209 compares the input voltage Sout corresponding to the N signal with the input voltage VRAMP corresponding to the ramp signal Ramp1, and outputs an H level as the comparison signal PCOMP while the input voltage Sout is higher than the ramp signal Ramp1. The voltage level of the ramp signal Ramp1 rises over time, and when it exceeds the input voltage Sout, the comparison signal PCOMP is inverted to an L level. When the comparison signal PCOMP is inverted from H level to L level, the counter latch circuit 210 stores the time count value of the counter as a digital value of the N signal.

[0035] When AD conversion of the N signal is completed, a level determination period begins in which the comparison circuit 209 is used as a level determination circuit. During the level determination period, the signal level of the S signal accumulated in the pixel 111 of the pixel circuit 110 is determined. First, the S signal accumulated in the pixel 111 arranged in the pixel circuit 110 is read out to the signal output line VL. Meanwhile, the ramp circuit 140 supplies a fixed voltage Vth, which serves as a threshold for determining the signal level, to at least one of the ramp signal line 141 and the ramp signal line 142. The selection circuit 201 selects the ramp signal line 141, 142 to which the fixed voltage Vth is supplied, and supplies the fixed voltage Vth to the comparison circuit 209 as an input voltage VRAMP. The comparison circuit 209 compares an input voltage Sout corresponding to the S signal with the fixed voltage Vth, and outputs an H level if the input voltage Sout is higher than the fixed voltage Vth, and outputs an L level if the input voltage Sout is lower than the fixed voltage Vth. For example, from the pixel 111 where the amount of incident light from the subject was small, an input voltage Sout1 below the fixed voltage Vth is input as an S signal, and the comparison circuit 209 outputs an L level as the comparison signal PCOMP. From the pixel 111 where the amount of incident light was large, an input voltage Sout2 above the fixed voltage Vth is input, and the comparison circuit 209 outputs an H level as the comparison signal PCOMP. When the input voltage Sout and the input voltage VRAMP become stable, the judgment holding circuit 211 holds the level of the comparison signal PCOMP as the judgment signal jdg.

[0036] Next, during the period in which the S signal is AD converted, the selection circuit 201 selects one of the ramp signals Ramp1 and Ramp2 supplied from the ramp circuit 140 based on the determination signal jdg from the corresponding determination holding circuit 211. If the determination signal jdg is at L level, the selection circuit 201 selects the ramp signal Ramp1, which has a gentle slope, as the input voltage VRAMP. If the determination signal jdg is at H level, the selection circuit 201 selects the ramp signal Ramp2, which has a steep slope, as the input signal VRAMP. The counter of the counter / latch circuit 210 starts counting time upon start of supply of the input voltage VRAMP (ramp signal Ramp1 or ramp signal Ramp2). The comparison circuit 209 compares the input voltage Sout corresponding to the S signal with the input voltage VRAMP corresponding to the ramp signal Ramp1 or ramp signal Ramp2 selected by the selection circuit 201. The comparison circuit 209 outputs an H level as the comparison signal PCOMP while the input voltage Sout is higher than the input signal VRAMP. The voltage level of the input signal VRAMP increases over time, and when it exceeds the input voltage Sout, the comparison signal PCOMP inverts to L level. In response to the inversion of the comparison signal PCOMP from H level to L level, the counter latch circuit 210 stores the time count value of the counter as a digital value of the S signal.

[0037] If the slope of ramp signal Ramp2 is N times that of ramp signal Ramp1, the time it takes for ramp signal Ramp2 to equalize with input voltage Sout is 1 / N times the time it takes for ramp signal Ramp1 to equalize with input voltage Sout. Based on the level determination result, input voltage Sout with a low voltage level is AD converted using ramp signal Ramp1 with a small slope as the input voltage VRAMP. On the other hand, input voltage Sout with a high voltage level is AD converted using ramp signal Ramp2 with a large slope as the input voltage VRAMP. This reduces the time required for AD conversion. For a pixel signal (input voltage Sout) with the same signal level, when ramp signal Ramp2 with a large slope is selected, the time count value is 1 / N times that when ramp signal Ramp1 with a small slope is selected. Therefore, by applying an N-fold correction gain to pixel values ​​AD converted using ramp signal Ramp2 as the input voltage VRAMP through bit shifting or correction by a downstream signal processing circuit, it becomes possible to treat the pixel values ​​as pixel signals with the same gradation as pixel values ​​AD converted using ramp signal Ramp1.

[0038] As described above, in this embodiment, the ramp signal to be used is selected according to the level of the pixel signal input to the AD conversion circuit 220. In other words, the photoelectric conversion device 1 performs an operation in which a different ramp signal can be selected for each comparison circuit 209 arranged in each AD conversion circuit 220.

[0039] Next, the physical layout of each circuit block constituting the AD conversion unit 150 will be described using the conceptual diagram of FIG. 5. Among the circuit blocks constituting the AD conversion unit 150, circuit blocks of the same type are laid out so that they are arranged in adjacent areas. This is because forming the circuit elements arranged in the same type of circuit blocks in adjacent areas is suitable for reducing manufacturing-related characteristic variations between circuit blocks of the same type. Here, among the circuit blocks corresponding to the signal output lines VL1, VL2, VL3, and VL4, the selection circuits 201a, 201b, 201c, and 201d and the buffer circuits 202a, 202b, 202c, and 202d are arranged in adjacent areas. Furthermore, the comparison circuits 209a, 209b, 209c, and 209d are arranged in adjacent areas. The wiring area 200 represents the area extending from the buffer circuits 202a, 202b, 202c, and 202d to the comparison circuits 209a, 209b, 209c, and 209d. Portions 203a, 203b, 203c, and 203d, portions 204a, 204b, 204c, and 204d, which are parts of the supply line SL, and input capacitances 205a, 205b, 205c, and 205d are arranged in the wiring area 200. Portions 206a, 206b, 206c, and 206d, portions 207a, 207b, 207c, and 207d, which are parts of the signal output lines VL1, VL2, VL3, and VL4, and input capacitances 208a, 208b, 208c, and 208d are also arranged in the wiring area 200.

[0040] 6(a) and 6(b) show wiring layouts corresponding to the wiring region 200 shown in FIG. 5. FIGS. 6(a) and 6(b) can also be considered wiring layouts that focus on the portions 203 and 204 of the supply line SL and the input capacitance 205 in FIG. 3. FIG. 6(a) shows a planar layout of the wiring layer in which the supply line SL is arranged. FIG. 6(b) is a cross-sectional view taken along line A-A' in FIG. 6(a). As shown in FIG. 6(a), the wiring region 200 includes a region 212 in which the portions 203 and 204 of each AD conversion circuit 220 are arranged parallel to each other on the same wiring layer M4. In this case, for example, portions 203a and 204a corresponding to one AD conversion circuit 220 are arranged opposite each other, thereby forming an input capacitance 205a between the portions 203a and 204a. The supply line SL included in each AD conversion circuit 220 can supply ramp signals Ramp1 and Ramp2 from the selection circuit 201 to the comparison circuit 209 by capacitive coupling between the portion 203 and the portion 204 in the region 212. In the configuration shown in FIG. 6(a), the portion 203 and the portion 204 of the supply line SL are arranged on the wiring layer M4, and an input capacitance 205 is formed therebetween. However, this is not limited thereto, and a capacitance element may be formed as the input capacitance in the wiring layers M1 to M3 and M5 different from the wiring layer M4 on which the portions 203 and 204 are arranged. In this case, the portion 203 and the capacitance element and the portion 204 and the capacitance element may be connected by a conductive pattern via a conductive via or the like.

[0041] Now, let us focus on the adjacent AD conversion circuits 220. A shielded line 230 is arranged between portions 203a and 204a of a supply line SL1 included in the AD conversion circuit 220 including the comparison circuit 209a and portions 203b and 204b of a supply line SL2 included in the AD conversion circuit 220 including the comparison circuit 209b, in order to reduce crosstalk caused by capacitive coupling. A shielded line 230 is also arranged between portions 203b and 204b of a supply line SL2 included in the AD conversion circuit 220 including the comparison circuit 209b and portions 203c and 204c of a supply line SL3 included in the AD conversion circuit 220 including the comparison circuit 209c. Similarly, a shield line 230 is arranged between portions 203c and 204c of a supply line SL3 included in the AD conversion circuit 220 including the comparison circuit 209c and portions 203d and 204d of a supply line SL4 included in the AD conversion circuit 220 including the comparison circuit 209d. As shown in FIG. 6(a), the shield line 230 may be fixed to, for example, ground level. However, due to gaps in the shield line 230 or the like, parasitic capacitances 214, 215, and 216 may be generated between adjacent supply lines SL across the shield line 230. As shown in FIG. 6(b), the supply line SL is arranged on the wiring layer M4. Although the shield line 230 is also arranged on the same wiring layer M4, parasitic capacitances 214, 215, and 216 may be generated via, for example, the dielectric between the wiring layer M4 and the wiring layer M5.

[0042] Assume that these parasitic capacitances 214-216 occur between, for example, portion 204a of supply line SL1 connected to comparison circuit 209a and portion 203b of supply line SL2 connected to selection circuit 201b, which supplies a ramp signal to the adjacent comparison circuit 209b. In this case, the voltage level of portion 204a of supply line SL1 connected to comparison circuit 209a is not only influenced by the ramp signal supplied from selection circuit 201a via portion 203a, but also by the ramp signal supplied from selection circuit 201b via portion 203b of supply line SL2. Consider a case where the ramp signal input to comparison circuit 209a and the ramp signal input to comparison circuit 209b are different ramp signals. For example, consider a case where ramp signal Ramp1 is supplied from selection circuit 201a to comparison circuit 209b, and ramp signal Ramp2 is supplied from selection circuit 201b to comparison circuit 209b. In this case, the ramp signal input to the comparison circuit 209a via the portion 204a of the supply line SL1 changes from the slope of the ramp signal Ramp1 that is originally intended to be input to a slope that is intermediate between the slope of the ramp signal Ramp2. If such an unintended change in the slope of the ramp signal occurs in the AD conversion of some pixel signals during AD conversion of pixel signals, the uniformity of the AD conversion gain within the image is lost, which causes a deterioration in the quality of the resulting image.

[0043] To suppress this unintended change in the slope of the ramp signal, in this embodiment, the portions 203 and 204 of the supply line SL, to which the corresponding ramp signals are input, are arranged symmetrically across the shield line 230 in the region 212 between adjacent AD conversion circuits 220. Here, attention is focused on the adjacent AD conversion circuits 220 in the region 212 where the portions 203 and 204 of the supply line SL are arranged parallel to each other on the same wiring layer M4. For example, the portion 203a of the supply line SL1 included in the AD conversion circuit 220 including the comparator circuit 209a is arranged between the portion 204a of the supply line SL1 included in the AD conversion circuit 220 including the comparator circuit 209a and the portion 203b of the supply line SL2 included in the AD conversion circuit 220 including the comparator circuit 209b. Furthermore, for example, the portion 204c of the supply line SL3 included in the AD conversion circuit 220 including the comparator circuit 209c is arranged between the portion 204b of the supply line SL2 included in the AD conversion circuit 220 including the comparator circuit 209b and the portion 203c of the supply line SL3 included in the AD conversion circuit 220 including the comparator circuit 209c. In other words, in adjacent AD conversion circuits 220, the portion 203 of the supply line SL included in one AD conversion circuit 220 or the portion 204 of the supply line SL included in the other AD conversion circuit 220 is arranged between the portion 204 of the supply line SL included in one AD conversion circuit 220 and the portion 203 of the supply line SL included in the other AD conversion circuit 220.

[0044] Typically, in each circuit configuration arranged in the photoelectric conversion device 1, wiring patterns having the same function are formed in the same shape and can have the same impedance. That is, the impedances of the portions 203 of the supply line SL can be the same, and the impedances of the portions 204 can also be the same. On the other hand, the impedances of the portions 203 and 204 can be different. When wiring patterns with different impedances are close to each other, potential fluctuations are likely to affect the wiring pattern on the high-impedance side from the wiring pattern on the low-impedance side.

[0045] Therefore, the above-described arrangement of the supply line SL reduces the parasitic capacitance between the portion 204 of the supply line SL extending from the comparison circuit 209 and the portion 203 connecting the portion 204 and the selection circuit 201, between adjacent AD conversion circuits 220. This reduces crosstalk when different ramp signals are supplied to the comparison circuit 209 between adjacent AD conversion circuits 220, and prevents changes in the slope of the ramp signal. As a result, it is possible to obtain a photoelectric conversion device 1 in which the uniformity of the AD conversion gain within an image is maintained and degradation of the image quality of the resulting image is suppressed.

[0046] Second embodiment Next, a second embodiment of the present disclosure will be described with reference to FIGS. 7 and 8. FIG. 7 is a diagram illustrating a modified example of the pixel circuit 110 and the AD conversion unit 150 shown in FIG. 2 in the photoelectric conversion device 1. Similar to the configuration shown in FIG. 2, the AD conversion units 150u and 150d are provided on both sides of the pixel circuit 110. The configuration of the AD conversion units 150u and 150d may be the same as the configuration shown in FIG. 2. However, in the configuration shown in FIG. 7, the arrangement of the signal output line VL connecting the pixel 111 and the comparison circuit 209 arranged in each AD conversion circuit 220 of the AD conversion unit 150 is different from the configuration shown in FIG. 2. More specifically, the pixel signal from each pixel 111 arranged in the pixel circuit 110 can be output to both the AD conversion unit 150u and the AD conversion unit 150d via the signal output line VL. The other configurations may be the same as those of the above-described embodiment. For example, the arrangement of the portions 203 and 204 of the supply line SL connecting the selection circuit 201 and the comparison circuit 209 may have the above-mentioned symmetrical configuration in the region 212 .

[0047] In the photoelectric conversion device 1 having the configuration of this embodiment shown in FIG. 7 , in addition to the drive mode in which different ramp signals can be supplied to adjacent AD conversion circuits 220 according to the levels of pixel signals, the photoelectric conversion device 1 may operate in the following drive mode. In the AD conversion unit 150u, the selection circuit 201 selects, for example, the ramp signal line 142 that supplies the ramp signal Ramp1 from among the multiple ramp signal lines 141 and 142, and the ramp signal Ramp1 is supplied to the comparison circuit 209. In this case, in the AD conversion unit 150d, the selection circuit 201 selects, from the multiple ramp signal lines 141 and 142, the ramp signal line 141 that supplies the ramp signal Ramp2, which is different from the ramp signal line 142 that supplies the ramp signal Ramp1. This is the drive mode in which the ramp signal Ramp2 is supplied to the comparison circuit 209 of the AD conversion unit 150d. In other words, this is a drive mode in which, while the ramp signal Ramp1 (or Ramp2) is supplied to the comparison circuit 209 of a certain AD conversion circuit 220 in the AD conversion units 150u and 150d, the ramp signal Ramp1 (or Ramp2) is supplied to the comparison circuit 209 of the AD conversion circuit 220 adjacent to the certain AD conversion circuit 220. This drive mode can also be described as a drive mode in which, while the ramp signal Ramp1 (or Ramp2) is supplied to the comparison circuit 209 of a certain AD conversion circuit 220, the ramp signal Ramp2 (or Ramp1) is not supplied to the comparison circuit 209 of the AD conversion circuit 220 adjacent to the certain AD conversion circuit 220. This drive mode can be used, for example, to expand the dynamic range of pixel signals by converting pixel signals output from one pixel 111 with different AD conversion gains and combining the converted signals with different AD conversion gains. The photoelectric conversion device 1 may be configured to have the drive mode described in the first embodiment and the drive mode of this embodiment, and to be switchable between the drive modes.

[0048] FIG. 8 is a diagram illustrating the operation timing of the AD conversion units 150u and 150d of the photoelectric conversion device 1 having the configuration shown in FIG. 8. In the timing diagram shown in FIG. 8, in the AD conversion unit 150u, the selection circuit 201 selects the ramp signal line 142 to which the ramp signal Ramp1 is supplied. In the AD conversion unit 150d, the selection circuit 201 selects the ramp signal line 141 to which the ramp signal Ramp2 is supplied. As a result, a voltage corresponding to the ramp signal Ramp1 is supplied as the input voltage VRAMP to the comparison circuit 209 arranged in the AD conversion unit 150u, and a voltage corresponding to the ramp signal Ramp2 is supplied as the input voltage VRAMP to the comparison circuit 209 arranged in the AD conversion unit 150d. This operation ensures that ramp signals with the same slope are supplied to adjacent AD conversion circuits 220. In other words, unintended changes in the slope of the ramp signal due to the parasitic capacitance described above are suppressed.

[0049] 8 shows an example in which the ramp signal Ramp1 is supplied to the AD conversion unit 150u and the ramp signal Ramp2 is supplied to the AD conversion unit 150d. However, it is sufficient if ramp signals with the same slope are supplied to the AD conversion units 150u and 150d. That is, for example, the ramp signal Ramp2 may be supplied to the AD conversion unit 150u and the ramp signal Ramp1 may be supplied to the AD conversion unit 150d.

[0050] In the drive modes of this embodiment described with reference to FIGS. 7 and 8, the ramp signal input to one comparison circuit 209 is fixed to one ramp signal regardless of the level of the pixel signal. Therefore, it is possible to omit the operation of determining the level of the pixel signal (level determination period) in the first embodiment described with reference to FIG. 4(b). Furthermore, the AD conversion units 150u and 150d simultaneously read pixel signals from the same pixel 111, and perform AD conversion at different AD conversion gains in the AD conversion units 150u and 150d. As described above, two signals obtained by converting one pixel signal at different AD conversion gains are combined in the downstream signal processing circuit 170, image processing LSI 2, or the like, thereby achieving an expansion of the dynamic range of the resulting image. Furthermore, the same ramp signal is supplied to the AD conversion circuits 220 adjacent to each other in the AD conversion units 150u and 150d. As a result, changes in the slope of the ramp signal are suppressed, the uniformity of the AD conversion gain within the image is maintained, and it is possible to obtain a photoelectric conversion device 1 in which degradation of the image quality of the resulting image is suppressed.

[0051] Third embodiment Next, a third embodiment of the present disclosure will be described with reference to Fig. 9. Fig. 9 is a diagram showing a modified example of the pixel circuit 110 and the AD conversion unit 150 shown in Figs. 2 and 7 of the photoelectric conversion device 1. As in the configurations shown in Figs. 2 and 7, in this embodiment as well, the AD conversion units 150u and 150d are provided on both sides (top and bottom) of the pixel circuit 110.

[0052] 9, the photoelectric conversion device 1 has a drive mode in which, while a predetermined ramp signal is supplied to the comparison circuit 209 in a certain AD conversion circuit 220 arranged in the AD conversion unit 150, a constant voltage is supplied to the comparison circuit 209 in an AD conversion circuit 220 adjacent to the AD conversion circuit 220. The photoelectric conversion device 1 may be configured to have the drive modes of the first and second embodiments described above and the drive mode of this embodiment, and to be operable by switching between the drive modes. A configuration for realizing the drive mode of this embodiment will be described below.

[0053] 9, a stop signal PSAVE is input from the controller circuit 300 to the buffer circuits 202 of the AD conversion units 150u and 150d via a stop signal line 811. The buffer circuits 202 that have received the stop signal PSAVE (for example, high level) stop operating, and their output voltages are fixed to a constant voltage, for example, the ground level. That is, some of the buffer circuits 202 also function as circuits for stopping the supply of a ramp signal from the selection circuit 201 to the comparison circuit 209. By fixing the output voltage of the buffer circuit 202 included in the AD conversion circuit 220 to a constant voltage using the stop signal PSAVE, the supply of the ramp signal from the AD conversion circuit 220 to the comparison circuit 209 is stopped.

[0054] In each of the AD conversion units 150u and 150d, the stop signal PSAVE can be supplied to, for example, the buffer circuits 202 of every other AD conversion circuit 220 among the multiple AD conversion circuits 220 arranged corresponding to one pixel column. In the photoelectric conversion device 1 having the configuration shown in FIG. 9, when the device is operated in a drive mode in which the pixel signal level is determined as described above and a ramp signal corresponding to the pixel signal level is supplied, a high level stop signal PSAVE is input. This fixes the output voltage of the buffer circuit 202 connected to the stop signal line 811 to, for example, ground level. The pixels 111 include pixels that output pixel signals only to AD conversion circuits 220 that are not supplied with the stop signal PSAVE, and pixels that output pixel signals to both AD conversion circuits 220 that are not supplied with the stop signal PSAVE and AD conversion circuits 220 that are supplied with the stop signal PSAVE. AD conversion is then performed using only the AD conversion circuits 220 that are not supplied with the stop signal PSAVE. The driving mode of this embodiment can also be said to be a driving mode in which AD conversion is performed by thinning out the AD conversion circuits 220.

[0055] As described above, the buffer circuit 202 is disposed in the portion 203 of the supply line SL. Therefore, in the wiring layout shown in FIGS. 6(a) and 6(b), for example, portions 203b and 203d of the supply lines SL2 and SL4 are fixed to the ground level. Accordingly, portions 204b and 204d of the supply lines SL2 and SL4 are also fixed to the ground level. Therefore, even if different ramp signals are supplied to the supply lines SL1 and SL3, multiple wiring patterns fixed to the ground level, including the shield line 230, are disposed between the supply lines SL1 and SL3. This prevents the slope of the ramp signal from unintentionally changing due to capacitive coupling between the supply lines SL connected to different AD conversion circuits 220, as described above. As a result, the uniformity of the AD conversion gain within an image is maintained, and a photoelectric conversion device 1 can be obtained in which degradation of the image quality of the resulting image is suppressed.

[0056] The circuit configurations shown in FIGS. 2, 7, and 9 may be used in combination as appropriate. That is, the photoelectric conversion device 1 may have a circuit configuration capable of operating in the three drive modes of each of the above-described embodiments. For example, one photoelectric conversion device 1 may be provided with at least two of the drive modes described above and may be used by switching between them as appropriate through user operation or the like. For example, the photoelectric conversion device 1 normally operates in the drive mode described in the first embodiment. On the other hand, when a mode that expands the dynamic range is selected by the user, the photoelectric conversion device 1 operates in the drive mode described in the second embodiment. Furthermore, when a mode that requires higher-precision AD conversion to improve image quality or the like is selected, the photoelectric conversion device 1 operates in the drive mode described in the third embodiment. This not only improves image quality by suppressing crosstalk during AD conversion, but also provides a photoelectric conversion device 1 with improved characteristics that are user-friendly and easy to use, such as an expanded dynamic range.

[0057] An application example of the photoelectric conversion device 1 of this embodiment will now be described with reference to Fig. 10. Fig. 10 is a schematic diagram of an apparatus 9191 including the photoelectric conversion device 1. As shown in Fig. 10, the photoelectric conversion device 1 is housed in a package 920. The package 920 can include a base on which the photoelectric conversion device 1 is fixed and a lid such as glass that faces the photoelectric conversion device 1. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base to pads provided on the photoelectric conversion device 1.

[0058] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the photoelectric conversion device 1. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0059] The processing device 960 processes the signal output from the photoelectric conversion device 1. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device 1. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device 1. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0060] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the photoelectric conversion device 1 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 may further include a storage device 980 and a processing device 960 in addition to the storage circuit and arithmetic circuit provided in the photoelectric conversion device 1. The mechanical device 990 may be controlled based on the signal output from the photoelectric conversion device 1.

[0061] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operations. Alternatively, the mechanical device 990 in the camera can move the photoelectric conversion device 1 for vibration isolation operations.

[0062] The device 9191 can also be applied to an on-board camera mounted on transportation equipment such as a vehicle, a ship, an airplane, or an industrial robot. The mechanical device 990 in transportation equipment can be used as a mobile device. The device 9191 as transportation equipment is suitable for transporting the photoelectric conversion device 1 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a mobile device based on information obtained by the photoelectric conversion device 1. The device 9191 incorporating the photoelectric conversion device 1 is not limited to transportation equipment, but can be widely applied to equipment that uses object recognition, such as an intelligent transport system (ITS). Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, or an office machine such as a copier.

[0063] The disclosure of this specification includes the following photoelectric conversion devices and instruments.

[0064] (Item 1) A photoelectric conversion device comprising: a pixel circuit in which a plurality of pixels are arranged to form a plurality of rows and a plurality of columns; a plurality of ramp signal lines to which ramp signals having different slopes are supplied; and an AD conversion unit in which a plurality of AD conversion circuits, including a first AD conversion circuit and a second AD conversion circuit adjacent to each other, are arranged corresponding to one column, each of the plurality of AD conversion circuits includes: a selection circuit that selects a ramp signal line to select a ramp signal to be used for AD conversion from the plurality of ramp signal lines; a comparison circuit that compares the ramp signal selected by the selection circuit with a pixel signal from a pixel; and a supply line that supplies the ramp signal from the selection circuit to the comparison circuit; the supply line includes a first portion extending from the comparison circuit and a second portion connecting the first portion and the selection circuit; a wiring area in which the supply line is arranged, the wiring area including an area in which the second part of the first AD conversion circuit or the first part of the second AD conversion circuit is arranged between the first part of the first AD conversion circuit and the second part of the second AD conversion circuit;

[0065] (Item 2) The photoelectric conversion device described in item 1, characterized in that in the region, the first portion and the second portion of the first AD conversion circuit and the first portion and the second portion of the second AD conversion circuit are arranged in parallel on the same wiring layer.

[0066] (Item 3) 3. The photoelectric conversion device according to item 1 or 2, wherein the supply line provided in each AD conversion circuit supplies a ramp signal from the selection circuit to the comparison circuit by capacitive coupling between the first portion and the second portion in the region.

[0067] (Item 4) 4. The photoelectric conversion device according to any one of items 1 to 3, wherein a shielded wire is arranged in the region between the first portion and the second portion of the first AD conversion circuit and the first portion and the second portion of the second AD conversion circuit.

[0068] (Item 5) 5. The photoelectric conversion device according to any one of items 1 to 4, characterized in that the selection circuit selects a ramp signal line from the plurality of ramp signal lines that supplies a ramp signal used for AD conversion in accordance with a level of the pixel signal.

[0069] (Item 6) The photoelectric conversion device according to any one of items 1 to 5, wherein, in the first AD conversion circuit, the selection circuit selects a ramp signal line that supplies a first ramp signal from among the plurality of ramp signal lines, and while the first ramp signal is being supplied to the comparison circuit, the second AD conversion circuit has a drive mode in which the first ramp signal is supplied to the comparison circuit or a drive mode in which a constant voltage is supplied.

[0070] (Item 7) A photoelectric conversion device comprising: a pixel circuit in which a plurality of pixels are arranged to form a plurality of rows and a plurality of columns; a plurality of ramp signal lines to which ramp signals having different slopes are supplied; and an AD conversion unit in which a plurality of AD conversion circuits, including a first AD conversion circuit and a second AD conversion circuit adjacent to each other, are arranged corresponding to one column, each of the plurality of AD conversion circuits includes: a selection circuit that selects a ramp signal line to select a ramp signal to be used for AD conversion from the plurality of ramp signal lines; a comparison circuit that compares the ramp signal selected by the selection circuit with a pixel signal from a pixel; and a supply line that supplies the ramp signal from the selection circuit to the comparison circuit; the supply line includes a first portion extending from the comparison circuit and a second portion connecting the first portion and the selection circuit; a wiring region in which the supply line is arranged includes a region in which the first portion and the second portion included in the first AD conversion circuit and the first portion and the second portion included in the second AD conversion circuit are arranged in parallel in the same wiring layer; the photoelectric conversion device is characterized in that, in the first AD conversion circuit, the selection circuit selects a ramp signal line that supplies a first ramp signal from among the plurality of ramp signal lines, and while the first ramp signal is being supplied to the comparison circuit, the second AD conversion circuit has at least one of a drive mode in which the first ramp signal is supplied to the comparison circuit and a drive mode in which a constant voltage is supplied to the comparison circuit.

[0071] (Item 8) 8. The photoelectric conversion device according to item 7, wherein, while the first ramp signal is supplied to the comparison circuit in the first AD conversion circuit, a ramp signal different from the first ramp signal is not supplied to the selection circuit in the second AD conversion circuit.

[0072] (Item 9) the AD conversion unit includes a first AD conversion unit and a second AD conversion unit; the pixel circuit is disposed between the first AD conversion unit and the second AD conversion unit; Item 9. The photoelectric conversion device according to item 7 or 8, characterized in that the photoelectric conversion device has a drive mode in which, in the first AD conversion unit, the selection circuit selects a ramp signal line that supplies a first ramp signal from among the plurality of ramp signal lines, and in the second AD conversion unit, the selection circuit selects, from the plurality of ramp signal lines, a ramp signal line that supplies a second ramp signal different from the ramp signal line that supplies the first ramp signal.

[0073] (Item 10) 10. The photoelectric conversion device according to item 9, wherein each of the plurality of pixels is configured to be able to output a pixel signal to both the first AD conversion unit and the second AD conversion unit.

[0074] (Item 11) The photoelectric conversion device according to any one of items 7 to 10, characterized in that a circuit for stopping the supply of a ramp signal from the selection circuit to the comparison circuit is provided in the supply line of the second AD conversion circuit.

[0075] (Item 12) a buffer circuit is provided on the supply line; 12. The photoelectric conversion device according to item 11, wherein the supply of the ramp signal is stopped by fixing the output voltage of the buffer circuit included in the second AD conversion circuit at the constant voltage.

[0076] (Item 13) Item 13. The photoelectric conversion device according to item 12, wherein the constant voltage includes a ground level.

[0077] (Item 14) 14. The photoelectric conversion device according to item 12 or 13, wherein the buffer circuit is disposed in the second portion of the supply line.

[0078] (Item 15) 15. The photoelectric conversion device according to any one of items 11 to 14, wherein the plurality of pixels include a pixel that outputs a pixel signal to a first AD conversion circuit and a pixel that outputs a pixel signal to the first AD conversion circuit and the second AD conversion circuit.

[0079] (Item 16) A photoelectric conversion device according to any one of items 1 to 15, a processing device that processes a signal output from the photoelectric conversion device; An apparatus characterized by comprising:

[0080] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0081] 1: photoelectric conversion device, 110: pixel circuit, 111: pixel, 141, 142: lamp signal line, 150: AD conversion unit, 200: wiring area, 201: selection circuit, 203, 204: part, 209: comparison circuit, 212: area, 220: AD conversion circuit, SL: supply line

Claims

1. A photoelectric conversion device comprising: a pixel circuit in which a plurality of pixels are arranged to form a plurality of rows and a plurality of columns; a plurality of ramp signal lines to which ramp signals having different slopes are supplied; and an AD conversion unit in which a plurality of AD conversion circuits, including a first AD conversion circuit and a second AD conversion circuit adjacent to each other, are arranged corresponding to one column, each of the plurality of AD conversion circuits includes: a selection circuit that selects a ramp signal line to select a ramp signal to be used for AD conversion from the plurality of ramp signal lines; a comparison circuit that compares the ramp signal selected by the selection circuit with a pixel signal from a pixel; and a supply line that supplies the ramp signal from the selection circuit to the comparison circuit; the supply line includes a first portion extending from the comparison circuit and a second portion connecting the first portion and the selection circuit; A photoelectric conversion device characterized in that the wiring area in which the supply line is arranged includes an area in which the second part of the first AD conversion circuit or the first part of the second AD conversion circuit is arranged between the first part of the first AD conversion circuit and the second part of the second AD conversion circuit.

2. The photoelectric conversion device according to claim 1, characterized in that in the region, the first part and the second part provided in the first AD conversion circuit and the first part and the second part provided in the second AD conversion circuit are arranged parallel to each other in the same wiring layer.

3. The photoelectric conversion device according to claim 1, characterized in that the supply line provided in each AD conversion circuit supplies a ramp signal from the selection circuit to the comparison circuit by capacitive coupling between the first part and the second part in the region.

4. 2. The photoelectric conversion device according to claim 1, wherein a shielded wire is arranged in the region between the first portion and the second portion of the first AD conversion circuit and the first portion and the second portion of the second AD conversion circuit.

5. 2. The photoelectric conversion device according to claim 1, further comprising a drive mode in which the selection circuit selects, from the plurality of ramp signal lines, a ramp signal line that supplies a ramp signal used for AD conversion in accordance with a level of the pixel signal.

6. 2. The photoelectric conversion device according to claim 1, wherein, in the first AD conversion circuit, the selection circuit selects a ramp signal line that supplies a first ramp signal from among the plurality of ramp signal lines, and while the first ramp signal is being supplied to the comparison circuit, the second AD conversion circuit has a drive mode in which the first ramp signal is supplied to the comparison circuit, or a drive mode in which a constant voltage is supplied.

7. A photoelectric conversion device comprising: a pixel circuit in which a plurality of pixels are arranged to form a plurality of rows and a plurality of columns; a plurality of ramp signal lines to which ramp signals having different slopes are supplied; and an AD conversion unit in which a plurality of AD conversion circuits, including a first AD conversion circuit and a second AD conversion circuit adjacent to each other, are arranged corresponding to one column, each of the plurality of AD conversion circuits includes: a selection circuit that selects a ramp signal line to select a ramp signal to be used for AD conversion from the plurality of ramp signal lines; a comparison circuit that compares the ramp signal selected by the selection circuit with a pixel signal from a pixel; and a supply line that supplies the ramp signal from the selection circuit to the comparison circuit; the supply line includes a first portion extending from the comparison circuit and a second portion connecting the first portion and the selection circuit; a wiring region in which the supply line is arranged includes a region in which the first portion and the second portion of the first AD conversion circuit and the first portion and the second portion of the second AD conversion circuit are arranged in parallel in the same wiring layer; the photoelectric conversion device is characterized in that, in the first AD conversion circuit, the selection circuit selects a ramp signal line that supplies a first ramp signal from among the plurality of ramp signal lines, and while the first ramp signal is being supplied to the comparison circuit, the second AD conversion circuit has at least one of a drive mode in which the first ramp signal is supplied to the comparison circuit and a drive mode in which a constant voltage is supplied to the comparison circuit.

8. 8. The photoelectric conversion device according to claim 7, wherein, while the first ramp signal is supplied to the comparison circuit in the first AD conversion circuit, a ramp signal different from the first ramp signal is not supplied to the selection circuit in the second AD conversion circuit.

9. the AD conversion unit includes a first AD conversion unit and a second AD conversion unit, the pixel circuit is disposed between the first AD conversion unit and the second AD conversion unit; 8. The photoelectric conversion device according to claim 7, wherein the photoelectric conversion device includes a drive mode in which, in the first AD conversion unit, the selection circuit selects a ramp signal line that supplies a first ramp signal from among the plurality of ramp signal lines, and in the second AD conversion unit, the selection circuit selects a ramp signal line that supplies a second ramp signal that is different from the ramp signal line that supplies the first ramp signal from among the plurality of ramp signal lines.

10. 10. The photoelectric conversion device according to claim 9, wherein each of the plurality of pixels is configured to be able to output a pixel signal to both the first AD conversion unit and the second AD conversion unit.

11. 8. The photoelectric conversion device according to claim 7, wherein a circuit for stopping the supply of a ramp signal from the selection circuit to the comparison circuit is provided on the supply line of the second AD conversion circuit.

12. a buffer circuit is provided on the supply line; 12. The photoelectric conversion device according to claim 11, wherein the supply of the ramp signal is stopped by fixing the output voltage of the buffer circuit included in the second AD conversion circuit at the constant voltage.

13. 13. The photoelectric conversion device according to claim 12, wherein the constant voltage includes a ground level.

14. 13. The photoelectric conversion device according to claim 12, wherein the buffer circuit is disposed in the second portion of the supply line.

15. 12. The photoelectric conversion device according to claim 11, wherein the plurality of pixels include a pixel that outputs a pixel signal to a first AD conversion circuit and a pixel that outputs a pixel signal to the first AD conversion circuit and the second AD conversion circuit.

16. The photoelectric conversion device according to any one of claims 1 to 15, a processing device that processes a signal output from the photoelectric conversion device; An apparatus characterized by comprising:

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