Manufacturing method for semiconductor device and semiconductor device

Abstract

To provide a manufacturing method for a semiconductor device and a semiconductor device capable of reducing failure in disconnection of an electric fuse.SOLUTION: A manufacturing method for a semiconductor device includes: a step in which a current control circuit 30 causes an AND circuit 4 to switch a disconnection control transistor 3 into an on state to flow a current of a first current value through an electric fuse 2 so as to start fusion of a disconnection region of the electric fuse 2 by using heat generated by flowing the current of the first current value through the electric fuse 2; a step in which a current detection circuit 31 detects a second current value which is smaller than the first current value and larger than 0 ampere; a step in which the current detection circuit 31 outputs a low current detection signal S1 to a detection signal processing circuit 32 based on the detection of the second current value; and a step in which the detection signal processing circuit 32 outputs a control signal to the AND circuit 4 based on the low current detection signal S1 and the AND circuit 4 switches the disconnection control transistor 3 into an off state based on the control signal to disconnect the electric fuse 2.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, for example, to a method for manufacturing a semiconductor device having an electrical fuse and a semiconductor device. [Background technology]

[0002] Some semiconductor devices are equipped with an electric fuse (Patent Document 1 and Patent Document 2). In such semiconductor devices, by cutting the electric fuse, it is possible to adjust the circuit characteristics or remove a defective circuit. To cut the electric fuse, a method of blowing the electric fuse by irradiating it with laser light or a method of blowing the electric fuse by Joule heat caused by passing an electric current is used. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-222691 [Patent Document 2] Japanese Patent Application Publication No. 2024-15652 Summary of the Invention [Problem to be solved by the invention]

[0004] Of the above-mentioned methods for cutting an electric fuse, the method of blowing it by Joule heat is performed as follows. First, a high voltage for cutting the electric fuse is applied from a tester external to the semiconductor device. Then, a clock signal for controlling the cutting time of the electric fuse is input from the tester. Then, when the clock signal is activated, a current flows through the electric fuse, and the electric fuse is blown. However, because the cutting control relies on a tester external to the semiconductor device, there are cases where the electric fuse does not cut properly due to process variations, etc.

[0005] The embodiments described below have been made in consideration of the above, and other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: (d1) electrically disconnecting a fuse element using an externally applied first voltage; and (d2) after step (d1), a current control circuit instructs a control circuit to switch a first transistor to an on state, causing a current having a first current value to flow through the electrical fuse, and starting melting of a disconnection region of the electrical fuse using heat generated by the current of the first current value flowing through the electrical fuse, while applying the first voltage to a first terminal of the electrical fuse. The current detection circuit detects a second current value that is smaller than the first current value and greater than 0 amperes. The current detection circuit outputs a detection signal to a detection signal processing circuit based on the detection of the second current value after step (d2). The detection signal processing circuit outputs a control signal to the control circuit based on the detection signal, and the control circuit switches the first transistor to an off state based on the control signal, thereby disconnecting the electrical fuse. [Effects of the Invention]

[0007] According to the embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing an example of a circuit configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a top view showing an example of the configuration of an electrical fuse in the semiconductor device of FIG. [Figure 3] FIG. 3 is a cross-sectional view of the electrical fuse of FIG. 2 taken along line A. FIG. [Figure 4]FIG. 4 is a top view showing an example of a conventional electrical fuse in which a disconnection failure occurs. [Figure 5] FIG. 5 is a cross-sectional view of the electrical fuse of FIG. 4 taken along line B. FIG. [Figure 6] FIG. 6 is a cross-sectional view of the electrical fuse of FIG. 4 taken along line C. [Figure 7] FIG. 7 is a circuit diagram showing an electrical fuse and a cutoff control transistor. [Figure 8] FIG. 8 is a diagram showing an example of changes in the blowing high voltage, the potential on the other terminal side of the electrical fuse, and the blowing current in the circuit of FIG. [Figure 9] FIG. 9 is a diagram showing a schematic diagram of an electric fuse. [Figure 10] FIG. 10 is a diagram showing a state in which the first portion of the fuse body of the electrical fuse in FIG. 9 has melted. [Figure 11] FIG. 11 is an explanatory diagram showing how the remaining region of the fuse body of the electrical fuse in FIG. 10 is melted by the residual heat. [Figure 12] FIG. 12 is a detailed circuit diagram of the semiconductor device of FIG. [Figure 13] FIG. 13 is a timing chart showing the operation of the semiconductor device of FIG. [Figure 14] FIG. 14 is a block diagram showing an example of a circuit configuration of a semiconductor device according to the second embodiment. [Figure 15] FIG. 15 is a block diagram showing an example of a circuit configuration of a semiconductor device according to the third embodiment. [Figure 16] FIG. 16 is a diagram illustrating the problem of the third embodiment. [Figure 17] FIG. 17 is a diagram illustrating the problem of the third embodiment. [Figure 18] FIG. 18 is a detailed circuit diagram of the semiconductor device of FIG. [Figure 19] FIG. 19 is a timing chart showing the operation of the semiconductor device of FIG. [Figure 20] FIG. 20 is a block diagram showing an example of a circuit configuration of a semiconductor device according to another embodiment. [Figure 21] FIG. 21 is a flowchart of a method for manufacturing a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0009] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0010] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0011] Furthermore, the circuit elements constituting each functional block of the embodiments are formed on a semiconductor substrate such as single crystal silicon using integrated circuit technology such as known CMOS (complementary metal oxide semiconductor transistor). In the embodiments, a MOSFET (metal oxide semiconductor field effect transistor) (abbreviated as MOS transistor) is used as an example of a MISFET (metal insulator semiconductor field effect transistor), but this does not exclude non-oxide films as gate insulating films. In the embodiments, a p-channel MOSFET and an n-channel MOSFET are referred to as a pMOS transistor and an nMOS transistor, respectively.

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated description thereof will be omitted.

[0013] (First embodiment) A schematic diagram of the circuit configuration of a semiconductor device according to this embodiment is shown in Fig. 1. As shown in Fig. 1, the semiconductor device 1 includes an electric fuse 2, a cutoff control transistor 3, an AND circuit 4, a control unit 5, and a current control circuit 30.

[0014] The electrical fuse 2 has one terminal (first terminal) electrically connected to the current control circuit 30 and the other terminal (second terminal) electrically connected to the drain terminal of the cutoff control transistor 3. In Fig. 1, two electrical fuses 2a and 2b are shown as the electrical fuse 2, but three or more may be connected.

[0015] 2, the disconnection control transistor 3 is configured as an nMOS transistor. The drain terminal of the disconnection control transistor 3 is electrically connected to the other terminal of the electrical fuse 2, and the source terminal is supplied with a ground voltage. In other words, the disconnection control transistor 3 functions as a first transistor connected in series between the other terminal of the electrical fuse 2 and the ground potential. As will be described later, this disconnection control transistor 3 switches whether or not a current flows through the electrical fuse 2. Note that although the disconnection control transistor 3 is configured as an nMOS transistor in this embodiment, it may also be configured as a pMOS transistor.

[0016] An output terminal of the AND circuit 4 is electrically connected to the gate terminal of the disconnection control transistor 3. Although two disconnection control transistors 3a and 3b are shown as the disconnection control transistor 3 in FIG. 1, three or more disconnection control transistors may be connected in accordance with the number of electrical fuses 2.

[0017] One input terminal of the AND circuit 4 is electrically connected to a detection signal processing circuit 32 (described later), and the other input terminal is electrically connected to the control unit 5. The output terminal of the AND circuit 4 is connected to the gate terminal of the disconnection control transistor 3. Although FIG. 1 shows only the AND circuit 4 connected to the disconnection control transistor 3a, in reality, a plurality of AND circuits 4 are provided for each disconnection control transistor 3. In other words, each AND circuit 4 controls whether or not to disconnect the corresponding electrical fuses 2a, 2b for each disconnection control transistor 3a, 3b. The AND circuit 4 outputs the logical product of the output signal (control signal) of the detection signal processing circuit 32 (described later) and the output signal of the control unit 5. In other words, the AND circuit 4 functions as a control circuit that controls the switching of the first transistor based on the control signal from the detection signal processing circuit 32.

[0018] The output terminal of the control unit 5 is connected to the other input terminal of the AND circuit 4. The control unit 5 is a circuit that selects, for example, one electrical fuse 2 to be cut, and outputs a selection signal to the AND circuit 4 corresponding to the selected electrical fuse 2.

[0019] The current control circuit 30 includes a current detection circuit 31 and a detection signal processing circuit 32. The current detection circuit 31 is electrically connected to one terminal of the electrical fuse 2. A blowing high voltage VDD is applied to the current detection circuit 31 from a tester 100 provided outside the semiconductor device 1. The blowing high voltage VDD is, for example, 7.5 V. A current reference voltage FVDD_REF is input to the current detection circuit 31 from the tester 100. The current reference voltage FVDD_REF is a reference voltage (second voltage) that serves as a reference for detecting a low current, which will be described later. When the current detection circuit 31 detects a low current, it outputs a low current detection signal S1 to the detection signal processing circuit 32.

[0020] The detection signal processing circuit 32 is electrically connected to the current detection circuit 31. The detection signal processing circuit 32 receives the low current detection signal S1 from the current detection circuit 31. The detection signal processing circuit 32 also receives the disconnection clock signal CLK from the tester 100. The detection signal processing circuit 32 outputs a control signal to the AND circuit 4 based on the low current detection signal S1 and the disconnection clock signal CLK.

[0021] The AND circuit 4 receives the control signal and turns on the disconnection control transistor 3. Then, a disconnection current I1 based on the disconnection high voltage VDD applied from the tester 100 flows through the electrical fuse 2, and the electrical fuse 2 is blown by the disconnection current I1.

[0022] [Supplementary information about the assignment] Here, a disconnection failure of the electrical fuse 2 formed in the semiconductor device 1 will be described with reference to Fig. 2 to Fig. 6. Fig. 2 is a diagram of the electrical fuse 2 formed in the semiconductor device 1 as viewed from above the chip. As shown in Fig. 2, the electrical fuse 2 includes an anode 21, a cathode 22, and a fuse body 23.

[0023] The anode 21 corresponds to one of the terminals described above, and a voltage is applied to it via a current detection circuit 31. The cathode 22 corresponds to the other terminal described above, and is grounded via a cutoff control transistor 3. The fuse body 23 is provided between the anode 21 and the cathode 22, and serves as the portion (cutoff region) that melts down due to the current that accompanies the applied voltage.

[0024] Fig. 3 shows a cross-sectional view taken along line A in Fig. 2. The substrate on which the fuse body 23 is formed has an STI (Shallow Trench Isolation) region 23b formed on an HVNW (High Voltage N-Well) 23a. The fuse body 23 is formed in the shape of a wiring by a polysilicon film 23c formed on the STI region 23b and a metal silicide film 23d, such as a cobalt silicide film (CoSi), formed on the polysilicon film 23c. A silicon nitride film (SiN) 23e is formed on the fuse body 23 so as to cover the polysilicon film 23c and the metal silicide film 23d.

[0025] Fig. 4 is a diagram of the electrical fuse 2 shown in Fig. 2 in a defective cut state, viewed from above the wafer. As shown in Fig. 4, the fuse body 23 is blown by the current flowing from the anode 21 to the cathode 22, and a void Vo is formed on the anode 21 side of the blown fuse body 23. However, melted polysilicon extends from the cathode 22 side of the blown fuse body 23, thereby establishing electrical continuity with the anode 21 side. This is thought to be because the melting point of the silicon nitride film 23e is low, and the melted region of this silicon nitride film 23e serves as a path for the melted polysilicon when the fuse body 23 is blown.

[0026] Fig. 5 shows a cross-sectional view taken along line B in Fig. 4. Fig. 4 shows the cathode 22 side of the blown fuse body 23. As described above, extensions 23ca and 23cb are formed from the polysilicon film 23c in the area where the silicon nitride film 23e was formed.

[0027] Fig. 6 shows a cross-sectional view taken along line C in Fig. 4. Fig. 6 shows the anode 21 side of the blown fuse body 23. The extension 23ca extends so as to avoid the gap Vo. As shown in Fig. 4, the extension 23ca is electrically connected to the anode 21 side of the fuse body 23.

[0028] Next, the current application time for cutting the electrical fuse 2 will be described with reference to Fig. 7 to Fig. 11. Fig. 7 is a circuit diagram showing the electrical fuse 2 and the cutoff control transistor 3.

[0029] 7, VDD indicates the blowing high voltage VDD. VDD measurement indicates measuring the potential on one terminal side of the electrical fuse 2. VD measurement indicates measuring the potential on the other terminal side of the electrical fuse 2. VG indicates the gate terminal of the blowing control transistor 3. I1 is the blowing current I1 described above.

[0030] Figure 8 shows an example of changes in the fusing high voltages VDD and VD and the fusing current I1 in the circuit of Figure 7. In Figure 8, the dashed line indicates the fusing high voltage VDD, the dashed line indicates VD, and the dashed two-dot line indicates I1.

[0031] In FIG. 8, VG is the voltage applied to the gate terminal of the fusing control transistor 3. When the gate voltage VG is applied (high level), the fusing control transistor 3 turns on. Then, the fusing current I1 starts to flow, and VD starts to decrease. Then, VD becomes 0 V after the fusing current I1 exceeds its peak, but the fusing current I1 continues to flow while decreasing, and reaches 0 mA. Then, after the fusing current I1 reaches 0 mA, the gate voltage VG is stopped (low level). As a result, the gate voltage VG is applied more than necessary, which increases the amount of polysilicon film 23c that dissolves, making it easy for the extension 23ca to occur.

[0032] 8, after the peak of the blow current I1, the polysilicon film 23c melts and VD changes to approximately 0 V, but at this timing the blow current I1 is still flowing and complete blowing has not yet occurred. The timing at which the blow current I1 reaches approximately 0 mA is the timing at which the fuse body 23 is completely blown. However, even if the blow current I1 is just about to reach approximately 0 mA, it is possible for the polysilicon film 23c to be blown by the amount of heat remaining in the electrical fuse 2.

[0033] Therefore, in this embodiment, the cutoff control transistor 3 is turned off when the cutoff current I1 reaches almost 0 mA. The circuit shown in Figure 1 has the function of detecting a preset current value of the cutoff current I1 and autonomously turning off the cutoff control transistor 3. Detailed operation will be described later.

[0034] Here, the fact that the polysilicon film 23c can be blown by the amount of heat remaining in the electrical fuse 2 will be described with reference to FIGS. 9 to 11. FIG. 9 is a schematic diagram of the electrical fuse 2 as a rectangular parallelepiped. In FIG. 9, the anode 21, fuse body 23, and cathode 22 are arranged in this order from left to right. The anode 21, fuse body 23, and cathode 22 are all rectangular parallelepipeds with lengths of 600 nm in the x direction, 180 nm in the y direction, and 200 nm in the z direction. The blowing high voltage VDD is 8 V.

[0035] To blow the polysilicon film 23c of the fuse body 23 having the size shown in FIG. 9, if the sheet resistance is 17.1 [Ω / □], then 10.5×10 -9 In addition, because the current required to cut the wire is very large, if the terminal potential difference is 6.0 V, the current peak will be about 35 mA, assuming a peak time of 50 ns. Current I=35mA(=6V / 171Ω) Heat amount=10.5[nJ](=6V×35mA×50ns)

[0036] A part of the 10.5 nJ is dissipated to the electrodes on both ends (anode 21, cathode 22), and the remaining heat melts a region of 600 nm (x direction).

[0037] The area that can be melted with the above amount of heat is 600 nm × 180 nm × 170 nm, and a remaining area 23z of 600 nm × 180 nm × approximately 30 nm is generated (FIG. 10). In FIG. 10, the melted portion (first portion) is indicated by reference symbol 23y. Resistance: 171Ω×2 / 3+171Ω×200nm / 30nm×1 / 3=494Ω Current I=16.2mA(=8V / 494Ω) Heat amount=9.7[nJ](=8V×16.2mA×150ns / 2)

[0038] Most of the heat of 9.7 nJ generated by the current of 16.2 mA is generated in the remaining region 23z of 30 nm (Z direction), and the remaining region 23z is melted by this heat.

[0039] Furthermore, based on the evaluation trends of the inventors so far, it has been found that even if the application of gate voltage VG is interrupted and the current is stopped, the upper limit of the cutting distance that can be achieved with the residual heat is 5.3 nm (Z direction) (Figure 11). Resistance: 171Ω×2 / 3+171Ω×200nm / 5.3nm×1 / 3=2265Ω Current I=3.5mA(=8V / 2265Ω)

[0040] In other words, if the thickness is 5.3 nm or less, it can be cut by residual heat, so the cutting current I1 is preferably 3.5 mA or less. In other words, the cutting current I1 is preferably equal to or less than the current value calculated from the upper limit of the polysilicon wiring film thickness that can be completely melted by residual heat.

[0041] In this way, the timing when the fusing current I1 falls to, for example, 3.5 mA or less is detected, and at that timing the application of the gate voltage VG is interrupted to stop the fusing current I1. Thereafter, the remaining region 23z can be melted by the residual heat. Therefore, the gate voltage VG is not applied more than necessary, and the generation of the extension portion 23ca can be suppressed.

[0042] [Circuit of this embodiment] Fig. 12 shows a detailed circuit diagram of the semiconductor device 1 shown in Fig. 1. Fig. 12 shows a detailed circuit of the current control circuit 30 (current detection circuit 31, detection signal processing circuit 32) shown in Fig. 1. For convenience of illustration, Fig. 12 shows only one electrical fuse 2 and one cutoff control transistor 3.

[0043] The current detection circuit 31 includes a resistor R1 and a sense circuit 311. The resistor R1 is a resistive element having one terminal electrically connected to the tester 100 and to which a blowing high voltage VDD is applied. The other terminal of the resistor R1 is electrically connected to one terminal of the electrical fuse 2. The other terminal of the resistor R1 is also electrically connected to the sense circuit 311. The resistor R1 has a resistance value that does not hinder the blowing of the electrical fuse 2.

[0044] The sense circuit 311 includes a pMOS transistor 31a, a pMOS transistor 31b, an nMOS transistor 31c, an nMOS transistor 31d, an nMOS transistor 31e, an nMOS transistor 31f, a pMOS transistor 31g, an nMOS transistor 31h, and an nMOS transistor 31i.

[0045] The pMOS transistor 31a has a source terminal electrically connected to a power supply. The pMOS transistor 31a has a drain terminal electrically connected to the drain terminal of the nMOS transistor 31c, the gate terminal of the pMOS transistor 31g, and the gate terminal of the nMOS transistor 31h. The pMOS transistor 31a has a gate terminal electrically connected to the gate terminal and drain terminal of the pMOS transistor 31b and the drain terminal of the nMOS transistor 31d.

[0046] The pMOS transistor 31b has a source terminal electrically connected to the power supply.

[0047] The nMOS transistor 31c has a source terminal electrically connected to the source terminal of the nMOS transistor 31d and the drain terminal of the nMOS transistor 31e. The nMOS transistor 31c has a gate terminal electrically connected to the tester 100 and receives the current reference voltage FVDD_REF.

[0048] The nMOS transistor 31d has a gate terminal electrically connected to the other terminal of the resistor R1.

[0049] The source terminal of the nMOS transistor 31e is electrically connected to the drain terminal of the nMOS transistor 31f. The write enable signal wr_e is input to the gate terminal of the nMOS transistor 31e.

[0050] The nMOS transistor 31f has a source terminal to which the ground voltage is supplied, and a gate terminal to which the bias signal bN is input.

[0051] The pMOS transistor 31g has a source terminal electrically connected to a power supply, and a drain terminal electrically connected to the drain terminal of the nMOS transistor 31h, the drain terminal of the nMOS transistor 31i, and the detection signal processing circuit 32.

[0052] The nMOS transistor 31h has a source terminal to which the ground voltage is supplied.

[0053] The nMOS transistor 31i has a source terminal supplied with a ground voltage, and a gate terminal to which a write enable n signal wr_en is input. The write enable n signal wr_en is an inverted signal of the write enable signal wr_e.

[0054] The sense circuit 311 compares the current reference voltage FVDD_REF input to the gate terminal of the nMOS transistor 31c with the potential at the other terminal of the resistor R1 input to the gate terminal of the nMOS transistor 31d. When the potential at the other terminal of the resistor R1 falls below the current reference voltage FVDD_REF, the low current detection signal S1 output to the detection signal processing circuit 32 goes high. Here, the current reference voltage FVDD_REF is a voltage value for detecting a current value (low current value) that can melt the remaining region of the polysilicon film 23c with residual heat, such as 3.5 mA, as described in Figures 9 to 11, and is a voltage value lower than the fusing high voltage VDD. The current reference voltage FVDD_REF is a voltage value lower than the fusing high voltage VDD by the voltage drop that occurs when the low current value flows through the resistor R1.

[0055] The detection signal processing circuit 32 includes an inverter circuit 32a, a NAND circuit 32b, a NAND circuit 32c, an inverter circuit 32d, an inverter circuit 32e, a NAND circuit 32f, a NAND circuit 32g, and an AND circuit 32h.

[0056] The inverter circuit 32a has an input terminal electrically connected to the output of the current detection circuit 31 (sense circuit 311). The inverter circuit 32a has an output terminal electrically connected to the second input terminal of the NAND circuit 32c and the input terminal of the inverter circuit 32e.

[0057] The NAND circuit 32b has a first input terminal electrically connected to the tester 100 and receiving the disconnection clock signal CLK. The NAND circuit 32b has a second input terminal electrically connected to the output terminal of the NAND circuit 32c. The NAND circuit 32b has an output terminal electrically connected to the input terminal of the inverter circuit 32d and the first input terminal of the NAND circuit 32c.

[0058] The inverter circuit 32d has an output terminal electrically connected to a first input terminal of the NAND circuit 32f.

[0059] The inverter circuit 32e has an output terminal electrically connected to a second input terminal of the NAND circuit 32g.

[0060] The second input terminal of the NAND circuit 32f is electrically connected to the output terminal of the NAND circuit 32g, and the output terminal of the NAND circuit 32f is electrically connected to the second input terminal of the AND circuit 32h and the first input terminal of the NAND circuit 32g.

[0061] The AND circuit 32h has a first input terminal electrically connected to the tester 100 and receiving the disconnection clock signal CLK, and an output terminal electrically connected to the first input terminal of the AND circuit 4.

[0062] The detection signal processing circuit 32 has a latch circuit formed by the NAND circuits 32b and 32c, and a latch circuit formed by the NAND circuits 32f and 32g, i.e., the detection signal processing circuit 32 has a double NAND latch circuit configuration.

[0063] Here, the current detection circuit 31 must perform detection at the high voltage VDD for disconnection, so it is powered by the high voltage VDD for disconnection. The detection signal processing circuit 32 processes logical signals, so it is powered by the same power supply as the control unit 5.

[0064] Furthermore, the signal output from the current detection circuit 31 to the detection signal processing circuit 32 is a power supply crossover signal, which changes from a high voltage to a low voltage signal. For this reason, a circuit consisting of nMOS transistors 31i is provided at the output of the current detection circuit, so that the output of the current detection circuit 31 can be fixed at a low level. A write enable n signal wr_en, which is an inverted signal of the write enable signal wr_e, is input to this circuit consisting of nMOS transistors 31i. For this reason, even if the blowing high voltage VDD becomes 0V, such as when the electrical fuse 2 is not blown, the output of the current detection circuit 31 can be fixed.

[0065] The detailed circuits of the current detection circuit 31 and the detection signal processing circuit 32 described above are merely examples, and other types of circuits may be used as long as they perform the same operation as described above, and the positive logic and negative logic of the logic circuit may be defined arbitrarily.

[0066] [Operation of the Circuit of this Embodiment] Next, the operation of the current control circuit 30 (current detection circuit 31, detection signal processing circuit 32) configured as described above will be described with reference to the timing chart of FIG. 13. In the timing chart of FIG. 13, Sc represents the blow current I1 flowing from the resistor R1 in FIG. 12 to the electrical fuse 2. Sd represents the change in potential at the other terminal of the electrical fuse 2. Sa represents the current reference voltage FVDD_REF. Sb represents the potential at the other terminal of the resistor R1. Sh represents the output signal of the NAND circuit 32f. Sg represents the output signal of the inverter circuit 32d. Sf represents the output signal of the current detection circuit 31. Se represents the output signal of the detection signal processing circuit 32.

[0067] First, as a disconnection voltage rise, at time t0, the tester 100 starts to apply the disconnection high voltage VDD and also starts to output the current reference voltage FVDD_REF, which causes the voltages Sb and Sd to start rising.

[0068] Next, at time t1, the write enable signal wr_e is set to high level to start cutting, and at this time the bias signal bN is also set to high level.

[0069] Next, at time t2, the disconnection clock signal CLK is input from the tester 100 (rising to high level). As a result, Sg and Se go to high level. Sg is a write (disconnection) start signal generated by the first-stage latch (NAND circuit 32b, NAND circuit 32c) of the detection signal processing circuit 32. Se is the control signal mentioned above. If a selection signal is output from the control unit 5 to the AND circuit 4 at time t2, the output of the control signal Se causes the output of the AND circuit 4 to go to high level, and the disconnection control transistor 3 turns on. When the disconnection control transistor 3 turns on, a disconnection current I1 (Sc) begins to flow through the electrical fuse 2.

[0070] As the fusing current I1(Sc) begins to flow, the potentials of Sd and Sb also begin to drop. Then, at time t3, when the potential of Sb falls below Sa (current reference voltage FVDD_REF), Sf, which is the low current detection signal S1, goes high. Sb detects the voltage drop in resistor R1 due to the fusing current I1(Sc), and when that voltage drop falls below the current reference voltage FVDD_REF, the low current detection signal S1(Sf) goes high.

[0071] After time t3, the blow current I1(Sc) passes its peak (first current value) and starts to decrease, which indicates that the melting of the fuse body 23 progresses and the wiring (polysilicon) of the fuse body 23 begins to blow.

[0072] Then, at time t4, when the voltage of Sb exceeds Sa, Sf and Sh go low. This indicates that a current (e.g., 3.5 mA) that is determined to be a low-current state due to the voltage drop across resistor R1 has been detected. That is, the current detection circuit 31 outputs a low-current detection signal S1 (Sf: detection signal) to the detection signal processing circuit 32. Sh is a write (cut) end signal generated by the second-stage latch (NAND circuit 32f, NAND circuit 32g) of the detection signal processing circuit 32. Because Sh goes low, Se (control signal), which is the output of AND circuit 32h, goes low. When Se goes low, the AND circuit 4 goes low, and the cutoff control transistor 3 turns off. This stops (ends) the current flowing through the fuse body 23. Thereafter, the fuse is cut off by the residual heat, as described above.

[0073] Then, at time t5, the disconnection clock signal CLK falls to low level, causing Sg to go low and Sh to go high.

[0074] By operating in the above manner, it is possible to turn off the blow control transistor 3 when the electrical fuse 2 is in an ultra-high resistance state and the blow current I1 is barely flowing. Therefore, as shown by the arrow ar in FIG. 13, the application time of Se (the gate voltage of the blow control transistor 3) can be shortened. Furthermore, the blow current I1 can be detected and the length of the ON period of the blow control transistor 3 can be autonomously adjusted. Therefore, it is possible to optimally blow the electrical fuse 2 while using the blow clock signal CLK output from the conventional tester 100.

[0075] Furthermore, the effective period for applying the gate voltage to the disconnection control transistor 3 is determined by the voltage drop across resistor R1. Therefore, even if there are process variations, the effective period for applying the gate voltage can be autonomously adjusted in accordance with those variations, thereby improving product yield.

[0076] (Second embodiment) Next, a second embodiment will be described. In the following, explanations of parts that overlap with the above-described embodiment will be omitted in principle.

[0077] A schematic diagram of the circuit configuration of the semiconductor device according to this embodiment is shown in Fig. 14. As shown in Fig. 14, the semiconductor device 1A includes a bias voltage generating unit 33 and a level shift circuit (L / S) 34 in addition to the configuration shown in Fig. 1.

[0078] [Issues in this embodiment] As explained in the first embodiment, the failure of the electrical fuse 2 to cut is caused by a large amount of polysilicon melting when the fuse is cut. Here, one of the reasons for this is thought to be that, in a current-controlled MOS transistor, variations in threshold voltage Vth cause an increase in the peak current when the fuse is cut. This is because an increase in the peak current when the fuse is cut increases the amount of polysilicon melted, increasing the possibility of electrical conduction through the extension 23ca.

[0079] Therefore, in this embodiment, a circuit is added that generates the peak current at the time of disconnection as a bias current in an internal circuit, thereby suppressing the peak current more than necessary.

[0080] [Circuit Configuration in This Embodiment] 14 includes a constant current source 33a and an nMOS transistor 33b. The constant current source 33a is a current source that matches the peak current value, such as 35 mA, that flows through the electrical fuse 2.

[0081] The nMOS transistor 33b is a replica having the same size and characteristics as the disconnection control transistor 3. That is, the nMOS transistor 33b functions as a second transistor having the same characteristics as the first transistor. The drain terminal of the nMOS transistor 33b is electrically connected to the constant current source 33a, the gate terminal of the nMOS transistor 33b, and the level shift circuit 34. The source terminal of the nMOS transistor 33b is supplied with a ground voltage. The bias voltage generation unit 33 supplies the drain voltage of the nMOS transistor 33b to the level shift circuit 34 as a bias voltage Vb.

[0082] The level shift circuit 34 has three input terminals and one output terminal. The first input terminal of the level shift circuit 34 is electrically connected to the output terminal of the AND circuit 4. The write enable signal wr_e is input to the second input terminal of the level shift circuit 34. The bias voltage generation unit 33 is electrically connected to the third input terminal of the level shift circuit 34, and the bias voltage Vb is input to the third input terminal of the level shift circuit 34.

[0083] When the write enable signal wr_e is at a high level and the output of the AND circuit 4 is at a high level, the level shift circuit 34 applies the bias voltage Vb as the gate voltage of the disconnection control transistor 3. By applying the bias voltage Vb to the disconnection control transistor 3 as the gate voltage, the drain current (disconnection current I1) of the disconnection control transistor 3 can be limited to a value corresponding to the bias voltage Vb.

[0084] According to the configuration of this embodiment, the amount of polysilicon melted can be reduced by suppressing the peak current when the electrical fuse 2 is cut. Therefore, it is possible to prevent the electrical fuse 2 from failing to cut due to variations in the threshold voltage Vth of the MOS transistor.

[0085] (Third embodiment) Next, a third embodiment will be described. In the following, explanations of parts that overlap with the above-described embodiments will be omitted in principle.

[0086] A schematic diagram of the circuit configuration of the semiconductor device according to this embodiment is shown in Fig. 15. As shown in Fig. 15, the semiconductor device 1B includes a PathTr control circuit 35 and a PathTr 36 in addition to the configuration shown in Fig. 1.

[0087] [Issues in this embodiment] Fig. 16 is a re-illustration of Fig. 11. As shown in Fig. 16, just before the cutoff control transistor 3 is turned off, the anode 21 side becomes 0 V or an intermediate potential close to 0 V due to the influence of charge movement due to the unmelted portion (residual region 23z) and delays in the current control circuit 30, etc.

[0088] As a result, the anode 21 is at 0V (or an intermediate potential), and the cathode 22 is at the high voltage VDD for cutting. As shown in Figure 17, if there is residual charge e in the polysilicon of the melted extension 23ca at this time, the melted polysilicon will be prone to movement due to the attractive force of the high voltage VDD for cutting that has been applied since before cutting. For this reason, in order to further reduce defects, it is also important to eliminate (or reduce) the potential difference between the two terminals of the electrical fuse after cutting.

[0089] [Circuit of this embodiment] Fig. 18 shows a detailed circuit diagram of the semiconductor device 1B shown in Fig. 15. Fig. 18 shows detailed circuits of the detection signal processing circuit 32 and the PathTr control circuit 35 shown in Fig. 15.

[0090] The circuit of the detection signal processing circuit 32 shown in Fig. 18 is the same as that shown in Fig. 12, and therefore a detailed description thereof will be omitted. In Fig. 18, the output of the NAND circuit 32f is electrically connected to a first input terminal of a level shift circuit that constitutes the PathTr control circuit 35.

[0091] As described above, the PathTr control circuit 35 is configured with a level shift circuit. The output of the NAND circuit 32f of the detection signal processing circuit 32 is input to a first input terminal of the level shift circuit. The write enable signal wr_e is input to a second input terminal of the level shift circuit. The output terminal of the level shift circuit is electrically connected to the gate terminal of the PathTr 36. The PathTr control circuit 35 controls the gate voltage of the PathTr 36.

[0092] The PathTr 36 is configured with a pMOS transistor. The source terminal of the PathTr 36 is electrically connected to one terminal (on the current detection circuit 31 side) of the electrical fuse 2. The drain terminal of the PathTr 36 is electrically connected to the other terminal (on the cutoff control transistor 3 side) of the electrical fuse 2. In other words, the PathTr 36 functions as a third transistor connected in parallel with the electrical fuse 2. Note that in this embodiment, the PathTr 36 is a pMOS transistor, but it may also be an nMOS transistor. If an nMOS transistor is used, it goes without saying that the signal level output by the PathTr control circuit 35 is also changed appropriately.

[0093] [Operation of the Circuit of this Embodiment] Next, the operation of the circuit (current detection circuit 31, detection signal processing circuit 32) configured as described above will be described with reference to the timing chart of Fig. 19. Sd, Sh, Sg, Sf, CLK, and Se in the timing chart of Fig. 19 are the same as the signals with the same names shown in the timing chart of Fig. 13. The timing from time t0 to time t5 is also the same as that in Fig. 13.

[0094] 19, Sh (write end signal) is low level from time t4 to time t5. Sh is input to the PathTr control circuit 35 and is essentially a signal that controls PathTr 36. The PathTr control circuit 35 converts the low-voltage level Sh into a signal with a high disconnection voltage VDD level and outputs it to PathTr 36. Therefore, PathTr 36 is on from time t4 to time t5. Also, since PathTr 36 is on at time t4, Sd (the other terminal of the electrical fuse 2) is high level.

[0095] Furthermore, the write enable signal wr_e is input to the PathTr control circuit 35, and the PathTr 36 is controlled to be off except during disconnection, so that the read operation after writing (disconnection) is not affected.

[0096] With the configuration of this embodiment, the potential difference between both ends of the electrical fuse 2 disappears after the electrical fuse 2 is cut, making it possible to alleviate voltage stress.

[0097] [Other embodiments] Next, another embodiment will be described. In the following, explanations of parts that overlap with the above-described embodiment will be omitted in principle.

[0098] Fig. 20 is a schematic diagram of the circuit configuration of the semiconductor device according to this embodiment. As shown in Fig. 20, the semiconductor device 1C includes a delay circuit 37 in addition to the configuration shown in Fig. 1. The delay circuit 37 delays the signal output by the detection signal processing circuit 32 by a predetermined time. In detail, the delay circuit 37 delays the trailing edge (the portion where the signal Se changes from high level to low level) of the signal Se shown in Figs. 13 and 19.

[0099] In the first embodiment and other examples, the current value at which the low current detection signal S1 is output is 3.5 mA. However, if an even smaller current is detected, the difference between the current reference voltage FVDD_REF and the blowing high voltage VDD becomes smaller. Therefore, there is a risk that the detection accuracy will be affected and the low current detection signal S1 will be output at a timing that is different from the intended timing. If the low current detection signal S1 is output earlier than the intended timing, it is possible that the residual heat will not be enough to melt the fuse body 23. Therefore, the delay circuit 37 is used to delay the timing. This allows the residual heat to melt the fuse body 23.

[0100] [Method of manufacturing semiconductor device] Next, a method for manufacturing the semiconductor device 1 described in the above embodiment will be described with reference to Fig. 21. In the following description, the semiconductor device 1 will be described, but the semiconductor device 1A, semiconductor device 1B, or semiconductor device 1C may also be used.

[0101] First, a semiconductor substrate is prepared, and then a plurality of circuits are formed on the surface of an area of ​​the semiconductor substrate that will become a semiconductor chip (semiconductor device 1), including an electric fuse 2, a current control circuit 30 equipped with a current detection circuit 31 and a detection signal processing circuit 32, a cutoff control transistor 3, an AND circuit 4, and a control unit 5. This completes the semiconductor manufacturing pre-process (S11).

[0102] Next, the semiconductor device 1 manufactured in the semiconductor pre-manufacturing process is tested (S12). Based on the results of this test process, conditions for the next process of cutting the electrical fuse 2 are obtained. The conditions include, for example, which bit (electrical fuse 2) to cut.

[0103] Next, based on the conditions acquired in S12, the electrical fuse 2 is electrically cut (blown) using a cutting high voltage VDD (first voltage) applied from the external tester 100 (S12a). This process includes the following four steps:

[0104] First, a blowing high voltage VDD is applied to one terminal (first terminal) of the electrical fuse 2. Then, a blowing clock signal CLK is input, and the current control circuit 30 controls the voltage applied to the gate terminal of the blowing control transistor 3 (first transistor) by the AND circuit 4 (control circuit) from low level (first gate voltage) to high level (second gate voltage). This control switches the blowing control transistor 3 to the on state. Then, a blowing current I1 (first current) having a first current value flows through the electrical fuse 2. Therefore, the amount of heat generated by passing the blowing current I1 through the electrical fuse 2 starts to melt the fuse body 23 of the electrical fuse 2. This completes the first step.

[0105] Next, after the first step, as the melting of fuse body 23 progresses, the current value of blow current I1 gradually decreases from the first current value, and current detection circuit 31 detects a second current value that is smaller than the first current value and greater than 0 amperes. An example of the second current value is 3.5 mA as mentioned above. This completes the second step.

[0106] Next, after the second step, the current detection circuit 31 detects the second current value and outputs the low current detection signal S1 to the detection signal processing circuit 32. This completes the third step.

[0107] Next, after the third step, the detection signal processing circuit 32 outputs a control signal to the AND circuit 4 based on the low current detection signal S1. Then, based on the control signal, the AND circuit 4 controls the voltage applied to the gate terminal of the blow control transistor 3 from high level to low level, thereby switching the blow control transistor 3 to the off state. Then, the remaining region 23z of the electrical fuse 2 is blown. This completes the fourth step.

[0108] After the electrical fuses 2 are cut by the above four steps, the semiconductor device 1 is cut from the semiconductor substrate by a dicing step, and individual chip-shaped semiconductor devices 1 are obtained, thus carrying out a post-semiconductor manufacturing step (S13).

[0109] According to the manufacturing method described above, the effective period for applying the gate voltage to the cutoff control transistor 3 is determined by the voltage drop across the resistor R1. Therefore, even if there is process variation, the effective period for applying the gate voltage can be automatically adjusted in accordance with the variation. Furthermore, the electrical fuse 2 can be cut with high precision without individually adjusting the cutoff clock signal CLK. Therefore, the electrical fuse 2 can be cut with high precision. This makes it possible to improve the product yield.

[0110] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0111] 1. Semiconductor device 2 Electrical fuses 3 Disconnection control transistor 4 AND Circuit 30 Current control circuit 31 Current detection circuit 32 Detection signal processing circuit 33 Bias voltage generation unit 34 Level shift circuit 35 PathTr control circuit 36 PathTr S11 Semiconductor manufacturing front-end process S12 Semiconductor Manufacturing Test S12a fuse blown S13 Semiconductor manufacturing post-process

Claims

1. A method of manufacturing a semiconductor device having an electrical fuse, comprising: (a) providing a semiconductor substrate; (b) forming a semiconductor substrate on a surface of a region that will become a semiconductor chip; the electrical fuse; a current control circuit including a current detection circuit electrically connected to a first terminal of the electrical fuse and a detection signal processing circuit electrically connected to the current detection circuit; a first transistor connected in series between the second terminal of the electrical fuse and a ground potential, for switching whether or not a current flows through the electrical fuse; a control circuit that controls switching of the first transistor based on a control signal from the detection signal processing circuit; forming a plurality of circuits including: (c) testing the semiconductor chip on which the plurality of circuits are formed; (d) electrically disconnecting the electrical fuse using an externally applied first voltage based on the result of the test in (c); (e) cutting the semiconductor substrate to obtain the semiconductor chips as the semiconductor device; The step (d) (d1) in a state where the first voltage is applied to the first terminal of the electrical fuse, the current control circuit causes the control circuit to switch the first transistor to an on state, causing a current having a first current value to flow through the electrical fuse, and starting to melt a cutting region of the electrical fuse using heat generated by flowing the current of the first current value through the electrical fuse; (d2) after step (d1), the current detection circuit detects a second current value that is smaller than the first current value and greater than 0 amperes; (d3) after the step (d2), the current detection circuit outputs a detection signal to the detection signal processing circuit based on the detection of the second current value; (d4) after the step (d3), the detection signal processing circuit outputs the control signal to the control circuit based on the detection signal, and the control circuit switches the first transistor to an off state based on the control signal, thereby cutting the electric fuse. A method for manufacturing a semiconductor device.

2. 2. The method for manufacturing a semiconductor device according to claim 1, the wiring that becomes the disconnection region of the electrical fuse is made of polysilicon, the second current value is equal to or less than a current value calculated from an upper limit of the thickness of the polysilicon wiring film that can be completely melted by the residual heat in the disconnection region after switching the first transistor to the off state in the (d4) step. A method for manufacturing a semiconductor device.

3. 2. The method for manufacturing a semiconductor device according to claim 1, The detection of the second current value in the step (d2) is performed by detecting a voltage drop occurring across a resistor element provided in the current detection circuit. A method for manufacturing a semiconductor device.

4. 4. The method for manufacturing a semiconductor device according to claim 3, The detection of the second current value in the step (d2) is performed based on a second voltage input to the current detection circuit from an external source. A method for manufacturing a semiconductor device.

5. 5. The method for manufacturing a semiconductor device according to claim 4, the first voltage and the second voltage are each a voltage supplied from a tester; A method for manufacturing a semiconductor device.

6. 3. The method for manufacturing a semiconductor device according to claim 2, a silicon nitride film is formed on the upper layer of the polysilicon so as to cover the polysilicon; A method for manufacturing a semiconductor device.

7. 2. The method for manufacturing a semiconductor device according to claim 1, a bias voltage generated based on a second transistor having the same characteristics as the first transistor is applied to a gate terminal of the first transistor in the step (d); A method for manufacturing a semiconductor device.

8. 2. The method for manufacturing a semiconductor device according to claim 1, a third transistor is connected in parallel with the electrical fuse; After the step (d4), the detection signal processing circuit controls the third transistor so that the potential difference between both ends of the electrical fuse is eliminated. A method for manufacturing a semiconductor device.

9. 2. The method for manufacturing a semiconductor device according to claim 1, In the step (b), delay circuits that delay the control signal are formed as the plurality of circuits; In the step (d4), the control signal output from the detection signal processing circuit is delayed by the delay circuit. A method for manufacturing a semiconductor device.

10. Electric fuses and a current control circuit including a current detection circuit electrically connected to a first terminal of the electrical fuse and a detection signal processing circuit electrically connected to the current detection circuit; a first transistor connected in series between the second terminal of the electrical fuse and a ground potential, for switching whether or not a current flows through the electrical fuse; a control circuit that controls switching of the first transistor based on a control signal from the detection signal processing circuit; Equipped with the current control circuit causes a current having a first current value to flow through the electrical fuse, and melts a cutting region of the electrical fuse using heat generated by the current having the first current value flowing through the electrical fuse; the current detection circuit detects a second current value, which is smaller than the first current value and larger than 0 amperes, of the current value applied to the electrical fuse, and outputs a detection signal to the detection signal processing circuit; the detection signal processing circuit outputs the control signal to the control circuit based on the detection signal; the control circuit switches the first transistor to an off state based on the control signal; Semiconductor device.

11. 11. The semiconductor device according to claim 10, A bias voltage generated based on a second transistor having the same characteristics as the first transistor is applied to a gate terminal of the first transistor. Semiconductor device.

12. 11. The semiconductor device according to claim 10, a third transistor connected in parallel with the electrical fuse; the third transistor is controlled by the detection signal processing circuit; Semiconductor device.

13. 11. The semiconductor device according to claim 10, a delay circuit for delaying the control signal; Semiconductor device.

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