Semiconductor device

Abstract

To provide a semiconductor device capable of improving voltage-withstanding.SOLUTION: A semiconductor device includes: a semiconductor substrate 1; an insulating layer 2 which is provided on the semiconductor substrate 1; a first high-resistance portion RP which is embedded in the insulating layer 2 and arranged so as to surround a first electrode E1 in a plan view; a second high-resistance portion RN which is embedded in the insulating layer 2 and arranged so as to surround a second electrode E2 in a plan view; and low-resistance portions (RPS, RNS) for voltage detection which are electrically connected to the first high-resistance portion RP and the second high-resistance portion RN and have resistance values lower than respective resistance values of the first high-resistance portion RP and the second high-resistance portion RN.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a plurality of resistor elements within a chip. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2023 / 085026

[0004] [overview] The present disclosure provides a semiconductor device capable of improving the breakdown voltage.

[0005] The semiconductor device of the present disclosure comprises a semiconductor substrate, an insulating layer provided on the semiconductor substrate, a first high resistance portion embedded in the insulating layer and arranged to surround the first electrode in a planar view, a second high resistance portion embedded in the insulating layer and arranged to surround the second electrode in a planar view, and a low resistance portion for voltage detection electrically connected to the first high resistance portion and the second high resistance portion and having a resistance value lower than the resistance values ​​of the first high resistance portion and the second high resistance portion. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram of a high voltage detection device. [Figure 2] FIG. 2 is a circuit diagram of a resistor of a first example (FIG. 2(A)) and a circuit diagram of a resistor of a second example (FIG. 2(B)). [Figure 3] FIG. 3 is a plan view of a semiconductor package equipped with a high-voltage detection device. [Figure 4] FIG. 4 is a plan view of the resistor chip. [Figure 5] FIG. 5 is a plan view of the resistor chip. [Figure 6] FIG. 6 is a graph showing the relationship between the distance r from the center of the first electrode or the second electrode and the magnitude of the voltage V. [Figure 7] FIG. 7 is a plan view of the high resistance portion according to the first embodiment. [Figure 8] FIG. 8 is a diagram showing a vertical cross-sectional configuration of a high resistance portion. [Figure 9] FIG. 9 is a plan view of a high resistance portion according to the second embodiment. [Figure 10] FIG. 10 is a diagram showing a vertical cross-sectional configuration of the high resistance portion. [Figure 11] FIG. 11 is a plan view of a high resistance portion according to the third embodiment. [Figure 12] FIG. 12 is a plan view of a high resistance portion according to the fourth embodiment. [Figure 13] 13A, 13B, and 13C are plan views of the low resistance portion for voltage detection.

[0007] [Detailed explanation] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in the drawings will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0008] First, the basic structure of the high voltage detection device will be described.

[0009] 1 is a circuit diagram of a high-voltage detection device. The high-voltage detection device includes a resistor circuit C10 (voltage divider circuit) and a voltage detection circuit C20. A first input terminal HV(+) of the resistor circuit C10 is electrically connected to the positive electrode of the battery 200. A second input terminal HV(-) of the resistor circuit C10 is electrically connected to the negative electrode of the battery 200. The first input terminal HV(+) is electrically connected to a first electrode E1 (electrode pad). The second input terminal HV(-) is electrically connected to a second electrode E2 (electrode pad).

[0010] The resistance circuit C10 includes a first high resistance section RP (first resistor), a first low resistance section RPS, a second low resistance section RNS, and a second high resistance section RN (second resistor). The first high resistance section RP, the first low resistance section RPS, the second low resistance section RNS, and the second high resistance section RN are connected in series in this order between the first electrode E1 and the second electrode E2. The first high resistance section RP and the second high resistance section RN have a function of reducing a high voltage and each have a high resistance value. The first low resistance section RPS and the second low resistance section RNS have a function of detecting a voltage and each have a relatively low resistance value compared to the high resistance sections.

[0011] An exemplary resistance value of one high resistance section is 500 MΩ, but it can also be 1 MΩ or more and 1000 MΩ or less. The resistance value of the high resistance section can also be 100 MΩ or more and 800 MΩ or less. The resistance value of the high resistance section can also be 300 MΩ or more and 600 MΩ or less. This resistance value should be a resistance value that can withstand high voltages and allows voltage detection.

[0012] The resistance of one low resistance section (RPS or RNS) is equal to or less than K% of the resistance of the high resistance section. Exemplary values ​​of K are 5%, 3%, 1%, 0.5%, 0.3%, 0.1%, 0.05%, or 0.01%, and the resistance of the low resistance section can be, for example, 0.01 MΩ to 10 MΩ.

[0013] A first output electrode EP (electrode pad) is electrically connected to the connection point between the first high resistance section RP and the first low resistance section RPS. A second output electrode EN (electrode pad) is electrically connected to the connection point between the second high resistance section RN and the second low resistance section RNS. A reference electrode EG (electrode pad) is electrically connected between the first low resistance section RPS and the second low resistance section RNS.

[0014] The resistor circuit C10 is a voltage divider circuit, which can obtain a voltage corresponding to the resistance value between two selected points within the resistor circuit C10. The first output electrode EP is electrically connected to the first input terminal INP of the voltage detection circuit C20. The second output electrode EN is electrically connected to the second input terminal INN of the voltage detection circuit C20. The reference electrode EG is electrically connected to the reference terminal VC of the voltage detection circuit C20. The potential of the reference terminal VC can be set to, for example, ground potential. The voltage detection circuit C20 can output an output voltage Vout. The output voltage Vout can be the sum of a first potential difference between the first input terminal INP and the reference terminal VC and a second potential difference between the second input terminal INN and the reference terminal VC. The voltage detection circuit C20 can include a source follower (amplifier) ​​that amplifies the voltage input from the input terminals and a differential amplifier circuit that obtains the sum of the input voltages. The voltage detection circuit C20 has an input terminal for a power supply voltage Vcc for operating the internal circuit and an input terminal for setting the ground potential GND.

[0015] Resistor circuit C10 may include a dummy resistor.

[0016] FIG. 2 shows a circuit diagram of a resistor of a first example (FIG. 2(A)) and a circuit diagram of a resistor of a second example (FIG. 2(B)).

[0017] In the resistor circuit C10 of FIG. 2A, one end of a dummy resistor R (Dmy) is electrically connected to the input side of the first high resistance section RP. The dummy resistor R (Dmy) is electrically connected to the input side of the second high resistance section RN. The dummy resistor does not need to be electrically connected to a resistor. For example, resistors at both ends of a resistor chip may have different resistance characteristics compared to resistors near the center. Treating such resistors as dummy resistors may improve detection accuracy.

[0018] The resistor circuit C10 in FIG. 2(B) has a configuration that is a modification of the circuit of the first example. In this example, the first high resistance section RP is composed of a high resistance section RP1 and a high resistance section RP2 connected in series, and the second high resistance section RN is composed of a high resistance section RN1 and a high resistance section RN2 connected in series. In addition, the reference electrode EG is separated into a first reference electrode EG1 and a second reference electrode EG2, and these electrodes are electrically connectable on the voltage detection circuit side. Furthermore, compared to the circuit of the first example, one or more dummy resistors R (Dmy) are provided between each resistor section.

[0019] The dummy resistor is a resistor through which no current flows, and is provided to maintain electrical equivalence in the resistor circuit C10, maintain electrical stability, or reduce error factors that may occur during resistor manufacturing in the manufacturing process. The circuit configuration of the high voltage detection device is not limited to these, and the shape and arrangement of the resistor may be changed as long as the basic voltage detection function is achieved.

[0020] The high-voltage detection device described above can be housed in a single semiconductor package, and the functions of each circuit can be separated into a resistor chip and an amplifier chip and mounted in the package.

[0021] 3 is a plan view of a semiconductor package 100 equipped with a high-voltage detection device, with the top cover removed.

[0022] The semiconductor package 100 includes a case 30 having a recess D1. The case 30 is made of an insulating material such as resin or ceramic. The semiconductor package 100 includes a resistor chip 10 (semiconductor device) disposed on a first die pad 110 within the recess D1 and an amplifier chip 20 (semiconductor device) disposed on a second die pad 120 within the recess D1. The open end of the recess D1 of the semiconductor package 100 is sealed with a lid (not shown), creating an enclosed space within the recess D1. The lid may be made of an insulating material such as resin, and the recess D1 may be filled with a gas or an insulating material. An appropriate potential, such as ground potential, is applied to the first die pad 110 and the second die pad 120 via a lead frame. If necessary, the potential of the first die pad 110 may be set to a high potential, for example.

[0023] The resistor chip 10 includes the resistor circuit C10 described above. The amplifier chip 20 includes the voltage detection circuit C20 described above. Therefore, the output voltage of the resistor chip 10 is input to the amplifier chip 20. The amplifier chip 20 outputs an output voltage Vout corresponding to the detected voltage.

[0024] The positive terminal of the battery 200 is electrically connected to the first inner lead 10a and connected to the first electrode of the resistor chip 10 via a bonding wire. The negative terminal of the battery 200 is electrically connected to the second inner lead 10b and connected to the second electrode of the resistor chip 10 via a bonding wire.

[0025] Each terminal of the amplifier chip 20 can be connected to the third inner lead 10c, the fourth inner lead 10d, the fifth inner lead 10e, the sixth inner lead 10f, the seventh inner lead 10g, the eighth inner lead 10h, and the ninth inner lead 10i via bonding wires.

[0026] For example, the third inner lead 10c is supplied with a power supply voltage Vcc and input to the amplifier chip 20. The ninth inner lead 10i is supplied with a ground potential GND and input to the amplifier chip 20. The sixth inner lead 10f can output an output voltage Vout. The fourth inner lead 10d can output a monitor signal corresponding to the potential of the first output electrode EP (FIG. 1) described above. The eighth inner lead 10h can output a monitor signal corresponding to the potential of the second output electrode EN (FIG. 1) described above. The fifth inner lead 10e and the seventh inner lead 10g can be used for other purposes as needed.

[0027] FIG. 4 is a plan view of the resistor chip 10. As shown in FIG.

[0028] The resistor chip 10 is constructed by forming an insulating layer on a semiconductor substrate and embedding a resistor within the insulating layer. The resistor chip 10 has a rectangular planar shape and includes a first side surface 10A, a second side surface 10B, a third side surface 10C, and a fourth side surface 10D. A ring-shaped conductor 1R can be embedded within the insulating layer along these sides. The ring-shaped conductor 1R can be constructed of a metal material (e.g., copper). However, if necessary, a ring-shaped conductor 1R made of another material (e.g., a resistive material CrSi) electrically connected to the top or bottom of the metal material by a via electrode (e.g., tungsten) can be provided. The ring-shaped conductor can contribute to improving waterproofing and electrical stability.

[0029] The resistor chip 10 includes, in a plan view, a first high resistance portion RP arranged to surround the periphery of the first electrode E1 and a second high resistance portion RN arranged to surround the periphery of the second electrode E2. The resistor chip 10 also includes low resistance portions (RPS, RNS) for voltage detection. The low resistance portions (RPS, RNS) are electrically connected to the first high resistance portion RP and the second high resistance portion RN, and have resistance values ​​lower than the resistance values ​​of the first high resistance portion RP and the second high resistance portion RN.

[0030] In this example, in a plan view, the first high resistance portion RP, the first output electrode EP, the first low resistance portion RPS, the reference electrode EG, the second low resistance portion RNS, the second output electrode EN, and the second high resistance portion RN are aligned in one direction. The first output electrode EP is located between the first high resistance portion RP and the first low resistance portion RPS. The second output electrode EN is located between the second high resistance portion RN and the second low resistance portion RNS. A second layer, on which the high resistance portions (RP, RN) and the low resistance portions (RPS, RNS) connected to the buried wiring via via electrodes are formed, is located on a first layer on which the buried wiring for electrical connection is formed. A third layer, on which the first electrode E1 and the second electrode E2 connected to the buried wiring via via electrodes are formed, is located closer to the substrate surface than the second layer.

[0031] In a plan view, the shortest distance between the first high resistance portion RP and the first side surface 10A of the semiconductor chip (semiconductor substrate) is L min The shortest distance between the second high resistance portion RN and the third side surface 10C of the semiconductor chip (semiconductor substrate) is also L min The shortest distance L min The shortest distance L may be between 20 μm and 1000 μm. min The shortest distance L can be set to 40 μm or more and 160 μm or less. min An exemplary design value of the shortest distance L may be 58 μm. min The lower limit of can be set based on processing constraints such as dicing. If it is below the lower limit, the margin during dicing will be small, and the high resistance portion may be more susceptible to the influence of the side surface after cutting. The dimension cut by the dicing blade can be set to 20 μm on one side of the dicing blade. Dicing can also be performed using laser light instead of a dicing blade. In the case of a design in which the distance from the high resistance portion to the side position of the chip is long, or when other circuits such as an LSI (large scale integrated circuit) are mounted on the same chip, the shortest distance L min The value of can be increased, for example, to 1000 μm or less. In the semiconductor device of the present disclosure, the high resistance portion can be brought closer to the chip edge.

[0032] The annular high resistance portion can reduce the rate of change of the potential with respect to distance around the first electrode E1 or the second electrode E2, thereby reducing the electric field strength around the electrodes. This can increase the withstand voltage of the resistor chip 10. By reducing the potential around the periphery of the annular high resistance portion, the influence on the chip side surface can also be reduced, so that the shortest distance L min The resistor can operate stably even if the shortest distance L min The range of (a) is a value that can be set when a ring-shaped high resistance portion is provided.

[0033] FIG. 5 is a plan view of a resistor chip 10 according to another example of arrangement.

[0034] The resistor chip 10 of this example differs from the resistor chip shown in FIG. 4 in the following respects, but the other configurations are the same as those shown in FIG.

[0035] In this example, in a plan view, the first output electrode EP is located to the side of the first high resistance portion RP. The second output electrode EN is located to the side of the second high resistance portion RN. The first low resistance portion RPS and the second low resistance portion RNS are disposed between the first output electrode EP and the second output electrode EN. In other words, the first output electrode EP, the second output electrode EN, the first low resistance portion RPS, and the second low resistance portion RNS are not located on the line connecting the first electrode E1 and the second electrode E2. A reference electrode EG is electrically connected to the connection point between the first low resistance portion RPS and the second low resistance portion RNS.

[0036] FIG. 6 is a graph showing the relationship between the distance r from the center of the first electrode E1 or the second electrode E2 (see FIG. 4 or FIG. 5) and the magnitude of the voltage V.

[0037] The center of gravity of the first electrode E1 (or the second electrode E2) is defined as the origin 0. In a plan view, the position of one edge of the electrode along one direction is defined as the first position Ed1, and the position of the other edge is defined as the second position Ed2. If the high resistance portion of the first electrode E1 were to extend only to the first position Ed1 side, the voltage V (potential) on the second position Ed2 side would rapidly decrease as the distance r increases, as shown by the dotted line, resulting in an increase in electric field strength and causing breakdown. In the resistor chip according to the embodiment, the high resistance portion is provided so as to surround the first electrode E1 (or the second electrode E2). Therefore, the voltage V (potential) also on the second position Ed2 side would gradually decrease as the distance r increases, as shown by the solid line, reducing the electric field strength and preventing breakdown. Note that when a spiral-shaped resistor is used, as in the structure of the first embodiment, the magnetic flux generated at the center of the spiral may contribute to improving resistance to surge voltages.

[0038] The shape of the annular high resistance portion will be exemplified.

[0039] FIG. 7 is a plan view of the high resistance portion according to the first embodiment.

[0040] The figure shows the first high resistance section RP (or the second high resistance section RN), which includes a resistor R. The resistor R is a resistive layer made of a resistive material, and extends linearly so as to surround the first electrode E1 (or the second electrode E2) in a plan view. Specifically, the shape of the resistor R in the first high resistance section RP and the shape of the resistor R in the second high resistance section RN are each spiral in a plan view. More specifically, the shape of the resistor R is a polygonal spiral, and in the figure, it has a shape in which linear resistors extending along each side of a hexagon are connected to form a spiral. This polygon may be hexagonal or more. Note that the polygon is at least triangular or more. A resistor extending linearly may be called a linear resistor.

[0041] The direction from the first output electrode EP (or the second output electrode EN) toward the first electrode E1 (second electrode E2) is defined as the X-axis direction, the thickness direction of the resistor chip is defined as the Z-axis direction, and the direction perpendicular to both the X-axis and the Z-axis is defined as the Y-axis direction. The first electrode E1 (second electrode E2) is connected to the via electrode VE C Through the buried wiring BE located below C It is physically and electrically connected to the buried wiring BE. C is physically and electrically connected to one end (the end closest to the center) of the resistor R located above it through a via electrode. The other end (the end closest to the periphery) of the resistor R is connected to the buried wiring BE located below it through a via electrode. P It is physically and electrically connected to the buried wiring BE. P extends to below the first output electrode EP (second output electrode EN), and the via electrode VE P is physically and electrically connected to the first output electrode EP (second output electrode EN) via the

[0042] FIG. 8 is a diagram showing a vertical cross-sectional configuration of the high resistance portion (cross-section along the arrow AA in FIG. 7).

[0043] The resistor chip includes a semiconductor substrate 1, an insulating layer 2 provided on the semiconductor substrate 1, and a protective film 4 provided on the insulating layer 2.

[0044] The insulating layer 2 includes a plurality of laminated dielectric layers (first dielectric layer 2A, second dielectric layer 2B). At least one of the plurality of dielectric layers (first dielectric layer 2A) is made of a material containing silicon oxide. At least one of the plurality of dielectric layers (second dielectric layer 2B) is made of a material containing silicon nitride. In this example, the first dielectric layer 2A and the second dielectric layer 2B are alternately laminated. The silicon oxide in this example is SiO2, but the elemental composition ratio may be changed or other elements may be included as necessary. The silicon nitride in this example is Si3N4, but the elemental composition ratio may be changed or other elements may be included as necessary. The thickness of the insulating layer 2 may be, for example, 5 μm or more and 50 μm or less.

[0045] The insulating layer 2 is a lower dielectric layer 2A formed on a second dielectric layer 2B located at the top. L and the lower dielectric layer 2A L A first upper dielectric layer 2A formed on H1 and the second upper dielectric layer 2A H2 The lower dielectric layer 2A L , first upper dielectric layer 2A H1 and the second upper dielectric layer 2A H2 The exemplary material is the same as the material of the first dielectric layer 2A.

[0046] The protective film 4 includes a first protective film 4A, a second protective film 4B, and a third protective film 4C, which are sequentially stacked on the insulating layer 2. The first protective film 4A may be made of an inorganic insulator such as silicon oxide or silicon nitride, for example, SiO2. The second protective film 4B is formed on the first protective film 4A. The second protective film 4B is made of an inorganic insulator such as silicon oxide or silicon nitride, and may be the same as or different from the material of the first protective film 4A, for example, silicon nitride. The third protective film 4C is made of a resin (insulator) such as polyimide.

[0047] The protective film 4 is removed in the areas directly above the first electrode E1 (second electrode E2) and the first output electrode EP (second output electrode EN). Therefore, the upper surfaces of the first electrode E1 (second electrode E2) and the first output electrode EP (second output electrode EN) are exposed. Wiring (bonding wires, wiring patterns) are connected to the upper surfaces of these electrodes (electrode pads).

[0048] Embedded wiring BE C and buried wiring BE P is the lower dielectric layer 2A L The resistive layer constituting the resistor R is formed on the first upper dielectric layer 2A. H1 The first electrode E1 (second electrode E2) is formed on the second upper dielectric layer 2A. H2 Via electrode VE C is the first electrode E1 (second electrode E2) and the buried wiring BE CThe via electrode VE is connected to the C2 is buried wiring BE C and one end of the annular center of the resistor R. P2 is connected to one end of the periphery of the annular resistor R and the buried wiring BE P The via electrode VE is connected to the P is buried wiring BE P and the first output electrode EP (second output electrode EN).

[0049] FIG. 9 is a plan view of a high resistance portion according to the second embodiment.

[0050] The figure shows the first high resistance portion RP (or the second high resistance portion RN), which includes a resistor R. The resistor R is a resistive layer made of a resistive material, and extends linearly so as to surround the first electrode E1 in plan view. Specifically, the shape of the resistor R in the first high resistance portion RP and the shape of the resistor R in the second high resistance portion RN each have a shape that is folded back at a specific position in the circumferential direction in plan view.

[0051] Regarding the first high resistance portion RP, n is a natural number and N is a natural number (3≦N). In this example, N=8, and the resistor R includes eight annular linear regions (R(n): first linear region R(1) to eighth linear region R(8)). The shape of the resistor R in the first high resistance portion RP includes N linear regions R(n) extending along the circumferential direction of the first electrode E1 in a plan view. One linear region R(n) is, for example, the first linear region R(1), and seven linear resistors are arranged along seven sides of an octagon and two linear resistors are arranged along the remaining side.

[0052] The resistor R includes a first connection region R(Cn(n+1)) that radially connects one end of each of the n-th linear region R(n) and the n+1-th linear region R(n+1) that are radially adjacent from the inside among the linear regions R(n). The resistor R includes, for example, a first connection region R(C1(2)) that radially connects one end of each of the first linear region R(1) and the second linear region R(2).

[0053] The resistor R includes a second connection region R(n+1(n+2)) that radially connects the other ends of the n+1th linear region R(n+1) and the n+2th linear region R(n+2) that are radially adjacent from the inside among the linear regions R(n). The resistor R includes, for example, a second connection region R(C2(3)) that radially connects one end of the second linear region R(2) and the third linear region R(3).

[0054] In the figure, the wire resistors extending along each side of an octagon are joined together to form the folded structure. This polygon may be octagonal or larger. However, the polygon must have at least three sides.

[0055] Regarding the second high resistance portion RN, if m is a natural number and M is a natural number (3≦M), n and N in the above description are replaced with m and M, respectively.

[0056] In this case, the resistor R of the second high resistance section RN has a shape including M linear regions (R(m): first linear region R(1) to eighth linear region R(8)) extending in the circumferential direction of the second electrode E2 in a plan view. The resistor R includes a third connection region R(m(m+1)) that radially connects one end of each of the m-th linear region R(m) and the (m+1)-th linear region R(m+1) that are radially adjacent from the inside among the linear regions of the second high resistance section RN. The resistor R includes a fourth connection region R(Cm+1(m+2)) that radially connects the other end of each of the m+1-th linear region R(m+1) and the (m+2)-th linear region R(m+2) that are radially adjacent from the inside among the linear regions of the second high resistance section RN. Note that exemplary values ​​of n and m are odd numbers.

[0057] FIG. 10 is a diagram showing a vertical cross-sectional configuration of the high resistance portion (cross-section along the arrow AA in FIG. 9).

[0058] The resistor chip includes a semiconductor substrate 1, an insulating layer 2 provided on the semiconductor substrate 1, and a protective film 4 provided on the insulating layer 2. This semiconductor chip differs from the high resistance portion of the first embodiment (FIGS. 7 and 8) in that the resistor R has the folded structure described above, but is otherwise the same as the high resistance portion of the first embodiment.

[0059] FIG. 11 is a plan view of a high resistance portion according to the third embodiment.

[0060] The figure shows the first high resistance portion RP (or the second high resistance portion RN), which includes resistors R (first resistor R1, second resistor R2) that constitute the high resistance portion. The resistors R are resistive layers made of a resistive material, and extend linearly in a plan view so as to surround the first electrode E1 (or the second electrode E2).

[0061] The first resistor R1 has a shape that is folded back at a specific circumferential position in a plan view. The second resistor R2 has a shape that is folded back at a specific circumferential position in a plan view. The structures of the first resistor R1 and the second resistor R2 differ from the resistor R of the second embodiment in the folding back positions. In the second embodiment, the linear resistor extends from 0° to nearly 360° and then folds back, but each resistor (R1, R2) of this example extends from 0° to nearly 180° and then folds back. This example has a structure in which the resistor of the second embodiment is divided into two. By changing the folding back positions, it is possible to configure a resistor with multiple divisions, such as three, four, five, or six divisions.

[0062] The first electrode E1 (second electrode E2) is a via electrode VE C Through the buried wiring BE located below C1 , and buried wiring BE C2 These buried wirings may be common wirings.

[0063] Embedded wiring BE C1is physically and electrically connected to one end (the end closest to the center) of the first resistor R1 located above it through a via electrode. The other end (the end closest to the periphery) of the first resistor R1 is physically and electrically connected to the buried wiring BE located below it through a via electrode. P1 It is physically and electrically connected to the buried wiring BE. P1 extends to below the first output electrode EP (second output electrode EN), and the via electrode VE P is physically and electrically connected to the first output electrode EP (second output electrode EN) via the

[0064] Similarly, buried wiring BE C2 is physically and electrically connected to one end (the end closer to the center) of the second resistor R2 located above it through a via electrode. The other end (the end closer to the periphery) of the second resistor R2 is connected to the buried wiring BE located below it through a via electrode. P2 It is physically and electrically connected to the buried wiring BE. P2 extends to below the first output electrode EP (second output electrode EN), and the via electrode VE P is physically and electrically connected to the first output electrode EP (second output electrode EN) via the

[0065] Embedded wiring BE C1 and buried wiring BE P is the lower dielectric layer 2A L (See FIG. 10). The resistive layer constituting the resistor R is formed on the first upper dielectric layer 2A. H1 (See FIG. 10). The first electrode E1 (second electrode E2) is formed on the second upper dielectric layer 2A. H2 (See Figure 10)

[0066] The vertical cross-sectional configurations and connection relationships of the first resistor R1 and the second resistor R2 are the same as those in the second embodiment (see FIG. 10). C is the first electrode E1 (second electrode E2) and the buried wiring BE C (Buried wiring BE in Figure 11 C1 and buried wiring BE C2) is connected to the via electrode VE in Figure 10. C2 is buried wiring BE C (Buried wiring BE in Figure 11 C1 and buried wiring BE C2 ) and one end of the annular center of the resistor R. P2 is connected to one end of the periphery of the annular resistor R and the buried wiring BE P (Buried wiring BE in Figure 11 P1 and buried wiring BE P2 ) is connected to the via electrode VE. P is the buried wiring BE in Figure 10 P (Buried wiring BE in Figure 11 P1 and buried wiring BE P2 ) and the first output electrode EP (second output electrode EN).

[0067] FIG. 12 is a plan view of a high resistance portion according to the fourth embodiment.

[0068] The figure shows the first high resistance section RP (or second high resistance section RN), which includes resistors R (first resistor R1, second resistor R2) that constitute the high resistance section. The resistors R are resistance layers made of a resistance material, and extend linearly so as to surround the first electrode E1 (or second electrode E2) in plan view. The difference from the high resistance section of the third embodiment is that the orientation of the first resistor R1 is rotated 180° in plan view, and an embedded wiring BE is connected to the outer terminal end of the first resistor R1, which is located on the opposite side from the first output electrode EP (second output electrode EN). P3 The other points are the same as those in the structure of the third embodiment. P3 is the embedded wiring BE connected to the first output electrode EP (second output electrode EN). P1 That is, the buried wiring BE P3 is buried wiring BE P1 The insulating layer 100 can be formed in the same layer as the insulating layer 100 .

[0069] In the structure of the fourth embodiment, the outer terminal end of the resistor can be routed and connected to the first output electrode EP (second output electrode EN) regardless of its position, so this structure can easily be used for resistors that are divided into two or more parts.

[0070] The structure of the low resistance portion for voltage detection is not particularly limited, but an exemplary structure will be described.

[0071] 13A, 13B, and 13C are plan views of the low resistance portion for voltage detection.

[0072] The first low resistance section RPS (or the second low resistance section RNS) is made up of a plurality of linear resistors R E Each resistor R E A via electrode VE is provided below the end of the resistor, and is physically and electrically connected to the buried electrode BE located below the via electrode VE. The number of linear resistors may be three or more, or may be less than three.

[0073] In the example shown in FIG. 13(A), three linear resistors R E The linear resistor R E and one end of the second row of linear resistors R E The first end of the linear resistor R in the second row is connected to the first end of the linear resistor R in the second row through a via electrode VE and a buried electrode BE. E and the other end of the third row linear resistor R E The other end of the via electrode VE is connected to the other end of the buried electrode BE through a via electrode VE and a buried electrode BE.

[0074] In detail, the low resistance portion shown in FIG. 13(A) is made up of a plurality of linear resistors R E In plan view, each linear resistor R E The resistors R extend in a first direction (the left-right direction in the drawing). Eare arranged along the second direction (the vertical direction in the figure) perpendicular to the first direction. k is a natural number, and for example, is an odd number. The kth (e.g., first from the top) linear resistor R E The end of the first side (e.g., the right side of the figure) of the resistor R is connected to the k+1th (e.g., the second) linear resistor R E The k+1th (e.g., second) linear resistor R is electrically connected to the first side (e.g., right side) end of the resistor R. E The second end (e.g., the left side of the figure) of the resistor R is connected to the k+2th (e.g., the third) linear resistor R E is electrically connected to the end of the second side (e.g., the left side of the figure).

[0075] In the example shown in FIG. 13(B), the linear resistor in FIG. 13(A) is divided into two in each row, and a plurality of linear resistors R E Therefore, there are a total of six linear resistors R E In each row, a pair of adjacent linear resistors R E The opposing ends of the electrodes are connected via a via electrode VE and a buried electrode BE.

[0076] In other words, in the structure of FIG. 13(B), each linear resistor R in each row shown in FIG. 13(A) E is configured by connecting two or more linear resistors in series, each extending along a first direction (the left-right direction in the drawing).

[0077] In the example shown in FIG. 13(C), all the linear resistors R E One end of each of the linear resistors R is connected to the other end of each of the linear resistors R through a via electrode VE and a common buried electrode BE. E The other ends of the resistors are connected through a via electrode VE and a common buried electrode BE. In this example, the combined resistance value can be reduced more than that of the resistor shown in FIG.

[0078] In detail, the low resistance portion shown in FIG. 13(C) is made up of a plurality of rows of linear resistors (two or more linear resistors R per row). EIn plan view, the linear resistors in each row extend along a first direction (the left-right direction in the figure). In plan view, the linear resistors in multiple rows are arranged along a second direction (the up-down direction in the figure) that is perpendicular to the first direction. k is a natural number, and is illustratively an odd number. Both ends of the linear resistor in the kth row (e.g., the first from the top) are electrically connected to both ends of the linear resistor in the adjacent k+1th row (e.g., the second).

[0079] In this example, each of the linear resistors in each row is composed of two or more linear resistors R extending along the first direction. E Each row of linear resistors consists of a single linear resistor R E It may also consist of

[0080] The cross-sectional structure of the low resistance section (RPS, RNS) for detection can be the same as that of the high resistance section (RP, RN) except for the planar shape. E The via electrodes VE and the buried electrodes BE (buried wiring) are buried in an insulating layer formed on a semiconductor substrate.

[0081] Furthermore, the low resistance section may be formed of a wide resistive layer extending along a first direction in a plan view. In this case, the width of the resistive layer along a second direction perpendicular to the first direction is set wide. Specifically, the width of this resistive layer is wider than the width of the linear regions of the resistors constituting the first high resistance section and the second high resistance section. If the resistor constituting the high resistance section has a spiral shape, the width direction of this linear region is perpendicular to the direction of extension of the spiral in a plan view. If the resistor constituting the high resistance section has a meandering folded shape, the width direction of this linear region is perpendicular to the longitudinal direction of the meandering extending resistor in a plan view. This resistive layer may contain CrSi, but may also contain other resistive materials constituting the resistive layer, as described below.

[0082] The materials of each element will be explained.

[0083] The semiconductor substrate 1 (FIGS. 8 and 10) may have conductivity. For example, the impurity concentration of the semiconductor substrate 1 may be 5×10 13 (cm -3 ) or more 5 x 10 14 (cm -3 The thickness of the semiconductor substrate 1 may be 50 μm or more and 800 μm or less. The material of the semiconductor substrate 1 may be silicon (Si), but it is also possible to use a compound semiconductor such as SiC or SiGe.

[0084] The material of the resistive layer (wire resistor) constituting the resistor R is a resistive material with a higher resistivity than polysilicon. Specifically, the material of the resistor (resistive layer) is a material containing chromium (Cr) and silicon (Si), such as CrSi, CrSiC, or CrSiN. Other materials can also be used. Specifically, the material of the resistive layer constituting the resistor can include at least one metal compound selected from the group consisting of CrSi, CrSiN, CrSiO, TaN, and TiN. The resistive layer constituting the resistor can be formed using a sputtering method using a target containing a resistive material. Depending on the type of material of the resistor R, a plating method can also be used. The material of the resistor R may be composed of a single resistive material or a combination of multiple resistive materials. The thickness Rd of each resistive layer constituting the resistor R can be 1 nm≦Rd≦5 nm. When the thickness Rd is equal to or less than the upper limit, the resistance value can be sufficiently high, and when the thickness Rd is equal to or greater than the lower limit, the durability and strength of the resistive layer can be maintained.

[0085] The first electrode E1, the second electrode E2, and the buried electrodes (buried wiring) can be made of metal materials such as Al (aluminum) or Cu (copper).The various via electrodes can be made of high-melting-point metals such as tungsten (W), but other electrode materials can also be used.

[0086] As explained above, the resistor chip includes a first high resistance portion RP, a second high resistance portion RN, and a low resistance portion (RPS, RNS) for voltage detection connected therebetween. When a high voltage is applied to the first electrode E1 and the second electrode E2 (electrode pads), the voltage change per unit length near the electrodes becomes steep, and the electric field strength tends to increase. When the electric field strength is high, particularly when a surge voltage is input, the periphery of the electrode pads is easily destroyed. In the resistor chip of the embodiment, the first high resistance portion RP and the second high resistance portion RN surround the electrodes in an annular shape, dispersing the potential distribution in the lateral direction, reducing the voltage change per unit length, lowering the electric field strength, suppressing electric field concentration, and suppressing destruction of the electrode pads.

[0087] (Supplementary Note) As described above, various embodiments of the present disclosure can be defined as the following supplementary notes.

[0088] [A1] A semiconductor device comprising: a semiconductor substrate 1; an insulating layer 2 provided on the semiconductor substrate 1; a first high resistance portion RP embedded in the insulating layer 2 and arranged to surround the first electrode E1 in a planar view; a second high resistance portion RN embedded in the insulating layer 2 and arranged to surround the second electrode E2 in a planar view; and low resistance portions (RPS, RNS) for voltage detection electrically connected to the first high resistance portion RP and the second high resistance portion RN and having a resistance value lower than the resistance values ​​of the first high resistance portion RP and the second high resistance portion RN.

[0089] [A2] The semiconductor device according to [A1], wherein the resistor of the first high resistance portion RP and the resistor of the second high resistance portion RN each have a spiral shape in plan view.

[0090] [A3] The semiconductor device according to [A1], wherein n is a natural number and N is a natural number (3≦N), and the shape of the resistor R of the first high resistance portion RP, in a planar view, comprises: N linear regions extending circumferentially of the first electrode E1; a first connection region radially connecting one end of the n-th linear region and the n+1-th linear region radially adjacent from the inside among the linear regions; and a second connection region radially connecting the other end of the n+1-th linear region and the n+2-th linear region radially adjacent from the inside among the linear regions.

[0091] [A4] The semiconductor device according to [A3], wherein m is a natural number and M is a natural number (3≦M), and the shape of the resistor of the second high resistance section, in a planar view, comprises: M linear regions extending along the circumferential direction of the second electrode; a third connection region radially connecting one end of the m-th linear region and the (m+1)th linear region from the inside that are adjacent in the radial direction among the linear regions of the second high resistance section; and a fourth connection region radially connecting the other end of the (m+1)th linear region and the (m+2)th linear region from the inside that are adjacent in the radial direction among the linear regions of the second high resistance section.

[0092] [A5] In a plan view, the shortest distance L between the first high resistance portion and the side surface of the semiconductor substrate min is 1000 μm or less, and the shortest distance L between the second high resistance portion RN and the side surface of the semiconductor substrate 1 min The semiconductor device according to [A1], wherein the thickness is 1000 μm or less.

[0093] [A6] The semiconductor device according to any one of [A1] to [A5], wherein the low resistance section includes a plurality of linear resistors, each of which extends along a first direction in a plan view, and the linear resistors are arranged along a second direction perpendicular to the first direction in a plan view, and wherein, where k is a natural number, a first end of the k-th linear resistor is electrically connected to a first end of the k+1-th linear resistor adjacent thereto, and a second end of the k+1-th linear resistor is electrically connected to a second end of the k+2-th linear resistor adjacent thereto.

[0094] [A7] The semiconductor device according to [A6], wherein each linear resistor is configured by connecting two or more linear resistors in series, the linear resistors extending along the first direction.

[0095] [A8] The semiconductor device according to any one of [A1] to [A5], wherein the low resistance section includes a plurality of rows of linear resistors, the linear resistors in each row extending along a first direction in a planar view, the linear resistors arranged along a second direction perpendicular to the first direction in a planar view, and both ends of the kth linear resistor, where k is a natural number, are electrically connected to both ends of the adjacent k+1th linear resistor.

[0096] [A9] The semiconductor device according to [A8], wherein the linear resistors in each row are configured by connecting two or more linear resistors extending along the first direction in series.

[0097] [A10] The semiconductor device according to any one of [A1] to [A5], wherein the low resistance section comprises a resistive layer extending along a first direction in a planar view, and the width of the resistive layer along a second direction perpendicular to the first direction is wider than the width of a linear region in a resistor constituting the first high resistance section and the second high resistance section.

[0098] [A11] The semiconductor device according to [A10], wherein the resistive layer contains CrSi.

[0099] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Furthermore, elements from different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims. [Explanation of symbols]

[0100] 1...Semiconductor substrate 1R...Ring conductor 2...Insulating layer 2A...First dielectric layer 2B: Second dielectric layer 2A L ...lower dielectric layer 2A H1 ...first upper dielectric layer 2A H2 ...second upper dielectric layer 4...Protective film 4A…First protective film 4B…Second protective film 4C…Third protective film 10...Resistor chip 10a…1st inner lead 10b…Second inner lead 10c…3rd inner lead 10d…4th inner lead 10e…5th Inner Lead 10f...6th inner lead 10g...7th inner lead 10h…8th inner lead 10i…9th inner lead 10A...First side 10B…Second side 10C…Third side 10D…4th side 20...Amplifier chip 30…cases 100...Semiconductor package 110...First die pad 120...Second die pad 200...battery E1…1st electrode E2…Second electrode HV(+)...First input terminal HV(-)...Second input terminal R…Resistor R(n)…linear area R(m)…linear area R(Cn(n+1))...First connection region R(Cn+1(n+2))...Second connection region R(Cm(m+1))...Third connection region R(Cm+1(m+2))...4th connection region RP...1st high resistance section RN…Second high resistance section BE...buried electrode BE C ,BE C1 ,BE C2 ,BE P ,BE P1 ,BE P2 ,BE P3 …Buried wiring C10…Resistance circuit C20: Voltage detection circuit D1...recess Ed1…1st position Ed2…2nd position EG…Reference electrode EG1…1st reference electrode EG2…Second reference electrode EP…1st output electrode EN: Second output electrode GND: Ground potential INP...First input terminal INN: Second input terminal VC…Reference terminal L min ...shortest distance R(Dmy)...Dummy resistor R E …Linear resistor R1…1st resistor R2…Second resistor RPS...1st low resistance section RNS…Second low resistance section RN1,RN2,RP1,RP2…High resistance part Vcc: power supply voltage VE,VE C ,VE C2 ,VE P ,VE P2 ...Via electrodes Vout: Output voltage

Claims

1. a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a first high resistance portion that is embedded in the insulating layer and that is arranged to surround the first electrode in a plan view; a second high resistance portion that is embedded in the insulating layer and that is disposed so as to surround the second electrode in a plan view; a low resistance section for voltage detection electrically connected to the first high resistance section and the second high resistance section, and having a resistance value lower than each of the first high resistance section and the second high resistance section; A semiconductor device comprising:

2. The resistor of the first high resistance portion and the resistor of the second high resistance portion each have a spiral shape in a plan view. The semiconductor device according to claim 1 .

3. Let n be a natural number, N be a natural number (3≦N), The shape of the resistor of the first high resistance portion is In plan view, N linear regions extending along the circumferential direction of the first electrode; a first connection region that radially connects one end of each of the n-th and (n+1)-th linear regions from the inside, which are adjacent to each other in the radial direction, among the linear regions; a second connection region that radially connects the other end portions of the (n+1)th and (n+2)th linear regions from the inside, which are adjacent to each other in the radial direction, among the linear regions; Equipped with The semiconductor device according to claim 1 .

4. Let m be a natural number and M be a natural number (3≦M), The shape of the resistor of the second high resistance portion is In plan view, M linear regions extending along the circumferential direction of the second electrode; a third connection region that radially connects one end of each of the m-th and (m+1)-th linear regions from the inside, which are adjacent to each other in the radial direction, among the linear regions of the second high resistance portion; a fourth connection region that radially connects the other end portions of the (m+1)th and (m+2)th linear regions from the inside that are adjacent to each other in the radial direction among the linear regions of the second high resistance portion; Equipped with The semiconductor device according to claim 3 .

5. In plan view, The shortest distance L between the first high resistance portion and the side surface of the semiconductor substrate ｍｉｎ is 1000 μm or less, The shortest distance L between the second high resistance portion and the side surface of the semiconductor substrate ｍｉｎ is 1000 μm or less, The semiconductor device according to claim 1 .

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