Electronic component built-in substrate

Abstract

To improve a quality of an electronic component built-in substrate.SOLUTION: An electronic component built-in substrate includes: a core substrate having an opening part opened in a first surface; a plurality of pads provided in a first surface at a predetermined first pitch and having a predetermined pad diameter; an electronic component accommodated in the opening part; a plurality of terminals provided on the first surface side of the electronic component at a second pitch smaller than the first pitch and having a terminal diameter larger than the pad diameter, an insulating layer laminated on the core substrate and the electronic component on the first surface, a first via penetrating the insulating layer and connected to the pad, and a second via penetrating the insulating layer and connected to the terminal.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The disclosed technology relates to a substrate with built-in electronic components. [Background technology]

[0002] Patent Document 1 describes a substrate with built-in electronic components, in which electronic components are housed in a cavity of the substrate. A conductor layer is laminated on the substrate and the electronic components via an interlayer insulating layer, and the conductor layer and the terminal electrodes of the electronic components are connected by via conductors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-76656 Summary of the Invention [Problem to be solved by the invention]

[0004] In an electronic component-embedded substrate in which electronic components are housed in openings in a core substrate, multiple via conductors that penetrate an insulating layer are brought into contact with pads on the core substrate and terminals of the electronic components, respectively. In this case, it is desirable to bring the corresponding via conductors into good contact with the pads on the core substrate and the terminals of the electronic components, respectively. [Means for solving the problem]

[0005] The electronic component-embedded substrate of the present disclosure comprises a core substrate having an opening on a first surface, a plurality of pads arranged on the first surface at a predetermined first pitch and having a predetermined pad diameter, an electronic component housed in the opening, a plurality of terminals arranged on the first surface side of the electronic component at a second pitch smaller than the first pitch and having a terminal diameter larger than the pad diameter, an insulating layer laminated on the core substrate and the electronic component on the first surface, a first via that penetrates the insulating layer and is connected to the pad, and a second via that penetrates the insulating layer and is connected to the terminal.

[0006] According to the embodiments of the present disclosure, in an electronic component built-in substrate in which an electronic component is housed in an opening, vias can be brought into good contact with pads of a core substrate and terminals of the electronic component. [Brief explanation of the drawings]

[0007] [Figure 1A] 1 is a cross-sectional view showing an electronic component built-in substrate according to a first embodiment of the present disclosure. [Figure 1B] 1B is a cross-sectional view taken along line BB in FIG. 1A showing the electronic component built-in substrate according to the first embodiment of the present disclosure. [Figure 1C] 1B is a cross-sectional view taken along line CC in FIG. 1A showing the electronic component built-in substrate according to the first embodiment of the present disclosure. [Figure 1D] 1 is a perspective view showing an electronic component included in an electronic component built-in substrate according to a first embodiment of the present disclosure; [Figure 1E] FIG. 2 is a front view showing an electronic component included in the electronic component built-in substrate according to the first embodiment of the present disclosure. [Figure 2] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for an electronic component-embedded substrate according to the first embodiment of the present disclosure. [Figure 3] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for an electronic component-embedded substrate according to the first embodiment of the present disclosure. [Figure 4] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for an electronic component-embedded substrate according to the first embodiment of the present disclosure. [Figure 5] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for an electronic component-embedded substrate according to the first embodiment of the present disclosure. [Figure 6] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for an electronic component-embedded substrate according to the first embodiment of the present disclosure. [Figure 7] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for an electronic component-embedded substrate according to the first embodiment of the present disclosure. [Figure 8] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for an electronic component-embedded substrate according to the first embodiment of the present disclosure. [Figure 9] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for an electronic component-embedded substrate according to the first embodiment of the present disclosure. [Figure 10] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for an electronic component-embedded substrate according to the first embodiment of the present disclosure. [Figure 11] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for an electronic component-embedded substrate according to the first embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an example of an embodiment of the present disclosure will be described in detail with reference to the drawings.

[0009] Components indicated by the same reference numerals in each drawing are the same or similar components. Duplicate descriptions and reference numerals in the embodiments described below may be omitted. All drawings used in the following description are schematic. The dimensional relationships, ratios, etc. of each element shown in the drawings do not necessarily match those in reality. The dimensional relationships, ratios, etc. of each element do not necessarily match between multiple drawings.

[0010] [First embodiment] Fig. 1A is a cross-sectional view showing an electronic component built-in substrate 10 according to an embodiment. Fig. 1B is a cross-sectional view taken along line BB in Fig. 1A showing the electronic component built-in substrate 10. Fig. 1C is a cross-sectional view taken along line CC in Fig. 1A showing the electronic component built-in substrate 10.

[0011] Electronic component built-in substrate 10 has core substrate 11, resin insulating layer 21, and conductive pattern 22. Core substrate 11 has first surface 11F on the front side and second surface 11S on the back side, i.e., opposite first surface 11F.

[0012] The resin insulating layer 21 is formed on the first surface 11F of the core substrate 11 and on the second surface 11S.

[0013] The conductive patterns 22 are formed on the resin insulating layer 21. Furthermore, a solder resist layer 26 is formed on the outermost conductive pattern 22.

[0014] The core substrate 11 has an insulating base material 13K. In the example shown in Fig. 1, the insulating base material 13K is a single layer. However, a plurality of insulating base materials 13K may be arranged in layers.

[0015] On the outer surfaces in the thickness direction of the core substrate 11, that is, the first surface 11F and the second surface 11S, a conductor pattern 12 is formed on an insulating base material 13K.

[0016] Core substrate 11 has through-holes 15 formed therein that penetrate insulating base material 13K. Through-hole conductors 16 are formed on the inner walls of through-holes 15. The insides of through-hole conductors 16 are filled with hole-filling resin 17. Portions of through-hole conductors 16 are exposed on the first surface 11F side and the second surface 11S side of core substrate 11.

[0017] The portion of the through-hole conductor 16 exposed on the first surface 11F is a pad 18 located on the first surface 11F. The pad 18 is an example of a pad of the disclosed technology. The portion of the through-hole conductor 16 exposed on the second surface 11S is a pad 19 located on the second surface 11S.

[0018] As shown in FIGS. 1B and 1C, each of the pads 18 is circular when viewed normal to the first surface 11F of the core substrate 11. The pads 18 have a predetermined pad diameter D1. The pads 18 are arranged in a matrix on both sides of the opening 11A in the horizontal direction (arrow X direction) and in the vertical direction (arrow Y direction). The term "matrix" refers to the pads being arranged in multiple rows at a constant pitch in two intersecting directions when viewed normal to the first surface 11F of the core substrate 11. In the example shown in FIGS. 1B and 1C, the pads 18 are arranged in two orthogonal directions. The pads 18 are arranged in multiple rows at a first pitch P1 in the arrow X direction and in multiple rows at a first pitch P1 in the arrow Y direction. Each of the pads 18 is located at a lattice point in a square lattice.

[0019] The pads 18 may be arranged in two directions that intersect diagonally. In this case, each of the pads 18 is located at a lattice point of a diamond-shaped lattice. In this case, the pads 18 are also said to be arranged in a staggered pattern.

[0020] Furthermore, the value of the first pitch P1 may be different between the two arrangement directions of the plurality of pads 18.

[0021] The first pitch P1 is the minimum value of the distance between the outer edges of adjacent pads 18 in the direction in which the pads 18 are arranged.

[0022] An opening 11A is formed in the core substrate 11. The opening 11A penetrates the core substrate 11 in the thickness direction. The opening 11A is open to the first surface 11F and the second surface 11S.

[0023] The opening 11A accommodates an electronic component 80. There is no particular limitation on the type of the electronic component 80. The electronic component 80 is, for example, a chip capacitor.

[0024] The surface of electronic component 80 arranged on first surface 11F side is referred to as first component surface 80F of electronic component 80. The surface of electronic component 80 arranged on second surface 11S side is referred to as second component surface 80S of electronic component 80.

[0025] 1D and 1E, a plurality of terminals 81F are provided on a first component surface 80F of the electronic component 80. The terminals 81F are an example of the terminals of the disclosed technology.

[0026] As shown in FIGS. 1B and 1C, all of the plurality of terminals 81F are circular when viewed in the normal direction of the first surface 11F of the core substrate 11. The plurality of terminals 81F have a predetermined terminal diameter D2. The plurality of terminals 81F are arranged in a matrix on the first component surface 80F. By "matrix arrangement", as in the case of the pads 18, it means that when the first component surface 80F is viewed in the normal direction, they are arranged in a plurality of rows at a constant pitch in two intersecting directions. In the example shown in FIGS. 1B and 1C, the arrangement directions of the plurality of terminals 81F are orthogonal in two directions. The plurality of terminals 81F are arranged in a plurality of rows with a second pitch P2 in the arrow X direction, and also arranged in a plurality of rows with the second pitch P2 in the arrow Y direction. Each of the plurality of terminals 81F is located at the lattice point position in a square lattice.

[0027] The arrangement directions of the plurality of terminals 81F may be two directions that intersect obliquely. In this case, each of the plurality of terminals 81F is located at the lattice point position in a rhombic lattice. In this case, it can also be said that the plurality of terminals 81F are arranged in a staggered pattern.

[0028] Furthermore, the values of the second pitch P2 may be different in the two arrangement directions of the plurality of terminals 81F.

[0029] The second pitch P2 is the minimum value of the distance between the outer edges of adjacent terminals 81F in the arrangement direction of the plurality of terminals 81F.

[0030] In the disclosed technology, regarding the pad diameter D1 of the pads 18 and the terminal diameter D2 of the terminals 81F, D1 < D2. Also, regarding the first pitch P1 of the plurality of pads 18 and the second pitch P2 of the plurality of terminals 81F, P1 > P2.

[0031] The conductor pattern 22 on the first surface 11F side and the conductor pattern 22 on the second surface 11S side of the electronic component built-in substrate 10 are connected by via conductors 24 and through-hole conductors 16.

[0032] The height L1 of the external dimension of electronic component 80 is shorter than the thickness T2 of core substrate 11. The height L1 of the external dimension of electronic component 80 is the length from the outer surface of terminal 81F to second component surface 80S. The thickness T1 of core substrate 11 is the length from conductive pattern 12 on first surface 11F to conductive pattern 12 on second surface 11S.

[0033] An outer width W1 of electronic component 80 is shorter than an opening width W2 of opening 11A. The outer width W1 of electronic component 80 is the length between side surfaces 80G of electronic component 80. Side surface 80G of electronic component 80 is spaced apart from inner surface 11N of opening 11A.

[0034] On the first surface 11F side of core substrate 11, first component surface 80F of electronic component 80 is flush with the upper surface of conductor pattern 12 on first surface 11F side of core substrate 11. This "same surface" includes surfaces that are completely flush, as well as surfaces that are considered to be substantially flush with a slight misalignment. On the second surface 11S side of core substrate 11, second component surface 80S of electronic component 80 is located further inward in the thickness direction of core substrate 11 than second surface 11S of core substrate 11.

[0035] The gap between the electronic component 80 and the inner surface 11N of the opening 11A is filled with filled resin 30. The presence of filled resin 30 between the electronic component 80 and the opening 11A fixes the electronic component 80 within the opening 11A. On the second surface 11S side, the filled resin 30 is formed by a portion of the resin of the resin insulating layer 21 penetrating into the opening 11A. The filled resin 30 is integrated with the resin insulating layer 21 on the second surface 11S. The resin material constituting the filled resin 30 is the same as the resin material constituting the resin insulating layer 21.

[0036] The resin insulating layer 21 on the first surface 11F side covers the conductive patterns 12 on the first surface 11F. The resin insulating layer 21 on the first surface 11F side covers the insulating base material 13K in the portions on the first surface 11F where the conductive patterns 12 are not formed. The resin insulating layer 21 on the first surface 11F side covers the portions of the filled resin 30 exposed on the first surface 11F side from the openings 11A. The resin insulating layer 21 on the first surface 11F side covers the first component surface 80F of the electronic component 80. On the first surface 11F side of the core substrate 11, the resin material constituting the resin insulating layer 21 is filled between the conductive patterns 12.

[0037] The resin insulating layer 21 on the second surface 11S side covers the conductive patterns 12 on the second surface 11S. The resin insulating layer 21 on the second surface 11S side covers the insulating base material 13K in the portion on the second surface 11S where the conductive patterns 12 are not formed. The resin insulating layer 21 on the second surface 11S side covers the portion of the electronic component 80 on the second surface 11S side. A portion of the resin insulating layer 21 on the second surface 11S side enters the opening 11A and forms the filled resin 30. The resin material that constitutes the resin insulating layer 21 is also filled between the conductive patterns 12 on the second surface 11S side of the core substrate 11.

[0038] Via holes 23 are formed in resin insulating layer 21, penetrating resin insulating layer 21 in the thickness direction. Via holes 23 are filled with plating to form via conductors 24. Terminals 81F on first surface 11F of electronic component 80 are connected to conductive pattern 22 through via conductors 24.

[0039] As shown in FIG. 1C , among the via conductors 24, the via conductor connected to pad 18 is the first via 24A. Among the via conductors 24, the via conductor connected to terminal 81F is the second via 24B. The portion of the first via 24A that contacts pad 18 has the smallest diameter, and the via diameter of this portion is defined as the first via diameter V1. The portion of the second via 24B that contacts terminal 81F has the smallest diameter, and the via diameter of this portion is defined as the second via diameter V2. In the disclosed technology, regarding the first via diameter V1 and the second via diameter V2, V1≈V2. That is, the first via diameter V1 and the second via diameter V2 are substantially equal, excluding differences due to, for example, tolerances or dimensional variations during manufacturing. Specifically, for example, the second via diameter V2 may have a difference of ±10% with respect to the first via diameter V1.

[0040] Next, a description will be given of a method for manufacturing the electronic component built-in substrate 10. The electronic component built-in substrate 10 is manufactured as follows.

[0041] (1) As shown in Fig. 2, a core substrate 11 is prepared. Through holes 15 are formed in this core substrate 11. Through hole conductors 16 are formed on the inner walls of the through holes 15. The insides of the through hole conductors 16 are filled with a hole-filling resin 17. Parts of the through hole conductors 16 form pads 18 and 19. Openings 11A have not yet been formed in the core substrate 11. The insulating base material 13K included in the core substrate 11 is made of, for example, glass cloth impregnated with BT (bismaleimide triazine) resin, epoxy resin, or the like and cured.

[0042] (2) As shown in Fig. 3, openings 11A are formed in core substrate 11 by router processing. Openings 11A penetrate core substrate 11 in the thickness direction. Openings 11A are open to first surface 11F and second surface 11S.

[0043] 4, core substrate 11 is placed on adhesive tape 40, and opening 11A is closed by first surface 11F. At this time, first surface 11F of core substrate 11 faces adhesive tape 40.

[0044] 5, electronic component 80 is placed in opening 11A. Terminals 81F contact adhesive tape 40. First component surface 80F of electronic component 80 is flush with first surface 11F of core substrate 11.

[0045] (5) As shown in Fig. 6, a resin insulating layer 21 is formed on the second surface 11S of the core substrate 11. The resin material constituting the resin insulating layer 21 is filled between the conductive patterns 12 on the second surface 11S side. On the second surface 11S side, the resin insulating layer 21 covers the conductive patterns 12 and pads 19 on the second surface 11S, and the insulating base material 13K in the portion on the second surface 11S where the conductive patterns 12 and pads 19 are not formed.

[0046] A portion of the resin constituting resin insulating layer 21 is also filled between electronic component 80 and opening 11A. On the first surface 11F side, filled resin 30 contacts adhesive tape 40 from between electronic component 80 and opening 11A. As a result, the gap between electronic component 80 and inner surface 11N of opening 11A is filled with filled resin 30. Electronic component 80 is fixed within opening 11A by filled resin 30. Filled resin 30 is integral with resin insulating layer 21 on second surface 11S.

[0047] The resin insulating layer 21 is made of, for example, a resin film that does not contain a core material and contains an inorganic filler. The resin material that makes up the filled resin 30 is the same as the resin material that makes up the resin insulating layer 21.

[0048] (6) As shown in FIG. 7, the adhesive tape 40 is peeled off.

[0049] (7) As shown in Figure 8, a resin insulating layer 21 is formed on the first surface 11F of the core substrate 11. The resin material constituting the resin insulating layer 21 is filled between the conductive patterns 12 on the first surface 11F. On the first surface 11F side, the resin insulating layer 21 covers the conductive patterns 12 and pads 18 on the first surface 11F, the insulating base material 13K on the first surface 11F in a portion where the conductive patterns 12 and the through-hole conductors 16 are not formed, and the portion of the filling resin 30 exposed on the first surface 11F side from the opening 11A. On the first surface 11F side, the resin material constituting the resin insulating layer 21 is filled between the conductive patterns 12.

[0050] (8) As shown in FIG. 9, via holes 23 are formed by laser processing.

[0051] (9) An electroless plating process is performed, and electroless plated film 33 is formed on resin insulating layer 21 and in via hole 23. In via hole 23, electroless plated film 33 contacts the portion of through-hole conductor 16 that is exposed from first surface 11F and second surface 11S.

[0052] (10) As shown in FIG. 10, a plating resist 34 having a predetermined pattern is formed on the electroless plating film 33.

[0053] (11) An electrolytic plating process is carried out, and as shown in FIG. 11, the via holes 23 are filled with electrolytic plating to form via conductors 24.

[0054] (12) The plating resist 34 is peeled off, and the electroless plated film 33 below the plating resist 34 is removed. The remaining electroless plated film 33 then forms the conductive pattern 22.

[0055] (13) The same processes as those in steps (7) to (12) described above are carried out to form a predetermined number of resin insulating layers 21 and conductive patterns 22 on both the front and back surfaces. Furthermore, solder resist layers 26 are formed on both the front and back surfaces. Through the above steps, the electronic component-embedded substrate 10 shown in FIG. 1 is completed.

[0056] Note that the resin insulating layer 21 may be composed of a prepreg. A prepreg is a resin sheet formed by impregnating a resin containing an inorganic filler into a core material. The resin constituting the prepreg is thermosetting and in a semi-cured state. In this case, a copper foil is laminated on the resin insulating layer 21. Further, a conductor pattern 22 is formed by performing electroless plating treatment and electrolytic plating treatment.

[0057] In the manufacturing method of the electronic component built-in substrate 10 of the present embodiment, a filling resin 30 is filled between the electronic component 80 accommodated in the opening 11A of the core substrate 11 and the opening 11A.

[0058] In the electronic component built-in substrate 10 of the present embodiment, regarding the first via diameter V1 of the first via 24A connected to the pad 18 and the second via diameter V2 of the second via 24B connected to the terminal 81F, V1≈V2. Therefore, in the formation of the via hole 23 and the formation of the electroless plating film 33 in the via hole 23, it is not necessary to distinguish between the first via 24A and the second via 24B, and the manufacturing is easy.

[0059] In the electronic component built-in substrate 10 of the present embodiment, regarding the pad diameter D1 of the pad 18 and the terminal diameter D2 of the terminal 81F, D1<D2. In other words, it is a structure in which the terminal diameter D2 of the terminal 81F is larger than the pad diameter D1 of the pad 18. Therefore, it is easier to realize a state in which the via conductor 24 surely contacts the pad 18 as compared with a configuration in which D1≥D2.

[0060] In a structure in which the side surface 80G of the electronic component 80 is separated from the inner surface 11N of the opening 11A, it is easy to accommodate the electronic component 80 in the opening 11A. However, on the contrary, inside the opening 11A, the position of the electronic component 80 is likely to shift in the direction along the first surface 11F (the direction of arrow X, the direction of arrow Y in FIG. 1B, and the direction obtained by combining these). However, in the electronic component built-in substrate 10 of the present embodiment, even if the position of the electronic component 80 is shifted in this way, a state in which the via conductor 24 is separated from (non-contact with) the pad 18 can be avoided.

[0061] As described above, in a structure in which the terminal diameter D2 of the terminals 81F is larger than the pad diameter D1 of the pads 18, if P1≦P2 is satisfied, the arrangement density of the electronic components 80 on the first component surface 80F of the electronic components 80 will be low. In the electronic component-embedded substrate 10 of this embodiment, the first pitch P1 of the pads 18 and the second pitch P2 of the multiple terminals 81F satisfy P1>P2. Therefore, even in a structure in which the terminal diameter D2 of the terminals 81F is larger than the pad diameter D1 of the pads 18, the terminals 81F can be arranged at high density on the first component surface 80F of the electronic components 80.

[0062] In the electronic component-embedded substrate 10 of this embodiment, the resin material constituting the filled resin 30 and the resin material constituting the resin insulating layer 21 can be selected from resin materials having properties suited to their respective purposes. For example, the resin material constituting the filled resin 30 can be selected from a resin material that is less likely to produce voids when filling the opening 11A. The resin material constituting the resin insulating layer 21 can be selected from a resin material that has high adhesion to the first surface 11F and the second surface 11S of the core substrate 11. Furthermore, for example, by selecting a resin material constituting the resin insulating layer 21 that is less expensive than the resin material constituting the filled resin 30, it is possible to reduce the material cost of the electronic component-embedded substrate 10. Alternatively, the resin material constituting the filled resin 30 and the resin insulating layer 21 can be the same resin material. In this case, the filled resin 30 and the resin insulating layer 21 can be formed from a single resin material, facilitating the manufacture of the electronic component-embedded substrate 10.

[0063] [Other embodiments] (1) Electronic component-embedded substrate 10 may include multiple electronic components 80 with different heights L1. In this case, multiple electronic components 80 may be housed in one opening 11A. Also, multiple openings 11A formed in core substrate 11 may each house one electronic component 80.

[0064] (2) In the above embodiment, the core substrate 11 may be configured to include multiple layers of insulating base material 13K.

[0065] (3) The electronic component 80 may be a passive component such as a resistor or coil, or an active component such as an IC chip including a semiconductor element.

[0066] (4) The resin material constituting the filling resin 30 may be different from the resin material constituting the resin insulating layer 21.

[0067] (5) In a method for manufacturing the electronic component-embedded substrate 10, a support plate may be prepared, adhesive tape 40 (see Figures 4 to 6) may be applied to both sides of the support plate, and the electronic component-embedded substrate 10 may be manufactured in parallel on both sides of the support plate.

[0068] (6) In the above embodiment, the electronic component 80 may be placed on the adhesive tape 40, and then the core substrate 11 may be placed on the adhesive tape 40 so that the electronic component 80 fits within the opening 11A.

[0069] Furthermore, the electronic component-embedded substrate of the technology of the present disclosure is not limited to the structures illustrated in the drawings and the structures, shapes, and materials illustrated in this specification. As described above, the electronic component-embedded substrate of the embodiment may have any layered structure. The electronic component-embedded substrate of the embodiment may include any number of conductor layers and insulating layers.

[0070] The method for manufacturing a substrate with built-in electronic components according to the technology of the present disclosure is not limited to the method described with reference to the drawings. Furthermore, each insulating layer is not limited to a film-like resin, and may be formed using any type of resin. The method for manufacturing a substrate with built-in electronic components according to the embodiment may include any additional process in addition to the processes described above, or some of the processes described above may be omitted. [Explanation of symbols]

[0071] 10. Electronic component embedded board 11 Core board 11A opening 11F Front page 11N inner surface 11S second side 12 Conductor pattern 13K insulating substrate 15 through holes 16 through-hole conductor 17 Hole-filling resin 18 pads 19 Pads 21 Resin insulation layer 22 Conductor pattern 23 Beer Hall 24 via conductor 26 Solder resist layer 30 Filled Resin 33 Electroless plating film 34 Resist 40 adhesive tape 80 Electronic Components 80F First part side 80G side 80S 2nd part side 81F terminal D1 Pad diameter D2 terminal diameter P1 First pitch P2 Second pitch V1 First via diameter V2 Second via diameter

Claims

1. a core substrate having an opening on a first surface; a plurality of pads, each having a predetermined pad diameter, provided at a predetermined first pitch on the first surface; an electronic component accommodated in the opening; a plurality of terminals provided on the first surface of the electronic component at a second pitch smaller than the first pitch, the terminals having a terminal diameter larger than the pad diameter; an insulating layer laminated on the core substrate and the electronic component on the first surface; a first via that penetrates the insulating layer and is connected to the pad; a second via that penetrates the insulating layer and is connected to the terminal; A substrate having an embedded electronic component.

2. 2. The electronic component built-in substrate according to claim 1, A first via diameter at a portion where the first via contacts the pad is equal to a second via diameter at a portion where the second via contacts the terminal.

3. 2. The electronic component built-in substrate according to claim 1, When viewed in the normal direction of the first surface, the terminals are arranged in a plurality of rows in two intersecting directions.

4. 2. The electronic component built-in substrate according to claim 1, The gap between the electronic component and the inner surface of the opening is filled with a filling resin.

5. 2. The electronic component built-in substrate according to claim 1, A first component surface of the electronic component on the first surface side of the core substrate and an upper surface of the conductor pattern on the first surface side of the core substrate are flush with each other.

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