Underfill film and semiconductor package including the underfill film

Abstract

To provide an improved underfill film and a semiconductor package including the underfill film.SOLUTION: An underfill film according to the present invention includes a first film layer having a first dielectric constant and a second film layer disposed on the first film layer and having a second dielectric constant, the second dielectric constant being higher than the first dielectric constant.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an underfill film and a semiconductor package including the underfill film. [Background technology]

[0002] In the semiconductor industry, in response to the demand for smaller and lighter electronic devices, semiconductor packages mounted in electronic devices are being made smaller, lighter, and thinner while at the same time increasing in speed, functionality, and capacity. As a result, there is a growing need for packaging technology that can store more data and transmit data at higher speeds. As such packaging technology, stacked semiconductor devices (e.g., High Bandwidth Memory (HBM)) formed by stacking multiple individual semiconductor dies are being developed.

[0003] Stacked semiconductor devices are manufactured by bonding the same or different semiconductor dies together, but the key to this bonding is that the semiconductor dies must be bonded with high I / O (input / output) density. By increasing the I / O density and making the electrical signal connection density similar to the copper wiring density in the front-end semiconductor process, bonding the same or different semiconductor chips in the back-end semiconductor process can produce the same results as a single semiconductor chip made through the full semiconductor process.

[0004] To manufacture such stacked semiconductor devices, flip-chip bonding technology is used to bond between semiconductor dies. Stacked semiconductor devices manufactured using flip-chip bonding technology include microbumps for electrically connecting the semiconductor dies and an underfill film (non-conductive film (NCF)) placed between the semiconductor dies to protect the microbumps. The underfill film is made of a thermosetting resin with a silica-based inorganic filler added, or a thermosetting resin with an alumina-based inorganic filler added.

[0005] Silica-based underfill films have low viscosity in a liquid state. Therefore, during a bonding process, silica-based underfill films form fillets, which are protruding from between stacked semiconductor dies. Excessive fillets can affect the structure of stacked semiconductor devices and reduce their reliability. Furthermore, due to the low viscosity of silica-based underfill films in a liquid state, they can cause the solder on microbumps to flow during the bonding process, potentially resulting in short-circuiting of the microbumps. Furthermore, silica-based underfill films have low thermal conductivity and high thermal resistance, which can reduce the heat dissipation characteristics of stacked semiconductor devices.

[0006] Alumina-based underfill films have high viscosity in a liquid state, which can prevent the microbumps from wetting onto the bonding pads during the bonding process, and this can prevent the microbumps from bonding to the pads. Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention has been made in view of the above-mentioned problems in the prior art, and an object of the present invention is to provide an improved underfill film and a semiconductor package including the underfill film. [Means for solving the problem]

[0008] In order to achieve the above object, an underfill film according to one aspect of the present invention comprises a first film layer having a first dielectric constant and a second film layer disposed on the first film layer and having a second dielectric constant, the second dielectric constant being higher than the first dielectric constant.

[0009] In order to achieve the above-mentioned object, another aspect of the present invention provides an underfill film comprising a first film layer including a first thermosetting resin and a first inorganic filler, and a second film layer disposed on the first film layer and including a second thermosetting resin and a second inorganic filler, wherein the first film layer has a first dielectric constant and the second film layer has a second dielectric constant, the second dielectric constant being higher than the first dielectric constant.

[0010] In order to achieve the above-mentioned object, a semiconductor package according to one aspect of the present invention comprises a first semiconductor die, a second semiconductor die on the first semiconductor die, a plurality of connection members between the first semiconductor die and the second semiconductor die, and an underfill film surrounding the plurality of connection members between the first semiconductor die and the second semiconductor die, wherein the underfill film includes a first film layer having a first dielectric constant and a second film layer disposed on the first film layer and having a second dielectric constant, the second dielectric constant being higher than the first dielectric constant. [Effects of the Invention]

[0011] The underfill film of the present invention comprises a first film layer having a first dielectric constant and a second film layer disposed on the first film layer and having a second dielectric constant higher than the first dielectric constant, thereby enabling the first film layer to improve wetting of the microbumps to the bonding pads.

[0012] In addition, the second film layer has high thermal conductivity, low thermal resistance, and high viscosity, which improves heat dissipation properties, reduces fillets, and solves the problem of short-circuiting of microbumps. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment; [Figure 2] FIG. 2 is an enlarged cross-sectional view of an area A in FIG. [Figure 3] FIG. 10 is a cross-sectional view showing a semiconductor package according to another embodiment. [Figure 4] 1 is a cross-sectional view illustrating an underfill film according to an embodiment. [Figure 5] 1A-1C are cross-sectional views illustrating the step of providing a wafer including semiconductor dies attached to a carrier. [Figure 6] 1A-1C are cross-sectional views illustrating the step of applying a dicing tape onto a wafer containing semiconductor dies. [Figure 7] 1A-1C are cross-sectional views illustrating steps for removing a carrier from a wafer containing semiconductor dies. [Figure 8] 1A-1C are cross-sectional views illustrating the step of aligning an underfill film on a first side of a wafer including a semiconductor die. [Figure 9] 1A-1C are cross-sectional views illustrating the step of depositing an underfill film on a first side of a wafer including a semiconductor die. [Figure 10] 10A to 10C are cross-sectional views showing a step of removing the buffer layer and the base film from the underfill film. [Figure 11]1A-1C are cross-sectional views illustrating steps for singulating a wafer containing semiconductor dies. [Figure 12] 1A-1C are cross-sectional views illustrating steps of separating the semiconductor die from the dicing tape. [Figure 13] 10A-10C are cross-sectional views illustrating the step of aligning a semiconductor die on a buffer die. [Figure 14] 10A-10C are cross-sectional views illustrating a step of bonding a buffer die to a semiconductor die. DETAILED DESCRIPTION OF THE INVENTION

[0014]

[0033] Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings. The present invention can be embodied in several different forms and is not limited to the embodiments described herein.

[0015] In the drawings, in order to clearly illustrate the present invention, parts unnecessary for the explanation are omitted, and the same reference numerals are used throughout the specification to refer to the same or similar components.

[0016] Furthermore, the size and thickness of each component shown in the drawings are arbitrarily shown for the convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings.

[0017] Throughout the specification, when a part is said to be "connected" to another part, this includes not only "directly connected" but also "indirectly connected" through other members. Furthermore, when a part is said to "comprise" a certain element, this means that it can further include other elements, not excluding other elements, unless otherwise specified.

[0018] Furthermore, when a layer, film, region, plate, or other part is said to be "on" or "above" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Furthermore, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "above" in the opposite direction of gravity.

[0019] Also, throughout the specification, "on a plane" means a view of the subject part from above, and "on a cross section" means a view of the subject part cut vertically from the side.

[0020] Hereinafter, an underfill film 140 according to one embodiment, a semiconductor package 100 including the underfill film 140, a semiconductor package 200 including the underfill film 140, and a method for stacking semiconductor dies using the underfill film 140 will be described with reference to the drawings.

[0021] FIG. 1 is a cross-sectional view showing a semiconductor package 100 according to an embodiment.

[0022] 1 , the semiconductor package 100 is a high-bandwidth memory (HBM) 100. The high-bandwidth memory (HBM) 100 includes a buffer die (base die or base logic die) 110, a semiconductor die (memory die or core die) 120, interconnect structures 130 interleaved with the semiconductor dies 120, and a molding material 160. The high-bandwidth memory (HBM) 100 according to the present invention includes a semiconductor stack having eight semiconductor dies 120 stacked thereon, but is not limited thereto, and may include semiconductor stacks having various numbers of semiconductor dies 120 stacked thereon. For example, the high-bandwidth memory (HBM) 100 may include a semiconductor stack having four, twelve, sixteen, or twenty-four semiconductor dies stacked thereon.

[0023] The High Bandwidth Memory (HBM) 100 is a high-performance, three-dimensional (3D) stacked Dynamic Random-Access Memory (DRAM) that is fabricated by vertically stacking semiconductor dies 120 containing DRAM circuitry to form a semiconductor stack, forming thousands of tiny holes in the semiconductor dies 120 that vertically penetrate the stacked semiconductor dies 120, and filling the holes with conductive material to provide electrical connections using Through Silicon Via (TSV) (112 and 122) technology.

[0024] The high-bandwidth memory (HBM) 100 has various channels through a semiconductor stack manufactured by vertically stacking semiconductor dies 120, and can simultaneously achieve shorter latency and higher bandwidth than conventional DRAM products. It can also reduce the total area occupied by individual DRAMs on a printed circuit board (PCB), which is advantageous for high bandwidth relative to area and reduces power consumption.

[0025] The buffer die 110 is disposed at the bottom of the high-bandwidth memory (HBM) 100 and is disposed between the stacked semiconductor dies 120 and an external device (not shown). The buffer die 110 includes a buffer die base 111 and through-silicon vias 112 within the buffer die base 111. In one embodiment, the buffer die base 111 comprises silicon. The semiconductor dies 120 are disposed on the buffer die 110. Each of the semiconductor dies 120 includes a semiconductor die base 121 and through-silicon vias 122 within the semiconductor die base 121. In one embodiment, the semiconductor dies 120 are DRAM.

[0026] To achieve a high bandwidth per area, it is advantageous to stack as many semiconductor dies 120 as possible on the buffer die 110. However, when stacking the semiconductor dies 120, surface photography may accumulate, causing the horizontality of the semiconductor dies 120 (e.g., the direction parallel to the top surface 111S of the buffer die base 111) to shift, which may reduce etch uniformity during a subsequent through-silicon via formation process and cause bonding defects during a flip-chip bonding process, resulting in a significant yield loss.

[0027] The interconnect structures 130 have a configuration that physically and electrically connects the buffer die 110 and the semiconductor die 120, or between the semiconductor dies 120, so that as many semiconductor dies 120 as possible can be stacked on the buffer die 110. Each of the interconnect structures 130 is disposed between the buffer die 110 and the semiconductor die 120, or between adjacent ones of the semiconductor dies 120.

[0028] Each of the interconnect structures 130 includes an underfill film 140 , a first bonding pad 151 , a connecting member 152 , and a second bonding pad 153 .

[0029] The underfill film 140 is disposed between the buffer die 110 and the adjacent semiconductor die 120, or between the semiconductor die 120 and the adjacent semiconductor die 120. The underfill film 140 surrounds and protects the first bonding pads 151, the connecting members 152, and the second bonding pads 153. The underfill film 140 bonds the buffer die 110 to the adjacent semiconductor die 120, or the semiconductor die 120 to the adjacent semiconductor die 120. The underfill film 140 includes a first film layer 141 and a second film layer 142. In one embodiment, the underfill film 140 is referred to as a non-conductive film (NCF). In one embodiment, the first film layer 141 includes a silica-based inorganic filler. In one embodiment, the second film layer 142 includes an alumina-based inorganic filler.

[0030] The first bonding pads 151, connecting members 152, and second bonding pads 153 of each of the interconnect structures 130 are disposed between the buffer die 110 and the adjacent semiconductor die 120, or between the semiconductor die 120 and the adjacent semiconductor die 120. Each of the first bonding pads 151 is disposed between each of the connecting members 152 and each of the through-silicon vias (112 and 122). Each of the first bonding pads 151 electrically connects each of the connecting members 152 to each of the through-silicon vias (112 and 122). Each of the connecting members 152 is disposed between each of the first bonding pads 151 and each of the second bonding pads 153. Each of the connecting members 152 electrically connects each of the second bonding pads 153 to each of the first bonding pads 151. Each of the second bonding pads 153 is disposed between each of the connection members 152 and each of the through-silicon vias (112 and 122). Each of the second bonding pads 153 electrically connects each of the through-silicon vias (112 and 122) to each of the connection members 152. In one embodiment, each of the first bonding pad 151 and the second bonding pad 153 includes at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof. In one embodiment, the connection members 152 include microbumps. In one embodiment, the connection members 152 include at least one of tin, silver, lead, nickel, copper, or alloys thereof.

[0031] The molding material 160 is disposed on the buffer die 110 and covers the semiconductor die 120 and the underfill film 140. The molding material 160 serves to protect and insulate the semiconductor die 120 and the underfill film 140. In one embodiment, the molding material 160 is an epoxy molding compound (EMC).

[0032] FIG. 2 is an enlarged cross-sectional view of region A in FIG.

[0033] 2, underfill film 140 is disposed between buffer die 110 and semiconductor die 120. The contents of the underfill film 140 shown and described in FIG. 2 also apply to the underfill film 140 disposed between adjacent semiconductor dies 120. Underfill film 140 includes a first film layer 141 and a second film layer 142.

[0034] The first film layer 141 includes at least one of a first thermosetting resin, a first curing agent, a first catalyst, a first flux, a first thermoplastic resin, and a first inorganic filler.

[0035] The first thermosetting resin is selected from materials having thermal and mechanical properties suitable for an underfill film disposed between buffer die 110 and semiconductor die 120. In one embodiment, the first thermosetting resin includes an epoxy resin. In one embodiment, the epoxy resin includes at least one of a bisphenol-type epoxy resin and a novolac-type epoxy resin.

[0036] The first curing agent is added to the first thermosetting resin to cure the first thermosetting resin. The first curing agent is added to adjust the degree of cure of the first thermosetting resin. By adding the first curing agent to the first thermosetting resin, the mechanical properties of the first film layer 141 can be adjusted. In one embodiment, the first curing agent includes at least one of an amine-based compound, an acid anhydride-based compound, an amide-based compound, an imidazole-based compound, and a phenol-based compound.

[0037] The first catalyst is added to the first thermosetting resin to adjust the curing rate of the first thermosetting resin. The curing rate of the first thermosetting resin is adjusted depending on the content of the first catalyst, or by using a first catalyst that slows the curing rate. In one embodiment, the first catalyst includes at least one of a phosphorus-based compound, a boron-based compound, a phosphorus-boron-based compound, and an imidazole-based compound.

[0038] The first flux improves the wetting of the connecting member 152 to the first bonding pad 151. The first flux is selectively added to the first film layer 141. In one embodiment, the first flux includes at least one of a carboxylic acid, a phenol, and an amine. The first thermoplastic resin increases the fluidity of the first film layer 141 at a temperature (reflow temperature) at which flip-chip bonding is performed, thereby ensuring good bonding between the first bonding pad 151 and the connecting member 152. The first thermoplastic resin reduces thermal and mechanical stress between the buffer die 110 and the semiconductor die 120. In one embodiment, the first thermoplastic resin includes at least one of a polyimide-based resin, a polyetherimide-based resin, a polyesterimide-based resin, a polyamide-based resin, a polyethersulfone-based resin, a polyetherketone-based resin, a polyolefin-based resin, a polyvinyl chloride-based resin, a phenoxy-based resin, a butadiene rubber, a styrene-butadiene rubber, a modified butadiene rubber, a reactive butadiene-acrylonitrile copolymer rubber, a butadiene-acrylonitrile copolymer rubber, and an acrylate-based resin.

[0039] The first inorganic filler is a material having a lower dielectric constant than the second inorganic filler. Adding the first inorganic filler to the first film layer 141 results in the first film layer 141 exhibiting low viscosity characteristics (lower viscosity characteristics than the second film layer 142). This improves the wetting of the connecting member 152 to the first bonding pad 151, thereby improving the reliability of bonding between the first bonding pad 151 and the connecting member 152. In one embodiment, the first inorganic filler includes silica (silica particles). In one embodiment, the size of the silica (the particle diameter of the silicon particles contained in the first film layer 141) is about 50 nm to about 5 μm. In one embodiment, the silica content (the ratio to the total weight or mass of the first film layer 141, i.e., the silica content or amount of silica in the first film layer 141) is about 20 wt % to about 60 wt %. The viscosity of the first film layer 141 can be precisely adjusted by adjusting the size of the silica and the content of the silica within the above ranges.

[0040] As the size of the silica increases or the content of silica decreases, the viscosity of the first film layer 141 decreases. The viscosity of the first film layer 141 refers to the minimum viscosity. In one embodiment, the minimum viscosity of the first film layer 141 is about 100 Pa·s to about 3,000 Pa·s. In one embodiment, the temperature at which the first film layer 141 has the minimum viscosity is about 120°C to about 160°C.

[0041] The second film layer 142 includes at least one of a second thermosetting resin, a second curing agent, a second catalyst, a second flux, a second thermoplastic resin, and a second inorganic filler.

[0042] The second thermosetting resin is selected from materials having thermal and mechanical properties suitable for an underfill film disposed between buffer die 110 and semiconductor die 120. In one embodiment, the second thermosetting resin includes an epoxy resin. In one embodiment, the epoxy resin includes at least one of a bisphenol-type epoxy resin and a novolac-type epoxy resin.

[0043] The second curing agent is added to the second thermosetting resin to cure the second thermosetting resin. The second curing agent is added to adjust the degree of cure of the second thermosetting resin. By adding the second curing agent to the second thermosetting resin, the mechanical properties of the second film layer 142 can be adjusted. In one embodiment, the second curing agent includes at least one of an amine-based compound, an acid anhydride-based compound, an amide-based compound, an imidazole-based compound, and a phenol-based compound.

[0044] The second catalyst is added to the second thermosetting resin to adjust the curing rate of the second thermosetting resin. The curing rate of the second thermosetting resin is adjusted depending on the content of the second catalyst, or by using a second catalyst that slows the curing rate. In one embodiment, the second catalyst includes at least one of a phosphorus-based compound, a boron-based compound, a phosphorus-boron-based compound, and an imidazole-based compound.

[0045] The second flux improves the wetting of the connecting member 152 to the first bonding pad 151. The second flux is selectively added to the second film layer 142. In one embodiment, the second flux includes at least one of a carboxylic acid, a phenol, and an amine.

[0046] The second thermoplastic resin increases the fluidity of the second film layer 142 at a temperature (reflow temperature) at which flip-chip bonding is performed, thereby ensuring good bonding between the first bonding pads 151 and the connecting members 152. The second thermoplastic resin reduces thermal and mechanical stress between the buffer die 110 and the semiconductor die 120. In one embodiment, the second thermoplastic resin includes at least one of a polyimide-based resin, a polyetherimide-based resin, a polyesterimide-based resin, a polyamide-based resin, a polyethersulfone-based resin, a polyetherketone-based resin, a polyolefin-based resin, a polyvinyl chloride-based resin, a phenoxy-based resin, butadiene rubber, a styrene-butadiene rubber, a modified butadiene rubber, a reactive butadiene-acrylonitrile copolymer rubber, a butadiene-acrylonitrile copolymer rubber, and an acrylate-based resin.

[0047] The second inorganic filler is a material having a higher dielectric constant (High K) than the first inorganic filler. Adding the second inorganic filler having a high dielectric constant (High K) can improve the heat dissipation characteristics of the semiconductor package 100. Also, adding the second inorganic filler to the second film layer 142 forms the second film layer 142 with high viscosity (higher viscosity than the first film layer 141). This can prevent fillets from forming in the semiconductor package 100 or reduce the size of the fillets, thereby solving the problem of short circuits in the connection members 152 in the interconnect structure 130. In one embodiment, the second inorganic filler includes alumina (alumina particles). In one embodiment, the size of the alumina (particle diameter of the alumina particles contained in the second film layer 142) is about 50 nm to about 5 μm. In one embodiment, the alumina content (a ratio to the total weight or mass of the second film layer 142, i.e., the alumina content or amount of alumina in the second film layer 142) is about 40 wt% to about 80 wt%. By adjusting the alumina size and alumina content within the above ranges, the viscosity of the second film layer 142 can be precisely adjusted.

[0048] Reducing the size of the alumina or increasing the alumina content increases the viscosity of the second film layer 142. The viscosity of the second film layer 142 refers to the minimum viscosity. In one embodiment, the minimum viscosity of the second film layer 142 is about 1,500 Pa·s to about 10,000 Pa·s. In one embodiment, the temperature at which the second film layer 142 reaches its minimum viscosity is about 100°C to about 140°C.

[0049] The first film layer 141 contains silica as a first inorganic filler, which has a relatively low dielectric constant (lower than alumina), and the second film layer 142 contains alumina as a second inorganic filler, which has a relatively high dielectric constant (higher than silica). Based on these characteristics, the first film layer 141 and the second film layer 142 of the underfill film 140 have different mechanical properties as a composite film layer. The first film layer 141 has a first dielectric constant, and the second film layer 142 has a second dielectric constant higher than the first dielectric constant. The first film layer 141 has a first viscosity, and the second film layer 142 has a second viscosity higher than the first viscosity. The first film layer 141 has a first minimum viscosity, and the second film layer 142 has a second minimum viscosity higher than the first minimum viscosity.

[0050] The first film layer 141 contains silica (silica particles) as a first inorganic filler, and the second film layer 142 contains alumina (alumina particles) as a second inorganic filler. Based on these characteristics, the first film layer 141 and the second film layer 142 of the underfill film 140 have different thermal properties as a composite film layer. The first film layer 141 has a first thermal conductivity, and the second film layer 142 has a second thermal conductivity higher than the first thermal conductivity. In one embodiment, the first thermal conductivity is approximately 0.45 W / mK. In one embodiment, the second thermal conductivity is approximately 1 W / mK. The first film layer 141 has a first thermal resistance, and the second film layer 142 has a second thermal resistance lower than the first thermal resistance. In one embodiment, the thermal resistance of the underfill film 140 is approximately 0.21°C / W to approximately 0.24°C / W.

[0051] The first film layer 141 has a first thickness (H1) in the vertical direction. The vertical direction extends perpendicular to the top surface 111S of the buffer die base 111. In one embodiment, the first thickness (H1) of the first film layer 141 is about 1 μm to about 19 μm. The second film layer 142 has a second thickness (H2) in the vertical direction. In one embodiment, the second thickness (H2) of the second film layer 142 is about 1 μm to about 19 μm. The underfill film 140 has a third thickness (H3) in the vertical direction. The third thickness (H3) of the underfill film 140 is the sum of the first thickness (H1) and the second thickness (H2). In one embodiment, the ratio of the thicknesses of the first film layer 141 and the second film layer 142 in the vertical direction is about 1:19 to about 19:1. The first film layer 141 has a first width (L1) in the horizontal direction. The horizontal direction extends parallel to the top surface 111S of the buffer die base 111. The second film layer 142 has a second width (L2) in the horizontal direction that is smaller than the first width (L1).

[0052] FIG. 3 is a cross-sectional view showing a semiconductor package 200 according to another embodiment.

[0053] Referring to FIG. 3, the semiconductor package 200 is a 3D integrated circuit (3DIC) structure 200. The 3D integrated circuit (3DIC) structure 200 includes a first semiconductor die (lower semiconductor die) 210, an interconnect structure 130, and a second semiconductor die (upper semiconductor die) 220. The 3D integrated circuit (3DIC) structure 200 realizes an integrated circuit as a three-dimensional chip and refers to a technology that converts the stacking method of semiconductor dies from the conventional horizontal method to a vertical method. The vertical stacking method allows more elements to be realized in the same silicon wafer area, thereby reducing manufacturing costs and improving performance. In one embodiment, the 3D integrated circuit (3DIC) structure 200 is a chiplet stacked structure formed by stacking chiplets.

[0054] The first semiconductor die 210 is disposed at the bottom of the 3D integrated circuit (3DIC) structure 200. The first semiconductor die 210 is fabricated using through-silicon-via (TSV) 212 technology, in which fine holes are formed in the first semiconductor die base 211 vertically and filled with a conductive material for electrical connection. In one embodiment, the first semiconductor die 210 includes at least one of a central processing unit (CPU) and a graphic processing unit (GPU).

[0055] The second semiconductor die 220 is disposed on the first semiconductor die 210. In one embodiment, the second semiconductor die 220 includes at least one of memory, communications, and sensors.

[0056] The interconnect structure 130 is disposed between the first semiconductor die 210 and the second semiconductor die 220. The interconnect structure 130 has a configuration that physically and electrically connects the first semiconductor die 210 and the second semiconductor die 220. Each of the interconnect structures 130 includes an underfill film 140, a first bonding pad 151, a connecting member 152, and a second bonding pad 153. The same description of the semiconductor package 100 in FIGS. 1 and 2 applies to the interconnect structure 130, the underfill film 140, the first bonding pad 151, the connecting member 152, and the second bonding pad 153.

[0057] Additionally, the underfill film 140 can be applied to various semiconductor packages (e.g., a stacked structure of a package on package (PoP), or a structure based on a fan-out wafer level package (FOWLP) or fan-out panel level package (FOPLP) technology).

[0058] 4 is a cross-sectional view showing an underfill film 140 according to an embodiment. In FIG. 4, the underfill film 140 is shown in a finished state before being applied to a semiconductor package.

[0059] Referring to FIG. 4, the underfill film 140 includes, from the bottom, a release film 143, a second film layer 142, a first film layer 141, a buffer layer 144, and a base film 145.

[0060] The release film 143 provides a support for the other layers of the underfill film 140. The release film 143 is removed from the second film layer 142 by peeling. In one embodiment, the release film 143 comprises polyethylene terephthalate (PET). The second film layer 142 is disposed on the release film 143. The first film layer 141 is disposed on the second film layer 142. The buffer layer 144 is disposed on the first film layer 141. The buffer layer 144 functions as a buffer. In one embodiment, the buffer layer 144 comprises a pressure-sensitive adhesive (PSA). The base film 145 protects the other layers of the underfill film 140. In one embodiment, the base film 145 comprises a polyolefin. The buffer layer 144 and the base film 145 are removed from the first film layer 141 by peeling.

[0061] 5-14 are cross-sectional views illustrating a method for stacking the buffer die 110 and the semiconductor die 120 of the high bandwidth memory (HBM) 100 using the underfill film 140 of FIG. 4. This stacking method also applies to other stacking structures in which the underfill film 140 is used.

[0062] FIG. 5 is a cross-sectional view illustrating the step of providing a wafer (W) containing semiconductor dies 120 (see FIG. 12) attached to a carrier 410.

[0063] Referring to FIG. 5, a wafer (W) including semiconductor dies 120 is provided. In one embodiment, the wafer (W) is replaced with a panel. Connection members 152 connected to the through-silicon vias are formed on a first surface (W1) of the wafer (W), a temporary adhesive 420 is attached to the first surface (W1) on which the connection members 152 are formed, and a carrier 410 is attached to the temporary adhesive 420. The carrier 410 and the temporary adhesive 420 are attached to the first surface (W1) of the wafer (W) by performing a carrier bonding process of a wafer supporting system (WSS) process. In one embodiment, the carrier 410 includes a silicon-based material such as glass or silicon oxide, an organic material, or another material such as aluminum oxide, or any combination of these materials.

[0064] FIG. 6 is a cross-sectional view illustrating a step of attaching a dicing tape 430 onto a wafer (W) including semiconductor dies 120. As shown in FIG.

[0065] 6, a dicing tape 430 is attached to the second surface (W2) of the wafer (W) including the semiconductor die 120. The second surface (W2) is the opposite surface of the first surface (W1).

[0066] FIG. 7 is a cross-sectional view illustrating the step of removing the carrier 410 from the wafer (W) containing the semiconductor die 120.

[0067] 7, the carrier 410 is removed from the wafer (W) including the semiconductor die 120. A carrier debonding process of the WSS process is performed to remove the carrier 410. After removing the carrier 410, a cleaning process is performed to remove the temporary adhesive 420.

[0068] FIG. 8 is a cross-sectional view illustrating the step of aligning an underfill film 140 on a first side (W1) of a wafer (W) including semiconductor dies 120. As shown in FIG.

[0069] 8, an underfill film 140 is aligned on a first surface (W1) of a wafer (W) including semiconductor die 120. The underfill film 140 is obtained by removing the release film 143 from the underfill film 140 of FIG.

[0070] FIG. 9 is a cross-sectional view illustrating the step of depositing an underfill film 140 on a first side (W1) of a wafer (W) including semiconductor die 120. As shown in FIG.

[0071] 9, an underfill film 140 is attached to a first surface (W1) of a wafer (W) including a semiconductor die 120. A first film layer 141 and a second film layer 142 of the underfill film 140 penetrate a connecting member 152 and a second bonding pad 153.

[0072] FIG. 10 is a cross-sectional view showing the step of removing the buffer layer 144 and the base film 145 from the underfill film 140. As shown in FIG.

[0073] Referring to FIG. 10, the buffer layer 144 and the base film 145 are removed from the underfill film 140.

[0074] FIG. 11 is a cross-sectional view illustrating a step in singulation of a wafer (W) containing semiconductor dies 120.

[0075] 11, the wafer (W) containing the semiconductor dies 120 is singulated. In one embodiment, the singulation process is performed by a laser or sawing process. After the singulation process, the wafer (W) is separated into the semiconductor dies 120.

[0076] FIG. 12 is a cross-sectional view illustrating the step of separating the semiconductor die 120 from the dicing tape 430.

[0077] Referring to FIG. 12, the dicing tape 430 is irradiated with ultraviolet (UV) light to separate the semiconductor die 120 from the dicing tape 430 .

[0078] FIG. 13 is a cross-sectional view illustrating the step of aligning the semiconductor die 120 over the buffer die 110. As shown in FIG.

[0079] Referring to FIG. 13, the semiconductor die 120 is aligned on the buffer die 110.

[0080] FIG. 14 is a cross-sectional view illustrating a step of bonding the buffer die 110 and the semiconductor die 120 together.

[0081] Referring to FIG. 14 , the buffer die 110 and the semiconductor die 120 are bonded together. In one embodiment, the buffer die 110 and the semiconductor die 120 are bonded together using a thermal compression (TC) process. The underfill film 140 is in a gel state before the thermal compression process. During the thermal compression process, heat is applied, causing the underfill film 140 to change from the gel state to a liquid state and finally to a hardened state. The first film layer 141 has a first curing rate. The second film layer 142 has a second curing rate that is faster than the first curing rate. The underfill film 140 is attached between the buffer die 110 and the semiconductor die 120 and protects the first bonding pads 151, the connecting members 152, and the second bonding pads 153. The low viscosity first film layer 141 forms a fillet 141F that extends outward beyond the side 120S of the semiconductor die 120, but the high viscosity second film layer 142 located on the first film layer 141 prevents the formation of excessive fillet 141F.

[0082] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0083] 100 Semiconductor Packages (High Bandwidth Memory (HBM)) 110 Buffer Die 111 Buffer Dye Base 111S top surface 112, 122, 212 Through Silicon Vias 120 semiconductor dies 120S side 121 Semiconductor Die Base 130 Interconnect Structure 140 Underfill Film 141, 142 First and second film layers 141F Fillet 143 Release film 144 Buffer layer 145 base film 151, 153 First and second bonding pads 152 connecting member 160 Molding material 200 Semiconductor Package (3D Integrated Circuit (3DIC) Structure) 210 First semiconductor die (lower semiconductor die) 220 Second semiconductor die (upper semiconductor die) 211 First Semiconductor Die Base 410 Career 420 Temporary adhesive 430 Dicing Tape W wafer

Claims

1. a first film layer having a first dielectric constant; a second film layer disposed on the first film layer and having a second dielectric constant; The underfill film, wherein the second dielectric constant is higher than the first dielectric constant.

2. the first film layer has a first viscosity; the second film layer has a second viscosity; The underfill film according to claim 1 , wherein the second viscosity is higher than the first viscosity.

3. the first film layer has a minimum viscosity of 100 Pa·s to 3,000 Pa·s; 2. The underfill film according to claim 1, wherein the second film layer has a minimum viscosity of 1,500 Pa·s to 10,000 Pa·s.

4. the first film layer has a minimum viscosity temperature of 120°C to 160°C; The underfill film according to claim 3, wherein the second film layer has a minimum viscosity temperature of 100°C to 140°C.

5. the first film layer has a first thermal conductivity; the second film layer has a second thermal conductivity; The underfill film according to claim 1 , wherein the second thermal conductivity is higher than the first thermal conductivity.

6. the first film layer has a first thermal resistance; the second film layer has a second thermal resistance; The underfill film according to claim 1 , wherein the second thermal resistance is lower than the first thermal resistance.

7. a first film layer including a first thermosetting resin and a first inorganic filler; a second film layer disposed on the first film layer and including a second thermosetting resin and a second inorganic filler; the first film layer has a first dielectric constant; the second film layer has a second dielectric constant; The underfill film, wherein the second dielectric constant is higher than the first dielectric constant.

8. The underfill film of claim 7 , wherein the first inorganic filler includes silica.

9. 9. The underfill film according to claim 8, wherein the particle diameter of the silica is 50 nm to 5 μm.

10. 9. The underfill film according to claim 8, wherein the silica content of the first film layer is 20 wt % to 60 wt % as a ratio to the total weight of the first film layer.

11. The underfill film according to claim 7 , wherein the second inorganic filler comprises alumina.

12. The underfill film according to claim 11, wherein the alumina has a particle diameter of 50 nm to 5 μm.

13. 12. The underfill film according to claim 11, wherein the alumina content of the second film layer is 40 wt % to 80 wt % relative to the total weight of the second film layer.

14. The underfill film of claim 7 , wherein the first film layer further comprises a flux.

15. The underfill film according to claim 7 , wherein the first film layer and the second film layer each further include at least one of a curing agent, a catalyst, and a thermoplastic resin.

16. The underfill film of claim 7 , wherein the first thermosetting resin and the second thermosetting resin each include an epoxy.

17. a first semiconductor die; a second semiconductor die on the first semiconductor die; a plurality of connecting members between the first semiconductor die and the second semiconductor die; an underfill film between the first semiconductor die and the second semiconductor die, the underfill film surrounding the plurality of connection members; the underfill film includes a first film layer having a first dielectric constant and a second film layer disposed on the first film layer and having a second dielectric constant; The second dielectric constant is higher than the first dielectric constant.

18. 18. The semiconductor package of claim 17, wherein a thickness ratio of the first film layer to the second film layer in a vertical direction is 1:19 to 19:

1.

19. 18. The semiconductor package of claim 17, wherein the first film layer and the second film layer each have a vertical thickness of 1 μm to 19 μm.

20. 18. The semiconductor package according to claim 17, wherein the thermal resistance of the underfill film is 0.21° C. / W to 0.24° C. / W.

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