Semiconductor package

Abstract

To provide a semiconductor package having high process yield and improved signal reliability.SOLUTION: A semiconductor package according to the present invention includes: an interposer; a lower semiconductor chip located on the interposer and including a through-chip via; a plurality of lower stacked structures located on the interposer; a lower molding layer located on the interposer and surrounding a side surface of the lower semiconductor chip and a side surface of each lower stacked structure; a redistribution layer located on the lower molding layer and configured to be electrically connected to the through-chip via of the lower semiconductor chip; an upper semiconductor chip located on the redistribution layer; a plurality of upper stacked structures located on the redistribution layer; and an upper molding layer located on the redistribution layer and surrounding the side surface of the upper semiconductor chip and the side surface of the upper stacked structure.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to semiconductor packages, and more particularly to semiconductor packages that include interposers. [Background technology]

[0002] Recently, in response to the rapid development of the electronics industry and user needs, electronic devices have become smaller, more multifunctional, and have larger capacities, resulting in a demand for highly integrated semiconductor chips. Therefore, semiconductor packages have been devised that include highly integrated semiconductor chips with an increased number of connection terminals for input / output (I / O) while still ensuring connection reliability. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor package in which the size of the interposer substrate is reduced and the process yield is increased. Another object of the present invention is to provide a semiconductor package in which the signal distance between semiconductor chips is shortened.

[0004] The problems to be solved by the present invention are not limited to those mentioned above, and other problems will be apparent to those skilled in the art from the following description. [Means for solving the problem]

[0005] In order to achieve the above object, a semiconductor package according to one aspect of the present invention includes an interposer, a lower semiconductor chip positioned on the interposer and including a through-chip via, a plurality of lower laminate structures positioned on the interposer, a lower molding layer positioned on the interposer and surrounding sides of the lower semiconductor chip and sides of the lower laminate structure, a redistribution layer positioned on the lower molding layer and configured to be electrically connected to the through-chip via of the lower semiconductor chip, an upper semiconductor chip positioned on the redistribution layer, a plurality of upper laminate structures positioned on the redistribution layer, and an upper molding layer positioned on the redistribution layer and surrounding sides of the upper semiconductor chip and sides of the upper laminate structure.

[0006] In order to achieve the above object, a semiconductor package according to another aspect of the present invention includes a lower interposer, a lower semiconductor chip located on the lower interposer and including a through-chip via, a chip molding layer located on the lower interposer and surrounding a side of the lower semiconductor chip, a plurality of lower laminate structures located on the lower interposer, a lower molding layer located on the lower interposer and surrounding a side of the chip molding layer and a side of the lower laminate structure, a redistribution layer located on the lower molding layer and configured to be electrically connected to the through-chip via, an upper semiconductor chip located on top of the redistribution layer, a plurality of upper laminate structures located on top of the redistribution layer, and an upper molding layer located on top of the redistribution layer and surrounding a side of the upper semiconductor chip and a side of the upper laminate structure.

[0007] In order to achieve the above object, according to yet another aspect of the present invention, a semiconductor package includes a package substrate, an interposer located on the package substrate, a lower semiconductor chip located on the interposer and including a through-chip via, a chip molding layer located on the interposer and surrounding a side surface of the lower semiconductor chip, a plurality of lower laminate structures located on the interposer, a lower molding layer located on the interposer and surrounding a side surface of the chip molding layer and a side surface of the lower laminate structure, a redistribution layer located on the lower molding layer and configured to be electrically connected to the through-chip via of the lower semiconductor chip, the redistribution layer including a redistribution insulating layer and a bonding pad located within the redistribution insulating layer, an upper semiconductor chip located on the redistribution layer, an upper laminate structure located on the redistribution layer, and an upper molding layer located on the redistribution layer and surrounding a side surface of the upper semiconductor chip and a side surface of the upper laminate structure. [Effects of the Invention]

[0008] According to the present invention, the size of the interposer can be reduced, thereby improving yield, and the signal transmission distance between the mounted semiconductor chips is shortened, thereby suppressing noise and providing a semiconductor package with improved signal reliability. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view schematically illustrating a semiconductor package according to an embodiment of the present invention; [Figure 2] 2 is a cross-sectional view schematically showing the semiconductor package of FIG. 1 taken along line AA' of FIG. [Figure 3] 3 is an enlarged view schematically showing an "EX1" portion of the semiconductor package shown in FIG. 2.

[0023] FIG. [Figure 4] 1 is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment of the present invention. [Figure 5] 1 is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment of the present invention. [Figure 6]6 is an enlarged view schematically showing an "EX2" portion of the semiconductor package shown in FIG. 5. FIG. [Figure 7] 1 is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment of the present invention. [Figure 8] 1 is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment of the present invention. [Figure 9] 1 is a plan view schematically illustrating a semiconductor package according to an embodiment of the present invention; [Figure 10] 10 is a cross-sectional view schematically showing the semiconductor package of FIG. 9 taken along line BB' of FIG. 9. DETAILED DESCRIPTION OF THE INVENTION

[0010] Although the present invention may be modified in various ways and may have various forms, some embodiments are illustrated in the drawings and will be described in detail, but it is not intended to limit the present invention to the particular disclosed forms.

[0011] Fig. 1 is a plan view schematically illustrating a semiconductor package 1000 according to an embodiment of the present invention. Fig. 2 is a cross-sectional view schematically illustrating the semiconductor package 1000 of Fig. 1 taken along line A-A' in Fig. 1. Fig. 3 is an enlarged view schematically illustrating an "EX1" portion of the semiconductor package 1000 shown in Fig. 2.

[0012] 1 to 3, the semiconductor package 1000 includes an interposer 100, a lower semiconductor chip 210, a plurality of lower laminate structures 310, a lower molding layer ML1, a redistribution layer RDL, an upper semiconductor chip 220, a plurality of upper laminate structures 320, and an upper molding layer ML2.

[0013] Unless otherwise defined, hereinafter, the direction parallel to the top surface of interposer 100 is defined as the first horizontal direction (X direction), the direction perpendicular to the top surface of interposer 100 is defined as the vertical direction (Z direction), and the direction perpendicular to the first horizontal direction (X direction) and the vertical direction (Z direction) is defined as the second horizontal direction (Y direction). The horizontal direction is defined as the direction obtained by combining the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0014] The interposer 100 includes a first substrate 101 and first through vias 100_V that penetrate the first substrate 101. For example, the interposer 100 is a glass interposer in which the first substrate 101 includes glass and the first through vias 100_V are through glass vias (TGVs). However, the interposer 100 is not limited thereto, and may be a silicon interposer in which the first substrate 101 includes silicon and the first through vias 100_V are through silicon vias (TSVs).

[0015] The interposer 100 further includes an upper pad 100_UP and a lower pad 100_DP. The upper pad 100_UP is located on the upper surface of the first substrate 101 of the interposer 100, and the lower pad 100_DP is located on the lower surface of the first substrate 101 of the interposer 100. The upper pad 100_UP and the lower pad 100_DP are each electrically connected to a wiring region of the interposer 100. The upper pad 100_UP and the lower pad 100_DP are electrically connected by a first through via 100_V. In some embodiments, the size of the upper pad 100_UP is smaller than the size of the lower pad 100_DP.

[0016] External connection terminals CT1 are attached to the lower pads 100_DP. The external connection terminals CT1 are configured to electrically and physically connect the interposer 100 to an external device on which the interposer 100 is mounted. The external connection terminals CT1 are formed of, for example, solder balls or solder bumps.

[0017] The lower semiconductor chip 210 is located on the interposer 100. For example, the lower semiconductor chip 210 is located in a central region of the interposer 100. The lower semiconductor chip 210 includes an active surface and an opposing inactive surface. In some embodiments, the lower semiconductor chip 210 includes an application specific integrated circuit (ASIC).

[0018] In some embodiments, the lower semiconductor chip 210 is mounted on the interposer 100 such that an active surface of the lower semiconductor chip 210 faces the interposer 100. For example, the lower semiconductor chip 210 is disposed on the interposer 100 in a face-down manner. However, without being limited thereto, the lower semiconductor chip 210 may be disposed on the interposer 100 in a face-up manner such that an inactive surface of the lower semiconductor chip 210 faces the interposer 100.

[0019] In some embodiments, various types of individual devices are located on the active surface of the lower semiconductor chip 210. The individual devices of the lower semiconductor chip 210 are electrically connected to the wiring region of the lower semiconductor chip 210.

[0020] For example, the plurality of individual elements may include various microelectronic devices, such as complementary metal-oxide semiconductor transistors (CMOS transistors), metal-oxide-semiconductor field effect transistors (MOSFETs), system large scale integration (LSIs), image sensors such as CMOS imaging sensors (CISs), micro-electro-mechanical systems (MEMSs), active elements, and passive elements.

[0021] The lower semiconductor chip 210 further includes through-chip vias 210_V. The through-chip vias 210_V extend from the upper surface to the lower surface of the lower semiconductor chip 210. For example, the through-chip vias 210_V are electrically connected to a wiring region of the lower semiconductor chip 210.

[0022] The lower semiconductor chip 210 further includes upper pads 210_UP and lower pads 210_DP. For example, the upper pads 210_UP of the lower semiconductor chip 210 are located on the upper surface of the lower semiconductor chip 210 and are electrically connected to the wiring region of the lower semiconductor chip 210, and the lower pads 210_DP of the lower semiconductor chip 210 are located on the lower surface of the lower semiconductor chip 210 and are electrically connected to the wiring region of the lower semiconductor chip 210.

[0023] In some embodiments, the lower pads 210_DP of the lower semiconductor chip 210 are electrically connected to the upper pads 100_UP of the interposer 100 via the first connecting terminals CT21. However, without being limited thereto, the lower pads 210_DP of the lower semiconductor chip 210 and the upper pads 100_UP of the interposer 100 may be electrically connected to each other by an anisotropic film ACF, a non-conductive film NCF, direct bonding, or hybrid bonding.

[0024] The plurality of lower laminate structures 310 are positioned on the interposer 100. The plurality of lower laminate structures 310 are horizontally spaced apart from the lower semiconductor chip 210. For example, the plurality of lower laminate structures 310 are mounted on the interposer 100 so as to be positioned on both sides of the lower semiconductor chip 210. The plurality of lower laminate structures 310 and the lower semiconductor chip 210 transmit and receive electrical signals to and from each other via the interposer 100. For example, the semiconductor package 1000 includes one lower semiconductor chip 210 and four lower laminate structures 310.

[0025] Each of the plurality of lower laminate structures 310 includes a lower buffer chip 311, a plurality of lower core chips 312, and a lower core molding layer 313. The lower buffer chip 311 of each of the plurality of lower laminate structures 310 is located at the bottom end of the respective lower laminate structures 310, and the plurality of lower core chips 312 are stacked vertically (in the Z direction) on the lower buffer chip 311. The lower core molding layer 313 is located on the lower buffer chip 311 and encases the plurality of lower core chips 312.

[0026] For example, the upper surface of the lower core molding layer 313 is coplanar with the upper surface of the uppermost lower core chip 312U, so that the upper surface of the uppermost lower core chip 312U contacts the redistribution layer RDL.

[0027] The lower buffer chip 311 and each of the lower core chips 312 may include a semiconductor material such as silicon (Si) or germanium (Ge), or may include a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).

[0028] Each of the lower buffer chip 311 and the lower core chips 312 includes an active surface and an opposing inactive surface. Semiconductor devices including various types of individual devices are formed on the active surface of each of the lower buffer chip 311 and the lower core chips 312. Each of the lower buffer chip 311 and the lower core chips 312 includes a well doped with impurities, which serves as a wiring region. Each of the lower buffer chip 311 and the lower core chips 312 has various isolation structures, such as a shallow trench isolation (STI) structure.

[0029] The multiple individual elements of the lower buffer chip 311 include various microelectronic devices, for example, MOSFETs (metal-oxide-semiconductor field effect transistors) such as CMOS transistors (complementary metal-oxide-semiconductor transistors), system LSIs (large scale integration), image sensors such as CISs (CMOS imaging sensors), MEMS (micro-electro-mechanical systems), active elements, passive elements, etc.

[0030] The plurality of individual elements of each of the plurality of lower core chips 312 includes memory cells. For example, the memory cells are non-volatile memory cells such as flash memory, phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (ReRAM). In some embodiments, the memory cells are volatile memory cells such as dynamic random access memory (DRAM) or static random access memory (SRAM).

[0031] The plurality of individual elements of the lower buffer chip 311 are electrically connected to the wiring region of the lower buffer chip 311, and the plurality of individual elements of each of the plurality of lower core chips 312 are electrically connected to the respective wiring regions of the plurality of lower core chips 312.

[0032] In some embodiments, the lower buffer chip 311 includes a serial-parallel conversion circuit and may be a semiconductor chip for controlling the lower core chips 312, and the lower core chips 312 may be memory chips including memory cells. For example, each of the lower stack structures 310 is a High Bandwidth Memory (HBM), the lower buffer chip 311 is an HBM controller die, and each of the lower core chips 312 is a DRAM die.

[0033] In some embodiments, the lower core chip located at the top of the plurality of lower core chips 312 is referred to as the uppermost lower core chip 312U. Although Fig. 2 shows that each of the plurality of lower stack structures 310 has four lower core chips stacked therein, the number of lower core chips included in the plurality of lower stack structures 310 is not limited to this.

[0034] In some embodiments, the lower core chips 312, except for the uppermost lower core chip 312U, may further include through-core vias 312_V extending inward from the upper surface of the lower core chip. Each through-core via 312_V of the lower core chips 312 is electrically connected to a wiring region of the corresponding lower core chip. However, the uppermost lower core chip 312U may also include through-core vias 312_V.

[0035] Each of the plurality of lower core chips 312 is electrically connected to an adjacent lower core chip or lower buffer chip 311 through a through-core via 312_V. As a result, the plurality of lower core chips 312 are electrically connected to the interposer 100 through the through-core vias 312_V. For example, the wiring region of the uppermost lower core chip 312U is electrically connected to the interposer 100 through the through-core via 312_V of the core chip stacked below.

[0036] In some embodiments, the thickness of each of the plurality of lower core chips 312, that is, the length in the vertical direction (Z direction), is 20 μm to 80 μm. The thicknesses of the plurality of lower core chips 312 are substantially the same.

[0037] In some embodiments, lower pads 310_P are located on the lower surface of the lower buffer chip 311. The lower pads 310_P of the lower buffer chip 311 are electrically connected to the wiring region of the lower buffer chip 311 and the through-buffer vias 311_V of the lower buffer chip 311.

[0038] The lower pads 310_P of the lower buffer chip 311 and the interposer 100 are electrically connected by second connection terminals CT31. However, without being limited thereto, the lower pads 310_P of the lower buffer chip 311 and the interposer 100 may be electrically connected by an anisotropic film ACF, a non-conductive film NCF, direct bonding, or hybrid bonding.

[0039] The lower molding layer ML1 is located on the interposer 100 and surrounds the side surfaces of the plurality of lower laminate structures 310 and the side surfaces of the lower semiconductor chip 210. For example, the lower molding layer ML1 protects the plurality of lower laminate structures 310 and the lower semiconductor chip 210 from the outside.

[0040] In some embodiments, the upper surface of the lower molding layer ML1 is coplanar with the upper surfaces of each of the plurality of lower laminate structures 310 and the upper surface of the lower semiconductor chip 210. For example, the upper surfaces of each of the plurality of lower laminate structures 310, the upper surface of the lower semiconductor chip 210, and the upper surface of the lower molding layer ML1 are in contact with the redistribution layer RDL.

[0041] For example, the lower semiconductor chip 210 contacts one of the lower redistribution vias RV1 or the lower redistribution lines RL1 of the lower redistribution layer RLD1 of the redistribution layer RDL. For example, the lower redistribution insulating layer RD1 of the lower redistribution layer RDL1 of the redistribution layer RDL covers the upper surface of each of the plurality of lower stacked structures 310.

[0042] In some embodiments, the lower molding layer ML1 includes an epoxy resin, a polyimide resin, etc. The lower molding layer ML1 is made of, for example, an epoxy molding compound (EMC).

[0043] In some embodiments, there is an interface between the lower core molding layer 313 and the lower molding layer ML1 of each of the plurality of lower laminate structures 310. For example, the curing times of the lower core molding layer 313 and the lower molding layer ML1 may be different, and there may be an interface between each of the lower core molding layer 313 and the lower molding layer ML1.

[0044] The redistribution layer RDL is located on the lower molding layer ML1, the lower semiconductor chip 210, and the plurality of lower stacked structures 310. For example, the redistribution layer RDL contacts the lower molding layer ML1, the lower semiconductor chip 210, and the plurality of lower semiconductor chips 210. The redistribution layer RDL is electrically connected to the through-chip vias 210_V of the lower semiconductor chip 210. The redistribution layer RDL is electrically connected to the interposer 100 via the through-chip vias 210_V of the lower semiconductor chip 210.

[0045] In some embodiments, the horizontal area of ​​the redistribution layer RDL is the same as the horizontal area of ​​the interposer 100. For example, the area of ​​the top surface of the redistribution layer RDL and the area of ​​the top surface of the interposer 100 are equal to each other.

[0046] The upper semiconductor chip 220 is located on the redistribution layer RDL. The upper semiconductor chip 220 is electrically connected to the redistribution layer RDL. The upper semiconductor chip 220 is located in a central region of the redistribution layer RDL. For example, the upper semiconductor chip 220 overlaps the lower semiconductor chip 210 in the vertical direction (Z direction). In some embodiments, the upper semiconductor chip 220 includes an application specific integrated circuit (ASIC). In some embodiments, the upper semiconductor chip 220 may be the same type of semiconductor chip as the lower semiconductor chip 210.

[0047] The upper semiconductor chip 220 includes an active surface and an opposing inactive surface. In some embodiments, the upper semiconductor chip 220 is mounted on the redistribution layer RDL such that the active surface of the upper semiconductor chip 220 faces the redistribution layer RDL. For example, the upper semiconductor chip 220 is disposed face-down on the redistribution layer RDL.

[0048] In some embodiments, various types of individual devices are located on the active surface of the upper semiconductor chip 220. The individual devices of the upper semiconductor chip 220 are electrically connected to the wiring region of the upper semiconductor chip 220.

[0049] For example, the plurality of individual elements may include various microelectronic devices, such as complementary metal-oxide semiconductor transistors (CMOS transistors), metal-oxide-semiconductor field effect transistors (MOSFETs), system large scale integration (LSIs), image sensors such as CMOS imaging sensors (CISs), micro-electro-mechanical systems (MEMSs), active elements, and passive elements.

[0050] The upper semiconductor chip 220 includes lower pads 220_P, which are located on the lower surface of the upper semiconductor chip 220 and electrically connected to the wiring region of the upper semiconductor chip 220.

[0051] The plurality of upper laminate structures 320 are located on the redistribution layer RDL. The plurality of upper laminate structures 320 are spaced apart from the upper semiconductor chip 220 in the horizontal direction. For example, the plurality of upper laminate structures 320 are mounted on the redistribution layer RDL so as to be located on both sides of the upper semiconductor chip 220. For example, each of the plurality of upper laminate structures 320 overlaps each of the plurality of lower laminate structures 310 in the vertical direction (Z direction). The plurality of upper laminate structures 320 are electrically connected to the redistribution layer RDL.

[0052] The redistribution layer RDL is configured to transmit electrical signals between the plurality of upper stacked structures 320 and the upper semiconductor chip 220, and between the upper semiconductor chip 220 and the lower semiconductor chip 210. For example, the semiconductor package 1000 includes one upper semiconductor chip 220 and four upper stacked structures 320.

[0053] Each of the plurality of upper laminate structures 320 includes an upper buffer chip 321, a plurality of upper core chips 322, and an upper core molding layer 323. The upper buffer chip 321 of each of the plurality of upper laminate structures 320 is located at the bottom end of the respective plurality of upper laminate structures 320, and the plurality of upper core chips 322 are stacked in the vertical direction (Z direction) on the upper buffer chip 321. The upper core molding layer 323 is located on the upper buffer chip 321 and encases the plurality of upper core chips 322.

[0054] For example, the upper surface of the upper core molding layer 323 is coplanar with the upper surface of the uppermost upper core chip 322U, so that the upper surface of the uppermost upper core chip 322U is exposed to the outside of the semiconductor package 1000.

[0055] The upper buffer chip 321 and each of the upper core chips 322 may include a semiconductor material such as silicon (Si) or germanium (Ge), or may include a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).

[0056] Each of the upper buffer chip 321 and the upper core chips 322 includes an active surface and an opposing inactive surface. Semiconductor devices including various types of individual devices are formed on the active surface of each of the upper buffer chip 321 and the upper core chips 322. For example, the upper buffer chip 321 is substantially identical to the lower buffer chip 311. The upper core chips 322 are substantially identical to the lower core chips 312.

[0057] In some embodiments, the upper buffer chip 321 may be a semiconductor chip including a serial-parallel conversion circuit for controlling the upper core chips 322, and the upper core chips 322 may be memory chips including memory cells. For example, each of the upper stack structures 320 is a High Bandwidth Memory (HBM), the upper buffer chip 321 is an HBM controller die, and each of the upper core chips 322 is a DRAM die. For example, each of the upper stack structures 320 is substantially the same type of stack structure as each of the lower stack structures 310.

[0058] In some embodiments, the uppermost upper core chip among the plurality of upper core chips 322 is referred to as the uppermost upper core chip 322U. Although Fig. 2 shows that each of the plurality of upper stacked structures 320 has four upper core chips stacked therein, the number of upper core chips included in the plurality of upper stacked structures 320 is not limited to this.

[0059] In some embodiments, the upper core chips 322, except for the uppermost upper core chip 322U, may further include through-core vias 322_V extending inward from the top surface of the upper core chip. Each through-core via 322_V of the upper core chips 322 is electrically connected to a wiring region of the corresponding upper core chip. However, the uppermost upper core chip 322U may also include through-core vias 322_V.

[0060] Each of the upper core chips 322 is electrically connected to an adjacent upper core chip or upper buffer chip 321 through a through-core via 322_V. Thus, the upper core chips 322 are electrically connected to the redistribution layer RDL through the through-core vias 322_V. For example, the wiring region of the uppermost upper core chip 322U is electrically connected to the redistribution layer RDL through the through-core via 322_V of the core chip stacked below.

[0061] In some embodiments, the thickness of each of the upper core chips 322, that is, the length in the vertical direction (Z direction), is 20 μm to 80 μm. The thicknesses of the upper core chips 322 are substantially the same as each other.

[0062] In some embodiments, lower pads 320_P are located on the lower surface of the upper buffer chip 321. The lower pads 320_P of the upper buffer chip 321 are electrically connected to the wiring region of the upper buffer chip 321 and the buffer through vias 321_V of the upper buffer chip 321.

[0063] The lower pads 220_P of the upper semiconductor chip 220 and the lower pads 320_P of the upper buffer chip 321 of each of the plurality of upper stack structures 320 contact the redistribution layer RDL. For example, the upper semiconductor chip 220 and the plurality of upper stack structures 320 are electrically connected to the redistribution layer RDL without separate connection terminals. For example, the lower pads 220_P of the upper semiconductor chip 220 and the lower pads 320_P of the upper buffer chip 321 of each of the plurality of upper stack structures 320 contact the upper redistribution via RV2 of the upper redistribution layer RDL2 of the redistribution layer RDL.

[0064] In some embodiments, after the upper semiconductor chip 220, the plurality of upper stack structures 320, and the upper molding layer ML2 are mounted on a carrier substrate, an upper redistribution layer RDL2 is formed to cover the lower surface of the upper semiconductor chip 220, the lower surface of the plurality of upper stack structures 320, and the lower surface of the upper molding layer ML2. In other words, the upper semiconductor device SS2 is manufactured using a chip-first method.

[0065] The upper molding layer ML2 is located on the redistribution layer RDL and surrounds the side surfaces of the upper stacked structures 320 and the upper semiconductor chip 220. For example, the upper molding layer ML2 protects the upper stacked structures 320 and the upper semiconductor chip 220 from the outside.

[0066] In some embodiments, the upper surface of the upper molding layer ML2 is coplanar with the upper surfaces of the plurality of upper laminate structures 320 and the upper surface of the upper semiconductor chip 220. For example, the upper surfaces of the plurality of upper laminate structures 320, the upper surface of the upper semiconductor chip 220, and the upper surface of the upper molding layer ML2 are exposed to the outside of the semiconductor package 1000.

[0067] In some embodiments, the upper molding layer ML2 includes an epoxy resin, a polyimide resin, etc. The upper molding layer ML2 is made of, for example, an epoxy molding compound (EMC).

[0068] In some embodiments, there is an interface between the upper core molding layer 323 and the upper molding layer ML2 of each of the plurality of upper laminate structures 320. For example, the upper core molding layer 323 and the upper molding layer ML2 may be cured at different times, and there may be an interface between each of the upper core molding layer 323 and the upper molding layer ML2.

[0069] In the semiconductor package 1000 of the present invention, the redistribution layer RDL on which the upper semiconductor chip 220 and the plurality of upper laminate structures 320 are mounted is located above the lower semiconductor chip 210 and the plurality of lower laminate structures 310. This relatively reduces the size of the interposer 100. In the manufacturing process of the relatively small-sized interposer 100, the yield of the interposer 100 is improved and the process cost of the interposer 100 is reduced.

[0070] The redistribution layer RDL will be described more specifically with reference to FIG.

[0071] The redistribution layer RDL includes a redistribution insulating layer RD and a plurality of bonding pads BP. The plurality of bonding pads BP are embedded inside the redistribution insulating layer RD. The vertical levels (also referred to as vertical positions) of the lower surfaces of the plurality of bonding pads BP are equal. In this specification, the vertical level refers to the distance from the interposer 100 in the vertical direction (Z direction).

[0072] The redistribution layer RDL is divided into a lower redistribution layer RDL1 and an upper redistribution layer RDL2 on the lower redistribution layer RDL1. A portion of each of the plurality of bonding pads BP of the redistribution layer RDL is included in the upper redistribution layer RDL2, and another portion of each of the plurality of bonding pads BP is included in the lower redistribution layer RDL1. For example, the upper redistribution layer RDL2 and the lower redistribution layer RDL1 are divided based on the plurality of bonding pads BP of the redistribution layer RDL.

[0073] The upper redistribution layer RDL2 includes an upper redistribution pattern RP2 electrically connected to the plurality of bonding pads BP and an upper redistribution insulating layer RD2 covering the upper redistribution pattern RP2. The lower redistribution layer RDL1 includes a lower redistribution pattern RP1 electrically connected to the plurality of bonding pads BP and a lower redistribution insulating layer RD1 covering the lower redistribution pattern RP1. For example, the lower redistribution insulating layer RD1 and the upper redistribution insulating layer RD2 are collectively referred to as a redistribution insulating layer RD.

[0074] The redistribution insulating layer RD is made of an insulating material, such as a photoimageable dielectric (PID) resin. In some embodiments, the redistribution insulating layer RD may further include an inorganic filler. In some embodiments, the redistribution insulating layer RD may have a multi-layer structure in which a redistribution pattern is disposed in each layer. For example, each of the upper redistribution insulating layer RD2 and the lower redistribution insulating layer RD1 has a multi-layer structure.

[0075] The upper redistribution pattern RP2 includes an upper redistribution line RL2 extending horizontally and an upper redistribution via RV2 extending vertically (Z direction) from the upper redistribution line RL2. The upper redistribution line RL2 is disposed on at least one of the upper and lower surfaces of the upper redistribution insulating layer RD2 or inside the upper redistribution insulating layer RD2. The upper redistribution via RV2 penetrates the upper redistribution insulating layer RD2 and is connected to a portion of the upper redistribution line RL2.

[0076] The lower redistribution pattern RP1 includes a lower redistribution line RL1 extending horizontally and a lower redistribution via RV1 extending vertically (Z direction) from the lower redistribution line RL1. The lower redistribution line RL1 is disposed on at least one of the upper and lower surfaces of the lower redistribution insulating layer RD1 or inside the lower redistribution insulating layer RD1. The lower redistribution via RV1 penetrates the lower redistribution insulating layer RD1 and is connected to a portion of the lower redistribution line RL1.

[0077] In some embodiments, the width of the upper redistribution via RV2 increases as it approaches the interposer 100. For example, when the upper redistribution layer RDL2 is fabricated using a chip-first method, the width of the upper redistribution via RV2 increases as it moves downward in the vertical direction (Z direction). The width of the lower redistribution via RV1 decreases as it approaches the interposer 100. The upper redistribution via RV2 contacts the upper surface of the bonding pad BP, and the lower redistribution via RV1 contacts the lower surface of the bonding pad.

[0078] Each of the upper rewiring pattern RP2 and the lower rewiring pattern RP1 includes a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0079] The semiconductor package 1000 has a structure in which an upper semiconductor device SS2 including an upper redistribution layer RDL2, an upper semiconductor chip 220, a plurality of upper laminate structures 320, and an upper molding layer ML2 is stacked on a lower semiconductor device SS1 including an interposer 100, a lower semiconductor chip 210, a plurality of lower laminate structures 310, a lower molding layer ML1, and a lower redistribution layer RDL1.

[0080] In some embodiments, in the process of stacking the upper semiconductor device SS2 on the lower semiconductor device SS1, the upper redistribution layer RDL2 located at the bottom of the upper semiconductor device SS2 and the lower redistribution layer RDL1 located at the top of the lower semiconductor device SS1 are combined to form the redistribution layer RDL.

[0081] In some embodiments, the redistribution layer RDL may be fabricated by combining an upper redistribution layer RDL2 and a lower redistribution layer RDL1. The redistribution layer RDL is fabricated by combining the upper redistribution layer RDL2 and the lower redistribution layer RDL1 by hybrid bonding. However, the method of combining the upper redistribution layer RDL2 and the lower redistribution layer RDL1 is not limited thereto.

[0082] For example, the lower pad BP2 of the upper redistribution layer RDL2 is a part of the upper redistribution line RL2 of the upper redistribution layer RDL2 that is disposed on the lower surface of the upper redistribution insulating layer RD2 and exposed to the outside of the upper redistribution insulating layer RD2. The upper pad BP1 of the lower redistribution layer RDL1 is a part of the lower redistribution line RL1 of the lower redistribution layer RDL1 that is disposed on the upper surface of the lower redistribution insulating layer RD1 and exposed to the outside of the lower redistribution insulating layer RD1.

[0083] In some embodiments, the bonding pad BP is formed by thermal diffusion bonding a lower pad BP2 of the upper redistribution layer RDL2 and an upper pad BP1 of the lower redistribution layer RDL1. The redistribution insulating layer RD is formed by thermal diffusion bonding an upper redistribution insulating layer RD2 and a lower redistribution insulating layer RD1 during the formation of the bonding pad BP.

[0084] For example, the bonding pad BP is formed by diffusing and bonding a lower pad BP2 of the upper redistribution layer RDL2 and an upper pad BP1 of the lower redistribution layer RDL1 together, and the redistribution insulating layer RD is formed by diffusing and bonding an upper redistribution insulating layer RD2 and a lower redistribution insulating layer RD1 together.

[0085] In some embodiments, the thickness of the bonding pad BP is greater than the thickness of each of the upper redistribution line RL2 and the lower redistribution line RL1, for example, the thickness of the bonding pad BP is equal to the sum of the thickness of the upper redistribution line RL2 and the thickness of the lower redistribution line RL1.

[0086] In the semiconductor package 1000 of the present invention, the upper semiconductor chip 220 and the lower semiconductor chip 210 are overlapped in the vertical direction (Z direction) and electrically connected, thereby shortening the signal distance between the upper semiconductor chip 220 and the lower semiconductor chip 210, suppressing noise generation, and improving signal reliability.

[0087] In the semiconductor package 1000 of the present invention, the plurality of lower stacked structures 310 are connected to the plurality of upper stacked structures 320 via redistribution layers RDL, thereby increasing memory capacity. In addition, by stacking core semiconductor chips at high levels, the method of stacking stacked structures is relatively easy to manufacture and reduces manufacturing costs.

[0088] FIG. 4 is a cross-sectional view schematically illustrating a semiconductor package 1000a according to an embodiment of the present invention.

[0089] Referring to FIG. 4, the semiconductor package 1000a includes an interposer 100, a lower semiconductor chip 210, a plurality of lower laminate structures 310, a lower molding layer ML1, a redistribution layer RDL, an upper semiconductor chip 220, a plurality of upper laminate structures 320, and an upper molding layer ML2.

[0090] Most of the components and materials constituting the semiconductor package 1000a described below are substantially the same as or similar to those described above in Fig. 2. Therefore, for convenience of explanation, the following description will focus on the differences between the semiconductor package 1000a of Fig. 4 and the semiconductor package 1000 of Fig. 2 described above.

[0091] The lower semiconductor device SS1a includes an interposer 100, a lower semiconductor chip 210, a chip molding layer 211, a plurality of lower stacked structures 310, a lower molding layer ML1, and a lower rewiring layer RDL1.

[0092] The chip molding layer ML1 is located on the interposer 100 and surrounds the side surfaces of the lower semiconductor chip 210. In some embodiments, the thickness of the chip molding layer 211 is substantially the same as the thickness of the lower semiconductor chip 210. The upper surface of the chip molding layer 211 and the upper surface of the lower semiconductor chip 210 are coplanar, and the lower surface of the chip molding layer 211 and the lower surface of the lower semiconductor chip are coplanar. For example, the chip molding layer 211 and the lower semiconductor chip 210 are collectively referred to as the semiconductor chip. The chip molding layer 211 protects the lower semiconductor chip 210 from the outside.

[0093] In some embodiments, the area of ​​the top surface of lower semiconductor chip 210 is smaller than the area of ​​the top surface of upper semiconductor chip 220. In some embodiments, the sum of the area of ​​the top surface of lower semiconductor chip 210 and the area of ​​the top surface of chip molding layer 211 is the same as the area of ​​upper semiconductor chip 220.

[0094] The lower molding layer ML1 is positioned on the interposer 100 and surrounds the sides of each of the plurality of lower laminate structures 310 and the side of the chip molding layer 211. In some embodiments, there is an interface between the chip molding layer 211 and the lower molding layer ML1. For example, the hardening times of the chip molding layer 211 and the lower molding layer ML1 may be different, and there may be an interface between the chip molding layer 211 and the lower molding layer ML1.

[0095] In some embodiments, the chip molding layer 211 further includes a through-mold via 211_V. The through-mold via 211_V extends from the upper surface to the lower surface of the chip molding layer 211. The through-mold via 211_V is electrically connected to the upper pad 211_UP and the lower pad 211_DP of the chip molding layer 211. The lower pad 211_DP of the chip molding layer 211 is electrically connected to the interposer 100 via the first connecting terminal CT21, and the upper pad 211_UP of the chip molding layer 211 is in direct contact with and electrically connected to the redistribution layer RDL. For example, the through-mold via 211_V is electrically connected to the interposer 100 and the redistribution layer RDL.

[0096] In some embodiments, the width of the through-mold vias 211_V is greater than the width of the through-chip vias 210_V. Power is transferred from the interposer 100 to the redistribution layer RDL through the through-mold vias 211_V, and signals are transferred from the interposer 100 to the redistribution layer RDL through the through-chip vias 210_V.

[0097] In some embodiments, the width of the upper pad 211_UP of the chip molding layer 211 and the width of the lower pad 211_DP of the chip molding layer 211 are each greater than the width of the upper pad 210_UP of the lower semiconductor chip 210 and the width of the lower pad 210_DP of the lower semiconductor chip 210, respectively.

[0098] Fig. 5 is a cross-sectional view schematically illustrating a semiconductor package 1000b according to an embodiment of the present invention, and Fig. 6 is an enlarged view schematically illustrating an "EX2" portion of the semiconductor package 1000b shown in Fig. 5.

[0099] Referring to FIG. 5, the semiconductor package 1000b includes an interposer 100, a lower semiconductor chip 210, a chip molding layer 211, a plurality of lower laminate structures 310, a lower molding layer ML1, a redistribution layer RDL, an upper semiconductor chip 220, a plurality of upper laminate structures 320, and an upper molding layer ML2.

[0100] Most of the components and materials constituting the semiconductor package 1000b described below are substantially the same as or similar to those described above in Fig. 4. Therefore, for convenience of explanation, the following description will focus on the differences between the semiconductor package 1000b of Fig. 5 and the semiconductor package 1000a of Fig. 4 described above.

[0101] The upper semiconductor device SS2b includes an upper redistribution layer RDL2b, an upper semiconductor chip 220, a plurality of upper stack structures 320, and an upper molding layer ML2.

[0102] The upper semiconductor chip 220 and the plurality of upper stacked structures 320 are mounted on the upper redistribution layer RDL2b. For example, a third connecting terminal CT22 is located between the upper semiconductor chip 220 and the upper redistribution layer RDL2b, and a fourth connecting terminal CT32 is located between each of the plurality of upper stacked structures 320 and the upper redistribution layer RDL2b. The third connecting terminal CT22 electrically connects the lower pad 220_P of the upper semiconductor chip 220 to the upper redistribution pattern RP2b of the upper redistribution layer RDL2b, and the fourth connecting terminal CT32 electrically connects the lower pad 320_P of each upper buffer chip 321 of the plurality of upper stacked structures 320 to the upper redistribution pattern RP2b of the upper redistribution layer RDL2b. However, the upper semiconductor chip 220 and the plurality of upper laminate structures 320 may be electrically connected to the upper redistribution layer RDL2b by anisotropic film ACF, non-conductive film NCF, direct bonding, or hybrid bonding.

[0103] In some embodiments, the upper redistribution pattern RP2b of the upper redistribution layer RDL2b includes an upper redistribution line RL2 and an upper redistribution via RV2b. The width of the upper redistribution via RV2b decreases downward from the vertical direction. For example, the width of the upper redistribution via RV2b decreases as it approaches the interposer 100.

[0104] In some embodiments, in the process of fabricating the upper semiconductor device SS2b, an upper redistribution layer RDL2b is fabricated on a carrier substrate, and then the upper semiconductor chip 220 and a plurality of upper stack structures 320 are mounted on the upper redistribution layer RDL2b. That is, the upper semiconductor device SS2b is fabricated using a chip-last method.

[0105] FIG. 7 is a cross-sectional view schematically illustrating a semiconductor package 1000c according to an embodiment of the present invention.

[0106] Referring to FIG. 7, the semiconductor package 1000c includes an interposer 100, a lower semiconductor chip 210, a chip molding layer 211, a plurality of lower laminate structures 310c, a lower molding layer ML1, a redistribution layer RDL, an upper semiconductor chip 220, a plurality of upper laminate structures 320c, and an upper molding layer ML2.

[0107] Most of the components and materials constituting the semiconductor package 1000c described below are substantially the same as or similar to those described above in Fig. 4. Therefore, for ease of explanation, the following description will focus on the differences between the semiconductor package 1000c of Fig. 7 and the semiconductor package 1000a of Fig. 4 described above.

[0108] The plurality of lower laminate structures 310c are located on the interposer 100. Each of the plurality of lower laminate structures 310c includes a lower buffer chip 311, a plurality of lower core chips 312, and a lower core molding layer 313c.

[0109] The lower core molding layer 313c is positioned on the lower buffer chip 311 and covers the lower core chips 312. For example, the lower core molding layer 313c covers the side surfaces of the lower core chips 312 and the upper surface of the uppermost lower core chip 312U. For example, the lower core chips 312 are embedded inside the lower core molding layer 313c. For example, the lower core chips 312 are separated from the lower molding layer ML1 by the lower core molding layer 313c.

[0110] The upper stack structures 320c are located on the redistribution layer RDL, and each of the upper stack structures 320c includes an upper buffer chip 321, a plurality of upper core chips 322, and an upper core molding layer 323c.

[0111] The upper core molding layer 323c is positioned on the upper buffer chip 321 and encases the upper core chips 322. For example, the upper core molding layer 323c covers the side surfaces of each of the upper core chips 322 and the upper surface of the uppermost upper core chip 322U. For example, the upper core chips 322 are embedded inside the upper core molding layer 323c. For example, the upper core chips 322 are separated from the upper molding layer ML2 by the upper core molding layer 323c.

[0112] FIG. 8 is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment of the present invention.

[0113] Referring to FIG. 8, the semiconductor package 1000d includes an interposer 100, a lower semiconductor chip 210, a chip molding layer 211, a plurality of lower laminate structures 310, a lower molding layer ML1, a redistribution layer RDL, an upper interposer 120, an upper semiconductor chip 220, a plurality of upper laminate structures 320, and an upper molding layer ML2.

[0114] Most of the components and materials constituting the semiconductor package 1000d described below are substantially the same as or similar to those described above in Fig. 4. Therefore, for ease of explanation, the following description will focus on the differences between the semiconductor package 1000d of Fig. 8 and the semiconductor package 1000a of Fig. 4 described above.

[0115] The upper semiconductor device SS2d includes an upper interposer 120, an upper semiconductor chip 220, a plurality of upper laminate structures 320, and an upper molding layer ML2. The lower semiconductor device SS1d includes an interposer 100, a lower semiconductor chip 210, a plurality of lower laminate structures 310, a lower molding layer ML1, and a lower redistribution layer RDL1. The redistribution layer RDL of the semiconductor package 1000d is composed only of the lower redistribution layer RDL1.

[0116] Hereinafter, the interposer 100 of the lower semiconductor device SS1d will be referred to as a lower interposer. For example, a semiconductor package 1000d includes a lower interposer and an upper interposer 120 that overlap in the vertical direction.

[0117] The upper interposer 120 is located on the redistribution layer RDL. The upper semiconductor chip 220 and the plurality of upper stack structures 320 are located on the upper interposer 120 and are electrically connected to the upper interposer 120. The upper interposer 120 transmits signals between the upper semiconductor chip 220 and the plurality of upper stack structures 320, and between the upper semiconductor chip 220 and the redistribution layer RDL. In some embodiments, the areas of the top surfaces of the upper interposer 120, the redistribution layer RDL, and the interposer 100 are all equal.

[0118] The upper interposer 120 includes a second substrate 121 and second through vias 120_V that penetrate the second substrate 121. For example, the upper interposer 120 is a glass interposer in which the second substrate 121 includes glass and the second through vias 120_V are through glass vias (TGVs). However, the upper interposer 120 is not limited thereto, and may be a silicon interposer in which the second substrate 121 includes silicon and the second through vias 120_V are through silicon vias (TSVs).

[0119] The upper interposer 120 further includes upper pads 120_UP and lower pads 120_DP. The upper pads 120_UP are located on an upper surface of the second substrate 121 of the upper interposer 120, and the lower pads 120_DP are located on a lower surface of the second substrate 121 of the upper interposer 120. The upper pads 120_UP and the lower pads 120_DP are each electrically connected to a wiring region of the upper interposer 120. The upper pads 120_UP and the lower pads 120_DP are electrically connected by a second through via 120_V.

[0120] The third connecting terminals CT22 are located between the upper semiconductor chip 220 and the upper interposer 120, and the fourth connecting terminals CT32 are located between each of the plurality of upper stacked structures 320 and the upper interposer 120. The third connecting terminals CT22 electrically connect the lower pads 220_P of the upper semiconductor chip 220 to the upper pads 120_UP of the upper interposer 120, and the fourth connecting terminals CT32 electrically connect the lower pads 320_P of the upper buffer chips 321 of each of the plurality of upper stacked structures 320 to the upper rewiring patterns 120_UP of the upper interposer 120.

[0121] However, the upper semiconductor chip 220 and the plurality of upper laminate structures 320 may be electrically connected to the upper interposer 120 by anisotropic film ACF, non-conductive film NCF, direct bonding, or hybrid bonding.

[0122] In the process of bonding the upper semiconductor device SS2d onto the lower semiconductor device SS1d, the upper interposer 120 of the upper semiconductor device SS2d is mounted on the lower rewiring layer RDL1 of the lower semiconductor device SS1d.

[0123] In some embodiments, the upper pads BP1 of the lower redistribution layer RDL1 and the lower pads 120_DP of the upper interposer 120 are integrated by thermal diffusion bonding, thereby electrically and physically connecting the lower redistribution layer RDL1 and the upper interposer 120. However, without being limited thereto, the upper interposer 120 and the lower redistribution layer RDL1 may be electrically connected by an anisotropic film ACF, a non-conductive film NCF, or a connecting terminal.

[0124] 9 is a plan view schematically illustrating a semiconductor package 2000 according to an embodiment of the present invention, and FIG. 10 is a cross-sectional view schematically illustrating the semiconductor package 2000 of FIG. 9 taken along line BB' of FIG.

[0125] The semiconductor package 2000 of Figure 10 includes a package substrate 400, an interposer 100, a lower semiconductor chip 210, multiple lower laminate structures 310, a lower molding layer ML1, a redistribution layer RDL, an upper semiconductor chip 220, multiple upper laminate structures 320, and an upper molding layer ML2.

[0126] For example, the semiconductor package 2000 in FIG. 10 is an embodiment in which the above-mentioned semiconductor packages (1000 in FIG. 2, 1000a in FIG. 4, 1000b in FIG. 5, 1000c in FIG. 7, and 1000d in FIG. 8) are mounted on a package substrate 400.

[0127] Most of the components and materials constituting the semiconductor package 2000 described below are substantially the same as or similar to those described above in Fig. 4. Therefore, for ease of explanation, the following description will focus on the differences between the semiconductor package 2000 of Fig. 10 and the semiconductor package 1000a of Fig. 4 described above.

[0128] The package substrate 400 is a printed circuit board (PCB) including a core insulating layer. The core insulating layer generally has a flat plate or panel shape. The core insulating layer has upper and lower surfaces facing each other, and each of the upper and lower surfaces of the core insulating layer is flat. The core insulating layer includes at least one material selected from phenolic resin, epoxy resin, and polyimide.

[0129] For example, the core insulation layer includes at least one material selected from prepreg, polyimide, FR-4 (Flame Retardant 4), tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, bismaleimide triazine (BT), thermomount, cyanate ester, and liquid crystal polymer.

[0130] The package substrate 400 further includes an upper pad 400_UP located on the upper surface of the core insulating layer and a lower pad 400_DP located on the lower surface of the core insulating layer. The upper pad 400_UP and the lower pad 400_DP are electrically connected by through vias and / or internal wiring. For example, the upper pad 400_UP and the lower pad 400_DP may be made of copper, nickel, stainless steel, or beryllium copper.

[0131] The interposer 100 is disposed on a package substrate 400. The area of ​​the top surface of the package substrate 400 is larger than that of the interposer 100. The interposer 100 is electrically connected to the upper pads 400_UP of the package substrate 400 via the external connection terminals CT1. In some embodiments, the package substrate 400 further includes an underfill layer UF. The underfill layer UF is disposed between the interposer 100 and the package substrate 400 and covers the external connection terminals CT1.

[0132] A plurality of external connection terminals CT4 are attached to the lower pads 400_DP of the package substrate 400. The external connection terminals CT4 are configured to electrically and physically connect the package substrate 400 to an external device on which the package substrate 400 is mounted. The external connection terminals CT4 are formed of, for example, solder balls or solder bumps.

[0133] The lower semiconductor chip 210, the plurality of lower laminate structures 310, and the lower molding layer ML1 are located on the interposer 100. The redistribution layer RDL is located on the lower semiconductor chip 210 and the lower molding layer ML1. The upper semiconductor chip 220, the plurality of upper laminate structures 320, and the upper molding layer ML2 are located on the redistribution layer RDL.

[0134] In some embodiments, the redistribution layer RDL is fabricated by combining the lower redistribution layer RDL2 of the upper semiconductor device SS2 (see FIG. 4) and the upper redistribution layer RDL1 of the lower semiconductor device SS1a (see FIG. 4). The upper semiconductor chip 220 and the lower semiconductor chip 210 may be substantially the same type of chip. For example, each of the upper semiconductor chip 220 and the lower semiconductor chip 210 includes an ASIC. Each of the plurality of upper stacked structures 320 and each of the plurality of lower stacked structures 310 may be substantially the same type of stacked structure. For example, each of the plurality of upper stacked structures 320 and each of the plurality of lower stacked structures 310 is an HBM.

[0135] In some embodiments, the semiconductor package 2000 further includes a heat sink 500 positioned on the package substrate 400. For example, the heat sink 500 is horizontally spaced apart from the interposer 100, the lower molding layer ML1, and the upper molding layer ML2. However, without being limited thereto, the heat sink 500 may contact each side surface of the interposer 100, the lower molding layer ML1, and the upper molding layer ML2.

[0136] In some embodiments, the heat sink 500 is flat and includes a cavity extending from the top surface to the bottom surface, within which the interposer 100, the lower semiconductor chip 210, multiple lower laminate structures 310, the lower molding layer ML1, the redistribution layer RDL, the upper semiconductor chip 220, multiple upper laminate structures 320, and the upper molding layer ML2 are located.

[0137] The heat sink 500 is configured to dissipate heat generated in the semiconductor package 2000 to the outside of the semiconductor package 2000. The heat sink 500 prevents the package substrate 400 from being deformed by an external force.

[0138] The heat sink 500 includes a thermally conductive material having high thermal conductivity. For example, the heat sink 500 includes a metal such as copper (Cu) or aluminum (Al), or a carbon-containing material such as graphene, graphite, and / or carbon nanotubes. However, the material of the heat sink 500 is not limited to the above-mentioned materials. In an exemplary embodiment, the heat sink 500 includes a single metal layer or multiple stacked metal layers.

[0139] In some embodiments, the heat sink 500 is attached to the package substrate 400 via a thermal interface material (TIM) layer. The TIM layer includes a thermally conductive, electrically insulating material. For example, the TIM layer includes a polymer containing metal powder such as silver or copper, thermal grease, white grease, or a combination thereof.

[0140] Although the present invention has been described above with reference to the embodiments shown in the drawings, these are merely illustrative, and those skilled in the art will recognize that various modifications and equivalent embodiments are possible. Therefore, the true technical scope of protection of the present invention should be determined by the technical concept of the present invention. [Explanation of symbols]

[0141] 100: Interposer 210: Lower semiconductor chip 220: Upper semiconductor chip 310: Lower laminated structure 311: Lower buffer tip 312: Lower core chip 313: Lower core molding layer 320: Upper layer structure 321: Upper buffer tip 322: Upper core chip 323: Upper core molding layer 400: Package substrate 500: Heat sink ML1: Lower forming layer ML2: Upper forming layer RDL: Relay Layer

Claims

1. an interposer; a lower semiconductor chip positioned on the interposer and including a through-chip via; a plurality of lower stack structures positioned on the interposer and spaced apart from the lower semiconductor chip in a horizontal direction; a lower molding layer positioned on the interposer and surrounding a side surface of the lower semiconductor chip and a side surface of the plurality of lower laminate structures; a redistribution layer positioned on the lower molding layer, the lower semiconductor chip, and the plurality of lower stack structures, the redistribution layer being configured to be electrically connected to the through-chip vias of the lower semiconductor chip; an upper semiconductor chip located on the redistribution layer and electrically connected to the redistribution layer; a plurality of upper stack structures positioned on the redistribution layer and spaced apart from the upper semiconductor chip in the horizontal direction, the upper stack structures being electrically connected to the redistribution layer; an upper molding layer positioned on the redistribution layer and surrounding a side surface of the upper semiconductor chip and a side surface of the upper laminate structure.

2. the redistribution layer includes a redistribution insulating layer and a plurality of bonding pads embedded in the redistribution insulating layer; 2. The semiconductor package according to claim 1, wherein the vertical levels of the bonding pads of the redistribution layer are equal.

3. the redistribution layer includes a lower redistribution layer and an upper redistribution layer on the lower redistribution layer; each of the plurality of bonding pads of the redistribution layer includes a portion located inside the lower redistribution layer and a portion located inside the upper redistribution layer; the upper redistribution layer includes an upper redistribution line, an upper redistribution via extending vertically from the upper redistribution line, and an upper redistribution insulating layer surrounding the upper redistribution line and the upper redistribution via; the lower redistribution layer includes a lower redistribution line, a lower redistribution via extending vertically from the lower redistribution line, and a lower redistribution insulating layer surrounding the lower redistribution line and the lower redistribution via; the width of the upper redistribution via increases as it approaches the interposer, The semiconductor package of claim 2 , wherein the width of the lower redistribution via decreases as it approaches the interposer.

4. The semiconductor package of claim 3 , wherein the upper semiconductor chip and the plurality of upper stack structures contact the upper redistribution vias of the upper redistribution layer of the redistribution layer.

5. the redistribution layer includes a lower redistribution layer and an upper redistribution layer on the lower redistribution layer; each of the plurality of bonding pads of the redistribution layer includes a portion located in the lower redistribution layer and a portion located inside the upper redistribution layer; the upper redistribution layer includes an upper redistribution line, an upper redistribution via extending vertically from the upper redistribution line, and an upper redistribution insulating layer surrounding the upper redistribution line and the upper redistribution via; the lower redistribution layer includes a lower redistribution line, a lower redistribution via extending vertically from the lower redistribution line, and a lower redistribution insulating layer surrounding the lower redistribution line and the lower redistribution via; 3. The semiconductor package of claim 2, wherein the thickness of the upper redistribution line and the thickness of the lower redistribution line are each smaller than the thickness of each of the plurality of bonding pads.

6. 2. The semiconductor package according to claim 1, wherein the area of ​​the upper surface of the interposer is equal to the area of ​​the upper surface of the rewiring layer.

7. a lower interposer; a lower semiconductor chip positioned on the lower interposer and including a through-chip via; a through-mold via positioned on the lower interposer, electrically connected to the lower interposer, and horizontally spaced apart from the lower semiconductor chip; a plurality of lower stack structures positioned on the lower interposer and spaced apart from the lower semiconductor chip in a horizontal direction; a lower molding layer positioned on the lower interposer and surrounding a side surface of the lower semiconductor chip and a side surface of the lower laminate structure; a redistribution layer disposed on the lower molding layer, the lower semiconductor chip, the through-mold vias, and the plurality of lower stack structures, and configured to be electrically connected to the through-chip vias; an upper semiconductor chip located above the redistribution layer and electrically connected to the redistribution layer; a plurality of upper stack structures positioned above the redistribution layer and horizontally spaced apart from the upper semiconductor chip, the upper stack structures being electrically connected to the redistribution layer; an upper molding layer positioned above the redistribution layer and surrounding a side surface of the upper semiconductor chip and a side surface of the upper laminate structure.

8. 8. The semiconductor package of claim 7, wherein the area of ​​the upper surface of the lower semiconductor chip is smaller than the area of ​​the upper surface of the upper semiconductor chip.

9. a chip molding layer positioned on the lower interposer and in contact with a side surface of the lower semiconductor chip; 8. The semiconductor package of claim 7, wherein a side surface of the lower semiconductor chip is spaced apart from the lower molding layer with the chip molding layer interposed therebetween.

10. further comprising an upper interposer positioned on the redistribution layer; the upper semiconductor chip, the plurality of upper stack structures, and the upper molding layer are located on the upper interposer; The semiconductor package of claim 7 , wherein the upper interposer is configured to transmit signals between the upper semiconductor chip and the plurality of upper stack structures.

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