Semiconductor device

Abstract

To provide a semiconductor device which improves on-state characteristics of a transistor to achieve high-speed response and high-speed driving; and manufacture a semiconductor device having highly reliable and stable electric characteristics.SOLUTION: A semiconductor device has: a first oxide layer; an oxide semiconductor layer on the first oxide layer; a source electrode layer and a drain electrode layer which contact the oxide semiconductor layer; a second oxide layer on the oxide semiconductor layer; a gate insulation layer on the second oxide layer; and a gate electrode layer on the gate insulation layer, in which an end of the second oxide layer and an end of the gate insulation layer have a transistor overlapping the source electrode layer and the drain electrode layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electrical equipment are all semiconductor devices. [Background technology]

[0003] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology for constructing transistors (also called transistors) is attracting attention. It is widely used in electronic devices such as image display devices (display devices). Silicon-based semiconductor materials are widely known as applicable semiconductor thin films, but other materials are also Semiconductor materials using oxides are attracting attention as a new material.

[0004] For example, oxides containing In (indium), Ga (gallium), and Zn (zinc) (oxide semiconductors) A transistor using a conductor is disclosed in Patent Document 1.

[0005] In addition, a transistor using an oxide semiconductor layer for a channel formation region can be Carriers are generated by oxygen deficiency (oxygen defect) caused by oxygen desorption. Therefore, oxygen released from a silicon oxide film containing excess oxygen is supplied to the oxide semiconductor layer. By filling the oxygen vacancies in the oxide semiconductor layer, the change in electrical characteristics is small and the reliability is high. It is known that a semiconductor device can be provided (Patent Document 2). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-19207 Summary of the Invention [Problem to be solved by the invention]

[0007] A transistor using an oxide semiconductor for a channel formation region is formed by adding impurities such as hydrogen to the oxide semiconductor. Carriers are also generated when impurities such as silicon enter the material. This causes oxygen vacancies and generates carriers.

[0008] The generation of carriers in the oxide semiconductor increases the off-state current of the transistor and This causes an increase in the variation in the voltage, which in turn causes the electrical characteristics of the transistor to fluctuate and reduces the reliability of the semiconductor device. Reliability decreases.

[0009] Furthermore, as integrated circuits using transistors become larger in scale, high-speed driving and high-speed response of circuits are required. The on-state characteristics of the transistor (for example, on-state current and field-effect mobility) are improved. By doing so, it is possible to provide a semiconductor device with higher performance that can be driven at high speed and respond at high speed. can be done.

[0010] In view of the above problems, one embodiment of the present invention is to improve on-state characteristics of a transistor, thereby achieving high-speed response and high-speed operation. Another object of the present invention is to provide a semiconductor device that can achieve high speed driving. One object is to manufacture a semiconductor device that exhibits stable electrical characteristics. [Means for solving the problem]

[0011] In order to solve the above problems, one aspect of the present invention is a method for manufacturing a semiconductor device comprising: a first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer on the conductor layer; a gate insulating layer on the second oxide layer; and a gate insulating layer on the gate insulating layer. an end of the second oxide layer and an end of the gate insulating layer are connected to the source electrode layer and The semiconductor device is a semiconductor device in which the gate electrode layer and the drain electrode layer overlap each other.

[0012] Note that the first oxide layer and the second oxide layer contain impurities as main constituent elements in the oxide semiconductor layer. It is preferable that the first layer does not contain impurity elements such as silicon that form levels due to impurities. The first oxide layer and the second oxide layer are oxides containing the same element as the oxide semiconductor layer as a main constituent element. In the case of an oxide semiconductor layer, a thin film is formed at the interface between the oxide semiconductor layer and the first oxide layer and the second oxide layer. As a result, the interface scattering can be reduced and the field-effect mobility can be increased. and an oxide containing the same element as a main constituent element in the first oxide layer and the second oxide layer. By using this, there are fewer trap levels at the interface, and the transistor is less susceptible to deterioration over time and stress. The amount of variation in threshold voltage due to testing can be reduced.

[0013] By doing so, the oxide semiconductor layer can be in contact with the layer containing an impurity element such as silicon. Therefore, the oxide semiconductor layer can be formed without using an impurity source such as silicon. This prevents elements from entering the semiconductor device, thereby making it possible to provide a highly reliable semiconductor device.

[0014] Therefore, one embodiment of the present invention is a method for manufacturing a semiconductor device including a first oxide layer and an oxide semiconductor layer on the first oxide layer. a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer on the source electrode layer and the drain electrode layer; and a gate insulating layer on the second oxide layer. a gate electrode layer on the gate insulating layer, and an edge of the second oxide layer and the gate insulating layer The end portions of the semiconductor device overlap with the source electrode layer and the drain electrode layer.

[0015] The upper end of the second oxide layer coincides with the lower end of the gate insulating layer, and the upper end of the gate insulating layer The lower end of the gate electrode layer may be coincident with the lower end of the gate electrode layer. The gate electrode layer is used as a mask to form the second oxide layer and the gate insulating layer. It may include shapes obtained by etching.

[0016] In addition, a sidewall insulating layer may be formed in contact with the side surface of the gate electrode layer. The top edge of the oxide layer 2 coincides with the bottom edge of the gate insulating layer, and the top edge of the gate insulating layer is aligned with the sidewall insulating layer. The lower end of the edge layer may be aligned with the lower end of the edge layer. The second oxide layer and the gate insulating layer are etched using the sidewall insulating layer and the gate electrode layer as a mask. This may include shapes obtained by shaping.

[0017] In the oxide semiconductor layer, the first oxide layer, and the second oxide layer, the conduction band of the oxide semiconductor layer A well-shaped structure in which the bottom of the conduction band (also called the conduction band) is at the lowest energy level. (also called a well structure) is formed, and a channel is formed in the oxide semiconductor layer. To achieve this, the oxide semiconductor layer must have a minimum depth (electron density) from the vacuum level to the conduction band. It is preferable that the affinity between the first oxide layer and the second oxide layer is greater than that between the first oxide layer and the second oxide layer. In general, the oxide semiconductor layer has an electron affinity 0.5 times lower than that of the first oxide layer and the second oxide layer. It is preferable that it is 2 eV or more larger.

[0018] The electron affinity is determined by the energy difference between the vacuum level and the top of the valence band (the so-called ionization potential). potential), the energy difference between the bottom of the conduction band and the top of the valence band (the so-called band gap) It can be calculated by subtracting the value of

[0019] The ionization potential of the oxide semiconductor used to derive the electron affinity is determined by the ultraviolet photoelectron component. Optical analysis (UPS: Ultraviolet Photoelectron Spectr The typical UPS measurement device is the Vers aProbe (manufactured by PHI) is used. g ) is a fully automated spectroscopic The ionization potential can be measured using a lipometer UT-300. The energy at the bottom of the conduction band can be calculated by subtracting the energy band gap from Using this technique, a buried channel can be formed in the stacked structure disclosed herein. It can be confirmed that it is formed.

[0020] The first oxide layer, the second oxide layer, and the oxide semiconductor layer contain at least indium, and The oxide semiconductor layer contains indium at a higher atomic ratio than the first oxide layer and the second oxide layer. Alternatively, the first oxide layer, the second oxide layer, and the oxide semiconductor layer may contain at least In that case, the oxide semiconductor layer may contain indium, zinc, and gallium. The oxide layer preferably contains indium at a higher atomic ratio than the first oxide layer and the second oxide layer. In addition, the first oxide layer and the second oxide layer have a higher atomic ratio of gallium than the oxide semiconductor layer. It is preferable that it contains .

[0021] Further, an oxide insulating layer containing excess oxygen may be provided over the gate electrode layer. Thermal desorption spectroscopy analysis of the oxide insulating layer showed that the amount of oxygen released, converted to oxygen atoms, was 1. 0×10 19 atoms / cm 3 The oxide insulating layer containing excess oxygen is preferably It is preferable that the oxygen content be in excess of the stoichiometric composition.

[0022] The second oxide layer and the oxide semiconductor layer have crystalline regions in which the c-axis is oriented in a direction substantially perpendicular to the surface. It may have.

[0023] In another embodiment of the present invention, a first oxide layer and an oxide semiconductor layer are stacked, and A source electrode layer and a drain electrode layer are formed on the oxide layer and the oxide semiconductor layer of the first insulating film. An oxide film and a gate insulating film are laminated on the electrode layer and the drain electrode layer. A gate electrode layer is formed on the gate insulating film, and the gate electrode layer is used as a mask for etching. The oxide film and the gate insulating film are processed into an island shape to form a second oxide layer and a gate insulating layer. The source electrode layer, the drain electrode layer, the second oxide layer, the gate insulating layer, and the gate electrode layer are then formed. The present invention relates to a method for manufacturing a semiconductor device in which an oxide insulating layer is formed on a substrate.

[0024] In addition, a first oxide layer and an oxide semiconductor layer are stacked, and the first oxide layer and the oxide semiconductor layer are stacked. A source electrode layer and a drain electrode layer are formed on the semiconductor layer, and the source electrode layer and the drain electrode layer are An oxide film and a gate insulating film are laminated on the layer, and a gate insulating film is formed on the oxide film and the gate insulating film. an oxide insulating layer is formed on the gate insulating film and the gate electrode layer; The edge layer is etched to form a sidewall insulating layer in contact with the side surface of the gate electrode layer, and and a gate electrode layer as a mask to etch the oxide film and the gate insulating film. This is a method for producing the above. [Effects of the Invention]

[0025] According to one embodiment of the present invention, a semiconductor device capable of high-speed response and high-speed operation can be provided. Furthermore, it is possible to provide a semiconductor device that is highly reliable and exhibits stable electrical characteristics. [Brief explanation of the drawings]

[0026] [Figure 1] 1A and 1B are a cross-sectional view and a top view illustrating a semiconductor device of one embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 3] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A and 1B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. [Figure 5] 1A and 1B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. [Figure 6] 1A and 1B are a cross-sectional view and a top view illustrating a semiconductor device of one embodiment of the present invention. [Figure 7] 1A and 1B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A and 1B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. [Figure 11] FIG. 1 is a circuit diagram of a semiconductor device of one embodiment of the present invention. [Figure 12] 1A and 1B are a circuit diagram and a conceptual diagram of a semiconductor device of one embodiment of the present invention. [Figure 13] FIG. 1 is a block diagram of a semiconductor device of one embodiment of the present invention. [Figure 14] FIG. 1 is a block diagram of a semiconductor device of one embodiment of the present invention. [Figure 15] FIG. 1 is a block diagram of a semiconductor device of one embodiment of the present invention. [Figure 16] An electronic device to which the semiconductor device of one embodiment of the present invention can be applied. [Figure 17] 3 is a cross-sectional photograph of an example sample. [Figure 18] 3 is a cross-sectional photograph of an example sample. [Figure 19] FIG. 1 is a band diagram illustrating a semiconductor device of one embodiment of the present invention. [Figure 20] FIG. 1 is a diagram illustrating the diffusion of oxygen vacancies. [Figure 21] FIG. 10 is a diagram illustrating the electrical characteristics of the example samples. [Figure 22] FIG. 10 is a diagram illustrating the electrical characteristics of the example samples. [Figure 23] FIG. 10 is a diagram illustrating the electrical characteristics of the example samples. [Figure 24] FIG. 10 is a diagram illustrating the electrical characteristics of the example samples. [Figure 25] FIG. 10 is a diagram illustrating the electrical characteristics of the example samples. DETAILED DESCRIPTION OF THE INVENTION

[0027] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and it is understood by those skilled in the art that various modifications can be made to the modes and details. It will be easily understood. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0028] In the embodiments described below, the same reference numerals are used in common between different drawings. It should be noted that the thickness, width, relative position, etc. of the components shown in the drawings, i.e., layers and regions, may differ. In order to clarify the description of the embodiments, the positional relationships may be exaggerated. There is a match.

[0029] In this specification, the term "above" means that the positional relationship of a component is "directly above." For example, the expression "gate electrode layer on an insulating layer" is not limited to the insulating layer. This does not exclude the inclusion of other components between the layer and the gate electrode layer. is.

[0030] In addition, in this specification, the terms "electrode layer" and "wiring layer" refer to the functional components of these elements. For example, the "electrode layer" is used as part of the "wiring layer." Furthermore, the terms "electrode layer" and "wiring layer" may be used interchangeably. This also includes cases where multiple "electrode layers" or "wiring layers" are formed integrally.

[0031] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are used interchangeably. It is assumed that this is possible.

[0032] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects.

[0033] For example, "something that has some kind of electrical effect" includes electrodes and wiring.

[0034] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. refers to the state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This includes cases where the angle is between 85° and 95°.

[0035] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0036] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention will be described in detail with reference to drawings. FIG. 1 shows a semiconductor device of one embodiment of the present invention. FIG. 1B shows a semiconductor device of one embodiment of the present invention. 1A shows a top view, and FIG. 1A shows a cross-sectional view taken along the dashed line AB in FIG. 1B.

[0037] A transistor 420 included in the semiconductor device is formed by a base insulating layer 402 over a substrate 400 and a base insulating film 403. A stack of a first oxide layer 404a and an oxide semiconductor layer 404b on the edge layer 402, and a first oxide The source electrode layer 406a and the drain electrode layer 406b are formed on the oxide semiconductor layer 404a and the oxide semiconductor layer 404b. layer 406b and a second oxide layer 406c on the source electrode layer 406a and the drain electrode layer 406b. 04c, a gate insulating layer 408 on the second oxide layer 404c, and a gate insulating layer 408 on the gate insulating layer 408. The gate electrode layer 410, the source electrode layer 406a, the drain electrode layer 406b, and the second oxide The oxide insulating layer 412 on the layer 404c, the gate insulating layer 408, and the gate electrode layer 410, and the oxide insulating layer 412 on the oxide insulating layer 404c, the gate insulating layer 408, and the gate electrode layer 410 and an insulating layer 414 on the oxide insulating layer 412.

[0038] The oxide semiconductor layer 404b is thicker than the first oxide layer 404a and the second oxide layer 404c. An oxide having a large depth from the vacuum level to the bottom of the conduction band is used. The difference in electron affinity between the first oxide layer 404a and the second oxide layer 404c is 0.2 eV. With this structure, the oxide semiconductor layer 404b is The lower end of the conduction band has an energy level lower than that of the second oxide layer 404a and the second oxide layer 404c. A well structure is formed, and a channel is formed in the oxide semiconductor layer 404b. The channel structure may be a built-in channel structure.

[0039] To prevent impurities such as silicon from entering the oxide semiconductor layer 404b serving as a channel, an oxide The first oxide layer 404a and the second oxide layer 404c in contact with the oxide semiconductor layer 404b are mainly The first oxide layer 404 is a film that does not contain impurities such as silicon as a constituent element. The second oxide layer 404c and the oxide semiconductor layer 404b are prevented from scattering at the interface between the first oxide layer 404a and the oxide semiconductor layer 404b. In order to reduce trapping states, the first oxide layer 404a, the oxide semiconductor layer 404b, and the second oxide semiconductor layer 404c are It is preferable that the elements contained in the oxide layers 404c are the same.

[0040] Note that the oxide semiconductor layer 404b is formed by dividing the first oxide layer 404a and the second oxide layer 404c. By sandwiching the layers, the components of the base insulating layer 402 and the gate insulating layer 408 are transferred to the oxide semiconductor layer 40. For example, the insulating base layer 402 and the gate insulating layer 4 08 is a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, or a silicon nitride film. When using an insulating layer containing silicon such as silicon film (hereinafter also referred to as silicon insulating layer), Silicon contained in the insulating layer 402 and the gate insulating layer 408 is mixed into the oxide semiconductor layer 404b. This can prevent the intrusion of

[0041] Here, silicon oxynitride is a material whose composition contains more oxygen than nitrogen. For example, oxygen is 50 atomic % or more and 70 atomic % or less, and nitrogen is 0.5 atomic % or less. % or more and 15 atomic % or less, and silicon is contained in the range of 25 atomic % or more and 35 atomic % or less. However, the above range is not applicable to Rutherford backscattering spectroscopy or hydrogen forward scattering spectroscopy (HFS:H When measured using hydrogen forward scattering The total content of the constituent elements does not exceed 100 atomic percent.

[0042] The first oxide semiconductor layer 404b is formed to a thickness large enough to prevent impurity elements from entering the oxide semiconductor layer 404b. It is preferable that the oxide layer 404a and the second oxide layer 404c are thickened. As shown in the embodiment, the oxide semiconductor layer 404b is a layer including the source electrode layer 406a and the drain electrode layer 406b. The second oxide layer 404c is in contact with the source electrode layer 406a and the drain electrode layer 406b. Since the first oxide layer 404a and the second oxide layer 404b are disposed on the Even if the thickness of the oxide semiconductor layer 404b, the source electrode layer 406a, and the drain electrode layer 406c is increased, The resistance with 406b does not increase, and the degradation of the on-characteristics can be suppressed.

[0043] The band structure of the buried channel structure is shown in FIG. 19. The oxide layer 404a and the second oxide layer 404c are made of an oxide having an atomic ratio of In:Ga:Zn=1:1:1. The oxide semiconductor layer 404b is an In:Ga:Zn=3 atomic ratio. 1 is an energy band diagram when a first oxide layer 4 is used. The electron affinity of the oxide semiconductor layer 404a and the second oxide layer 404c is 4.7 eV. The electron affinity of the first oxide layer 404a and the second oxide layer 404b is 4.9 eV. The bottom of the conduction band of the oxide semiconductor layer 404c is higher than the bottom of the conduction band of the oxide semiconductor layer 404b. Therefore, the band structure in this stacked structure is as shown in FIG. The bottom of the conduction band is the deepest, forming a well-shaped structure. Carriers (electrons) travel through the oxide semiconductor layer 404b, that is, the transistor It can be considered that the channel formation region is substantially formed in the oxide semiconductor layer 404b. As described above, the oxide semiconductor layer 404b is formed from the base insulating layer 402 and the gate insulating layer 408. Therefore, defects due to oxygen vacancies and the like in the oxide semiconductor layer 404b are reduced. Therefore, carriers (electrons) traveling in the oxide semiconductor layer 404b are not affected by the defects. It becomes difficult.

[0044] The band structure in Figure 19 shows that the channel formation region of the transistor is buried inside the oxide semiconductor layer. The oxide semiconductor layer 404b serving as a channel formation region can be considered to be embedded in the oxide semiconductor layer 404b. Since the insulating layer 402 and the gate insulating layer 408 are not in contact with each other, the capacitance of the carriers traveling through the channel is The rear (electrons) are less susceptible to the effect of interface scattering. Even if the state of the channel changes over time (if interface states are generated), the carriers traveling through the channel A (electrons) can be made into a semiconductor device that is less susceptible to the influence of the interface and has high reliability.

[0045] The oxide insulating layer 412 preferably contains oxygen in excess of the stoichiometric composition. When the oxide semiconductor layer 404b contains oxygen in excess of the stoichiometric composition, oxygen is supplied to the oxide semiconductor layer 404b. For example, when a silicon oxide film is used as the oxide insulating layer 412, defects can be reduced. In this case, SiO (2+α) (where α>0).

[0046] By forming the oxide insulating layer 412 as the above film, the oxide insulating layer 4 12, and supplies oxygen to the oxide semiconductor layer 404b. By compensating for the oxygen vacancies in 404b, the threshold voltage of the transistor moves in the negative direction. The shift in TDS (Thermal Dispersion Strength) can be suppressed by releasing oxygen through heat treatment. Desorption Spectroscopy (thermal desorption spectroscopy) analysis The oxide insulating layer 412 has a low oxygen release rate converted into oxygen atoms in TDS analysis. But 1.0×10 19 atoms / cm 3 or more, preferably 3.0 × 10 19 atoms / cm 3 More preferably, 1.0 × 10 20 atoms / cm 3 It is good to have more than .

[0047] A second oxide layer 404c and a gate electrode layer 404d are formed over the source electrode layer 406a and the drain electrode layer 406b. The end of the gate insulating layer 408 is provided to overlap the second oxide layer 404c and The side surface of the gate insulating layer 408 is in contact with the oxide insulating layer 412. 04c, the gate insulating layer 408, or both, from the oxide insulating layer 412 to the oxide insulating layer 412. Oxygen can be supplied to the semiconductor layer 404b to compensate for oxygen vacancies. The gate electrode layer 410 and the source electrode layer 406a or the gate insulating layer 408 are In order to prevent the drain electrode layer 406b from being short-circuited, It is preferable that the width is 0 μm or more and 3 μm or less, and more preferably 0 μm or more and 1 μm or less.

[0048] Furthermore, if hydrogen is contained in the oxide semiconductor layer 404b, a donor is generated, which makes the oxide semiconductor layer 404b n-type. Therefore, hydrogen enters the oxide semiconductor layer 404b from the outside of the transistor 420. The insulating layer 414 is provided above or below the oxide semiconductor layer 404b as a protective layer to prevent the oxide semiconductor layer 404b from being broken. It is advisable to set it up in that direction.

[0049] Next, a method for manufacturing the transistor 420 will be described.

[0050] First, a base insulating layer 402 is formed on a substrate 400 .

[0051] There are no major restrictions on the substrate that can be used, but it should have at least enough heat resistance to withstand the subsequent heat treatment. For example, barium borosilicate glass and aluminoborosilicate glass Glass substrates such as glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used. can.

[0052] The substrate 400 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor A substrate, a compound semiconductor substrate such as silicon germanium, etc. may also be used. A plate, a semiconductor substrate on which a semiconductor element is provided, or the like can be used.

[0053] The insulating base layer 402 is formed by sputtering, MBE (Molecular Beam Epoxy), or the like. itaxy method, CVD (Chemical Vapor Deposition), Pulsed Laser Deposition (PLD) method, A Atomic Layer Deposition (LD) method or the like can be used as appropriate. do.

[0054] The base insulating layer 402 may be formed using an inorganic insulating film. Silicon nitride film, aluminum oxide film, aluminum oxynitride film, hafnium oxide film, acid gallium nitride film, silicon nitride film, aluminum nitride film, silicon nitride oxide film, aluminum nitride oxide film It is preferable to use an aluminum film or the like. In addition, these compounds may be used in a single layer structure or a laminate of two or more layers. It can be formed and used in a structure.

[0055] The base insulating layer 402 was formed by using a plasma CVD apparatus, and the inside of the evacuated processing chamber was heated to 1800 K. The temperature is maintained at 0°C or higher and 450°C or lower, more preferably 180°C or higher and 350°C or lower, and the temperature is maintained in the processing chamber. The pressure in the processing chamber is adjusted to 100 Pa or more and 250 Pa or less by introducing the raw material gas. The pressure is set to 100 Pa or more and 200 Pa or less, and the pressure applied to the electrodes installed in the processing chamber is 1.48 W / cm 2 Below Upper 2.46W / cm 2 or less, more preferably 1.48 W / cm 2 More than 1.97W / cm 2 Silicon oxide film or silicon oxynitride film is formed under the following conditions of supplying high frequency power. It may be formed.

[0056] As the source gas, a deposition gas containing silicon and an oxidizing gas are preferably used. Representative examples of silicon-containing deposition gases include silane, disilane, trisilane, and silicon fluoride. Oxidizing gases include oxygen, ozone, nitrous oxide, nitrogen dioxide, dry air, etc. There is a feeling.

[0057] As the film forming conditions, in the processing chamber at the above pressure, high frequency power with the above high power density is used. By supplying the source gas, the decomposition efficiency in the plasma increases, oxygen radicals increase, Since the oxidation of the deposition gas containing silicon progresses, the oxygen content in the base insulating layer 402 However, if the substrate temperature is within the temperature range described above, The bond between silicon and oxygen becomes weaker. As a result, the silicon becomes weaker than the oxygen that satisfies the stoichiometric composition. An oxide insulating layer containing a large amount of oxygen can be formed, from which part of the oxygen is released by heating. do.

[0058] Note that a deposition gas containing silicon for an oxidizing gas is used as a source gas for the base insulating layer 402. By increasing the proportion of the body and setting the high frequency power to the above power density, the deposition rate can be increased. At the same time, the oxygen content in the base insulating layer 402 can be increased.

[0059] Note that insulation between the substrate 400 and the oxide semiconductor layer 404b to be formed later can be ensured. If necessary, the base insulating layer 402 may not be provided.

[0060] Next, a first oxide layer 404a and an oxide semiconductor layer 404b are formed over the base insulating layer 402. The first oxide layer 404a and the oxide semiconductor layer 404b are formed by oxidizing the oxide semiconductor layer 404a. After laminating and forming a layer of a material film and heating it, selective etching is performed using a mask. It can be formed.

[0061] The first oxide layer 404a may be an oxide layer exhibiting insulating properties or an oxide layer exhibiting semiconducting properties. The oxide semiconductor layer 404b may be an oxide (oxide semiconductor) layer. However, the first oxide layer 404a has a higher electron affinity than the oxide semiconductor layer 404b. The material of the first oxide layer 404a and the oxide semiconductor are appropriately selected so that the difference is 0.2 eV or more. A material for the conductor layer 404b is selected.

[0062] Note that the first oxide layer 404a and the oxide semiconductor layer 404b are formed mainly from the same element. By using an oxide containing an element, the first oxide layer 404a and the oxide semiconductor layer 40 By suppressing the interface scattering at the interface of 4b, it is possible to provide a transistor with excellent mobility. In addition, the first oxide layer 404a and the oxide semiconductor layer 404b can be formed using the same element. By using oxides containing these elements as the main constituents, the trap levels can be reduced, and the transistor The amount of variation in threshold voltage due to deterioration over time or stress testing can be reduced.

[0063] The oxide insulator that can be used for the first oxide layer 404a is hafnium oxide, oxide Tantalum oxide, gallium oxide, aluminum oxide, magnesium oxide, zirconium oxide, etc. By using oxide insulators that do not contain silicon, the oxide This can prevent impurities such as silicon from entering the compound semiconductor layer 404b.

[0064] The oxide semiconductor layer 404b may be formed of an oxide The semiconductor preferably contains at least indium (In) or zinc (Zn). Alternatively, it is preferable that the oxide semiconductor contains both In and Zn. In order to reduce the variation in the electrical properties of the stabilizers, one or more stabilizers are used together with them. It is preferred that the compound has the following structure:

[0065] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, other stabilizers The lanthanides are lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0066] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. , Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In- Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, I n-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al -Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, I n-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy -Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide It is possible.

[0067] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as main constituent elements. The ratio of In, Ga, and Zn does not matter. Metal elements other than Ga and Zn may also be included.

[0068] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) It is also possible to use a material represented by the formula: where M is selected from Ga, Fe, Mn, and Co. It refers to one or more metal elements. In addition, as an oxide semiconductor, In2SnO5 (ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0069] However, the electron affinity of the oxide semiconductor layer 404b is higher than that of the first oxide layer 404a. Specifically, the material of the first oxide layer 404a is appropriately selected so that the difference is 0.2 eV or more. The material of the oxide semiconductor layer 404b is selected in this manner. The depth of the conduction band of the oxide semiconductor from the vacuum level is larger than that of the first oxide layer 404a from the vacuum level. The depth of the conduction band of the layer 404b increases, and a well-type band can be formed.

[0070] The first oxide layer 404a is made of aluminum, gallium, germanium, yttrium, silicon, or the like. The oxide semiconductor layer 404b contains zinc, lanthanum, or cerium at a higher atomic ratio than the oxide semiconductor layer 404b. Specifically, the first oxide layer 404a may be formed by using an oxide semiconductor layer 4 The above elements are present in an amount 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more, of the amount of O4b. The oxides contained in the above are used. The above elements bond strongly with oxygen, and the formation energy of oxygen vacancies is Therefore, the first alloy, which has a high atomic ratio of the above elements, has a high energy content and is less likely to develop oxygen deficiency. The oxide layer 404a is less likely to have oxygen vacancies than the oxide semiconductor layer 404b and is more stable. Therefore, the first oxide layer 404a has the above-mentioned properties. By increasing the atomic ratio of the elements, a stable interface with the silicon insulating layer can be formed. This makes it possible to provide a highly reliable semiconductor device.

[0071] However, the first oxide layer 404a is made of InGa X Zn Y O Z If the material contains ingredients that can be expressed as It is preferable that X does not exceed 10. The proportion of gallium contained in the oxide semiconductor layer As a result, the powdery material (also known as dust) generated during film formation in RF sputtering The amount of oxides (hereinafter referred to as oxides) increases, which may result in deterioration of the characteristics of the semiconductor device.

[0072] The oxide semiconductor film is formed by RF sputtering, which uses a high frequency power source. In addition to the sputtering method, there are also DC sputtering methods that use a direct current power supply and AC sputtering methods that use an alternating current power supply. In particular, when DC sputtering is used, the film formation is This can reduce the amount of dust that is generated and also make the film thickness distribution uniform.

[0073] The first oxide layer 404a and the oxide semiconductor layer 404b are made of In-Ga-Zn oxide. In this case, the ratio of In, Ga, and Zn is, for example, In:Ga:Zn=1:1:1, In :Ga:Zn=2:2:1, In:Ga:Zn=3:1:2, In:Ga:Zn=1:3 :2, In:Ga:Zn=1:4:3, In:Ga:Zn=1:5:4, In:Ga:Z n=1:6:6, In:Ga:Zn=2:1:3, In:Ga:Zn=1:6:4, In :Ga:Zn=1:9:6, In:Ga:Zn=1:1:4, In:Ga:Zn=1:1 :2 or oxides having compositions close to these may be used.

[0074] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with c=1) is In:Ga:Zn=A:B:C (A+B+C = 1), the oxide composition is close to (aA) 2 +(bB) 2 + (cC) 2 ≦r 2 The value of r can be set to, for example, 0.05. The same applies to other oxides.

[0075] The oxide semiconductor layer 404b contains more indium than the first oxide layer 404a. In oxide semiconductors, the s orbitals of heavy metals mainly contribute to carrier conduction. By increasing the In content, more s orbitals overlap, so In is more abundant than Ga. Oxides with a composition containing a large amount of In have a higher In content than oxides with a composition containing the same amount of Ga or less. Therefore, when the oxide semiconductor layer 404b contains an oxide semiconductor having a high indium content, the oxide semiconductor layer 404b has high mobility. By using such a material, high mobility can be achieved.

[0076] The first oxide layer 404a is formed by In:Ga:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor When the conductor layer 404b has an atomic ratio of In:Ga:Zn=x2:y2:z2, y1 / x The first oxide layer 404a and the oxide semiconductor layer 404b are arranged such that y2 / x2 is larger than y2 / x2. Preferably, y1 / x1 is 1.5 times or more larger than y2 / x2. The first oxide layer 404a and the oxide semiconductor layer 404b are formed. , the first oxide layer 404a and the second oxide layer 404b are formed so that y1 / x1 is at least twice as large as y2 / x2. The oxide semiconductor layer 404b is formed. More preferably, y1 / x1 is 3 times smaller than y2 / x2. The first oxide layer 404a and the oxide semiconductor layer 404b are formed so that the thickness of the first oxide layer 404a and the oxide semiconductor layer 404b is at least twice as large as that of the first oxide layer 404a. .

[0077] The oxide semiconductor layer is substantially intrinsic. 0 17 / cm 3 Less than 1 × 10 16 / cm 3 Less than or equal to 1×10 1 5 / cm 3 Less than or equal to 1×10 14 / cm 3 Less than or equal to 1×10 1 3 / cm 3 This means that:

[0078] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen that bonds with metal atoms to form water. In addition, defects are formed in the lattice from which oxygen has been desorbed (or in the portion from which oxygen has been desorbed). In addition, when some of the hydrogen bonds with oxygen, electrons are generated as carriers. Therefore, by drastically reducing impurities including hydrogen in the oxide layer deposition process, Therefore, it is possible to remove as much hydrogen as possible and achieve high By using the purified oxide layer as the channel formation region, the threshold voltage can be reduced The leakage current at the source and drain of the transistor can be suppressed. (Typically, off-state current, etc.) can be reduced to several yA / μm to several zA / μm. As a result, the electrical characteristics of the transistor can be improved.

[0079] The drain current of a transistor using an oxide semiconductor film in an off state is (approximately) 1 x 10 -18 A or less, preferably 1×10 -21 A or less, more preferably 1×10 -24 A or less, or 1 x 10 at 85°C -15 A or less, preferably 1×10 - 18 A or less, more preferably 1 × 10 -21 A or less. Note that the transistor is off. In the case of an n-channel transistor, the gate voltage is sufficiently smaller than the threshold voltage. Specifically, the gate voltage is 1 V or more, preferably 2 V or more, higher than the threshold voltage. If the voltage is greater than or equal to V, more preferably less than 3 V, the transistor is in the off state.

[0080] When forming an oxide semiconductor film, a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas In the case of a mixed gas atmosphere of rare gas and oxygen, In this case, it is preferable to increase the gas ratio of oxygen to rare gas. The target to be used may be appropriately selected depending on the composition of the oxide semiconductor film to be formed.

[0081] As an example of the target, an In-Ga-Zn oxide target will be described below.

[0082] InO X powder, GaO Y Powder and ZnOZ The powders are mixed in a predetermined molar ratio and pressurized. By heat treatment at a temperature between 1000℃ and 1500℃, polycrystalline In-Ga -Zn oxide target. Note that X, Y and Z are arbitrary positive numbers. The mole ratio of InO X powder, GaO Y Powder and ZnO Z Powder is 2:2:1 , 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. The type of powder and the molar ratio of the powder to be mixed can be changed depending on the target to be produced. good.

[0083] Note that the first oxide layer 404a, the oxide semiconductor layer 404b, and the second oxide layer 404c are bonded together. Oxides of different crystallinity may be used. That is, a single crystal oxide film, a polycrystalline oxide film, an amorphous oxide film, etc. The film may be a film obtained by appropriately combining oxide films and the like.

[0084] The structure of the oxide semiconductor film will be described below.

[0085] Oxide semiconductor films are roughly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. Physical semiconductor film, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor film, etc.

[0086] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not contain a crystalline component. The film is a compound semiconductor film. It does not have any crystalline parts even in the microscopic areas, and the entire film has a completely amorphous structure. A typical example is an oxide semiconductor film.

[0087] The microcrystalline oxide semiconductor film is made up of, for example, microcrystals (nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor film has a lower atomic number than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film has a higher order of molecular arrangement than the amorphous oxide semiconductor film. The defect level density is also low.

[0088] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is so large that it fits inside a cube with a side length of less than 100 nm. The crystals contained in the S film are cubic with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller defect density than the microcrystalline oxide semiconductor film. The CAAC-OS film has a low density of recessed states. .

[0089] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a crystalline microscope, clear boundaries between the crystals, i.e., crystal boundaries, are clearly visible. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0090] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) It can be confirmed that the metal atoms are arranged in layers in the crystalline part. Each layer has a surface on which the CAAC-OS film is formed (also referred to as a surface on which the CAAC-OS film is formed) or an uneven surface on which the CAAC-OS film is formed. The shape reflects this and is aligned parallel to the surface on which the CAAC-OS film is formed or the top surface.

[0091] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (planar TEM). When observed, it was found that the metal atoms were arranged in triangular or hexagonal shapes in the crystals. However, there is no regularity in the arrangement of metal atoms between different crystal parts. stomach.

[0092] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It turns out that there are.

[0093] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was found by structural analysis using the device. In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0094] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0095] From the above, it is concluded that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. Although it is regular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0096] The crystalline part is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed or the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0097] The crystallinity of the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The area near the surface may have a higher degree of crystallinity than the area near the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region where the impurities are added changes, resulting in partial In some cases, regions of different crystallinity may be formed.

[0098] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferable that the peak is exhibited at 2θ of around 36° and that the peak is not exhibited at 2θ of around 36°.

[0099] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0100] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CA The AC-OS film may be a laminated film having two or more kinds of films.

[0101] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0102] By increasing the substrate heating temperature during film formation, the migration of sputtered particles after reaching the substrate is reduced. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably 20 The film is formed at a temperature between 0°C and 500°C. By increasing the substrate heating temperature during film formation, a flat plate-shaped When sputtering particles reach the substrate, migration occurs on the substrate, and the sputtering The flat surface of the sputtering particle adheres to the substrate. At this time, the sputtering particle becomes positively charged. By doing so, the sputtering particles repel each other while adhering to the substrate, To form a CAAC-OS film with uniform thickness without uneven particle overlap. can be done.

[0103] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be reduced. In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas having a temperature of 80° C. or less, preferably −100° C. or less, is used.

[0104] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition can be reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0105] After the CAAC-OS film is formed, heat treatment may be performed. The temperature is set to 740°C or higher, preferably 200°C or higher and 500°C or lower. The heating time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be carried out in an active atmosphere or an oxidizing atmosphere. Preferably, the heat treatment is carried out in an inert atmosphere. After that, heat treatment is performed in an oxidizing atmosphere. The impurity concentration of the OS film can be reduced in a short time. In this case, oxygen vacancies may be generated in the CAAC-OS film in an oxidizing atmosphere. The heat treatment can reduce the oxygen vacancies. The crystallinity of the CAAC-OS film can be further improved. The reaction may be carried out under reduced pressure of 100 Pa or less, 10 Pa or less, or 1 Pa or less. In this case, the impurity concentration of the CAAC-OS film can be reduced in an even shorter time.

[0106] Alternatively, the CAAC-OS film may be formed by the following method.

[0107] First, a first oxide semiconductor film is formed to a thickness of 1 nm or more and less than 10 nm. The semiconductor film is formed by sputtering. Specifically, the substrate temperature is set to 100°C or higher for 5 00℃ or less, preferably 150℃ or more and 450℃ or less, and the oxygen ratio in the deposition gas is 30 The film is formed at a volume percentage of at least 100%, preferably 100%.

[0108] Next, heat treatment is performed to convert the first oxide semiconductor film into a first CAAC-OS film with high crystallinity. The temperature of the heat treatment is 350°C or higher and 740°C or lower, preferably 450°C or higher and 650°C or lower. The heat treatment time is 1 minute to 24 hours, preferably 6 minutes to 4 hours. The heat treatment may be carried out in an inert atmosphere or an oxidizing atmosphere. Or, after heat treatment in an inert atmosphere, heat treatment is performed in an oxidizing atmosphere. By the heat treatment in air, the impurity concentration of the first oxide semiconductor film can be reduced in a short time. On the other hand, oxygen vacancies are generated in the first oxide semiconductor film by heat treatment in an inert atmosphere. In this case, the oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere. Heat treatment can be carried out at a pressure of 1000 Pa or less, 100 Pa or less, 10 Pa or less, or The treatment may be performed under reduced pressure of 1 Pa or less. Under reduced pressure, the impurity concentration of the first oxide semiconductor film can be reduced to It can be reduced in an even shorter time.

[0109] The first oxide semiconductor film has a thickness of 1 nm or more and less than 10 nm. Compared with nanometers or larger, it can be easily crystallized by heat treatment.

[0110] Next, a second oxide semiconductor film having the same composition as the first oxide semiconductor film is formed to a thickness of 10 nm or more and 50 nm or more. The second oxide semiconductor film is deposited to a thickness of 100 nm or less by sputtering. Specifically, the substrate temperature is set to 100°C or higher and 500°C or lower, preferably 150°C or higher and 450°C or lower. The oxygen ratio in the deposition gas is set to 30% by volume or more, preferably 100% by volume. do.

[0111] Next, heat treatment is performed to form a second oxide semiconductor film by solid-phase growth from the first CAAC-OS film. The heat treatment temperature was 350°C. The temperature is set to 450°C or higher and 740°C or lower, preferably 450°C or higher and 650°C or lower. The heating time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be carried out in an active atmosphere or an oxidizing atmosphere. Preferably, the heat treatment is carried out in an inert atmosphere. After that, heat treatment is performed in an oxidizing atmosphere. The impurity concentration of the semiconductor film can be reduced in a short time. Oxygen vacancies may be generated in the second oxide semiconductor film by the treatment. The oxygen deficiency can be reduced by heat treatment in a 10 atmosphere. The pressure may be reduced to 00 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration of the second oxide semiconductor film can be reduced in a shorter time. do.

[0112] In this manner, a CAAC-OS film having a total thickness of 10 nm or more can be formed. can.

[0113] Note that the oxide semiconductor layer 404b serving as a channel contains silicon, which is one of the Group 14 elements. If the oxide semiconductor layer 404b is covered with the oxide semiconductor layer 404b, the crystallinity of the oxide semiconductor layer 404b is reduced, which makes it difficult to form a CAAC-OS film. Therefore, problems such as a decrease in carrier mobility and the like occur. The concentration of silicon contained in the oxide semiconductor layer 404b is preferably reduced. The concentration of silicon in 21 atoms / cm 3 Below, preferably 4 .0×10 19 atoms / cm 3 The crystallinity of the oxide semiconductor layer 404b can be improved by the following: The decrease in silicon concentration can be suppressed. 21 atoms / cm 3 By setting the following, it is possible to suppress the decrease in carrier mobility. The concentration of 2.0 x 10 19 atoms / cm 3 The oxide semiconductor layer 404 The oxygen vacancies contained in b can be reduced, and the reliability can be improved.

[0114] The oxide semiconductor layer 404b is formed by etching so that impurities such as silicon do not enter the oxide semiconductor layer 404b. The first oxide layer 404a and the second oxide layer 404c in contact with the first oxide layer 404b are mainly composed of silicon dioxide. The first oxide layer 404a and the second oxide layer 40 4c is a film formed by removing impurity elements such as silicon from the base insulating layer 402 and the gate insulating layer 408. It functions as a protective film to prevent the metal from penetrating into the semiconductor layer 404b.

[0115] Impurities such as silicon are introduced into the first oxide layer 404a and the second oxide layer 404c. The interface between the base insulating layer 402 and the first oxide layer 404a and / or the gate insulating layer 408 At the interface between the first oxide layer 404c and the second oxide layer 404b, a region of silicon contamination may form. The silicon-mixed region does not affect the oxide semiconductor layer 404b, and the oxide semiconductor layer 4 The first oxide layer 404a and the second oxide layer 404b are formed in a thin film to prevent silicon from entering the first oxide layer 404a and the second oxide layer 404b. It is preferable that O4c be made thick enough.

[0116] In the region where silicon is mixed, the oxygen in the oxide layer bonds with the silicon, causing oxidation. The crystallinity of the oxide semiconductor layer is reduced, and oxygen vacancies are easily formed. The oxygen vacancies contained in the silicon diffuse into the silicon-mixed region and are captured in the silicon-mixed region. This is shown in Figure 20. The shaded area is the area where silicon is mixed into the oxide layer, and Vo is the oxygen vacancy. Here, the diffusion of oxygen vacancies means that oxygen atoms near the oxygen vacancies compensate for the oxygen vacancies. The oxygen atoms that were filled in create new oxygen vacancies in the original locations, This refers to the defect appearing to move.

[0117] The oxygen vacancies trapped in the silicon-contaminated region are formed in the underlying insulating layer 402 and the gate insulating layer 408. Therefore, the first oxide layer 404a and the second oxide layer This does not mean that the oxygen vacancies in 404c increase.

[0118] In this way, oxygen vacancies in the oxide semiconductor layer 404b are diffused and captured in the silicon-containing region. By this, the insulating layer 404 is formed in a region separated from the base insulating layer 402 and the gate insulating layer 408. Therefore, oxygen vacancies in the oxide semiconductor layer 404b can be reduced.

[0119] In this embodiment, the substrate temperature is set to room temperature, and the atomic ratio of In:Ga:Zn=1:3:2 is used. The first oxide layer 404a having an amorphous structure is formed using a target. The thickness of the first oxide layer 404a is 1 nm or more and 50 nm or less, preferably 20 nm or more. When the first oxide layer 404a is made thick, the formation of the base insulating layer 402 is prevented. For example, the insulating layer 4 When O2 is silicon oxide, silicon is introduced into the oxide semiconductor layer 404b. It can be prevented.

[0120] The oxide semiconductor layer 404b was formed at a substrate temperature of 400° C. and an In:Ga:Zn The oxide semiconductor layer 404b is formed by a target having an atomic ratio of 1:1:1. The film contains crystals whose c-axes are oriented in the perpendicular direction, and is preferably a CAAC-OS film. The thickness of the oxide semiconductor layer 404b is 1 nm to 40 nm, preferably 5 nm to 20 nm. The deposition temperature of the oxide semiconductor layer 404b is preferably higher than or equal to 400° C. and lower than or equal to 550° C. The temperature is preferably 450°C or higher and 500°C or lower. However, if the wiring layer already formed cannot withstand this temperature, The test shall be carried out within the temperature range specified.

[0121] The heat treatment after the oxide layer formation is carried out in a nitrogen, oxygen, or nitrogen and oxygen atmosphere under reduced pressure. 50°C or higher and lower than the strain point of the substrate, preferably 250°C or higher and 450°C or lower, more preferably The temperature is between 300℃ and 450℃. The heat treatment removes excess hydrogen (water and The heating temperature after the heat treatment is While maintaining or slowly cooling from the heating temperature, high-purity oxygen gas or ultra-dry Air (measured using a CRDS (cavity ring-down laser spectroscopy) dew point meter) The moisture content when the temperature is low is 20 ppm (-55°C in terms of dew point), preferably 1 ppm or less, The oxygen gas acts to dehydrate or The oxides that are reduced during the dehydrogenation process are It supplies oxygen, the main constituent element.

[0122] After the oxide semiconductor layer 404b is formed, heat treatment is performed to form the oxide semiconductor layer 404b. In this case, the hydrogen concentration is 5×10 18 atoms / cm 3 Less than 1 x 10 18 a toms / cm 3 Less than or equal to 5 × 10 17 atoms / cm 3 Below are some more good ones: Preferably 1 x 10 16 atoms / cm 3 It can be as follows:

[0123] Heat treatment is carried out using rare gases such as helium, neon, argon, xenon, krypton, or nitrogen. The heating is carried out in an inert gas atmosphere containing oxygen. Alternatively, the heating is carried out in an inert gas atmosphere, followed by heating in an oxygen atmosphere. It should be noted that the inert atmosphere and oxygen atmosphere do not contain hydrogen, water, etc. The treatment time is preferably 3 minutes to 24 hours. Well, the timing doesn't matter.

[0124] Next, a source electrode layer 406a and a drain electrode layer 406b were formed over the oxide semiconductor layer 404b. The conductive film is formed by plasma CVD or sputtering. Molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium Formed using metallic materials such as aluminum and scandium, or alloy materials containing these as the main constituent elements. In addition, indium tin oxide, indium oxide containing tungsten oxide, oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Conductive materials such as indium tin oxide, indium zinc oxide, and titanium dioxide Also, a laminated structure of the conductive material and the metal material can be applied. It is also possible.

[0125] After the conductive film is formed, the source electrode layer 406a and the drain electrode layer 406b are formed by etching. The source electrode layer 406a can be formed on the gate electrode 406b (see FIG. 2B). During etching for forming the source electrode layer 406a and the drain electrode layer 406b, At the same time, the oxide semiconductor layer 404b in a region sandwiched between the drain electrode layers 406b is also etched. Therefore, the thickness of the source electrode layer of the oxide semiconductor layer 404b may be reduced. The region that does not overlap with the drain electrode layer may have a smaller film thickness than the overlapping region. .

[0126] Subsequently, a second oxide layer 404c is formed over the source electrode layer 406a and the drain electrode layer 406b. and a gate insulating film 407 which will be a gate insulating layer 408. (See Figure 2(C)).

[0127] The oxide film 405 is formed using a material and a method similar to those of the first oxide layer 404a. However, the thickness of the oxide film 405 is thinner than that of the first oxide layer 404a. The oxide film 405 may be thicker than the oxide semiconductor layer 404b. Since the oxide semiconductor layer 404b overlaps with the oxide semiconductor layer 404b, the crystals of the oxide semiconductor layer 404b are used as seeds. Therefore, the first oxide layer 404a is likely to grow as a crystal and become a film having a crystalline structure. Even if the second oxide layer 404 is formed using the same material and method, the crystal structure is different. However, the second oxide layer 404c may have a high crystallinity. The crystallinity of the second oxide layer 404c is lower than that of the oxide semiconductor layer 404b. The crystallinity may be different between a region in contact with the oxide semiconductor layer 404b and a region not in contact with the oxide semiconductor layer 404b. do.

[0128] The interface between the oxide semiconductor layer 404b and the second oxide layer 404c may be mixed. The interface is mixed, and the interface between the oxide semiconductor layer 404b and the second oxide layer 404c Scattering is reduced.

[0129] Also, a part of the second oxide layer 404c, that is, the source electrode layer 406a and the drain electrode A region in contact with the oxide semiconductor layer 406b but not in contact with the oxide semiconductor layer 404b is likely to have an amorphous structure. The thickness of the second oxide layer 404c is 1 nm or more and 40 nm or less, preferably 5 nm or less. The thickness of the second oxide layer 404c is set to be greater than or equal to 100 nm and less than or equal to 30 nm. In particular, the components of the oxide semiconductor layer 404b can be prevented from entering the oxide semiconductor layer 404b. When silicon oxide is used for the gate insulating layer, silicon is introduced into the oxide semiconductor layer 404b. The second oxide layer 404c can prevent the source electrode layer 406a and the The oxide semiconductor layer 404b and the drain electrode layer 406b are provided on the drain electrode layer 406b. The second oxide layer is formed without increasing the resistance between the source electrode layer 406a and the drain electrode layer 406b. The layer 404c can be made thicker.

[0130] The gate insulating layer 408 can be formed using a material and a method similar to those of the base insulating layer 402. Cut.

[0131] Next, a gate electrode layer 410 is formed on the gate insulating film 407 (see FIG. 2(D)). The source electrode layer 406a and the drain electrode layer 406b are made of the same material and The method can be used to form the

[0132] The gate electrode layer 410 overlaps with the source electrode layer 406a and the drain electrode layer 406b. By adopting such a structure, the high electric field near the drain electrode layer 406b is alleviated. As a result, the on-state characteristics of the transistor 420 can be improved.

[0133] Subsequently, the oxide film 405 and the gate insulating film 407 are selectively etched using a mask. The second oxide layer 404c and the gate insulating layer 408 are formed (see FIG. 3A).

[0134] The second oxide layer 404c and the edge of the gate insulating layer 408 are connected to the source electrode layer 406a and the drain electrode layer 406b. The second insulating layer 412 overlaps with the oxide electrode layer 406b, and its side surface is in contact with the oxide insulating layer 412 to be formed later. The oxide layer 404c and a portion of the gate insulating layer 408 are etched and removed. As a result, oxygen released from the oxide insulating layer 412 is transported to the second oxide layer 404c and the gate insulating layer 412. The oxide semiconductor layer 404b can be supplied through the layer 408 or both.

[0135] The etching of the second oxide layer 404c and the gate insulating layer 408 is performed after the etching of the gate electrode layer 4 The etching may be performed before forming the first oxide film 10. The mask used for etching the oxide semiconductor layer 404a and the oxide semiconductor layer 404b was reused. By reusing the mask, the number of masks can be reduced.

[0136] Subsequently, an oxide insulating layer 412 is formed over the gate electrode layer 410. The oxide insulating layer 412 The oxide insulating layer 4 can be formed using a material and a method similar to those of the base insulating layer 402. Examples of the film 12 include a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, and an aluminum oxynitride film. An oxide insulating layer such as an aluminum film, a hafnium oxide film, or a gallium oxide film, or a nitrogen The oxide insulating layer 412 is preferably an oxide insulating layer containing It is preferable to form the film so as to contain excess oxygen so that oxygen can be supplied to the substrate.

[0137] In addition, as a film capable of supplying oxygen, a plasma CVD apparatus is used, similar to the base insulating layer 402. Under vacuum conditions, film formation is performed using high-frequency power with high power density, and excess oxygen is removed. It is preferable that the film contains the oxygen and easily releases oxygen.

[0138] The oxide insulating layer 412 may be formed by an ion implantation method, an ion doping method, a plasma immersion method, or the like. Oxygen may be added by using an ion implantation method or the like. The oxide insulating layer 412 contains excess oxygen, and the oxide insulating layer 412 is then heated to a temperature of 1000. Oxygen can be supplied to the conductor layer 404b.

[0139] After the oxide insulating layer 412 is formed, heat treatment is performed. The acid formed by etching or exposure to plasma after the formation of the dielectric layer 404b is damaged. Therefore, heat treatment is performed to supply oxygen to the oxide semiconductor layer 404b. By reducing oxygen vacancies, damage caused after the formation of the oxide semiconductor layer 404b can be reduced. The temperature of the heat treatment is typically 200°C or higher and 450°C or lower. By the heat treatment, oxygen contained in the oxide insulating layer 412 can be released.

[0140] The heat treatment is performed, for example, in a mixed atmosphere of nitrogen and oxygen at 350° C. for 1 hour. The hydrogen atoms and oxygen atoms contained in the oxide semiconductor layer 404b are converted into In the oxide semiconductor layer 404b, the position from which the oxygen atoms are released is an oxygen vacancy. However, there are more oxygen atoms than the oxygen atoms that satisfy the stoichiometric composition contained in the oxide insulating layer. It moves to the location of the oxygen deficiency and compensates for the oxygen deficiency.

[0141] Thus, by the heat treatment after the formation of the oxide insulating layer 412, the oxide semiconductor layer 404b The nitrogen, hydrogen, or water content in the film is reduced to approximately 1 It can be reduced to about one tenth.

[0142] An insulating layer 414 is formed over the oxide insulating layer 412. The insulating layer 414 is made of silicon nitride, silicon oxide, or the like. Aluminum, aluminum oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide If a film containing hafnium, yttrium oxide nitride, hafnium oxide, hafnium oxide nitride, etc. is used, The insulating layer 414 prevents impurities from the upper part of the semiconductor device from entering the oxide semiconductor layer 404b. or oxygen contained in the oxide semiconductor layer 404b and the oxide insulating layer 412 This can prevent the metal from being desorbed to the upper part of the semiconductor device.

[0143] Through the above steps, a semiconductor device can be manufactured (see FIG. 3B).

[0144] The semiconductor device described in this embodiment has an oxide semiconductor layer serving as a channel, a base insulating layer, and a a first oxide layer and a second oxide layer are formed between the first oxide layer and the gate insulating layer, respectively; Impurity elements such as silicon enter the oxide semiconductor layer from the base insulating layer and the gate insulating layer. This suppresses the intrusion of transistors, reducing the fluctuations in transistor characteristics and resulting in highly reliable semiconductors. The device can be realized.

[0145] The source electrode layer 406a and the drain electrode layer 406b are formed in contact with the oxide semiconductor layer 404b. A second oxide layer 404c is formed on the source electrode layer 406a and the drain electrode layer 406b. By forming the oxide semiconductor layer 404b, the source electrode layer 406a, and the drain electrode layer 406b, The first oxide layer and the second oxide layer are formed without reducing the contact resistance with the electrode layer 406b. By increasing the thickness of the first oxide layer and the second oxide layer, Impurities can be prevented from entering the oxide semiconductor layer, and the characteristics of the transistor can be stabilized. It can be determined as follows.

[0146] Furthermore, the oxide film 405 and the gate insulating film 407 are selectively etched to form a second oxide layer. 404c and the gate insulating layer 408 are formed, and the oxide insulating layer 412 provided over the gate insulating layer 408 to the oxide semiconductor layer 404b. Oxygen can be supplied to the oxide semiconductor layer 404b to fill oxygen vacancies. By doing so, it is possible to stabilize the transistor characteristics and provide a highly reliable semiconductor device. This can be done.

[0147] Note that the structure of the transistor described in this embodiment is not limited to the above structure. As shown in A), a transistor 430 includes a first oxide layer 404a and an oxide semiconductor layer 404 In the transistor 430, the first oxide layer 404a is In a region where the oxide semiconductor layer 404b is not provided, the source electrode layer 406a and the drain electrode layer 406b are By adopting such a configuration, the source electrode layer 4 The first oxide layer 406a and the drain electrode layer 406b are formed without deteriorating the step coverage of the first oxide layer 406a and the drain electrode layer 406b. The oxide semiconductor layer 404a can be thickened, and the impurity element can be prevented from entering the oxide semiconductor layer 404b. This can suppress congestion.

[0148] 4B, the source electrode layer 406a and the drain electrode layer 406b are The peripheral portion of the gate electrode layer 406b overlapping with the gate electrode layer 410 may be formed in a stepped shape. The stepped periphery is formed by multiple etchings (etching with recession (shrinkage) of the resist mask). The resist mask is then removed and etched. The stepped peripheries of the source electrode layer 406a and the drain electrode layer 406b are The step coverage of the oxide layer 404c can be improved.

[0149] In addition, as in a transistor 450 shown in FIG. 4C, The transistor 450 shown in FIG. The first source electrode layer 416a and the first drain electrode layer 416b determine the length of the line. The source electrode layer 416a and the first drain electrode layer 416b are formed over the source electrode layer 416a and the first drain electrode layer 416b. The second source electrode layer 418a and the second drain electrode layer 418b are formed on the second gate electrode 418c to reduce the resistance of the entire source electrode layer 418a and the drain electrode layer 418b. and a drain electrode layer 418b.

[0150] The transistor 45 is formed between the first source electrode layer 416a and the first drain electrode layer 416b. The channel length of the transistor 450 is set to less than 50 nm, preferably 3 When the thickness is less than 0 nm, a mask is used in which the resist is exposed to an electron beam and developed. It is preferable to use the above as an etching mask. At this time, it is possible to irradiate with an electron beam. In such an electron beam writing apparatus, it is preferable to irradiate the electron beam with a minimum beam diameter of 2 nm or less. stomach.

[0151] However, the mask that can be formed by the electron beam is thin, so the resist that becomes the mask In consideration of the coverage of the first source electrode layer 416a and the first drain electrode layer 416 However, it is preferable to thin the first source electrode layer 416a and the first drain electrode layer 416b. If the thickness of the electrode layer 416b is reduced, the resistance increases. A second source electrode layer 418a and a second drain electrode layer 418b that can be formed into a film are formed. It is preferable.

[0152] 5, a source electrode layer 406a and a drain electrode layer 406b are formed on and in contact with the first oxide layer 404a. The drain electrode layer 406b is formed on the source electrode layer 406a and the drain electrode layer 406b. The oxide semiconductor layer 404b may be formed in contact with the oxide semiconductor layer 404b. A second oxide layer 404c and a gate insulating layer 408 are stacked on the gate insulating layer 404c.

[0153] The transistor 460 shown in FIG. 5A has a source electrode 404a in contact with the first oxide layer 404a. The source electrode layer 406a and the drain electrode layer 406b are provided. The oxide semiconductor layer 404b on the drain electrode layer 406b, the second oxide layer 404c, and the gate The insulating layer 408 is etched using the same mask. 4b, the second oxide layer 404c is formed on the surface of the oxide film 404. The surface of the compound semiconductor layer 404b is not damaged by etching, and stable The semiconductor device can have the following characteristics.

[0154] The transistor 470 illustrated in FIG. 5B has the same structure as the transistor 440 illustrated in FIG. The source electrode layer 406a and the drain electrode layer 406b have stepped edges. By forming the oxide semiconductor layer 404b, the second oxide layer 404c, and the gate insulating film 404a into such a shape, The coverage of the gate insulating layer 408 is improved.

[0155] The transistor described in this embodiment can be applied in appropriate combination with other embodiments. can.

[0156] (Embodiment 2) In this embodiment, a semiconductor device different from that in the first embodiment will be described. The same parts as those in the first embodiment are denoted by the same reference numerals, and detailed explanations thereof will be omitted. 6(B) shows a top view of the semiconductor device of this embodiment mode. FIG. 6A is a cross-sectional view taken along the dashed line CD shown in FIG. 6B.

[0157] 6A includes a base insulating layer 402 over a substrate 400 and a The first oxide layer 404a and the oxide semiconductor layer 404b on the insulating layer 402, The source electrode layer 406a and the drain electrode layer 406b are formed on the oxide semiconductor layer 404a and the oxide semiconductor layer 404b. 406b, and the second oxide layer 40 on the source electrode layer 406a and the drain electrode layer 406b. 4c, a gate insulating layer 408 on the second oxide layer 404c, and a gate insulating layer 408 on the gate insulating layer 408. The gate electrode layer 410, the source electrode layer 406a, the drain electrode layer 406b, and the second oxide layer 404c, an oxide insulating layer 412 on the gate insulating layer 408 and the gate electrode layer 410; and an insulating layer 414 on the insulating layer 412.

[0158] The upper end of the second oxide layer 404c coincides with the lower end of the gate insulating layer 408. The upper end of 408 coincides with the lower end of the gate electrode layer 410. The gate insulating layer 408 and the second oxide layer 404c are etched using the electrode layer 410 as a mask. By using the gate electrode layer 410 as a mask, the number of masks can be reduced. can be reduced.

[0159] The term "match" does not necessarily mean a strict match, but rather a match achieved by etching using the same mask. Therefore, the degree of conformity in the shape obtained by the second oxide layer 404c is included. If the end of the gate insulating layer 408 protrudes or recedes further than the bottom end of the gate insulating layer 408, the gate The upper end of the gate insulating layer 408 protrudes or is located deeper than the lower end of the gate electrode layer 410. Sometimes it's backwards.

[0160] The structure of the transistor described in this embodiment is not limited to this. 4B, the transistor 530 shown in FIG. The source electrode layer 406a and the drain electrode layer 406b are provided with peripheral portions overlapping with the gate electrode layer 410. It may be formed in a stepped shape.

[0161] Like the transistor 540 shown in FIG. 7B, the transistor 450 shown in FIG. Similarly, the source electrode layer and the drain electrode layer may have a two-layer structure.

[0162] 7C, a transistor 550 having a gate electrode layer 410 A sidewall insulating layer 413 may be formed thereon.

[0163] The transistor 550 includes a base insulating layer 402 over a substrate 400 and a first insulating film 404 over the base insulating layer 402. a stack of the first oxide layer 404a and the oxide semiconductor layer 404b, and The source electrode layer 406a and the drain electrode layer 406b are formed over the oxide semiconductor layer 404b. The second oxide layer 404c on the source electrode layer 406a and the drain electrode layer 406b, and the second oxide layer 404b on the drain electrode layer 406a and the drain electrode layer 406b are a gate insulating layer 408 on the oxide layer 404c, and a gate electrode layer 410 on the gate insulating layer 408; The sidewall insulating layer 413 covers the side surface of the gate electrode layer 410, the source electrode layer 406a, the drain electrode layer 406b, and the gate insulating layer 413 cover the side surface of the gate electrode layer 410. the oxide insulating layer 412 on the gate electrode layer 406b, the gate electrode layer 410, and the sidewall insulating layer 413; and an insulating layer 414 over the oxide insulating layer 412.

[0164] The bottom edge of the sidewall insulating layer 413 coincides with the top edge of the gate insulating layer 408, and the gate insulating layer 408 The bottom edge of the second oxide layer 404c is aligned with the top edge of the second oxide layer 404c. 413 and the gate electrode layer 410 as a mask, the gate insulating layer 408 and the second oxide layer It can be formed by etching 404c. Note that the term "matching" here does not require strict matching. It does not include the degree of agreement between the shapes obtained by etching using the same mask. Therefore, the upper end of the second oxide layer 404c is closer to the lower end of the gate insulating layer 408 than the lower end of the gate insulating layer 408. If the gate insulating layer 408 is protruding or recessed, the upper end of the gate insulating layer 408 may be In some cases, it may protrude further than the lower end of 13 or may be set back further.

[0165] The sidewall insulating layer 413 is provided to prevent the source electrode layer 406a and the drain electrode layer 406b from being damaged. The insulating property between the electrode layer 406b and the gate electrode layer 410 can be improved.

[0166] Here, a method for manufacturing the transistor 550 will be described. The parts will be omitted.

[0167] The transistor 550 has the same structure as the transistor described in Embodiment 1 until the gate electrode layer 410 is formed. The transistor 420 can be fabricated using the same method as that of the transistor 420. Therefore, the method for manufacturing the structure shown in FIG. Please refer to the description.

[0168] The transistor shown in FIG. 8A includes a base insulating layer 402 on a substrate 400 and a base insulating layer 40 2, a stack of the first oxide layer 404a and the oxide semiconductor layer 404b, and an oxide semiconductor layer 4 The source electrode layer 406a and the drain electrode layer 406b on the gate electrode layer 404b, and the source electrode layer 406a The oxide film 405 on the drain electrode layer 406b and the gate insulating film 406 on the oxide film 405 407 and a gate electrode layer 410 on the gate insulating film 407.

[0169] An insulating film 411 that will become a sidewall insulating layer 413 is formed on the gate electrode layer 410 (FIG. 8(B) The insulating film 411 can be formed using a method and material similar to those of the oxide insulating layer 412 described in Embodiment 1. Subsequently, the insulating film 411 is anisotropically etched to form a sidewall insulating film. An edge layer 413 is formed (see FIG. 8(C)).

[0170] Next, the sidewall insulating layer 413 and the gate electrode layer 410 are used as a mask to form the oxide film 405 and the gate electrode layer 410. The gate insulating film 407 is selectively etched to remove the second oxide layer 404c and the gate insulating layer 40 8 is formed (see FIG. 9(A)).

[0171] Here, during the etching for forming the second oxide layer 404c and the gate insulating layer 408, In the case where the source electrode layer 406a and the drain electrode layer 406b are also etched, In addition, when the source electrode layer 406a and the drain electrode layer 406b are etched, The metal removed from these layers by etching is then deposited on the second oxide layer 404c and the gate electrode. The second oxide layer 404c and the gate insulating layer 408 may adhere to the side surfaces of the gate insulating layer 408. The gate electrode layer 410 and the source electrode layer 406a are connected to each other through the metal attached to the side of the layer 408. Alternatively, the drain electrode layer 406b may become conductive.

[0172] Therefore, by providing the sidewall insulating layer 413, the source electrode layer 406a and the drain electrode layer 406b are The electrode layer 406b is etched to expose the second oxide layer 404c and the gate insulating layer 408. Even if metal is attached to the side, the gate electrode layer 410, the source electrode layer 406a, and the drain electrode layer 406b are Conduction of the electrode layer 406b can be suppressed.

[0173] Subsequently, the source electrode layer 406a, the drain electrode layer 406b, the second oxide layer 404c, and the gate electrode layer 406b are formed. An oxide insulating layer 412 and an oxide insulating layer 413 are formed on the gate insulating layer 408, the gate electrode layer 410, and the sidewall insulating layer 413. The oxide insulating layer 412 and the insulating layer 414 are stacked (see FIG. 9B). The element 414 can be formed using the same method and material as in the first embodiment.

[0174] The transistors described in this embodiment are not limited to those described above. As shown in FIG. 1, the source electrode layer 406a and the drain electrode layer 406b are formed on and in contact with the first oxide layer 404a. 6b is formed on and in contact with the source electrode layer 406a and the drain electrode layer 406b. A second oxide semiconductor layer 404b may be formed on the oxide semiconductor layer 404b. A layer 404c and a gate insulating layer 408 are stacked.

[0175] The transistor 560 in FIG. 10A has the same structure as the transistor 460 in FIG. The first oxide layer 404a is not etched, and the source electrode layer 406a and the drain electrode layer 406b are left unetched. The oxide semiconductor layer 404b extends below the electrode layer 406b, and the second oxide layer 404c The gate insulating layer 408 is etched using the gate electrode layer 410 as a mask.

[0176] The transistor 570 shown in FIG. 10B has the same structure as the transistor 470 shown in FIG. The source electrode layer 406a and the drain electrode layer 406b overlap with the gate electrode layer 410. The peripheral portion is formed in a stepped shape, and the oxide semiconductor layer 404b, the second oxide layer 404c, and The gate insulating layer 408 is etched using the gate electrode layer 410 as a mask.

[0177] The semiconductor device described in this embodiment has an oxide semiconductor layer serving as a channel, a base insulating layer, and a a first oxide layer and a second oxide layer are formed between the first oxide layer and the gate insulating layer, respectively; Impurity elements such as silicon enter the oxide semiconductor layer from the base insulating layer and the gate insulating layer. Therefore, the transistor characteristics are prevented from fluctuating.

[0178] The source electrode layer 406a and the drain electrode layer 406b are formed in contact with the oxide semiconductor layer 404b. A second oxide layer 404c is formed on the source electrode layer 406a and the drain electrode layer 406b. By forming the oxide semiconductor layer 404b, the source electrode layer 406a, and the drain electrode layer 406b, The first oxide layer and the second oxide layer are formed without reducing the contact resistance with the electrode layer 406b. By increasing the thickness of the first oxide layer and the second oxide layer, Impurities can be prevented from entering the oxide semiconductor layer, and the characteristics of the transistor can be stabilized. It can be determined as follows.

[0179] Furthermore, the second oxide layer 404c and the gate insulating layer 408 are selectively etched and removed. By this, the second oxide layer 404c and the gate insulating layer 408 are provided on the In addition, oxygen can be supplied from the oxide insulating layer 412 to the oxide semiconductor layer 404b.

[0180] During etching of the second oxide layer 404c and the gate insulating layer 408, the gate electrode layer 4 By using the insulating layer 10 and the sidewall insulating layer 413 as a mask, the number of masks can be reduced. This can be done.

[0181] Furthermore, the sidewall insulating layer 413 is formed in contact with the side surface of the gate electrode layer 410. Thus, the source electrode layer 406a and the drain electrode layer 406b are electrically connected to the gate electrode layer 410. This can suppress the occurrence of defects and improve the reliability of the transistor.

[0182] The transistor described in this embodiment can be applied in appropriate combination with other embodiments. can.

[0183] (Embodiment 3) As an example of a semiconductor device, a circuit diagram of a NOR type circuit, which is a logic circuit, is shown in FIG. FIG. 11(B) is a circuit diagram of a NAND type circuit.

[0184] In the NOR circuit shown in FIG. 11(A), the transistor is a p-channel transistor. The transistors 801 and 802 are transistors using a single crystal silicon substrate in the channel formation region. The transistors 803 and 804 are n-channel transistors. a transistor having a structure similar to that of the transistor described in Embodiment 2, in which an oxide semiconductor film is formed in a channel formation region; A transistor using

[0185] In the NOR circuit shown in FIG. 11A, the transistors 803 and 804 are The gate electrode layer is placed over the semiconductor film, which controls the electrical characteristics of the transistor. A conductive layer may be provided. The potential of the conductive layer may be controlled to, for example, GND, thereby The threshold voltage of the transistors 803 and 804 is set to a more positive value, and the normally-off transistor It can be used as a data.

[0186] In the NAND circuit shown in FIG. 11B, the transistors are n-channel transistors. The transistors 812 and 813 have the same structure as the transistors described in Embodiments 1 and 2. A transistor having a structure in which an oxide semiconductor film is used for a channel formation region is used.

[0187] In the NAND circuit shown in FIG. 11B, the transistors 812 and 813 are The gate electrode layer is placed over the gate electrode layer through the nitride semiconductor film to control the electrical characteristics of the transistor. A conductive layer may be provided to control the potential of the conductive layer, for example, to GND. The threshold voltage of transistors 812 and 813 is set to a more positive value, and the normally-off transistor It can be a star.

[0188] In the semiconductor device described in this embodiment, an oxide semiconductor is used in the channel formation region. By using transistors with extremely small capacitance, power consumption can be significantly reduced. .

[0189] In addition, by using the transistors described in Embodiments 1 and 2, high-speed operation is possible. We provide NOR and NAND circuits that are highly reliable and exhibit stable characteristics. It is possible.

[0190] The semiconductor device of this embodiment mode may be used in appropriate combination with any of the semiconductor devices described in other embodiments. It is possible.

[0191] (Fourth embodiment) In this embodiment, the transistors described in Embodiments 1 and 2 are used, and It is a semiconductor that can retain its memory contents even when power is not supplied and has no limit on the number of times it can be written. An example of the physical device (memory device) will be described with reference to the drawings.

[0192] FIG. 12A is a circuit diagram showing the semiconductor device of this embodiment.

[0193] The transistor 260 shown in FIG. 12A has a channel formed in silicon and is capable of high-speed operation. In addition, the transistor 262 may be the same as the transistor shown in the first and second embodiments. A transistor can be applied, and its characteristics allow it to retain charge for a long period of time.

[0194] It should be noted that the above transistors are all n-channel transistors. However, the transistor used in the semiconductor device described in this embodiment is a p-channel transistor. A transistor can also be used.

[0195] In FIG. 12A, the first wiring (1st Line) and the source of the transistor 260 The electrode layer is electrically connected to the second wiring (2nd Line) and the transistor 260. The drain electrode layer is electrically connected to the third wiring (3rd Line ) is electrically connected to one of the source electrode layer and the drain electrode layer of the transistor 262. The fourth line and the gate electrode layer of the transistor 262 are electrically connected to each other. The gate electrode layer of transistor 260 and the gate electrode layer of transistor 2 The other of the source electrode layer and the drain electrode layer of the capacitor 264 is electrically connected to one of the electrodes of the capacitor 264. The fifth wiring (5th Line) and the other electrode of the capacitor element 264 are electrically connected. are actively connected.

[0196] In the semiconductor device illustrated in FIG. 12A, the potential of the gate electrode layer of the transistor 260 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0197] The writing and retention of data will be described. First, the potential of the fourth wiring is applied to the transistor 2. 62 is set to a potential at which the transistor 262 is turned on, thereby turning on the transistor 262. The potential of the third wiring is applied to the gate electrode layer of the transistor 260 and the capacitor 264. That is, a predetermined charge is applied to the gate electrode layer of the transistor 260 (write Here, charges that give two different potential levels (hereinafter, low-level charges, H Then, the voltage of the fourth wiring is The potential is set to a potential at which the transistor 262 is turned off, and the transistor 262 is turned off. By doing so, the charge given to the gate electrode layer of the transistor 260 is held ( retention).

[0198] Since the off-state current of the transistor 262 is extremely small, the gate electrode layer of the transistor 260 The charge is retained for a long time.

[0199] Next, we will explain how to read information. When a predetermined potential (constant potential) is applied to the first wiring, Then, when an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 260 The second wiring has a different potential depending on the amount of charge held in the electrode layer. If the transistor 260 is an n-channel type, a high level is applied to the gate electrode layer of the transistor 260. The apparent threshold voltage V for a given charge th_H is the gate of transistor 260. The apparent threshold voltage V when a low-level charge is applied to the gate electrode layer th_L twist Here, the apparent threshold voltage is the voltage at which the transistor 260 is turned on. This refers to the potential of the fifth wiring required to achieve the "state." The potential of V th_H and V th_LBy setting the potential V0 between For example, in writing, the charge given to the gate electrode layer can be determined. If a Bell charge is applied, the potential of the fifth wire is V0 (>V th_H ) then When a low level charge is applied, transistor 260 is in the "on state." The potential of the fifth wire is V0( <V th_L ), transistor 260 remains "off" Therefore, by observing the potential of the second wiring, the stored information It can be read out.

[0200] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode layer The potential at which transistor 260 is in the "off state" regardless of V th_H Alternatively, a lower potential may be applied to the fifth wiring regardless of the state of the gate electrode layer. The potential at which transistor 260 is "on," i.e., V th_L Larger power Just give the position to the fifth wire.

[0201] FIG. 12B shows an example of a structure of a different memory device. 12(C) is a conceptual diagram showing an example of a semiconductor device. The semiconductor device shown in FIG. 12(B) will be described first, followed by the semiconductor device shown in FIG. 12(C). The location will be explained below.

[0202] In the semiconductor device shown in FIG. 12B, the bit line BL and the source voltage of the transistor 262 The word line WL and the transistor 262 are electrically connected to one of the electrode and drain electrode. The gate electrode layer of the transistor 262 is electrically connected to the source electrode or drain electrode of the transistor 262. The other electrode and a first terminal of the capacitor 254 are electrically connected to each other.

[0203] The transistor 262 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 262 is turned off, the first The potential of the terminal (or the charge stored in the capacitance element 254) is kept constant for an extremely long time. It is possible to retain it.

[0204] Next, data is written and stored in the semiconductor device (memory cell 250) shown in FIG. This section explains how to do this.

[0205] First, the potential of the word line WL is set to a potential at which the transistor 262 is turned on. The transistor 262 is turned on. As a result, the potential of the bit line BL is changed to the potential of the capacitor 254. The potential of the word line WL is then applied to the first terminal (write). By setting the potential at which the transistor 262 is turned off, the capacitance The potential of the first terminal of the capacitance element 254 is held (held).

[0206] Since the off-state current of the transistor 262 is extremely small, the potential of the first terminal of the capacitor 254 (or the charge stored in the capacitance element) can be held for a long period of time.

[0207] Next, the reading of information will be described. When the transistor 262 is turned on, the floating The bit line BL and the capacitance element 254 are electrically connected to each other. As a result, the potential of the bit line BL changes. The amount of change in potential is determined by the potential of the first terminal of the capacitance element 254 (or the potential stored in the capacitance element 254). It takes on different values ​​depending on the charge.

[0208] For example, the potential of the first terminal of the capacitance element 254 is V, the capacitance of the capacitance element 254 is C, and the bit line The capacitance component of BL (hereinafter also referred to as bit line capacitance) is CB, and the capacitance before charge redistribution is If the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB×VB0+C×V) / (CB+C). Therefore, the state of memory cell 250 is Therefore, if the potential of the first terminal of the capacitance element 254 takes two states, V1 and V0 (V1>V0), Then, the potential of the bit line BL when the potential V1 is maintained is (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the bit line BL when the potential V0 is maintained (=(CB× VB0+C×V0) / (CB+C)).

[0209] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0210] As described above, in the semiconductor device illustrated in FIG. 12B, the off-state current of the transistor 262 is extremely low. Because of its small size, the charge stored in the capacitance element 254 can be maintained for a long time. In other words, refresh operations become unnecessary or the frequency of refresh operations can be reduced. This allows the power consumption to be reduced significantly. In addition, even if there is no power supply, the memory contents can be retained for a long period of time. be.

[0211] Next, the semiconductor device shown in FIG. 12C will be described.

[0212] The semiconductor device shown in FIG. 12C has a memory cell shown in FIG. 12B as a memory circuit thereon. The memory cell array 251a and the memory cell array 251b each have a plurality of memory cells 250. At the bottom, the memory cell array 251 (memory cell array 251a and memory cell array 25 1b) has a peripheral circuit 253 necessary for operating the memory. The memory cell array 251 is electrically connected to the memory cell array 251 .

[0213] By using the configuration shown in FIG. 12C, the peripheral circuit 253 is connected to the memory cell array 251. (memory cell array 251a and memory cell array 251b) Therefore, the semiconductor device can be made smaller.

[0214] The transistors provided in the peripheral circuit 253 are made of a different semiconductor material from the transistor 262. It is more preferable to use silicon, germanium, silicon germanium, Silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor can also be used. Alternatively, organic semiconductor materials may be used. The transistor is capable of sufficiently high speed operation. It is possible to realize various circuits (logic circuits, drive circuits, etc.) that require high-speed operation. be.

[0215] In the semiconductor device shown in FIG. 12C, two memory cell arrays 251 (memory cells In the illustrated example, a stacked memory cell array 251a and a stacked memory cell array 251b are used. The number of memory cell arrays to be stacked is not limited to this. It may also be configured as follows.

[0216] The transistor 262 is preferably a transistor using an oxide semiconductor for a channel formation region. By using this function, it is possible to retain the memory contents for a long period of time. Semiconductor memory that does not require refresh operations or that requires extremely low frequency of refresh operations Since it is possible to use the device as a storage device, power consumption can be reduced sufficiently.

[0217] In addition, as the semiconductor device described in this embodiment, the oxide semiconductor device described in Embodiments 1 and 2 The oxide semiconductor layer that becomes the channel formation region is located on the surface of the oxide semiconductor stack. By applying a transistor that is away from the surface, it is possible to achieve highly reliable and stable electrical characteristics. The semiconductor device can exhibit this property.

[0218] (Embodiment 5) In this embodiment mode, the semiconductor device described in the above embodiment mode is applied to a mobile phone, a smartphone, an An example of application to an electronic device such as a child book will be described with reference to FIGS.

[0219] A block diagram of the electronic device is shown in Fig. 13. The electronic device shown in Fig. 13 includes an RF circuit 901, an analog a digital baseband circuit 902, a digital baseband circuit 903, a battery 904, and a power supply Circuit 905, application processor 906, flash memory 910, display A controller 911, a memory circuit 912, a display 913, a touch sensor 919, It is composed of an audio circuit 917, a keyboard 918, etc. The display 913 is The device is composed of a power supply 914, a source driver 915, and a gate driver 916. The application processor 906 includes a CPU 907, a DSP 908, and an interface (IF Generally, the memory circuit 912 is composed of an SRAM or a DRAM. By adopting the semiconductor device described in the previous embodiment in this portion, High speed writing and reading, long-term memory retention, and low power consumption Therefore, it is possible to provide a highly reliable electronic device.

[0220] FIG. 14 shows a display in which the semiconductor device described in the previous embodiment is used in a memory circuit 950 of the display. The memory circuit 950 shown in FIG. The memory controller 951 is also configured with a switch 954, a switch 955, and a memory controller 951. The memory circuit receives image data (input image data) input from a signal line, and stores the image data in the memory 952 and the and a disk for reading and controlling the data (stored image data) stored in the memory 953. Displayed by signals from the spray controller 956 and the display controller 956 A display 957 is connected to the device.

[0221] First, certain image data is generated by an application processor (not shown). The input image data A is input to the memory 952 via the switch 954. The image data stored in the memory 952 (stored image data A) is then 955 and a display controller 956 to a display 957. , will be displayed.

[0222] If there is no change in the input image data A, the stored image data A usually has a frequency of about 30 to 60 Hz. The display controller 956 reads the data from the memory 952 via the switch 955. It is revealed.

[0223] Next, for example, when the user rewrites the screen (i.e., input image data A If there is a change in the input image data, the application processor The input image data B is stored in the memory 953 via the switch 954. During this time, the stored image data A is periodically read out from the memory 952 via the switch 955. When the new image data (stored image data B) has been stored in the memory 953, From the next frame of the display 957, the stored image data B is read out, and the switch 95 5, and the stored image data is displayed on the display 957 via the display controller 956. Data B is sent and displayed. This reading is followed by the next new image data being sent to memory 9. This will continue until it is stored in 52.

[0224] In this way, the memory 952 and the memory 953 alternately write and receive image data. By reading out the data, the display 957 displays the data. The memory 52 and the memory 953 are not limited to being separate memories, but may be divided into one memory. The semiconductor device described in the above embodiment may be used as the memory 952 and the memory 953. By adopting this technology, it is possible to write and read information at high speed and retain data for a long period of time. Moreover, the power consumption can be reduced sufficiently. A highly reliable semiconductor device that is less susceptible to such influences can be obtained.

[0225] Figure 15 shows a block diagram of an electronic book. , microprocessor 1003, flash memory 1004, audio circuit 1005, keyboard a card 1006, a memory circuit 1007, a touch panel 1008, a display 1009, It is configured by a display controller 1010.

[0226] Here, the semiconductor device described in the previous embodiment is used for the memory circuit 1007 in FIG. The memory circuit 1007 has the function of temporarily storing the contents of a book. For example, when the user uses the highlight function, the memory circuit 1007 stores the highlight information specified by the user. The highlight function is a function that allows users to highlight the text as they read an e-book. When you are using the Marking can be done by drawing lines, making the letters thicker, or changing the font to make the letters stand out from the surroundings. The memory circuit 1007 is used for short-term information storage and long-term information storage. The data stored in the memory circuit 1007 is copied to the flash memory 1004. In such a case, the semiconductor device described in the previous embodiment may be adopted. This allows for high-speed writing and reading of information, long-term storage, and This allows for a sufficient reduction in power consumption. Therefore, a highly reliable semiconductor device that is resistant to such damage can be obtained.

[0227] Specific examples of electronic devices are shown in Fig. 16. Fig. 16(A) and Fig. 16(B) show a foldable tablet. The tablet terminal is in an open state. 9630, display unit 9631a, display unit 9631b, display mode changeover switch 9034 , power switch 9035, power saving mode switch 9036, fastener 9033, operation It has an operating switch 9038.

[0228] The semiconductor device described in the above embodiment can be used for the display portion 9631a and the display portion 9631b. This makes it possible to create a highly reliable tablet terminal. The memory device shown in the embodiment may be applied to the semiconductor device of this embodiment.

[0229] A part of the display unit 9631a can be used as a touch panel area 9632a. By touching the operation keys 9638, data can be input. In 1a, for example, half of the area has a display function only, and the other half The display unit 96 has a touch panel function, but is not limited to this. The entire surface of 31a is displayed as a keyboard button to serve as a touch panel, and the display part 9631b is displayed. It can be used as a screen.

[0230] In addition, in the display unit 9631b, as in the display unit 9631a, a part of the display unit 9631b The area 9632b of the touch panel can be used as the keyboard of the touch panel. By touching the area where the display switch button 9639 is displayed with your finger or a stylus, Keyboard buttons can be displayed on the display portion 9631b.

[0231] In addition, touch panel area 9632a and touch panel area 9632b can be touched simultaneously. You can also input characters using the touchpad.

[0232] The display mode switch 9034 is used to change the display orientation, such as portrait or landscape. You can switch between black and white and color display. The Switch 9036 detects external light during use using a light sensor built into the tablet device. The tablet device can optimize the display brightness according to the amount of light in the room. In addition to sensors, other detection devices such as gyros and acceleration sensors that detect tilt are also included. It may be built-in.

[0233] FIG. 16A shows an example in which the display area of ​​the display portion 9631b is the same as that of the display portion 9631a. However, there is no particular limitation, and one size may be different from the other, and the display For example, one display panel may be capable of displaying images with higher resolution than the other. It may also be possible to use the following.

[0234] FIG. 16(B) shows the tablet terminal in a closed state, and the tablet terminal includes a housing 9630 and a solar cell 96 33, a charge / discharge control circuit 9634, a battery 9635, and a DC / DC converter 9636 16B, a battery 9635 is used as an example of the charge / discharge control circuit 9634. , a configuration having a DC-DC converter 9636 is shown.

[0235] In addition, since the tablet device can be folded in half, the housing 9630 can be folded when not in use. Therefore, the display portions 9631a and 9631b can be protected, and thus the display portions 9631a and 9631b can be withstood. This makes it possible to provide a tablet terminal that is highly durable and reliable even from the perspective of long-term use.

[0236] In addition, the tablet terminals shown in Figs. 16(A) and 16(B) can store various information. Functions that display information (still images, videos, text images, etc.), calendars, dates, or times The function to display the information on the display, and the function to operate or edit the information displayed on the display. It has functions such as inputting characters, controlling processes using various software (programs), etc. It is possible.

[0237] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination. [Example]

[0238] In this example, a transistor having a similar structure to the transistor 530 shown in FIG. 7A was used as an example sample. A transistor was fabricated and its cross-sectional shape was examined.

[0239] First, the method for preparing the example samples will be described.

[0240] First, a silicon oxide film with a thickness of 300 nm was formed on a silicon substrate as an underlying insulating film. The silicon oxide film was formed by sputtering with argon and oxygen (argon: oxygen = 25 s ccm: 25sccm) mixed atmosphere, pressure 0.4Pa, power supply power (power output) The target was heated to 5.0 kW, the distance between the silicon substrate and the target was set to 60 mm, and the substrate temperature was set to 10 The film was formed under the condition of 0°C.

[0241] After polishing the surface of the silicon oxide film, a first oxide film with a thickness of 20 nm and a second oxide film with a thickness of 10 nm are formed. The film formation conditions were as follows: the first oxide film was In:Ga:Zn=1: Argon and oxygen were deposited by sputtering using an oxide target with a 3:2 (atomic ratio). Under a mixed atmosphere of argon and oxygen (argon:oxygen = 30sccm:15sccm), the pressure was 0.4 Pa, power supply power 0.5kW, distance between target and substrate 60mm, substrate temperature The oxide semiconductor film was formed at 200°C with an atomic ratio of In:Ga:Zn=1:1:1. Argon and oxygen (argon:oxygen = 30sccm:15sccm) mixed atmosphere, pressure 0.4Pa, power supply power 0.5 kW was applied, the distance between the target and the substrate was 60 mm, and the substrate temperature was 300°C. Note that the first oxide film and the oxide semiconductor film were successively formed without exposure to the air.

[0242] Next, a heat treatment was carried out. The heat treatment was carried out in a nitrogen atmosphere at 450°C for 1 hour, and then the The heating was carried out at 450°C for 1 hour under atmospheric pressure.

[0243] Next, the first oxide film and the oxide semiconductor film are subjected to inductively coupled plasma (ICP) deposition. Inductively Coupled Plasma (ICP) etching is performed using boron trichloride and Under a mixed atmosphere of chlorine (BCl3:Cl2 = 60sccm:20sccm), power supply power was 450 The first oxide was etched at 1.9 Pa with a bias power of 100 W and a pressure of 1.9 Pa. The resulting layer was processed into an oxide semiconductor layer and an oxide semiconductor layer.

[0244] Subsequently, a source electrode layer and a drain electrode layer are formed on the first oxide layer and the oxide semiconductor layer. The deposition conditions were as follows: a tungsten target was used; The sputtering method was used under an argon (argon 80sccm) atmosphere. 0.8 Pa, power supply power (power output) 1.0 kW was applied, and the silicon substrate and target The film was formed under the conditions of a distance of 60 mm and a substrate temperature of 230°C.

[0245] Next, a resist mask was formed on the tungsten film, and a first etching was performed. The ching was prepared by ICP etching using chlorine, carbon tetrafluoride, and oxygen (Cl2:CF4:O 2 = 45sccm: 55sccm: 55sccm) mixed atmosphere, power supply power 3000W, The bias power was 110 W and the pressure was 0.67 Pa.

[0246] After the first etching, oxygen plasma ashing is performed to shrink the resist mask. The resist mask was shrunk in the same chamber as the first etching, using oxygen (O2 = 100sccm) atmosphere, power supply power 2000W, bias power 0W, pressure 3.0Pa I went there.

[0247] Then, using a reduced resist mask, chlorine, carbon tetrafluoride, and oxygen (Cl2:CF4 :O2 = 45sccm: 55sccm: 55sccm) mixed atmosphere, power supply power 3000 The second etching was performed at 100 W, a bias power of 110 W, and a pressure of 0.67 Pa. The source electrode has a stepped edge due to the reduction of the area and the two etching processes before and after. The layer and the drain electrode layer could be formed.

[0248] Next, a second oxide film having a thickness of 10 nm was formed on the oxide semiconductor layer, the source electrode layer, and the drain electrode layer. The film formation conditions were In:Ga:Zn=1:3:2 (atomic ratio) oxide ternary Argon and oxygen (argon: oxygen = 30 scc) were deposited by sputtering using a get. In a mixed atmosphere of 15 sccm (m), a pressure of 0.4 Pa and a power supply of 0.5 kW were applied. The distance between the target and the substrate was 60 mm, and the substrate temperature was 200°C.

[0249] Subsequently, a silicon oxynitride film serving as a gate insulating film was formed to a thickness of 20 nm by CVD.

[0250] The thickness was determined by sputtering using a tantalum nitride target on a silicon oxynitride film. A 30 nm tantalum nitride film was deposited under a nitrogen (N2 = 50 sccm) atmosphere at a pressure of 0.2 Pa. The power supply was 12 kW, the distance between the target and the substrate was 400 mm, and the substrate temperature was room temperature. A tungsten film with a thickness of 135 nm was then deposited on top of the film in argon (Ar=100 sc The target was placed in a 1000-millimeter (cm) atmosphere, with a pressure of 2.0 Pa and a power supply of 4 kW. The film was formed by laminating at a distance of 60 mm and a substrate temperature of 230°C.

[0251] Next, the stack of the tantalum nitride film and the tungsten film is etched by ICP etching. The etching conditions were chlorine, carbon tetrafluoride, and oxygen (Cl2:CF4:O2 = 45s ccm: 55sccm: 55sccm mixed atmosphere, power supply power 3000W, bias voltage The first etching was carried out at a power of 110 W and a pressure of 0.67 Pa. After the first etching, in a mixed atmosphere of boron trichloride and chlorine (BCl3:Cl2 = 150sccm:50sccm) Below, the second etching was performed at a source power of 1000 W, a bias power of 50 W, and a pressure of 0.67 Pa. Then, a gate electrode layer was formed by etching.

[0252] Next, the second oxide film and the gate electrode layer are removed by ICP etching using the gate electrode layer as a mask. The gate insulating film stack was etched. The etching conditions were a mixture of boron trichloride and chlorine (BCl 3: Cl2 = 60sccm: 20sccm) mixed atmosphere, power supply power 450W, bias The first etching was performed at a power of 100 W and a pressure of 1.9 Pa. In an oxygen (O2 = 80 sccm) atmosphere, the power supply was 300 W, the bias power was 50 W, and the pressure A second etching was performed at 4.0 Pa to form a second oxide layer and a gate insulating layer. .

[0253] Next, a silicon oxynitride film having a thickness of 300 nm is formed on the gate electrode layer by the CVD method. A silicon nitride film having a thickness of 50 nm was formed thereon by the CVD method.

[0254] A cross-sectional STEM photograph of the example sample prepared by the above method is shown in FIG. 17. 17A is an enlarged view of the area surrounded by the dotted line in FIG. 17A. 18(B) shows an enlarged view of the area A enclosed by the dotted line in FIG. 17, and FIG. 18(C) shows an enlarged view of the area B enclosed by the dotted line in FIG. 18A and 18B show the transistor 530 shown in FIG. The same symbols are used.

[0255] As shown in FIG. 18(A), a second oxide layer 404c is formed on the drain electrode layer 406b. The drain electrode layer 406b has a stepped periphery, which allows It was confirmed that the coverage of the oxide layer 404c was improved and that no defects in shape such as cuts occurred. was done.

[0256] As shown in FIG. 18(B), the first gate electrode layer 410 is etched using the gate electrode layer 410 as a mask. The oxide layer 404c and the gate insulating layer 408 of the second gate insulating layer 402 are etched. The interface between the gate electrode 410 and the oxide insulating layer 412 cannot be clearly seen in the STEM photograph. The upper end of the second oxide layer 404c and the gate electrode layer 410 are etched using the electrode layer 410 as a mask. The lower end of the gate insulating layer 408 is in contact with the upper end of the gate insulating layer 408 and the lower end of the gate electrode layer 410. It was confirmed that the ends were in contact. [Example]

[0257] In this example, the electrical characteristics of the example sample prepared in Example 1 were evaluated. The included transistor has a channel length (L) of 0.43 μm and a channel width (W) of 1 μm. It was.

[0258] A BT stress test was performed on the example sample. First, the initial V Measure g-Id characteristics.

[0259] The BT stress test is a type of accelerated test that measures the transients that occur during long-term use. The BT stress test can evaluate the change in characteristics of the device (i.e., the change over time) in a short time. Investigating the amount of change in transistor characteristics before and after is an important step in assessing reliability. It serves as an indicator.

[0260] The stress test in which a negative voltage is applied to the gate electrode is called the negative gate BT stress test. (-GBT), and a stress test in which a positive voltage is applied is called a positive gate BT stress test. (+GBT).

[0261] Here, the gate BT stress conditions are a stress temperature of 150°C and a stress time of 3 The gate electrode was set to -3.3V or +3.3V, and the source and drain electrodes were set to -3.3V or +3.3V. At this time, the electric field strength applied to the gate insulating film was set to 0.66 MV / cm. did.

[0262] The results of the +GBT stress test and the -GBT stress test are shown in Figures 21 and 22. The dotted line in the figure shows the initial Vg-Id characteristics of the transistor, and the solid line in the figure shows the The graph shows the Vg-Id characteristics of the transistor after stress testing. The vertical axis indicates the voltage (Vg: [V]), and the vertical axis indicates the drain current (Id: [A]). This shows the Vg-Id characteristics when the drain voltage Vd is 0.1V and 3.3V. The drain voltage (Vd: [V]) is the potential difference between the drain and source with the source as the reference. "Gate voltage (Vg: [V])" is the potential difference between the gate and source with the source as the reference. do.

[0263] As shown in Figure 21, the change in threshold voltage (ΔVth) before and after the +GBT stress test The change in the shift value (ΔShift) was 0.44 V. As shown in Figure 1, the change in threshold voltage (ΔVth) before and after the -GBT stress test was 0.2 The change in the shift value (ΔShift) was 0.25 V. As shown, the amount of fluctuation is small, and it is clear that good switching characteristics are obtained.

[0264] Also, Source BT Stress Test (SBT) and Drain BT Stress Test (DBT) The source BT stress test and drain BT stress test were performed using the gate BT stress test. This is a type of accelerated test, similar to the stress test, and measures the characteristics of transistors that occur over a long period of use. Changes in sexual function (i.e., changes over time) can be evaluated in a short period of time.

[0265] First, the initial Vg-Id characteristics of the transistor are measured.

[0266] Here, the source BT stress conditions are a stress temperature of 150°C and a stress time of The time was 3600 seconds, and −3.3 V was applied to the drain electrode, and 0 V was applied to the source electrode and gate electrode. At this time, the electric field strength applied to the gate insulating film was set to 0.66 MV / cm.

[0267] The drain BT stress conditions were a stress temperature of 150°C and a stress time of The time was 3600 seconds, and 3.3 V was applied to the drain electrode, and 0 V was applied to the source electrode and gate electrode. At this time, the electric field strength applied to the gate insulating film was set to 0.66 MV / cm.

[0268] The results of the SBT stress test and the DBT stress test are shown in Figures 23 and 24. The dotted line in the figure shows the initial Vg-Id characteristics of the transistor, and the solid line in the figure shows the The graph shows the Vg-Id characteristics after the stress test. The horizontal axis shows the gate voltage (Vg The vertical axis indicates the drain current (Id: [A]). The figure shows the Vg-Id characteristics when the voltage Vd is 0.1V and 3.3V.

[0269] As shown in Figure 23, the change in threshold voltage (ΔVth) before and after the SBT stress test is The change in the shift value (ΔShift) was 0.47V. As shown, the change in threshold voltage (ΔVth) before and after the DBT stress test is 0.17V. The change in the shift value (ΔShift) was 0.11 V. As can be seen, the transistor of the example sample has a small amount of fluctuation and exhibits good switching characteristics. It was found that [Example]

[0270] In this example, an example sample has an island-shaped source electrode surrounded by a gate electrode. The first oxide layer and the oxide semiconductor layer are surrounded by an island-shaped source electrode and a drain electrode. The electrical characteristics of the first oxide were evaluated. The composition of the oxide semiconductor layer and the source electrode, drain electrode, and gate electrode Except for the configuration, Example 1 can be referred to.

[0271] In the transistor of this embodiment, the source electrode, the drain electrode, and the gate electrode are each formed of a lead. The routing wiring is electrically connected.

[0272] The film formation conditions for the first oxide layer were In:Ga:Zn=1:3:2 (atomic ratio) oxide. Argon and oxygen (argon: oxygen = 30 sc) were deposited by sputtering using a target. cm: 15sccm) mixed atmosphere, pressure 0.4Pa, power supply power 0.5kW The distance between the target and the substrate was 60 mm, and the substrate temperature was 200°C. The oxide semiconductor film was formed under the conditions of In:Ga:Zn=1:1:1 (atomic ratio). Argon and oxygen (argon:oxygen = 30sccm:15sccm) mixed atmosphere, pressure 0.4Pa, power supply power 0.5 kW was applied, the distance between the target and the substrate was 60 mm, and the substrate temperature was 300°C. The first oxide film and the oxide semiconductor film were successively formed without exposure to the air. It was.

[0273] The transistor has a channel length (L) of 1.13 μm and a channel width (W) of 13.6 μm.

[0274] Next, the measurement results of the initial Vg-Id characteristics of the transistor are shown in FIG. In this figure, the drain voltage (Vd: [V]) is 0.1V (dotted line) and 3.0V. The horizontal axis represents the gate voltage (Vg: [V]) and the vertical axis represents the The axis indicates the drain current (Id: [A]).

[0275] As shown in Figure 25, the on-current is 38 μA when the gate voltage and drain voltage are 3 V. The shift value at a drain voltage of 3 V is 0.1 V, and the S value at a drain voltage of 0.1 V is 84.3 m Excellent electrical characteristics of V / dec were obtained. [Explanation of symbols]

[0276] 250 memory cells 251 Memory Cell Array 251a Memory Cell Array 251b memory cell array 253 Peripheral Circuits 254 Capacitor 260 transistors 262 transistors 264 Capacitive Element 400 boards 402 Undercoat insulation layer 404a First oxide layer 404b Oxide semiconductor layer 404c Second oxide layer 405 Oxide film 406a Source electrode layer 406b Drain electrode layer 407 Gate insulating film 408 Gate insulating layer 410 gate electrode layer 411 Insulating film 412 Oxide insulating layer 413 Sidewall insulating layer 414 Insulating Layer 416a Source electrode layer 416b Drain electrode layer 418a Source electrode layer 418b Drain electrode layer 420 transistors 430 transistors 440 transistors 450 transistors 460 transistors 470 transistors 520 transistor 530 Transistor 540 transistor 550 transistors 560 transistors 570 Transistors 801 transistors 802 transistors 803 Transistor 804 transistor 812 transistors 813 Transistor 901 RF circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power supply circuit 906 Application Processor 907 CPU 908 DSP 910 Flash Memory 911 Display Controller 912 Memory Circuit 913 Display 914 Display section 915 Source Driver 916 Gate Driver 917 Voice Circuit 918 keyboard 919 Touch Sensor 950 Memory Circuit 951 Memory Controller 952 memory 953 memory 954 Switch 955 Switch 956 Display Controller 957 Display 1001 Battery 1002 Power supply circuit 1003 Microprocessor 1004 Flash Memory 1005 Audio Circuit 1006 keyboard 1007 Memory Circuit 1008 Touch Panel 1009 Display 1010 Display Controller 9033 Fasteners 9034 Switch 9035 Power Switch 9036 Switch 9038 Operation switch 9630 chassis 9631a Display section 9631b Display section 9632a area 9632b area 9633 Solar Cells 9634 Charge / Discharge Control Circuit 9635 Battery 9636 DC / DC Converter 9638 Operation key 9639 Button

Claims

[Claim 1] a first oxide layer; and an oxide semiconductor layer on the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer on the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a gate insulating layer on the second oxide layer; a gate electrode layer on the gate insulating layer, an end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer;

Images