Method for performing image decompression with limited hardware resources, associated image processing circuitry, and associated electronic device

Abstract

To provide a method for performing an image decompression on a limited hardware resource, an image processing circuit, and an electronic device.SOLUTION: A method includes steps of performing, using dequantization circuitry in an image processing circuit, dequantization processing according to a bitstream carrying compressed data of a predetermined image to generate a first processing result, and performing, using an upsampling circuit in the image processing circuit, upsampling processing on the first processing result to generate a second processing result to generate a decompressed image as a reconstructed version of the predetermined image. The image processing circuit avoids a use of any entropy decoding circuit, any quantization table, any de-zigzag circuit and any entropy decoding circuit described above, any inverse transform circuit associated with any quantization table described above and any de-zigzag circuitry described above while generating the decompressed image according to the bitstream.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to image processing, and more particularly to a method for performing image decompression with limited hardware resources, an associated image processing circuit, and an associated electronic device. [Background technology]

[0002] In image compression, most of the conventional proposals focus on the compression rate and compression quality of the image, which is likely to involve problems such as high hardware cost, complex design, and poor performance. For example, the image decoding device 10 shown in FIG. 1 includes an entropy decoding circuit 11, a quantization table 12, an inverse quantization circuit 13, a digitizing circuit 15, and an inverse transform circuit 17, and its complex architecture is likely to cause the above problems. In addition, there seems to be no suitable technical solution in related technologies to reduce the associated costs. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] SE Tsai, et al., "A Fast DCT Algorithm for Watermarking in Digital Signal Processor", Mathematical Problems in Engineering, Volume 2017, Article ID 7401845, (2017 / 02 / 09), https: / / doi.org / 10.1155 / 2017 / 7401845 [Non-patent document 2] Borko Furht, "IMAGE PRESENTATION AND COMPRESSION" (1999 / 01), https: / / www.researchgate.net / publication / 229038449_IMAGE_PRESENTATION_AND_COMPRESSION Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION In order to solve the above problems, it is an object of the present invention to provide a method for performing image decompression with limited hardware resources, an associated image processing circuit, and an associated electronic device. [Means for solving the problem]

[0005] At least one embodiment of the present invention provides a method for performing image decompression with limited hardware resources, the method being applicable to an image processing circuit, and may include: utilizing an inverse quantization circuit in the image processing circuit to perform an inverse quantization process according to a bitstream to generate a first processed result, the bitstream carrying compressed data of a predetermined image; and utilizing an upsampling circuit in the image processing circuit to perform an upsampling process on the first processed result to generate a second processed result, so as to generate a decompressed image as a reproduced version of the predetermined image, wherein while generating the decompressed image according to the bitstream, the image processing circuit is configured to avoid the use of any entropy decoding circuit, any quantization table, any dezigzag circuit, and any inverse transform circuit associated with any of the entropy decoding circuit, any of the quantization table, and any of the dezigzag circuit.

[0006] At least one embodiment of the present invention provides an image processing circuit that performs image decompression with limited hardware resources. The image processing circuit may include an inverse quantization circuit and an upsampling circuit coupled to the inverse quantization circuit. For example, the inverse quantization circuit may be configured to perform an inverse quantization process according to a bitstream to generate a first processed result, the bitstream carrying compressed data of a predetermined image, and the upsampling circuit may be configured to perform an upsampling process on the first processed result to generate a second processed result to generate a decompressed image as a reproduced version of the predetermined image, and the image processing circuit is configured to avoid the use of any entropy decoding circuit, any quantization table, any dezigzag circuit, and any inverse transform circuit associated with any of the entropy decoding circuit, any of the quantization table, and any of the dezigzag circuit.

[0007] At least one embodiment of the present invention provides an electronic device comprising the image processing circuit described above, the electronic device further comprising the processing circuit and a storage device coupled to the processing circuit. The processing circuit may be configured to control operation of the electronic device, and the storage device may be configured to store information for the electronic device, the information including compressed data. Further, the processing circuit may be configured to generate a decompressed image according to the bitstream for display on a display of the electronic device. [Effects of the Invention]

[0008] An advantage of the present invention is that, with proper design, the method, related image processing circuit, and related electronic device of the present invention can operate normally in the absence of any of the entropy decoding circuits, any of the quantization tables, any of the digitizing circuits, and any of the inverse transform circuits described above, and compression / decompression can work very well, especially for icons. For example, products operating according to the method of the present invention can achieve optimized performance within a budget. Furthermore, when implemented according to the present invention, the associated costs are low, the compression algorithm is simple, there are no usage restrictions, and there is no dependency between data, making it highly suitable for speedup using multiple hardware in parallel processing.

[0009] These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram of a prior art image decoding device. [Figure 2] 1 is a diagram of an image processing circuit according to an embodiment of the present invention, which operates according to the method of the present invention for performing image decompression with limited hardware resources. [Figure 3] FIG. 2 illustrates the compression and decompression steps of a method according to an embodiment of the present invention. [Figure 4A] 4 illustrates some implementation details of the compression and decompression procedures shown in FIG. 3, according to one embodiment of the present invention. [Figure 4B] 4B illustrates some other implementation details of the compression and decompression procedures shown in FIG. 3, according to the embodiment illustrated in FIG. 4A. [Figure 5] 5 illustrates the compression and decompression steps of a method according to another embodiment of the invention. [Figure 6] FIG. 4 is a diagram of an image processing circuit according to another embodiment of the present invention. [Figure 7]7 illustrates some implementation details of the image processing circuitry shown in FIG. 6 according to one embodiment of the present invention. [Figure 8] 1 is a diagram of an electronic device according to one embodiment of the present invention. [Figure 9] 1 shows a flowchart of a method according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] 2 is a diagram of an image processing circuit 100 according to an embodiment of the present invention, which may be included in an electronic device and may operate according to a method for performing image decompression with limited hardware resources according to the present invention. The image processing circuit 100 may include an inverse quantization circuit 113, an upsampling circuit 114, and a conversion circuit 116, and may include a dictionary decoding circuit 108, such as a selectively enabled optional decoding circuit 108 (labeled "dictionary decoding, optional" for brevity). In this embodiment, the upsampling circuit 114 and the conversion circuit 116 may be implemented as a YUV upsampling circuit 114 and a YUV-to-RGB conversion circuit 116, respectively. According to some embodiments, the upsampling circuit 114, such as the YUV upsampling circuit 114, the conversion circuit 116, such as the YUV-to-RGB conversion circuit 116, and / or the associated color spaces may change.

[0012] For example, the inverse quantization circuit 113 may be configured to perform an inverse quantization process according to a bitstream to generate a first processed result, the bitstream carrying compressed data of a predetermined image. The YUV upsampling circuit 114 may perform an upsampling process on the first processed result to generate a second processed result to generate a decompressed image as a reproduced version of the predetermined image. More specifically, the YUV-RGB conversion circuit 116 may perform image format conversion on the second processed result to generate a third processed result to generate a decompressed image. The image processing circuit 100 may selectively enable the dictionary decoding circuit 108 for pre-generated compressed data in accordance with control by a higher-layer circuit (e.g., a processor) within the electronic device. If the compressed data is highly compressed, particularly if it has been processed using dictionary encoding, the image processing circuit 100 may enable the dictionary decoding circuit 108. In this case, the dictionary decoding circuit 108 may perform dictionary decoding on the bitstream to generate a pre-processed result, and the inverse quantization circuit 113 may perform an inverse quantization process on the pre-processed result to generate a first processed result.

[0013] While generating a decompressed image according to the bitstream, the image processing circuit 100 can avoid the use of any entropy decoding circuit, any quantization table, any digitizing circuit, and any inverse transform circuit associated with the entropy decoding circuit, any quantization table, and any digitizing circuit. More specifically, the image processing circuit 100 does not include any entropy decoding circuit (e.g., entropy decoding circuit 11), any quantization table (e.g., quantization table 12), any digitizing circuit (e.g., digitizing circuit 15), or any inverse transform circuit (e.g., inverse transform circuit 17). Furthermore, the dictionary decoding circuit 108, the YUV upsampling circuit 114, and the YUV-RGB conversion circuit 116 are all low-cost, high-performance, and compact modules / circuits. Therefore, the image processing circuit 100 (which may be considered an image decompression circuit) can perform image decompression with very limited hardware resources. For example, the predetermined image may represent a predetermined icon image. In some examples, the predetermined image may represent any other image.

[0014] 3 is a diagram illustrating a compression procedure and a decompression procedure of a method according to an embodiment of the present invention. The compression procedure may include steps S11 to S14, and the decompression procedure may include steps S21 to S23. An image compression circuit corresponding to the image decompression circuit (or the image processing circuit 100) may be configured to perform the compression procedure, and the image decompression circuit (or the image processing circuit 100) may be configured to perform the decompression procedure. For example, the image compression circuit may be implemented by a computer (or a processor therein) running an image compression software module. For better understanding, the associated data may be as follows: (1) Raw data such as raw pixel data 300, which may be represented by pixel data for color channels such as red (R), green (G), and blue (B), having a first format that may represent any of a plurality of formats such as 16 bits / pixel, 24 bits / pixel, and 32 bits / pixel; (2) multiple sets of uncompressed pixel data, such as multiple sets of RGB data 310 having a second format (e.g., the RGB888 format (labeled "RGB888" for simplicity) with 24 bits per pixel and 8 bits each for the R, G, and B channels described above); (3) a plurality of sets of luminance and chrominance data, such as a plurality of sets of YUV data 320 having a third format (e.g., a YUV444 format (labeled "YUV444" for simplicity's sake)); (4) multiple sets of downsampled luminance and chrominance data, such as multiple sets of downsampled YUV data 330 (labeled "downsampled YUV" for simplicity); (5) a plurality of sets of quantized downsampled luminance and chrominance data (i.e., quantized luminance and chrominance data obtained by quantizing the “downsampled luminance and chrominance data”) in compressed data, such as a plurality of sets of quantized YUV data 340 (labeled “quantized YUV” for simplicity); Here, luminance and chrominance in the color space (Y,U,V) may be represented as luminance Y and chrominance (U,V), respectively. Taking the above data 300, 310, 320, 330, and 340 as an example, performing an inverse quantization process may include performing inverse quantization on data 340 to generate data 330. A first process result may include data 330 corresponding to data 340, a second process result may include data 320 corresponding to data 330, and a third process result may include data 310 corresponding to data 320. According to some embodiments, the color channels, the number of bits per pixel, the image format, and / or the associated color space may change. Furthermore, the compression and decompression procedures are inverse procedures, and the compression and decompression procedures at the same layer may be considered to be inverse procedures.

[0015] The image compression circuit may convert the raw pixel data 300 into data 310 in RGB888 format in step S11, convert the data 310 in RGB888 format into data 320 in YUV444 format in step S12, perform a downsampling process on the data 320 in YUV444 format and convert the data 320 in YUV444 format into downsampled YUV data 330, such as data 330 in YUV422 format or YUV411 format, in step S13, perform a quantization process on the downsampled YUV data 330 and convert the downsampled YUV data 330 into quantized YUV data 340 to complete the image compression, where the image compression circuit may selectively determine the quantization degree of different YUV planes in step S14. Furthermore, the image decompression circuit (or image processing circuit 100) may perform an inverse quantization process on the quantized YUV data 340 in step S21 to convert the quantized YUV data 340 into downsampled YUV data 330, such as data 330 in YUV422 format or YUV411 format, perform an upsampling process on the downsampled YUV data 330 in step S22 to convert the downsampled YUV data 330 into data 320 in YUV444 format, and convert the data 320 in YUV444 format into data 310 in RGB888 format in step S2, thereby completing the image decompression.

[0016] For example, RGB-YUV conversion is done using the following formula: Y=0.299*R+0.587*G+0.144*B, U=-0.169*R-0.331*G+0.5*B+128, and V=0.5*R-0.419*G-0.081*B+128 Here, the data 310 and 320 may be expressed as RGB888 format data (R, G, B) and YUV444 format data (Y, U, V), respectively. In step S12, the image compression circuit converts the RGB888 format data (R, G, B) into YUV444 format data (Y, U, V) using the above RGB-YUV conversion formula, and in step S13, performs downsampling on the YUV444 format data (Y, U, V) to convert the original four pixels into YUV444 data such as {[Y0, U0, V0], [Y1, U1, V1], [Y2, U2, V2], [Y3, U3, V3]}. The data (Y, U, V) in the format is converted into downsampled YUV data 330 such as a bitstream {Y0, U0, Y1, V1, Y2, U2, Y3, V3} arranged in the YUV422 format, and in step S14, quantization may be performed on the bitstream {Y0, U0, Y1, V1, Y2, U2, Y3, V3}, for example, by shifting by 2 bits for all three planes of YUV, as shown in Figures 4A and 4B.

[0017] 4A and 4B illustrate some implementation details of the compression and decompression procedures shown in FIG. 3, respectively, according to an embodiment of the present invention. As shown in FIG. 4A, one set of downsampled YUV data among the multiple sets of downsampled YUV data 330 may include bytes {Byte_A, Byte_B, Byte_C, Byte_D, Byte_E, Byte_F, Byte_G, Byte_H}, which may each include bits {A_0, ..., A_7}, {B_0, ..., B_7}, {C_0, ..., C_7}, {D_0, ..., D_7}, {E_0, ..., E_7}, {F_0, ..., F_7}, {G_0, ..., G_7}, and {H_0, ..., H_7}. As shown in FIG. 4B, one set of quantized YUV data among the multiple sets of quantized YUV data 340 may include partial bits of each of bytes {Byte_A, Byte_B, Byte_C, Byte_D, Byte_E, Byte_F, Byte_G, Byte_H}, such as most bits {A_2, ..., A_7}, {B_2, ..., B_7}, {C_2, ..., C_7}, {D_2, ..., D_7}, {E_2, ..., E_7}, {F_2, ..., F_7}, {G_2, ..., G_7} and {H_2, ..., H_7}, respectively, starting from the most significant bit (MSB).

[0018] [Table 1] Tables 1A, 1B, and 1C show theoretical compression ratios for raw data with 24 bits per pixel (such as in RGB888 format) under different configurations (e.g., various sample types and various quantization bit counts, such as quantization removal bit counts).

[0019] [Table 2] Tables 2A, 2B, and 2C show theoretical compression ratios for raw data having 16 bits / pixel (such as in RGB565 format), raw data having 24 bits / pixel (such as in RGB888 format), and raw data having 32 bits / pixel (such as in ARGB8888 format) under the different configurations described above.

[0020] FIG. 5 illustrates a compression procedure and a decompression procedure of a method according to another embodiment of the present invention. The compression procedure may include steps S11 to S15, and the decompression procedure may include steps S20 to S23. An image compression circuit may be configured to perform the compression procedure, and an image decompression circuit (or image processing circuit 100) may be configured to perform the decompression procedure. Furthermore, the image compression circuit and the image decompression circuit (or image processing circuit 100) may perform distortion-free dictionary encoding and dictionary decoding using the FastLZ algorithm, respectively. The FastLZ algorithm may be considered an ANSI C / C90 implementation of the Lempel-Ziv 77 (LZ77) algorithm for lossless data compression. For example, in step S15, the image compression circuit may further compress the quantized YUV data 340 and convert the quantized YUV data 340 into FastLZ compressed data 350 to complete the image compression. In another example, the image decompression circuit (or the image processing circuit 100) may decompress the FastLZ compressed data 350 in step S20 and convert the FastLZ compressed data 350 into quantized YUV data 340. For the sake of brevity, similar descriptions related to this embodiment will not be repeated in detail here.

[0021] 6 is a diagram of an image processing circuit 600 according to another embodiment of the present invention. The image processing circuit 600 can be considered as an example of the image processing circuit 100. The image processing circuit 600 may include a receive (RX) first-in-first-out (FIFO) buffer 608 (labeled "RX FIFO" for simplicity), a decompressor 610, and a transmit (TX) FIFO buffer 618 (labeled "TX FIFO" for simplicity). In particular, the decompressor 610 may include a bitstream buffer 611, multiple decompressors {612}, such as decompressors {612a, 612b, 612c}, and a TX FIFO handler 613, which may include a section control circuit 614 and a pixel buffer 615. Here, the inverse quantization circuit 113 and the YUV upsampling circuit 114 shown in FIG. 1 may be located within the decompressor 612c. In this embodiment, the multiple decompressors {612}, such as decompressors {612a, 612b, 612c}, may be implemented as a run-length encoding (RLE) decompressor 612a, a FastLZ decompressor 612b, and a dequantized upsampling YUV2RGB (or YUV-to-RGB) decompressor 612c, respectively. According to some embodiments, the multiple decompressors {612}, such as decompressors {612a, 612b, 612c, ...}, and / or their number may vary. Furthermore, the image processing circuit 600 may communicate with other components within the electronic device via a bus (e.g., an Advanced Peripheral Bus (APB) or an Advanced eXtensible Interface (AXI) bus) of the electronic device and signals conforming to a DMA handshaking protocol (labeled "APB / AXI DMA handshaking" for simplicity).

[0022] The image processing circuit 600 can be implemented using a pipeline hardware architecture and a highly practical modular architecture, and data transmission between modules in the modular architecture can be implemented using a unified handshaking interface, resulting in the following advantages: (1) Changes in compression algorithms or extension functions can be achieved quickly by replacing modules without significantly changing the architecture; (2) There is no need to design additional pause control circuitry. More specifically, when the direct memory access (DMA) data flow is interrupted, the image processing circuit 600 (or any module in the modular architecture) can pause operation by itself by stopping handshaking; can be achieved.

[0023] For example, the RX FIFO buffer 608 may be configured to receive compressed data moved via DMA, the bitstream buffer 611 may be configured to buffer a bitstream carrying the compressed data for use by subsequent stages such as multiple decompressors {612}, multiple decompressors {612} such as decompressors {612a, 612b, 612c} may be configured to perform decompression, and the TX FIFO handler 613 may be configured to temporarily store first decompressed data from at least some of the decompressors {612} of the multiple decompressors {612} and select at least some of the data from the first decompressed data as the second decompressed data. The TX FIFO handler 613 (or a section control circuit 614 therein) may temporarily store the first decompressed data in a pixel buffer 615 and control which of the first decompressed data (e.g., some or all of the decompressed data) is sent / written to the TX FIFO buffer 618 to become the second decompressed data. The TX FIFO buffer 618 may be configured to output the second decompressed data, and more specifically, may be configured to move the second decompressed data from the TX FIFO buffer 618 using DMA, where the second decompressed data may include data for the decompressed image.

[0024] 7 illustrates some implementation details of the image processing circuit 600 shown in FIG. 6 according to an embodiment of the present invention. Subdiagrams (a), (b), and (c) of FIG. 7 respectively illustrate related signals of a bitstream buffer 611, a decompressor 612, and a TX FIFO handler 613. The decompressor 612 may represent any one of the multiple decompressors {612} (e.g., the RLE decompressor 612a, the FastLZ decompressor 612b, and the inverse quantization upsampling YUV2RGB decompressor 612c shown in FIG. 6). The decompressor 612 may perform handshaking with each of the previous and subsequent stages using multiple handshaking signals. The multiple handshaking signals may include multiple first handshaking signals corresponding to the previous stage and multiple second handshaking signals corresponding to the subsequent stage, as shown in subdiagram (b), enabling the pipeline architecture of the image processing circuit 600 to operate correctly. The image processing circuit 600 may be configured to selectively enable at least one decompressor 612 of the plurality of decompressors {612} to perform image decompression. More specifically, in the pipeline architecture, a bitstream buffer 611 and a TX FIFO handler 613 are respectively disposed before and after the at least one decompressor 612, an RX FIFO buffer 608 is disposed before the bitstream buffer 611, and a TX FIFO buffer 618 is disposed after the TX FIFO handler 613.Similarly, the bitstream buffer 611 may have its own first and second handshaking signals corresponding to its own previous stage (e.g., RX FIFO buffer 608) and subsequent stage (e.g., decompressor 612), respectively, as shown in subdiagram (a), in order to perform handshaking with these previous / subsequent stages in the pipeline architecture, and the TX FIFO handler 613 may have its own first and second handshaking signals corresponding to its own previous stage (e.g., decompressor 612) and subsequent stage (e.g., TX FIFO buffer 618), respectively, as shown in subdiagram (c), in order to perform handshaking with these previous / subsequent stages in the pipeline architecture.

[0025] As shown in subdiagram (a), for bitstream buffer 611, its first handshaking signals may include signals {in_ready, in_data, in_valid} and its second handshaking signals may include signals {out_dec_req_bytes, out_ready, out_data, out_valid}. As shown in subdiagram (b), for any decompressor 612, the first handshaking signals may include signals {in_dec_req_bytes, in_ready, in_data, in_valid} and the second handshaking signals may include signals {out_ready, out_dec_out_bytes, out_data, out_valid}. As shown in subdiagram (c), with respect to TX FIFO handler 613, its first handshaking signals may include signals {in_ready, in_dec_out_bytes, in_data, in_valid}, and its second handshaking signals may include signals {out_ready, out_data, out_valid}. For example, in a pipeline architecture, bitstream buffer 611 and TX FIFO handler 613 may be located to the left and right of decompressor 612, respectively.

[0026] For two adjacent stages of the circuit, the meaning of these signals can be explained as follows: (1) a valid signal (such as in_valid and out_valid) configured to indicate whether the previous stage has valid data for use by the subsequent stage; (2) ready signals (such as in_ready and out_ready) configured to indicate whether the subsequent stage is ready to receive data sent by the previous stage; (3) data signals (such as in_data and out_data) configured to carry data transmitted from a previous stage to a subsequent stage; (4) dec_req_bytes signals (such as in_dec_req_bytes and out_dec_req_bytes) configured to indicate the amount of useful data that a subsequent stage wants to provide to a previous stage, as determined by the decompressor 612 according to different compression algorithms, for example; (5) dec_out_bytes signals (such as in_dec_out_bytes and out_dec_out_bytes) configured to indicate the amount of data that the previous stage decompression circuitry currently decodes to the next stage, for example, as determined by the decompressor 612 according to different compression algorithms; If valid=1 and ready=1 between two adjacent stages of a circuit, it means that a set of valid data is transmitted from the previous stage to the next stage, and the two adjacent stages of the circuit may automatically perform data transmission of valid data from the previous stage to the next stage. If not (for example, valid=0 or ready=0), the two adjacent stages of the circuit may automatically pause operation.

[0027] In the present invention, the main purpose of additionally designing the bitstream buffer 611 and not allowing the decompressor 612 to directly obtain data from the RX FIFO buffer 608 can be explained as follows: In a situation where the bitstreams required by different algorithms are not fixed length, using an RX FIFO buffer with a fixed data width in the previous stage would complicate the design. Therefore, in the present invention, the bitstream buffer 611 is designed for buffering to ensure that the decompressor 612 can retrieve data within the time of one clock (or clock cycle). Furthermore, in the present invention, the main purpose of additionally designing the TX FIFO handler 613 and not allowing the decompressor 612 to directly write data to the TX FIFO buffer 618 can be explained as follows: In a situation where the decompressed data decompressed by the decompressor 612 is not fixed length, using a TX FIFO buffer with a fixed data width in the subsequent stage would complicate the design. Therefore, in the present invention, the TX FIFO handler 613 is designed for buffering to ensure that the decompressor 612 can write data within one clock (or clock cycle) time.

[0028] FIG. 8 is a diagram of an electronic device 800 according to one embodiment of the present invention. The image processing circuit 600 shown in FIG. 6 can be implemented in the electronic device described above, such as the electronic device 800. More specifically, only two sets of DMA handshaking interfaces and one set of Advanced Microcontroller Bus Architecture (AMBA) APB or AXI interface are required to integrate the image processing circuit 600 into the electronic device 800 as an image decompression unit (IDU) 860, and the architecture shown in FIG. 8 may be illustrated here using the APB interface as an example. The electronic device 800 may include an AXI bus 801, a bridge circuit 802, an APB 803, an asynchronous bridge circuit 804, a processing circuit (or processor) such as a central processing unit (CPU) 810, a serial peripheral interface controller (SPIC) 811, a flash memory 812 (labeled "FLASH" for simplicity), a static random access memory (SRAM) 820, a DMA circuit (DMAC) 821, and a display controller 830. The IDU 860 may be coupled to the APB 803 and may communicate with the DMAC 821 via signals {DMA_Handshake0, DMA_Handshake1} conforming to a DMA handshaking protocol. A processing circuit such as the CPU 810 may be configured to control the operation of the electronic device 800, and a stopper device such as a flash memory 812 may be configured to store information for the electronic device 800 (which may include compressed data such as compressed data 813). The CPU 810 may send commands to the IDU 860 and / or set control registers within the IDU 860 to utilize the IDU 860 to perform associated operations. If necessary, the CPU 810 may control the IDU 860 to perform image decompression, such as: (1) Use of one or more compression algorithms; (2) Use distortion-free or distortion-causing compression algorithms, or both; and (3) When selecting to use a distorted algorithm, setting any of different distortion levels; may be selected.

[0029] 9 shows a flowchart of a method according to an embodiment of the present invention. An electronic device may utilize the image processing circuit 100 to perform the workflow shown in FIG.

[0030] In step S30, the electronic device may selectively utilize the dictionary decoding circuit 108 in the image processing circuit 100 to perform dictionary decoding on the bitstream to generate pre-processing results.

[0031] In step S31, the electronic device may use the inverse quantization circuit 113 in the image processing circuit 100 to perform inverse quantization processing according to the bitstream to generate a first processing result.

[0032] In step S32, the electronic device may use the upsampling circuit 114 (e.g., the YUV upsampling circuit 114) in the image processing circuit 100 to perform an upsampling process on the first processing result to generate a second processing result.

[0033] In step S33, the electronic device may use the conversion circuit 116 (e.g., YUV-RGB conversion circuit 116) in the image processing circuit 100 to perform image format conversion on the second processing result to generate a third processing result in order to generate a decompressed image.

[0034] In step S34, the electronic device may use the image processing circuit 100 to check whether all data has been processed, and if so, end the workflow shown in Figure 9, otherwise go to step S30 to continue processing the next data set.

[0035] The method may be illustrated using the workflow shown in Figure 9. According to some embodiments, one or more steps may be added, deleted, or modified in the workflow shown in Figure 9. Taking the image processing circuit 600 as an example of the image processing circuit 100, the dictionary decoding circuit 108 may be implemented as a FastLZ decompressor 612b, the inverse quantization upsampling YUV2RGB decompressor 612c may include an inverse quantization circuit 113, and the upsampling circuit 114 (e.g., the YUV upsampling circuit 114) and the conversion circuit 116 (e.g., the YUV-RGB conversion circuit 116) more specifically include the corresponding circuit architecture shown in Figure 1, except for the dictionary decoding circuit 108.

[0036] As shown in the above embodiments, the image processing circuit 100 (e.g., image processing circuit 600) and electronic device 800 of the present invention can operate normally in the absence of the entropy decoding circuit (e.g., entropy decoding circuit 11), the quantization table (e.g., quantization table 12), the digitizing circuit (e.g., digitizing circuit 15), and the inverse transform circuit (e.g., inverse transform circuit 17), and compression / decompression can perform very well, especially for icons. For example, a product operating according to the method of the present invention can achieve optimized performance within an economical budget. Furthermore, when implemented according to the present invention, the associated costs are low, the compression algorithm is simple, there are no usage restrictions, and there is no dependency between data, making it highly suitable for speeding up the process using multiple hardware in parallel.

[0037] Those skilled in the art will readily appreciate that numerous modifications and variations of the apparatus and method may be practiced while retaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. An image processing circuit that performs image decompression using limited hardware resources, the image processing circuit comprising: an inverse quantization circuit configured to perform an inverse quantization process according to a bitstream to generate a first processed result, the bitstream carrying compressed data of a predetermined image; an upsampling circuit coupled to the inverse quantization circuit and configured to perform an upsampling operation on the first processed result to generate a second processed result for generating a decompressed image as a reproduced version of the predetermined image; Equipped with an image processing circuit configured to avoid the use of any entropy decoding circuit, any quantization table, any digitizing circuit, and any inverse transform circuit associated with the any entropy decoding circuit, the any quantization table, and the any digitizing circuit while generating the decompressed image according to the bitstream.

2. 2. The image processing circuit according to claim 1, wherein the optional entropy decoding circuit, the optional quantization table, the optional dzigzag circuit, and the optional inverse transform circuit are not present in the image processing circuit.

3. a conversion circuit coupled to the upsampling circuit and configured to perform an image format conversion on the second processed result to generate a third processed result for generating the decompressed image. The image processing circuit of claim 1 further comprising:

4. a dictionary decoding circuit coupled to the inverse quantization circuit and configured to perform dictionary decoding on the bitstream to generate a pre-processing result; Furthermore, The image processing circuit of claim 1 , wherein the inverse quantization circuit is configured to perform the inverse quantization process on the pre-processed result to generate the first processed result.

5. The image processing circuit of claim 1 , wherein the predetermined image represents a predetermined icon image.

6. 2. The image processing circuit of claim 1, wherein performing the inverse quantization process comprises performing inverse quantization on a plurality of sets of quantized downsampled luminance and chrominance data to generate a plurality of sets of downsampled luminance and chrominance data, the first processing result comprising the plurality of sets of downsampled luminance and chrominance data corresponding to the plurality of sets of quantized downsampled luminance and chrominance data, and the second processing result comprising the plurality of sets of luminance and chrominance data corresponding to the plurality of sets of downsampled luminance and chrominance data.

7. The image processing circuit a receive (RX) first-in-first-out (FIFO) buffer configured to receive the compressed data; a bitstream buffer coupled to the RX FIFO buffer and configured to buffer the bitstream carrying the compressed data; a plurality of decompressors coupled to the bitstream buffer and configured to perform decompression, the dequantization circuitry and the upsampling circuitry being located in a first decompressor of the plurality of decompressors; a transmit (TX) FIFO buffer configured to output data of the decompressed image; a TX FIFO handler coupled between the plurality of decompressors and the TX FIFO buffer, configured to temporarily store first decompressed data from at least some of the decompressors of the plurality of decompressors and to control which decompressed data in the first decompressed data is sent to the TX FIFO buffer to become second decompressed data; Equipped with The image processing circuit of claim 1 , wherein the TX FIFO buffer is configured to output the second decompressed data, the second decompressed data including the data of the decompressed image.

8. 8. The image processing circuit of claim 7, wherein any decompressor among the plurality of decompressors is configured to perform handshaking with each of a previous stage and a subsequent stage using a plurality of handshaking signals, the plurality of handshaking signals including a plurality of first handshaking signals corresponding to the previous stage and a plurality of second handshaking signals corresponding to the subsequent stage, enabling a pipeline architecture of the image processing circuit to operate correctly, the image processing circuit is configured to selectively enable at least one decompressor among the plurality of decompressors to perform image decompression, the bitstream buffer and the TX FIFO handler are located before and after the at least one decompressor, respectively, the RX FIFO buffer is located before the bitstream buffer, and the TX FIFO buffer is located after the TX FIFO handler.

9. An electronic device comprising the image processing circuit of claim 1, wherein the electronic device comprises: a processing circuit configured to control the operation of the electronic device; a storage device coupled to the processing circuit and configured to store information for the electronic device, the information including the compressed data; and Equipped with The electronic device, wherein the processing circuitry is configured to generate the decompressed image according to the bitstream for display on a display of the electronic device.

10. 1. A method for performing image decompression with limited hardware resources, the method being applicable to an image processing circuit, the method comprising: utilizing an inverse quantization circuit within the image processing circuit to perform an inverse quantization process according to a bitstream to generate a first processing result, the bitstream carrying compressed data of a predetermined image; performing an upsampling process on the first processed result using an upsampling circuit within the image processing circuit to generate a second processed result for generating a decompressed image as a reproduced version of the predetermined image; Including, The method, wherein, while generating the decompressed image according to the bitstream, the image processing circuit is configured to avoid the use of any entropy decoding circuit, any quantization table, any dezigzag circuit, and any inverse transform circuit associated with the any entropy decoding circuit, the any quantization table, and the any dezigzag circuit.

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