Signal transmission device

Abstract

To provide a signal transmission device capable of improving reliability and capable of supporting a variety of input systems.SOLUTION: In a signal transmission device (10), a drive circuit (2) has: an internal oscillator circuit (22) provided between an application end of an internal power supply voltage (VCCa) output from a first output end (Na) of a rectification circuit (1) and an application end of internal ground potential (GNDa) output from a second output end (Nb) of the rectification circuit; and a switch (23) connected between a first end or a second end of a primary side coil (31) and the application end of the internal power supply voltage or the application end of the internal ground potential, to be switched based on an oscillation signal (OSC) output from the internal oscillation circuit.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a signal transmission device. [Background technology]

[0002] In industrial equipment, an isolated input circuit is required to suppress the effects of surges. Conventionally, a circuit that transmits logic signals while isolating them using a photocoupler is known (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-096051

[0004] [overview] However, the isolation method using light, such as a photocoupler, has had problems in terms of reliability.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a signal transmission device that is improved in reliability and can accommodate various input methods.

[0006] A signal transmission device according to an aspect of the present disclosure includes a primary side circuit, a secondary side circuit, and a transformer, The primary side circuit includes: a first input terminal configured to receive a common voltage; a second input terminal configured to receive an input signal; a primary coil included in the transformer; a drive circuit configured to drive the primary coil; a rectifier circuit provided between the first input terminal and the second input terminal and the drive circuit; and The secondary side circuit includes: a secondary coil included in the transformer; a receiving circuit configured to monitor a current output from the secondary coil; an output unit configured to output an output signal based on a monitoring result by the receiving circuit; and The drive circuit an internal oscillator circuit provided between an application terminal to which an internal power supply voltage output from a first output terminal of the rectifier circuit is applied and an application terminal to which an internal ground potential output from a second output terminal of the rectifier circuit is applied; a switch connected between a first end or a second end of the primary coil and an application end of the internal power supply voltage or an application end of the internal ground potential, and configured to be switched based on an oscillation signal output from the internal oscillation circuit; The configuration has the following. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing the configuration of a signal transmission device according to a comparative example. [Figure 2] FIG. 2 is a diagram showing a case where the input method is a source type for a signal transmission device according to a comparative example. [Figure 3] FIG. 3 is a diagram showing the configuration of a signal transmission device according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a timing chart showing an example of the operation of the configuration shown in FIG. [Figure 5] FIG. 5 is a diagram showing a case where the input method is a source type for the signal transmission device according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a timing chart showing an example of the operation of the configuration shown in FIG. [Figure 7] FIG. 7 is a diagram showing a partial configuration of a signal transmission device according to a modified example of the first embodiment. [Figure 8] FIG. 8 is a diagram showing the configuration of a signal transmission device according to the second embodiment of the present disclosure. [Figure 9A] FIG. 9A is a plan view of a transformer chip according to the second embodiment. [Figure 9B]FIG. 9B is a perspective view of the transformer chip according to the second embodiment. [Figure 10] FIG. 10 is a diagram showing the configuration of a signal transmission device according to the third embodiment. [Figure 11A] FIG. 11A is a plan view of a transformer chip according to a third embodiment. [Figure 11B] FIG. 11B is a perspective view of the transformer chip according to the third embodiment. [Figure 12] FIG. 12 is a diagram illustrating an example of the configuration of the coil driving unit. [Figure 13] FIG. 13 is a diagram showing a modified example of the coil driving unit. [Figure 14] FIG. 14 is a diagram showing a configuration example in which an ESD protection element is provided in a signal transmission device. [Figure 15] FIG. 15 is a diagram showing the vertical structure of a floating NMOS transistor. [Figure 16] FIG. 16 is a diagram showing another example of a configuration in which an ESD protection element is provided in a signal transmission device. [Figure 17] FIG. 17 is a diagram showing a modified example of a rectifier circuit provided in a signal transmission device. [Figure 18] FIG. 18 is a diagram showing a configuration in which an ESD protection element is provided in a rectifier circuit similar to that in FIG.

[0008] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <Comparative Example> First, a comparative example will be described for comparison with the embodiments of the present disclosure. FIG. 1 is a diagram showing the configuration of a signal transmission device 100 according to the comparative example. The signal transmission device 100 transmits a logic signal from the primary side circuit 110 to the secondary side circuit 120 while isolating the primary side circuit 110 from the secondary side circuit 120 using a photocoupler PC, i.e., an optical insulation method. Resistors Ra1 and Ra2 are connected to the outside of the signal transmission device 100 (primary side circuit 110). The resistors Ra1 and Ra2 and the signal transmission device 100 are mounted on industrial equipment 150, as an example. A switch SW1 is provided outside the industrial equipment 150.

[0010] The primary side circuit 110 has an input terminal Tcom and an input terminal Ti1 as external terminals for establishing electrical connection with the outside.

[0011] FIG. 1 shows a case where a sink type input method is used for the signal transmission device 100. In this case, the application terminal of the common voltage COM is connected to the input terminal Tcom. The application terminal of the common voltage COM is connected to one end of a resistor Ra1. The other end of the resistor Ra1 is connected to the input terminal Ti1 and one end of a resistor Rb1. The other end of the resistor Rb1 is connected to the application terminal of the ground potential GND1 via the switch SW1. With this configuration, when the switch SW1 is in the off state, the input signal IN1 applied to the input terminal Ti1 is the common voltage COM, i.e., high level. On the other hand, when the switch SW1 is in the on state, the input signal IN1 is the voltage obtained by dividing the common voltage COM by the resistors Ra1 and Ra2, i.e., low level.

[0012] The primary side circuit 110 has light emitting diodes 111 and 112 included in a photocoupler PC. The anode of the light emitting diode 111 is connected to an input terminal Ti1. The cathode of the light emitting diode 111 is connected to an input terminal Tcom. The cathode of the light emitting diode 112 is connected to the input terminal Ti1. The anode of the light emitting diode 112 is connected to the input terminal Tcom.

[0013] The secondary circuit 120 includes a resistor 121, a phototransistor 122 included in a photocoupler PC, and an output unit 123. The secondary circuit 120 further includes external terminals, namely, a power supply terminal Tcc, an output terminal To1, and a ground terminal Tg.

[0014] The power supply terminal Tcc is connected to an application terminal of the power supply voltage VCC. The power supply terminal Tcc is connected to one end of a resistor 121. The other end of the resistor 121 is connected to one end of a phototransistor 122. The other end of the phototransistor 122 is connected to a ground terminal Tg. The ground terminal Tg is connected to an application terminal of the ground potential GND. One end of the phototransistor 122 is connected to an input terminal of an output unit 123. The output terminal of the output unit 123 is connected to an output terminal To1.

[0015] The signal transmission operation when the input method is a sink type as shown in Fig. 1 will be described. When the input signal IN1 is at a high level, no current flows through the light-emitting diodes 111 and 112, so the light-emitting diodes 111 and 112 do not emit light and no current flows through the phototransistor 122. As a result, the power supply voltage VCC is input to the output section 123, and the output section 123 outputs an output signal OUT1 (either a high level or a low level) indicating the first state. The output signal OUT1 is output to the outside from the output terminal To1.

[0016] On the other hand, when the input signal IN1 is at a low level, the input signal IN1 becomes lower than the common voltage COM, causing a current to flow through the light-emitting diode 112, which then emits light. As a result, a current flows through the phototransistor 122, the ground potential GND is input to the output unit 123, and the output unit 123 outputs an output signal OUT1 (the other of the high level and the low level) indicating the second state.

[0017] 2 shows a signal transmission device 100 according to a comparative example in which the input method is a source type. In this case, unlike the sink type, one end of resistor Ra1 is connected to the application terminal of ground potential GND1, and the other end of resistor Rb1 is connected to the application terminal of power supply voltage VIN via switch SW1. Therefore, common voltage COM=GND1.

[0018] When switch SW1 is in the off state, input signal IN1 is at the common voltage COM, i.e., low level. In this case, no current flows through light-emitting diodes 111 and 112, and output signal OUT1 indicating the first state is output. On the other hand, when switch SW1 is in the on state, input signal IN1 is at the voltage obtained by dividing power supply voltage VIN by resistors Ra1 and Rb1, i.e., high level. In this case, current flows through light-emitting diode 111, and output signal OUT1 indicating the second state is output.

[0019] As described above, the signal transmission device 100 according to the comparative example can accommodate both sink and source input methods. However, the optical isolation method has reliability issues. Therefore, to solve these issues, the following embodiments of the present disclosure are implemented.

[0020] First Embodiment Fig. 3 is a diagram showing the configuration of a signal transmission device 10 according to a first embodiment of the present disclosure. Fig. 1 shows a case where the input method for the signal transmission device 10 is a sink type, and resistors Ra1 and Rb1 and a switch SW1 are provided as in Fig. 1. The resistors Ra1 and Rb1 and the signal transmission device 10 are mounted on an industrial device 105, as an example.

[0021] The signal transmission device 10 includes a primary circuit 101 and a secondary circuit 102. The primary circuit 101 includes a rectifier circuit 1, a drive circuit 2, a primary coil (transmitting coil) 31, and input terminals Tcom and Ti1. The secondary circuit 102 includes a secondary coil (receiving coil) 32, a receiving circuit 4, an output unit 5, a power supply terminal Tcc, an output terminal To1, and a ground terminal Tg. The primary coil 31 and the secondary coil 32 are included in a transformer 3.

[0022] The rectifier circuit 1 is configured as a diode bridge and includes diodes 11 to 14. The anode of the diode 11 is connected to the input terminal Tcom. The cathode of the diode 11 is connected to the cathode of the diode 12. The anode of the diode 12 is connected to the input terminal Ti1. The cathode of the diode 13 is connected to the input terminal Tcom. The anode of the diode 13 is connected to the anode of the diode 14. The cathode of the diode 14 is connected to the input terminal Ti1.

[0023] The drive circuit 2 includes a clamp circuit 21, an internal oscillator circuit 22, and a switch 23. An internal power supply voltage VCCa is applied to a node Na where the cathodes of diodes 11 and 12 are connected, and an internal ground potential GNDa is applied to a node Nb where the anodes of diodes 13 and 14 are connected. The clamp circuit 21 is provided between the nodes Na and Nb, and prevents the potential difference between the internal power supply voltage Vcca and the internal ground potential GNDa from exceeding the allowable withstand voltage of the internal circuit.

[0024] The internal oscillator circuit 22 is provided between nodes Na and Nb, and starts oscillating when the potential difference between the internal power supply voltage Vcca and the internal ground potential GNDa reaches or exceeds a certain threshold voltage. One end of the primary coil 31 is connected to the node Na via a switch 23. The other end of the primary coil 31 is connected to the node Nb. The switch 23 is switched by an oscillation signal OSC output from the internal oscillator circuit 22. The internal oscillator circuit 22 is composed of, for example, a ring oscillator.

[0025] The receiving circuit 4 monitors the level of the current output from the secondary coil 32 and controls the output unit 5. The output unit 5 outputs an output signal OUT1 via an output terminal To1.

[0026] An example of the operation of the configuration shown in Fig. 3 will be described using the timing chart shown in Fig. 4. Fig. 4 shows example waveforms of the common voltage COM, the input signal IN1, the voltage Co1 at one end of the primary coil 31, and the voltage Co2 at the other end of the primary coil 31.

[0027] At timing t1, the switch SW1 is in the OFF state, IN1=COM, the switch 23 is maintained in the ON state, and the voltages Co1 and Co2 are a voltage (COM-1Vf) lower than COM by the forward voltage Vf of the diode 11.

[0028] After that, at timing t2, switch SW1 is switched on, and IN1 begins to drop. After that, at timing t3, when IN1 reaches a voltage (COM-2Vf) that is 2Vf lower than COM, determined by the Vf of diode 11 and the Vf of diode 14, diodes 11 and 14 are turned on, and Co2 begins to drop. After that, Co2 remains at a voltage (IN1+1Vf) that is higher than IN1 by the Vf of diode 14.

[0029] Subsequently, at timing t4, when the potential difference between Co1 and Co2 exceeds a certain threshold voltage VT, the internal oscillator circuit 22 begins to oscillate. Then, the oscillation signal OSC starts switching the switch 23. When the switch 23 is in the on state, Co1 becomes a voltage (COM-1Vf) lower than COM by the Vf of the diode 11, and when the switch 23 is in the off state, Co1 = Co2. At this time, an AC current flows through the primary coil 31, the magnetic field changes, and current flows through the secondary coil 32. The receiver circuit 4 monitors the current output from the secondary coil 32, and when the current amount exceeds a certain level, it determines that the state is 2. Then, the receiver circuit 4 causes the output unit 5 to output an output signal OUT1 indicating state 2.

[0030] After that, at timing t5, switch SW1 switches to the OFF state, IN1 starts to rise, and accordingly Co2 also starts to rise. Then, at timing t6, when the potential difference between VCCa (=Co1) and GNDa (=Co2) falls below VT, internal oscillator circuit 22 stops oscillating, switch 23 stops switching, and remains ON. As a result, Co1 becomes a voltage (COM-1Vf) that is lower than COM by Vf of diode 11.

[0031] Thereafter, at timing t7, when IN1 exceeds COM-2Vf, diodes 11 and 14 are turned off, and Co1 and Co2 are maintained at COM-1Vf. Because the potential difference between Co1 and Co2 disappears, no current flows through primary coil 31, the magnetic field stops changing, and the current output from secondary coil 32 stops. When the amount of current output from secondary coil 32 falls below a certain level, receiving circuit 4 determines that the state is 1 and causes output unit 5 to output output signal OUT1 indicating state 1.

[0032] Fig. 5 shows a case where the input method for the signal transmission device 10 according to this embodiment is a source type. The configuration of the input side of the signal transmission device 10 is the same as that shown in Fig. 2. An example of the operation of the configuration shown in Fig. 5 will be described using the timing chart shown in Fig. 6. Fig. 6 shows example waveforms of the common voltage COM, the input signal IN1, the voltage Co1 at one end of the primary coil 31, and the voltage Co2 at the other end of the primary coil 31.

[0033] At timing t11, the switch SW1 is in the OFF state, IN1=COM (=GND1), the switch 23 is maintained in the ON state, and the voltages Co1 and Co2 are a voltage (COM+1Vf) higher than COM by the forward voltage Vf of the diode 13.

[0034] After that, at timing t12, switch SW1 is switched on, and IN1 starts to rise. After that, at timing t13, when IN1 reaches a voltage (COM+2Vf) that is higher than COM by 2Vf, which is the result of the Vf of diode 13 and the Vf of diode 12, diodes 12 and 13 are turned on, and Co1 starts to rise. After that, Co1 remains at a voltage (IN1-1Vf) that is lower than IN1 by the Vf of diode 12.

[0035] After that, at timing t14, when the potential difference between Co1 and Co2 becomes equal to or greater than a certain threshold voltage VT, the internal oscillator circuit 22 starts oscillating. Then, the oscillation signal OSC starts switching the switch 23. When the switch 23 is in the on state, Co1 becomes a voltage (IN1-1Vf) lower than IN1 by the Vf of the diode 12, and when the switch 23 is in the off state, Co1 = Co2. At this time, an AC current flows through the primary coil 31, the magnetic field changes, and current flows through the secondary coil 32. The receiver circuit 4 monitors the current output from the secondary coil 32, and when the current amount exceeds a certain level, it determines that the state is 2. Then, the receiver circuit 4 causes the output unit 5 to output an output signal OUT1 indicating state 2.

[0036] After that, at timing t15, switch SW1 switches to the OFF state, IN1 starts to drop, and VCCa also starts to drop. Then, at timing t16, when the potential difference between VCCa (=Co1) and GNDa (=Co2) falls below VT, internal oscillator circuit 22 stops oscillating, switch 23 stops switching, and remains ON. As a result, Co1 becomes a voltage (IN1-1Vf) lower than IN1 by Vf of diode 12.

[0037] After that, at timing t17, when IN1 falls below COM+2Vf, diodes 12 and 13 are turned off, and Co1 and Co2 are maintained at COM+1Vf. Because the potential difference between Co1 and Co2 disappears, no current flows through primary coil 31, the magnetic field changes, and the current output from secondary coil 32 stops. When the amount of current output from secondary coil 32 falls below a certain level, receiving circuit 4 determines that the state is 1 and causes output unit 5 to output output signal OUT1 indicating state 1.

[0038] As described above, the signal transmission device 10 of this embodiment uses the transformer 3, i.e., magnetic coupling, as an isolation method, thereby improving reliability. Also, as described above, signal transmission can be performed in accordance with both sink and source input methods.

[0039] Fig. 7 is a diagram showing a partial configuration of a signal transmission device 10 according to a modified example of the first embodiment. In the configuration of Fig. 7, one end of a switch 23 in a drive circuit 2 is connected to the other end of a primary coil 31, and the other end of the switch 23 is connected to a node Nb (a terminal to which an internal ground potential GNDa is applied).

[0040] Second Embodiment 8 is a diagram showing the configuration of a signal transmission device 10X according to a second embodiment of the present disclosure. The signal transmission device 10X according to this embodiment supports multiple inputs (two inputs, for example). Here, the two input channels are referred to as a first channel and a second channel, respectively.

[0041] The signal transmission device 10X includes a primary circuit 101X and a secondary circuit 102X. The primary circuit 101X includes, as components for the first channel, a rectifier circuit 1A, a drive circuit 2A, a primary coil 31A included in a transformer 3A, and an input terminal Ti1. The secondary circuit 102X includes, as components for the first channel, a secondary coil 32A included in the transformer 3A, a receiving circuit 4A, an output unit 5A, and an output terminal To1.

[0042] The primary circuit 101X includes, as components for the second channel, a rectifier circuit 1B, a drive circuit 2B, a primary coil 31B included in a transformer 3B, and an input terminal Ti2. The secondary circuit 102X includes, as components for the second channel, a secondary coil 32B included in a transformer 3B, a receiver circuit 4B, an output unit 5B, and an output terminal To2.

[0043] The primary circuit 101X has an input terminal Tcom common to the first and second channels, and the secondary circuit 102X has a power supply terminal Tcc and a ground terminal Tg common to the first and second channels.

[0044] FIG. 8 shows a case where a sink type input method is used. As an input configuration for the first channel, resistors Ra1 and Rb1 and a switch SW1 are externally connected to input terminals Tcom and Ti1. As an input configuration for the second channel, resistors Ra2 and Rb2 and a switch SW2 are externally connected to input terminals Tcom and Ti2. As an example, resistors Ra1 and Rb1, resistors Ra2 and Rb2, and a signal transmission device 10X are mounted on an industrial device 105X. Switches SW1 and SW2 are provided externally to the industrial device 105X.

[0045] When a source type input method is used for the signal transmission device 10X of this embodiment, a configuration similar to that shown in Figure 5 is externally connected to the input terminals Tcom and Ti1 as the input configuration for the first channel, and a configuration similar to that shown in Figure 5 is externally connected to the input terminals Tcom and Ti2 as the input configuration for the second channel.

[0046] <Problems with the second embodiment> According to the second embodiment described above, signal transmission can be performed in response to a plurality of inputs. However, the following problem arises. In the signal transmission device 10X, each of the drive circuits 2A and 2B has the same configuration as the drive circuit 2 shown in FIG. 3, and each of the primary coils 31A and 31B is connected to each of the drive circuits 2A and 2B in the same manner as in FIG. 3.

[0047] Here, the signal transmission device 10X is provided with a transformer chip 30X including transformers 3A and 3B. Fig. 9A is a plan view of the transformer chip 30X, and Fig. 10 is a perspective view of the transformer chip 30X.

[0048] Both the primary coils 31A and 31B are formed on a first wiring layer (lower layer) 301 of the transformer chip 30X. Both the secondary coils 32A and 32B are formed on a second wiring layer (upper layer) 302 of the transformer chip 30X. The secondary coil 32A is disposed directly above the primary coil 31A and faces the primary coil 31A. The secondary coil 32B is disposed directly above the primary coil 31B and faces the primary coil 31B.

[0049] Pads Tp1, Tp2, and Tp3 are formed on the second wiring layer 302. A first end of the primary coil 31A is connected to the pad Tp1 via a wiring L1. A second end of the primary coil 31A is connected to the pad Tp2 via a wiring L2. A first end of the primary coil 31B is connected to the pad Tp3 via a wiring L3. A second end of the primary coil 31B is connected to the pad Tp4 via a wiring L4.

[0050] Pads Ts1, Ts2, Ts3, and Ts4 are formed on the second wiring layer 302. The pad Ts1 is provided at a first end of the secondary coil 32A, and the pad Ts2 is provided at a second end of the secondary coil 32A. The pad Ts3 is provided at a first end of the secondary coil 32B, and the pad Ts4 is provided at a second end of the secondary coil 32B.

[0051] Due to the above-described connection configuration between the primary coils 31A, 31B and the drive circuits 2A, 2B, the first and second ends of the primary coils 31A, 31B must be independent of each other, and therefore pads Tp1 to Tp4 are required. Furthermore, the connection between the secondary coils 32A, 32B and the receiver circuits 4A, 4B is as shown in FIG. 8, and therefore pads Ts1 to Ts4 are required. Thus, in the second embodiment, the number of pads in the transformer chip 30X is increased.

[0052] <Third embodiment> In consideration of the above-described problems with the second embodiment, the third embodiment of the present disclosure will be described below. Fig. 10 is a diagram showing the configuration of a signal transmission device 10Y according to the third embodiment. The signal transmission device 10Y includes a primary circuit 101Y and a secondary circuit 102Y.

[0053] In this embodiment, in the primary circuit 101Y, a first end of the primary coil 31A and a first end of the primary coil 31B are commonly connected to an input terminal Tcom (i.e., an application terminal of a common voltage COM). Second ends of the primary coils 31A and 31B are connected to the drive circuits 2A and 2B, respectively.

[0054] In the secondary circuit 102Y, a first end of the secondary coil 32A and a first end of the secondary coil 32B are commonly connected to a ground terminal Tg (i.e., a terminal to which the ground potential GND is applied). Second ends of the secondary coils 32A and 32B are connected to the receiving circuits 4A and 4B, respectively.

[0055] The transformer chip 30Y provided in the signal transmission device 10Y according to this embodiment has the following configuration: Fig. 11A is a plan view of the transformer chip 30Y, and Fig. 11B is a perspective view of the transformer chip 30Y.

[0056] In the transformer chip 30Y, a first end of the primary coil 31A and a first end of the primary coil 31B are commonly connected to a pad Tp2 via a wiring L2. The pad Tp2 is connected to an input terminal Tcom. A second end of the primary coil 31A is connected to a pad Tp1 via a wiring L1. A second end of the primary coil 31B is connected to a pad Tp3 via a wiring L3.

[0057] In the transformer chip 30Y, a pad Ts2 is provided commonly to a first end of the secondary coil 32A and a first end of the secondary coil 32B. A ground terminal Tg is connected to the pad Ts2. A pad Ts1 is provided at a second end of the secondary coil 32A, and a pad Ts3 is provided at a second end of the secondary coil 32B.

[0058] In this way, in this embodiment, the number of pads in the transformer chip 30Y can be reduced, which reduces the circuit area and the number of wires connected to the pads.

[0059] The internal power supply voltage VCCa and internal ground potential GNDa in the drive circuit 2A, and the internal power supply voltage VCCb and internal ground potential GNDb in the drive circuit 2B may be different voltages, and therefore cannot be common. Therefore, as described above, the first ends of the primary coils 31A and 31B are commonly connected to the application terminal of the common voltage COM. Accordingly, the coil driver 24A in the drive circuit 2A and the coil driver 24B in the drive circuit 2B shown in FIG. 10 are configured as described below.

[0060] Fig. 12 is a diagram showing an example of the configuration of each of the coil drivers 24A and 24B. In Fig. 12, the "x" attached to the reference numeral indicates "A" or "B." For example, the coil driver 24x refers to the coil driver 24A or 24B.

[0061] The coil driver 24x includes a switch 241x, a switch 242x, and an inverter 243x. The driver circuits 2A and 2B each have the same configuration as the clamp circuit 21 and the internal oscillator circuit 22 in the driver circuit 2 shown in Fig. 3. That is, the driver circuit 2x includes an internal oscillator circuit 22x.

[0062] Switch 241x is connected between the applied end of the internal power supply voltage VCCx and the second end of the primary coil 31x. Switch 242x is connected between the applied end of the internal ground potential GNDx and the second end of the primary coil 31x. Switch 241x is switched by the oscillation signal OSCx output from the internal oscillation circuit 22x. Switch 242x is switched by a signal obtained by inverting the oscillation signal OSCx by the inverter 243x. That is, switches 241x and 242x are switched complementarily (i.e., when one is in the on state, the other is in the off state).

[0063] According to such a configuration, when the input method is a sink type, when switch SW1 or SW2 is in the on state, input signal IN1 or IN2 becomes lower than the common voltage COM, and when switch 242x is in the on state, current flows from the primary coil 31x through switch 242x toward the applied end of the internal ground potential GNDx. On the other hand, when the input method is a source type, when switch SW1 or SW2 is in the on state, input signal IN1 or IN2 becomes higher than the common voltage COM, and when switch 241x is in the on state, current flows from the applied end of the internal power supply voltage VCCx through switch 241x toward the primary coil 31x. Thereby, signal transmission can be performed regardless of the input method.

[0064] However, in the configuration shown in FIG. 12, when current flows through switch 241x or 242x, the current continues to flow while switch 241x or 242x is in the on state. Therefore, from the viewpoint of reducing power consumption, the configuration of the coil driving unit 24x as shown in FIG. 13 may be adopted. That is, a capacitor Cx is provided between the node Nx to which switches 241x and 242x are connected and the second end of the primary coil 31x. Thereby, it is possible to suppress the continuous flow of current when switch 241x or 242x is in the on state.

[0065] <ESD countermeasure> In the signal transmission devices according to the above-described various embodiments of the present disclosure, an ESD (Electrostatic Discharge) protection element may be provided as a countermeasure against ESD.

[0066] 14 is a diagram showing a configuration example in which an ESD protection element is provided in a signal transmission device. Here, ESD protection elements NM1 and NM2, both configured as N-channel MOSFETs (metal-oxide-semiconductor field-effect transistors), are provided.

[0067] The drain of the ESD protection element NM1 is connected to the input terminal Tcom. The gate and source of the ESD protection element NM1 are shorted. As a result, the ESD protection element NM1 is in the off state. The back gate and source of the ESD protection element NM1 are shorted. The source of the ESD protection element NM1 is connected to the source of the ESD protection element NM2. The gate and source of the ESD protection element NM2 are shorted. As a result, the ESD protection element NM2 is in the off state. The back gate and source of the ESD protection element NM2 are shorted. The drain of the ESD protection element NM2 is connected to the input terminal Ti1.

[0068] The ESD protection element NM1 has a parasitic diode BD1. The ESD protection element NM2 has a parasitic diode BD2. The anodes of the parasitic diodes BD1 and BD2 are connected to each other. The cathode of the parasitic diode BD1 is connected to the input terminal Tcom, and the cathode of the parasitic diode BD2 is connected to the input terminal Ti1. As a result, if a surge occurs that causes the common voltage COM to become higher than the input signal IN1, the parasitic diode BD1 breaks down, and current flows from the input terminal Tcom to the input terminal Ti1 via the parasitic diodes BD1 and BD2. Also, if a surge occurs that causes the input signal IN1 to become higher than the common voltage COM, the parasitic diode BD2 breaks down, and current flows from the input terminal Ti1 to the input terminal Tcom via the parasitic diodes BD2 and BD1. Therefore, the internal circuitry can be protected in both surge cases.

[0069] In particular, when there are multiple input channels as in the second or third embodiment, floating NMOS transistors are used for the ESD protection elements NM1 and NM2. Fig. 15 is a diagram showing the vertical structure of the floating NMOS transistor NM. The floating NMOS transistor NM is made up of a P-type semiconductor substrate P-SUB, an N-well region NW, a P-well region PW, and a P + Regions PP1, PP2 and N + The N-well region NW is formed above the P-type semiconductor substrate P-SUB. The N-well region NW can separate the P-well region PW from the P-type semiconductor substrate P-SUB. The P-well region PW is formed above the N-well region NW. The surface layer of the P-well region PW has P-wells on both sides in the lateral direction. + Region PP1 and P + N laterally sandwiched by region PP1 + Regions NP1 and NP2 are formed. N well regions NW are formed on both sides of the surface of the N well region NW. + The region NP3 is formed on both sides of the P-type semiconductor substrate P-SUB in the lateral direction. + A region PP2 is formed.

[0070] P + The region PP1 corresponds to the back gate (BG). + Region NP1 corresponds to the drain (D). N + Region NP2 corresponds to the source (S). + A gate (G) is formed directly above the channel region between the regions NP1 and NP2. + The region PP2 is a region for fixing the potential of the P-type semiconductor substrate P-SUB. + It is connected to the application terminal of the internal power supply voltage VCCa via the region NP3 (FIG. 14).

[0071] 16 is a diagram showing another example of a configuration in which ESD protection elements are provided in a signal transmission device, in which ESD protection elements PM1 and PM2 made up of P-channel MOSFETs are provided.

[0072] The drain of the ESD protection element PM1 is connected to the input terminal Tcom. The gate and source of the ESD protection element PM1 are shorted. As a result, the ESD protection element PM1 is in the off state. The back gate and source of the ESD protection element PM1 are shorted. The source of the ESD protection element PM1 is connected to the source of the ESD protection element PM2. The gate and source of the ESD protection element PM2 are shorted. As a result, the ESD protection element PM2 is in the off state. The back gate and source of the ESD protection element PM2 are shorted. The drain of the ESD protection element PM2 is connected to the input terminal Ti1.

[0073] The ESD protection element PM1 has a parasitic diode BD3. The ESD protection element PM2 has a parasitic diode BD4. The cathodes of the parasitic diodes BD3 and BD4 are connected to each other. The anode of the parasitic diode BD3 is connected to the input terminal Tcom, and the anode of the parasitic diode BD4 is connected to the input terminal Ti1. As a result, if a surge occurs that causes the common voltage COM to become higher than the input signal IN1, the parasitic diode BD4 breaks down, and current flows from the input terminal Tcom to the input terminal Ti1 via the parasitic diodes BD3 and BD4. Also, if a surge occurs that causes the input signal IN1 to become higher than the common voltage COM, the parasitic diode BD3 breaks down, and current flows from the input terminal Ti1 to the input terminal Tcom via the parasitic diodes BD4 and BD3. Therefore, the internal circuitry can be protected in both surge cases.

[0074] <Modification of rectifier circuit> 17 is a diagram showing a modified example of a rectifier circuit provided in a signal transmission device. A rectifier circuit 1 according to the modified example has PMOS transistors 11A and 11B and NMOS transistors 11C and 11D instead of diodes.

[0075] The drain of the PMOS transistor 11A is connected to the input terminal Tcom. The gate of the PMOS transistor 11A is connected to the input terminal Ti1. The back gate and source of the PMOS transistor 11A are shorted. The sources of the PMOS transistor 11A and the PMOS transistor 11B are commonly connected to an application terminal of the internal power supply voltage VCCa. The back gate and source of the PMOS transistor 11B are shorted. The gate of the PMOS transistor 11B is connected to the input terminal Tcom. The drain of the PMOS transistor 11B is connected to the input terminal Ti1.

[0076] The drain of the NMOS transistor 11C is connected to the input terminal Tcom. The gate of the NMOS transistor 11C is connected to the input terminal Ti1. The back gate and source of the NMOS transistor 11C are shorted together. The sources of the NMOS transistor 11C and the NMOS transistor 11D are commonly connected to an application terminal of the internal ground potential GNDa. The back gate and source of the NMOS transistor 11D are shorted together. The gate of the NMOS transistor 11D is connected to the input terminal Tcom. The drain of the NMOS transistor 11D is connected to the input terminal Ti1.

[0077] Furthermore, the NMOS transistors 11C and 11D are each formed of a floating NMOS transistor, and each N-well region NW is connected to an application terminal of the internal power supply voltage VCCa.

[0078] When the input signal IN1 is lower than the common voltage COM, the PMOS transistor 11A is on, the PMOS transistor 11B is off, the NMOS transistor 11C is off, and the NMOS transistor 11D is on, the common voltage COM becomes the internal power supply voltage VCCa, and the input signal IN1 becomes the internal ground potential GNDa.

[0079] On the other hand, when the input signal IN1 is higher than the common voltage COM, the PMOS transistor 11A is in the off state, the PMOS transistor 11B is in the on state, the NMOS transistor 11C is in the on state, and the NMOS transistor 11D is in the off state, the common voltage COM becomes the internal ground potential GNDa, and the input signal IN1 becomes the internal power supply voltage VCCa.

[0080] 17 also includes ESD protection elements NM1 and NM2. The difference from the configuration shown in Fig. 14 is that the sources of the ESD protection elements NM1 and NM2 are commonly connected to an application terminal of the internal ground potential GNDa.

[0081] With this configuration, if a surge occurs that causes the common voltage COM to become higher than the input signal IN1, the breakdown of parasitic diode BD1 causes a current to flow from the input terminal Tcom to the input terminal Ti1 via the parasitic diode BD1 and the on-state NMOS transistor 11D, thereby protecting the internal circuit. In this case, in the configuration shown in Figure 14, the protection voltage is the breakdown voltage of parasitic diode BD1 plus the forward voltage of parasitic diode BD2, so the protection voltage is high. However, in the configuration shown in Figure 17, the forward voltage of parasitic diode BD2 is not added, so the protection voltage can be reduced.

[0082] Furthermore, if a surge occurs that causes the input signal IN1 to become higher than the common voltage COM, the breakdown of parasitic diode BD2 causes a current to flow from the input terminal Ti1 to the input terminal Tcom via the parasitic diode BD2 and the on-state NMOS transistor 11C, thereby protecting the internal circuit. In this case, in the configuration shown in Figure 14, the protection voltage is the breakdown voltage of parasitic diode BD2 plus the forward voltage of parasitic diode BD1, so the protection voltage is high. However, in the configuration shown in Figure 17, the forward voltage of parasitic diode BD1 is not added, so the protection voltage can be reduced.

[0083] Fig. 18 is a diagram showing a configuration in which ESD protection elements PM1 and PM2 are provided in a rectifier circuit 1 similar to that shown in Fig. 17. The difference from the configuration shown in Fig. 16 is that the sources of the ESD protection elements PM1 and PM2 are commonly connected to the application terminal of the internal power supply voltage VCCa.

[0084] With this configuration, if a surge occurs that causes the common voltage COM to become higher than the input signal IN1, the breakdown of parasitic diode BD4 causes a current to flow from the input terminal Tcom to the input terminal Ti1 via the on-state PMOS transistor 11A and the parasitic diode BD4, thereby protecting the internal circuit. In this case, in the configuration shown in Figure 16, the protection voltage is the breakdown voltage of parasitic diode BD4 plus the forward voltage of parasitic diode BD3, so the protection voltage is high. However, in the configuration shown in Figure 18, the forward voltage of parasitic diode BD3 is not added, so the protection voltage can be reduced.

[0085] Furthermore, if a surge occurs that causes the input signal IN1 to become higher than the common voltage COM, the breakdown of parasitic diode BD3 causes a current to flow from the input terminal Ti1 to the input terminal Tcom via the on-state PMOS transistor 11B and the parasitic diode BD3, thereby protecting the internal circuitry. In this case, in the configuration shown in Figure 16, the protection voltage is the breakdown voltage of parasitic diode BD3 plus the forward voltage of parasitic diode BD4, so the protection voltage is high, but in the configuration shown in Figure 18, the forward voltage of parasitic diode BD4 is not added, so the protection voltage can be reduced.

[0086] <Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0087] <Additional Notes> As described above, the signal transmission device (10) according to one aspect of the present disclosure includes a primary circuit (101), a secondary circuit (102), and a transformer (3), The primary side circuit includes: a first input terminal (Tcom) configured to receive a common voltage (COM); a second input terminal (Ti1) configured to receive an input signal (IN1); a primary coil (31) included in the transformer; a drive circuit (2) configured to drive the primary coil; a rectifier circuit (1) provided between the first input terminal, the second input terminal and the drive circuit; and The secondary side circuit includes: a secondary coil (32) included in the transformer; a receiving circuit (4) configured to monitor the current output from the secondary coil; an output unit (5) configured to output an output signal (OUT1) based on the monitoring result by the receiving circuit; and The drive circuit an internal oscillator circuit (22) provided between an application terminal to which an internal power supply voltage (VCCa) output from a first output terminal (Na) of the rectifier circuit is applied and an application terminal to which an internal ground potential (GNDa) output from a second output terminal (Nb) of the rectifier circuit is applied; a switch (23) connected between a first end or a second end of the primary coil and an application end of the internal power supply voltage or an application end of the internal ground potential, and configured to be switched based on an oscillation signal (OSC) output from the internal oscillation circuit; (first configuration).

[0088] In the first configuration, the switch (23) is connected between a first end of the primary coil and an application end of the internal power supply voltage, A second end of the primary coil may be connected to an application terminal of the internal ground potential (second configuration).

[0089] In the first configuration, the switch (23) is connected between a second end of the primary coil and an application end of the internal ground potential, A first end of the primary coil may be connected to an application terminal of the internal power supply voltage (third configuration).

[0090] In addition, in any one of the first to third configurations, a plurality of the transformers (3A, 3B) are provided, The primary side circuit (101X) the first input terminal (Tcom) common to a plurality of input channels; a plurality of second input terminals (Ti1, Ti2) provided corresponding to the plurality of input channels; a plurality of the rectifier circuits (1A, 1B) provided corresponding to the plurality of input channels; a plurality of the driving circuits (2A, 2B) provided corresponding to the plurality of input channels; a plurality of the primary coils (31A, 31B) provided corresponding to the plurality of input channels; and The secondary side circuit (102X) a plurality of the secondary coils (32A, 32B) provided corresponding to the plurality of input channels; a plurality of the receiving circuits (4A, 4B) provided corresponding to the plurality of input channels; a plurality of the output units (5A, 5B) provided corresponding to the plurality of input channels; (fourth configuration).

[0091] Furthermore, the fourth configuration may be configured to include a transformer chip (30X or 30Y) including the plurality of transformers (fifth configuration).

[0092] In the fifth configuration, the first ends of the primary coils may be commonly connected to the first input terminal (sixth configuration).

[0093] In the sixth configuration, each of the plurality of drive circuits (2A, 2B) has a coil drive unit (24A, 24B), The coil driving unit a first switch (241x) connected between a second terminal of the primary coil (31x) and an application terminal of the internal power supply voltage (VCCx); a second switch (242x) connected between a second end of the primary coil and an application terminal of the internal ground potential (GNDx); and The first switch and the second switch may be configured to be switched complementarily based on the oscillation signal (OSCx) (seventh configuration).

[0094] In addition, in the above seventh configuration, the coil driving unit may be configured to have a capacitor (Cx) connected between a node (Nx) to which the first switch and the second switch are connected and a second end of the primary side coil (eighth configuration).

[0095] In addition, in any one of the fifth to eighth configurations, the secondary side circuit has a ground terminal (Tg) common to the plurality of input channels, The first ends of the plurality of secondary coils may be commonly connected to the ground terminal (ninth configuration).

[0096] In addition, in any of the fourth to ninth configurations, the first main electrode may be connected to the first input terminal (Tcom) or the second input terminal (Ti1), and an ESD protection element (NM1, NM2) composed of a MOSFET may be provided (tenth configuration).

[0097] In the tenth configuration, the ESD protection elements (NM1, NM2) are each composed of an N-channel MOSFET having an N-well region (NW) for isolating a P-well region (PW) from a P-type semiconductor substrate (P-SUB), The N-well region may be electrically connected to an application terminal of the internal power supply voltage (eleventh configuration).

[0098] In addition, in any one of the fourth to eleventh configurations, the rectifier circuit (1) a first PMOS transistor (11A) having a drain connected to the first input terminal, a source connected to the application terminal of the internal power supply voltage, and a gate connected to the second input terminal; a second PMOS transistor (11B) having a drain connected to the second input terminal, a source connected to the application terminal of the internal power supply voltage, and a gate connected to the first input terminal; a first NMOS transistor (11C) having a drain connected to the first input terminal, a source connected to the application terminal of the internal ground potential, and a gate connected to the second input terminal; A second NMOS transistor (11D) having a drain connected to the second input terminal, a source connected to the application terminal of the internal ground potential, and a gate connected to the first input terminal (twelfth configuration).

[0099] In the twelfth configuration, the first NMOS transistor and the second NMOS transistor are each formed of an N-channel MOSFET having an N-well region for isolating a P-well region from a P-type semiconductor substrate; The N-well region may be electrically connected to an application terminal of the internal power supply voltage (thirteenth configuration).

[0100] In the twelfth or thirteenth configuration, a first ESD protection element (NM1) is configured by an N-channel MOSFET having a drain connected to the first input terminal, a source connected to the application terminal of the internal ground potential, a back gate and a source short-circuited, and a gate and a source short-circuited; The fourteenth configuration may also include a second ESD protection element (NM2) consisting of an N-channel MOSFET whose drain is connected to the second input terminal, whose source is connected to the application terminal of the internal ground potential, whose back gate and source are short-circuited, and whose gate and source are short-circuited.

[0101] Furthermore, in the twelfth or thirteenth configuration, a third ESD protection element (PM1) is configured of a P-channel MOSFET having a drain connected to the first input terminal, a source connected to the application terminal of the internal power supply voltage, a back gate and a source short-circuited, and a gate and a source short-circuited; The fifteenth configuration may also include a fourth ESD protection element (PM2) consisting of a P-channel MOSFET whose drain is connected to the second input terminal, whose source is connected to the application terminal of the internal power supply voltage, whose back gate and source are short-circuited, and whose gate and source are short-circuited. [Industrial Applicability]

[0102] The present disclosure can be used for signal input in industrial equipment, for example. [Explanation of symbols]

[0103] 1 Rectifier circuit 1A,1B rectifier circuit 2. Drive circuit 2A, 2B drive circuit 3. Transformer 3A, 3B transformer 4. Receiving circuit 4A, 4B receiving circuit 5 Output section 5A,5B output section 10 Signal transmission device 10X, 10Y signal transmission device 11A, 11B PMOS transistors 11C, 11D NMOS transistor 11~14 Diodes 21 Clamp Circuit 22 Internal oscillator circuit 23 Switch 24A, 24B Coil drive unit 30X, 30Y transformer chip 31 Primary coil 31A, 31B Primary coil 32 Secondary coil 32A, 32B Secondary coil 100 Signal transmission device 101 Primary side circuit 101X,101Y Primary side circuit 102 Secondary circuit 102X,102Y Secondary circuit 105 Industrial Equipment 105X Industrial Equipment 110 Primary side circuit 111,112 Light-emitting diodes 120 Secondary circuit 121 Resistance 122 Phototransistor 123 Output section 150 Industrial Equipment 241x switches 242x switch 243x Inverter 301 1st wiring layer 302 2nd wiring layer BD1~BD4 parasitic diodes Cx capacitor L1~L4 wiring NM Floating NMOS transistor NM1 ESD protection element NM1, NM2 ESD protection elements NM2 ESD protection element NMOS floating NP1 area NP1,NP2 area NP1~NP3 area NP2 area NP3 area NW N-well region Na,Nb nodes Nx Node P-SUB P-type semiconductor substrate PC Photocoupler PW P-well region PM1, PM2 ESD protection elements PP1,PP2 P + region PW P-well region Ra1, Ra2 resistors Rb1, Rb2 resistance SW1, SW2 switches Tcc power terminal Tcom input terminal Ti1, Ti2 input terminals Tg Ground terminal Ti1, Ti2 input terminals To1, To2 output terminals Tp1~Tp4 pads Ts1~Ts4 pads

Claims

1. The power supply includes a primary circuit, a secondary circuit, and a transformer, The primary side circuit includes: a first input terminal configured to receive a common voltage; a second input terminal configured to receive an input signal; a primary coil included in the transformer; a drive circuit configured to drive the primary coil; a rectifier circuit provided between the first input terminal and the second input terminal and the drive circuit; and The secondary side circuit includes: a secondary coil included in the transformer; a receiving circuit configured to monitor a current output from the secondary coil; an output unit configured to output an output signal based on a monitoring result by the receiving circuit; and The drive circuit an internal oscillator circuit provided between an application terminal to which an internal power supply voltage output from a first output terminal of the rectifier circuit is applied and an application terminal to which an internal ground potential output from a second output terminal of the rectifier circuit is applied; a switch connected between a first end or a second end of the primary coil and an application end of the internal power supply voltage or an application end of the internal ground potential, and configured to be switched on and off based on an oscillation signal output from the internal oscillation circuit; A signal transmission device having the following.

2. the switch is connected between a first end of the primary coil and an application terminal of the internal power supply voltage; The signal transmission device according to claim 1 , wherein a second end of the primary coil is connected to an application terminal of the internal ground potential.

3. the switch is connected between a second end of the primary coil and the application end of the internal ground potential; The signal transmission device according to claim 1 , wherein a first end of the primary coil is connected to an application terminal of the internal power supply voltage.

4. A plurality of the transformers are provided, The primary side circuit includes: the first input terminal common to a plurality of input channels; a plurality of the second input terminals provided corresponding to the plurality of input channels; a plurality of the rectifier circuits provided corresponding to the plurality of input channels; a plurality of the driving circuits provided corresponding to the plurality of input channels; a plurality of the primary coils provided corresponding to the plurality of input channels; and The secondary side circuit includes: a plurality of the secondary coils provided corresponding to the plurality of input channels; a plurality of the receiving circuits provided corresponding to the plurality of input channels; a plurality of the output units provided corresponding to the plurality of input channels; The signal transmission device according to claim 1 ,

5. The signal transmission device according to claim 4 , further comprising a transformer chip including the plurality of transformers.

6. The signal transmission device according to claim 5 , wherein first ends of the plurality of primary coils are commonly connected to the first input terminal.

7. each of the plurality of drive circuits has a coil drive unit; The coil driving unit a first switch connected between a second end of the primary coil and an application terminal of the internal power supply voltage; a second switch connected between a second end of the primary coil and the application terminal of the internal ground potential; and The signal transmission device according to claim 6 , wherein the first switch and the second switch are switched complementarily based on the oscillation signal.

8. 8. The signal transmission device according to claim 7, wherein the coil driving section has a capacitor connected between a node where the first switch and the second switch are connected and a second end of the primary coil.

9. the secondary side circuit has a ground terminal common to the plurality of input channels; 9. The signal transmission device according to claim 5, wherein first ends of the secondary coils are commonly connected to the ground terminal.

10. 5. The signal transmission device according to claim 4, further comprising an ESD protection element configured by a MOSFET, the first main electrode of which is connected to the first input terminal or the second input terminal.

11. the ESD protection element is composed of an N-channel MOSFET having an N-well region for isolating a P-well region from a P-type semiconductor substrate; 11. The signal transmission device according to claim 10, wherein the N-well region is electrically connected to an application terminal of the internal power supply voltage.

12. The rectifier circuit includes: a first PMOS transistor having a drain connected to the first input terminal, a source connected to the application terminal of the internal power supply voltage, and a gate connected to the second input terminal; a second PMOS transistor having a drain connected to the second input terminal, a source connected to the application terminal of the internal power supply voltage, and a gate connected to the first input terminal; a first NMOS transistor having a drain connected to the first input terminal, a source connected to the application terminal of the internal ground potential, and a gate connected to the second input terminal; a second NMOS transistor having a drain connected to the second input terminal, a source connected to the application terminal of the internal ground potential, and a gate connected to the first input terminal; The signal transmission device according to claim 4 , comprising:

13. the first NMOS transistor and the second NMOS transistor are each formed of an N-channel MOSFET having an N-well region for isolating a P-well region from a P-type semiconductor substrate; 13. The signal transmission device according to claim 12, wherein the N-well region is electrically connected to an application terminal of the internal power supply voltage.

14. a first ESD protection element configured by an N-channel MOSFET having a drain connected to the first input terminal, a source connected to the application terminal of the internal ground potential, a back gate and a source short-circuited, and a gate and a source short-circuited; a second ESD protection element configured by an N-channel MOSFET having a drain connected to the second input terminal, a source connected to the application terminal of the internal ground potential, a back gate and a source short-circuited, and a gate and a source short-circuited; The signal transmission device according to claim 12 or 13, comprising:

15. a third ESD protection element configured by a P-channel MOSFET having a drain connected to the first input terminal, a source connected to the application terminal of the internal power supply voltage, a back gate and a source short-circuited, and a gate and a source short-circuited; a fourth ESD protection element configured by a P-channel MOSFET having a drain connected to the second input terminal, a source connected to the application terminal of the internal power supply voltage, a back gate and a source short-circuited, and a gate and a source short-circuited; The signal transmission device according to claim 12 or 13, comprising:

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