Semiconductor device and manufacturing method for the same

Abstract

To improve the breakdown voltage performance of an outer peripheral breakdown voltage region by suppressing a trap of a hole at an interface between an insulating layer and a GaN substrate.SOLUTION: A semiconductor device includes a semiconductor substrate formed of a gallium nitride semiconductor, an electrode layer covering an upper surface of the semiconductor substrate, and an insulating layer covering a region around the electrode layer at the upper surface of the semiconductor substrate. The semiconductor substrate includes an element region existing below a contact region between the electrode layer and the upper surface, and a peripheral breakdown voltage region existing below a contact region between the insulating layer and the upper surface. The peripheral breakdown voltage region includes a p-type breakdown voltage layer in contact with the insulating layer, and an n-type breakdown voltage layer in contact with the p-type breakdown voltage layer from below. The p-type breakdown voltage layer includes an upper p-type breakdown voltage layer in contact with the insulating layer, and a lower p-type breakdown voltage layer provided in contact with the upper p-type breakdown voltage layer from below and having the p-type impurity concentration lower than that of the upper p-type breakdown voltage layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

[0002] Generally, semiconductor devices having an element region and a peripheral voltage-withstanding region are known. An electrode layer is provided on the upper surface of a semiconductor substrate in the element region. The element region includes semiconductor elements (e.g., transistors, diodes, etc.) connected to the electrode layer. The upper surface of the semiconductor substrate in the peripheral voltage-withstanding region is covered with an insulating layer. The peripheral voltage-withstanding region includes a p-type voltage-withstanding layer in contact with the insulating layer and an n-type voltage-withstanding layer in contact with the p-type voltage-withstanding layer from below. A depletion layer extends from the interface between the p-type voltage-withstanding layer and the n-type voltage-withstanding layer, thereby maintaining a potential difference in the peripheral voltage-withstanding region. In this type of semiconductor device, hot holes generated in the peripheral voltage-withstanding region may be trapped at the interface between the insulating layer and the p-type voltage-withstanding layer. When holes are trapped at the interface between the insulating layer and the p-type voltage-withstanding layer, the interface state density and positive charge density increase at the interface, making it difficult for the depletion layer to extend in the peripheral voltage-withstanding region. Therefore, when holes are trapped at the interface, the voltage-withstanding performance of the peripheral voltage-withstanding region deteriorates.

[0003] In response to this, Patent Document 1 discloses a technique for providing a semi-insulating layer in contact with the top surface of a p-type breakdown voltage layer. By providing a semi-insulating layer in this manner, hole trapping at the interface between the semi-insulating layer and the p-type breakdown voltage layer can be suppressed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2017-098440 Summary of the Invention [Problem to be solved by the invention]

[0005] In a semiconductor substrate made of a gallium nitride semiconductor (hereinafter referred to as a GaN substrate), holes are trapped in the region on the p-type breakdown layer side (i.e., the GaN substrate side) at the interface between the insulating layer and the p-type breakdown layer. Therefore, in a GaN substrate, hole trapping cannot be suppressed even if a semi-insulating layer is used as an insulating layer covering the peripheral breakdown region. Furthermore, because the semi-insulating layer has a fixed charge, providing a semi-insulating layer covering the peripheral breakdown region in a GaN semiconductor substrate actually reduces the breakdown voltage performance of the peripheral breakdown region. This specification proposes a technology for suppressing hole trapping at the interface between the insulating layer and the GaN substrate in a semiconductor device having a GaN substrate, thereby improving the breakdown voltage performance of the peripheral breakdown region. [Means for solving the problem]

[0006] The semiconductor device disclosed in this specification includes a semiconductor substrate made of a gallium nitride semiconductor, an electrode layer covering the upper surface of the semiconductor substrate, and an insulating layer covering the upper surface of the semiconductor substrate around the electrode layer. The semiconductor substrate includes an element region located below a contact region between the electrode layer and the upper surface, and a peripheral voltage-withstanding region located below a contact region between the insulating layer and the upper surface. The peripheral voltage-withstanding region includes a p-type voltage-withstanding layer in contact with the insulating layer and an n-type voltage-withstanding layer in contact with the p-type voltage-withstanding layer from below. The p-type voltage-withstanding layer includes an upper p-type voltage-withstanding layer in contact with the insulating layer and a lower p-type impurity layer in contact with the upper p-type voltage-withstanding layer from below and having a lower p-type impurity concentration than the upper p-type voltage-withstanding layer.

[0007] In this specification, gallium nitride semiconductor refers to a compound semiconductor containing nitrogen and gallium, such as GaN, AlGaN, InGaN, and AlInGaN.

[0008] In this specification, the p-type impurity concentration means the value obtained by dividing the sum of activated p-type impurities and non-activated p-type impurities by the volume of the semiconductor layer.

[0009] For example, as reported in Hidetoshi, M. et al. (2023). Applied Physics Express 16, 105501, holes are less likely to be trapped at the interface between a highly-doped p-type GaN and an insulating layer. In the semiconductor device disclosed herein, an upper p-type breakdown voltage layer having a high p-type impurity concentration is in contact with the insulating layer, thereby suppressing hole trapping at the interface between the insulating layer and the semiconductor substrate. Therefore, in this semiconductor device, degradation of breakdown voltage performance due to hole trapping is less likely to occur. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view of a semiconductor device 10 according to an embodiment. [Figure 2] 2 is a cross-sectional view of the semiconductor device 10 of the embodiment (a cross-sectional view taken along line II-II in FIG. 1). [Figure 3] 4 is a graph showing the p-type impurity concentration distribution in the p-type breakdown voltage region. [Figure 4] FIG. 1 is a cross-sectional view of a semiconductor substrate before processing. [Figure 5] FIG. 10 is a cross-sectional view of a semiconductor device according to a modified example. [Figure 6] FIG. 10 is a cross-sectional view of a semiconductor device according to a modified example. [Figure 7] FIG. 10 is a cross-sectional view of a semiconductor device according to a modified example. [Figure 8] FIG. 10 is a cross-sectional view of a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0011] A semiconductor device 10 shown in FIG. 1 includes a semiconductor substrate 12 made of a gallium nitride semiconductor. An upper electrode layer 14 is provided in the center of the upper surface of the semiconductor substrate 12. An insulating layer 16 is provided on the upper surface of the semiconductor substrate 12 in a region surrounding the upper electrode layer 14. The insulating layer 16 is made of silicon oxide. As shown in FIG. 2, the upper electrode layer 14 and the insulating layer 16 are in contact with the upper surface of the semiconductor substrate 12. Hereinafter, the region of the semiconductor substrate 12 below the contact region between the upper electrode layer 14 and the semiconductor substrate 12 will be referred to as an element region 20, and the region below the contact region between the insulating layer 16 and the semiconductor substrate 12 will be referred to as a peripheral voltage-withstanding region 22. The semiconductor device 10 also includes a lower electrode layer 18 in contact with the lower surface of the semiconductor substrate 12. The lower electrode layer 18 is in contact with the entire lower surface of the semiconductor substrate 12.

[0012] A semiconductor element capable of passing a current between the upper electrode layer 14 and the lower electrode layer 18 is provided in the element region 20. Although not particularly limited, a transistor such as a metal-oxide-semiconductor field effect transistor (MOSFET) or a high electron mobility transistor (HEMT) may be provided in the element region 20, or a diode such as a PIN diode or a Schottky barrier diode may be provided in the element region 20. FIG. 2 shows, as an example, a case where a MOSFET is provided in the element region 20. The MOSFET has a source layer 40, a body layer 42, a drift layer 44, a drain layer 46, a gate insulating film 30, a gate electrode 32, and an interlayer insulating film 34.

[0013] The gate insulating film 30, the gate electrode 32, and the interlayer insulating film 34 are disposed above the semiconductor substrate 12. The gate insulating film 30 covers part of the upper surface of the semiconductor substrate 12 in the element region 20. The gate electrode 32 is disposed above the gate insulating film 30. The gate electrode 32 is insulated from the semiconductor substrate 12 by the gate insulating film 30. The interlayer insulating film 34 covers the surface of the gate electrode 32. The gate electrode 32 is insulated from the upper electrode layer 14 by the interlayer insulating film 34.

[0014] The source layer 40, the body layer 42, the drift layer 44, and the drain layer 46 are provided inside the semiconductor substrate 12. The source layer 40 is an n-type layer, and a plurality of source layers 40 are provided inside the semiconductor substrate 12. Each source layer 40 is in contact with the upper electrode layer 14. The body layer 42 is a p-type layer, and a plurality of body layers 42 are provided inside the semiconductor substrate 12. Each body layer 42 contains Mg (magnesium) as a p-type impurity. Each body layer 42 is provided around the source layer 40. Each body layer 42 extends to the upper surface of the semiconductor substrate 12 at a position adjacent to the source layer 40. Each body layer 42 is in contact with the upper electrode layer 14 at a position not shown. The drift layer 44 is an n-type layer having a lower n-type impurity concentration than the source layer 40. The drift layer 44 is provided below each body layer 42. The drift layer 44 is separated from the source layer 40 by the body layer 42. The drift layer 44 extends to the upper surface of the semiconductor substrate 12 in a position where the body layer 42 is not provided. The gate insulating film 30 covers the upper surface of the semiconductor substrate 12 across the source layer 40, the body layer 42, and the drift layer 44. The drain layer 46 is an n-type layer having a higher n-type impurity concentration than the drift layer 44. The drain layer 46 is disposed below the drift layer 44. The drain layer 46 is in contact with the lower electrode layer 18 over the entire lower surface of the semiconductor substrate 12.

[0015] A p-type breakdown layer 50 and an n-type breakdown layer 60 are provided in the peripheral breakdown region 22. In this embodiment, a plurality of p-type breakdown layers 50 are provided in the peripheral breakdown region 22.

[0016] The multiple p-type voltage-breaking layers 50 are provided in a range including the upper surface of the semiconductor substrate 12. The multiple p-type voltage-breaking layers 50 are arranged at intervals in a direction from the element region 20 toward the outer peripheral edge 12a of the semiconductor substrate 12. Each p-type voltage-breaking layer 50 extends in an annular shape to surround the element region 20. Each p-type voltage-breaking layer 50 contains Mg as a p-type impurity. Each p-type voltage-breaking layer 50 has an upper p-type voltage-breaking layer 50a and a lower p-type voltage-breaking layer 50b having a lower p-type impurity concentration than the upper p-type voltage-breaking layer 50a. The upper p-type voltage-breaking layer 50a is in contact with the insulating layer 16. The lower p-type voltage-breaking layer 50b is arranged below the upper p-type voltage-breaking layer 50a and is in contact with the upper p-type voltage-breaking layer 50a. The n-type breakdown voltage layer 60 is an n-type layer that is continuous with the drift layer 44 in the element region 20 and has approximately the same n-type impurity concentration as the drift layer 44. The n-type breakdown voltage layer 60 is distributed from the drift layer 44 to the outer peripheral edge 12a of the semiconductor substrate 12. The n-type breakdown voltage layer 60 is distributed across the region below the multiple p-type breakdown voltage layers 50. The n-type breakdown voltage layer 60 is in contact with each lower p-type breakdown voltage layer 50b from below. The n-type breakdown voltage layer 60 also extends to the upper surface of the semiconductor substrate 12 at the intervals between the multiple p-type breakdown voltage layers 50. Therefore, the n-type breakdown voltage layer 60 is in contact with the side surface of each p-type breakdown voltage layer 50. The p-type breakdown voltage layers 50 are separated by the n-type breakdown voltage layer 60. A drain layer 46 is disposed below the n-type breakdown voltage layer 60.

[0017] FIG. 3 shows the concentration distribution of p-type impurities (i.e., Mg) in the depth direction within the p-type voltage-breaking layer 50 (i.e., the thickness direction of the semiconductor substrate 12). In FIG. 3, graph A shows the concentration distribution of p-type impurities implanted in the ion implantation process into the upper p-type voltage-breaking layer 50a, and graph B shows the concentration distribution of p-type impurities implanted in the ion implantation process into the lower p-type voltage-breaking layer 50b. Note that the p-type impurity concentration shown in FIG. 3 is the total concentration of activated p-type impurities and inactivated p-type impurities. As shown in FIG. 3, the p-type impurity concentration of the upper p-type voltage-breaking layer 50a is higher than the p-type impurity concentration of the lower p-type voltage-breaking layer 50b. The thickness of the upper p-type voltage-breaking layer 50a is smaller than the thickness of the lower p-type voltage-breaking layer 50b.

[0018] The activation rate of the p-type impurities in the upper p-type voltage-breaking layer 50a is lower than that of the p-type impurities in the lower p-type voltage-breaking layer 50b. The activation rate is calculated by dividing the number of activated p-type impurities (i.e., acceptors) by the sum of the activated p-type impurities and the inactivated p-type impurities. For example, the activation rate in the upper p-type voltage-breaking layer 50a is 90%, and the activation rate in the lower p-type voltage-breaking layer 50b is 99% or higher. The acceptor concentration (i.e., the concentration of activated p-type impurities) in the upper p-type voltage-breaking layer 50a may be higher or lower than the acceptor concentration in the lower p-type voltage-breaking layer 50b.

[0019] When the semiconductor device 10 is in use, a higher potential is applied to the lower electrode layer 18 than to the upper electrode layer 14. When a potential equal to or greater than the threshold is applied to the gate electrode 32, the MOSFET turns on, and current flows from the lower electrode layer 18 to the upper electrode layer 14 via the drain layer 46, the drift layer 44, the body layer 42 (i.e., the channel), and the source layer 40. When the potential of the gate electrode 32 is reduced to a value below the threshold, the MOSFET turns off. When the MOSFET turns off, a depletion layer extends from the body layer 42 to the drift layer 44 within the element region 20. The depleted drift layer 44 maintains the voltage applied to the MOSFET. Furthermore, when the MOSFET turns off, the potential at the outer periphery edge 12 a of the semiconductor substrate 12 increases, and a voltage is applied laterally to the outer periphery breakdown voltage region 22. This causes a depletion layer to extend from the body layer 42 toward the outer periphery edge 12 a via each p-type breakdown voltage layer 50. This extending depletion layer depletes the n-type breakdown voltage layer 60. The depleted n-type breakdown voltage layer 60 maintains the voltage applied to the peripheral breakdown voltage region 22. Furthermore, when the MOSFET is off, the lower p-type breakdown voltage layer 50b, which has a low p-type impurity concentration, is depleted. Depleting the lower p-type breakdown voltage layer 50b suppresses electric field concentration in the peripheral breakdown voltage region 22. Furthermore, the thin upper p-type breakdown voltage layer 50a also suppresses electric field concentration in the peripheral breakdown voltage region 22. Note that the upper p-type breakdown voltage layer 50a may be depleted when the MOSFET is off. By reducing the activation rate of the upper p-type breakdown voltage layer 50a, the upper p-type breakdown voltage layer 50a can be depleted when the MOSFET is off. When the upper p-type breakdown voltage layer 50a is depleted, electric field concentration in the peripheral breakdown voltage region 22 can be further suppressed.

[0020] When the MOSFET is off, hot holes generated in the n-type breakdown voltage layer 60 may penetrate the interface between the semiconductor substrate 12 and the insulating layer 16. Generally, in a gallium nitride semiconductor substrate, hot holes are easily trapped at the interface between the p-type semiconductor layer and the insulating layer. If hot holes are trapped at the interface between the p-type breakdown voltage layer 50 and the insulating layer 16, a depletion layer does not easily develop in the peripheral breakdown voltage region 22, resulting in a decrease in the breakdown voltage performance of the peripheral breakdown voltage region 22. However, in the semiconductor device 10 of the embodiment, the portion of the p-type breakdown voltage layer 50 that contacts the insulating layer 16 is formed by the upper p-type breakdown voltage layer 50a, which has a high p-type impurity concentration. This prevents hot holes from being trapped at the interface between the p-type breakdown voltage layer 50 and the insulating layer 16. Therefore, the breakdown voltage performance of the peripheral breakdown voltage region 22 is less likely to be reduced. Thus, with the structure of the semiconductor device 10 of the embodiment, even if hot holes are generated in the peripheral breakdown voltage region 22, the breakdown voltage performance of the peripheral breakdown voltage region 22 is less likely to be reduced.

[0021] Next, a first manufacturing method and a second manufacturing method will be described as manufacturing methods of the semiconductor device 10 of the embodiment. Note that these manufacturing methods are characterized by the processing step for the peripheral voltage-withstanding region 22, and therefore the processing step for the element region 20 (particularly the step of forming the MOSFET structure) will not be described.

[0022] In the first manufacturing method, first, a semiconductor substrate 12 is prepared, in which a low-concentration n-type layer (i.e., drift layer 44 and n-type breakdown layer 60) is provided on a drain layer 46, as shown in FIG. 4. For example, the n-type layer (i.e., drift layer 44 and n-type breakdown layer 60) can be formed on the drain layer 46 by epitaxial growth, thereby obtaining the semiconductor substrate 12 shown in FIG. 4. In FIG. 4, a specific region 20 is a region where a MOSFET will be formed later, and corresponds to the element region 20 in FIG. 2. Also, in FIG. 4, a peripheral region 22 is a region surrounding the specific region 20, and corresponds to the peripheral breakdown region 22 in FIG. 2. At this stage, the n-type breakdown layer 60 is exposed over the entire top surface of the semiconductor substrate 12 in the peripheral region 22. Next, p-type impurities (i.e., Mg) are selectively implanted into the n-type breakdown layer 60 through a mask, thereby forming a plurality of lower p-type breakdown layers 50b and a plurality of upper p-type breakdown layers 50a, as shown in FIG. 2. Either the lower p-type breakdown layer 50b or the upper p-type breakdown layer 50a may be formed first. When ion implanting the lower p-type breakdown layer 50b, p-type impurities are implanted at a low concentration deep into the n-type breakdown layer 60. When ion implanting the upper p-type breakdown layer 50a, p-type impurities are implanted at a high concentration shallow into the n-type breakdown layer 60. Next, the semiconductor substrate 12 is annealed to activate the p-type impurities in the upper p-type breakdown layer 50a and the lower p-type breakdown layer 50b. By adjusting the annealing conditions (i.e., temperature, time, etc.) of the semiconductor substrate 12, the activation rate of the p-type impurities in the lower p-type breakdown layer 50b, which has a low p-type impurity concentration, can be made higher than the activation rate of the p-type impurities in the upper p-type breakdown layer 50a, which has a high p-type impurity concentration. Thereafter, an insulating layer 16 is formed on the upper surface of the semiconductor substrate 12 in the peripheral region 22, thereby completing the structure of the peripheral breakdown region 22 shown in FIG. 2. The MOSFET structure can be formed in parallel with the processing step for peripheral breakdown voltage region 22. Next, upper electrode layer 14 is formed on the upper surface of semiconductor substrate 12 within element region 20. Next, lower electrode layer 18 is formed on the lower surface of semiconductor substrate 12. This completes semiconductor device 10 shown in FIG.

[0023] In the second manufacturing method, first, as shown in FIG. 4, a semiconductor substrate 12 is prepared, which has a low-concentration n-type layer (i.e., the drift layer 44 and the n-type breakdown layer 60) on the drain layer 46. At this stage, the n-type breakdown layer 60 is exposed over the entire upper surface of the semiconductor substrate 12 in the peripheral region 22. Next, p-type impurities (i.e., Mg) are selectively implanted into the n-type breakdown layer 60 through a mask, thereby forming multiple lower p-type breakdown layers 50b as shown in FIG. 2. In the ion implantation into the lower p-type breakdown layer 50b, the p-type impurities are implanted at a low concentration deep into the n-type breakdown layer 60. Next, the semiconductor substrate 12 is annealed to activate the p-type impurities inside the lower p-type breakdown layer 50b. Next, p-type impurities are selectively implanted into the n-type breakdown layer 60 through a mask, thereby forming multiple upper p-type breakdown layers 50a as shown in FIG. 2. In the ion implantation into the upper p-type voltage-breaking layer 50a, p-type impurities are implanted at a high concentration into a shallow portion of the n-type voltage-breaking layer 60. That is, p-type impurities are implanted at a high concentration into the area between the upper surface of the semiconductor substrate 12 and the lower p-type voltage-breaking layer 50b. An insulating layer 16 is then formed on the upper surface of the semiconductor substrate 12 in the peripheral voltage-breaking region 22, thereby completing the structure of the peripheral voltage-breaking region 22 shown in FIG. 2. The MOSFET structure can be formed in parallel with the processing steps for the peripheral voltage-breaking region 22. In the second manufacturing method, the upper p-type voltage-breaking layer 50a is formed after activation annealing, resulting in a low activation rate of the upper p-type voltage-breaking layer 50a. The second manufacturing method also allows the activation rate of the p-type impurities in the lower p-type voltage-breaking layer 50b to be higher than that of the p-type impurities in the upper p-type voltage-breaking layer 50a. Next, an upper electrode layer 14 is formed on the upper surface of the semiconductor substrate 12 in the element region 20. Next, a lower electrode layer 18 is formed on the lower surface of the semiconductor substrate 12. As a result, the semiconductor device 10 shown in FIG. 2 is completed.

[0024] In the above-described embodiment, multiple p-type breakdown voltage layers 50, which are separated from one another, are provided in the peripheral breakdown voltage region 22. However, as shown in FIG. 5, the p-type breakdown voltage layer 50 may be configured with one upper p-type breakdown voltage layer 50a and multiple lower p-type breakdown voltage layers 50b. In FIG. 5, multiple lower p-type breakdown voltage layers 50b are provided below a single, wide upper p-type breakdown voltage layer 50a. The multiple lower p-type breakdown voltage layers 50b are spaced apart in the direction from the device region 20 toward the peripheral edge 12a of the semiconductor substrate 12. Even in this configuration, the upper p-type breakdown voltage layer 50a, which has a high p-type impurity concentration, can suppress hot hole trapping. Furthermore, even in this configuration, the p-type breakdown voltage layer 50 can promote the extension of the depletion layer, thereby achieving high breakdown voltage performance in the peripheral breakdown voltage region 22.

[0025] 6, the p-type breakdown voltage layer 50 may be composed of one upper p-type breakdown voltage layer 50a and one lower p-type breakdown voltage layer 50b. In FIG. 6, a single lower p-type breakdown voltage layer 50b having a width similar to that of the upper p-type breakdown voltage layer 50a is provided below a single wider upper p-type breakdown voltage layer 50a. This configuration also suppresses hot hole trapping by the upper p-type breakdown voltage layer 50a having a high p-type impurity concentration. This configuration also promotes the extension of the depletion layer by the p-type breakdown voltage layer 50, thereby achieving high breakdown voltage performance in the peripheral breakdown voltage region 22.

[0026] 7, the lower p-type breakdown voltage layer 50b may include a high-concentration p-type layer 51 and a low-concentration p-type layer 52. The high-concentration p-type layer 51 has a higher p-type impurity concentration than the low-concentration p-type layer 52. However, the high-concentration p-type layer 51 has a lower p-type impurity concentration than the upper p-type breakdown voltage layer 50a. The low-concentration p-type layer 52 is disposed closer to the outer periphery than the high-concentration p-type layer 51 (i.e., closer to the outer periphery edge 12a). The low-concentration p-type layer 52 is adjacent to the high-concentration p-type layer 51. Even in this configuration, the upper p-type breakdown voltage layer 50a, which has a high p-type impurity concentration, can suppress hot hole trapping. Even in this configuration, the p-type breakdown voltage layer 50 can promote the extension of the depletion layer, thereby achieving high breakdown voltage performance in the outer periphery breakdown voltage region 22. In particular, the high-concentration p-type layer 51 and the low-concentration p-type layer 52 allow for more accurate control of the extension of the depletion layer, thereby achieving higher breakdown voltage performance.

[0027] 8, the lower p-type breakdown voltage layer 50b may have a plurality of high-concentration p-type layers 51 and a plurality of low-concentration p-type layers 52. The high-concentration p-type layers 51 and the low-concentration p-type layers 52 are alternately arranged in the direction from the device region 20 toward the outer periphery 12a of the semiconductor substrate 12. Even in this configuration, the upper p-type breakdown voltage layer 50a, which has a high p-type impurity concentration, can suppress hot hole trapping. Also in this configuration, the p-type breakdown voltage layer 50 can promote the extension of the depletion layer, thereby achieving high breakdown voltage performance in the outer periphery breakdown voltage region 22. In particular, the high-concentration p-type layers 51 and the low-concentration p-type layers 52 can more accurately control the extension of the depletion layer, thereby achieving higher breakdown voltage performance.

[0028] When the upper p-type voltage-breaking layer 50a is wide as shown in FIGS. 5 to 8, the upper p-type voltage-breaking layer 50a may be formed by epitaxial growth.

[0029] The configurations of the techniques disclosed in this specification are listed below. (Configuration 1) A semiconductor device, a semiconductor substrate made of a gallium nitride semiconductor; an electrode layer covering an upper surface of the semiconductor substrate; an insulating layer covering the upper surface of the semiconductor substrate in a region surrounding the electrode layer; and the semiconductor substrate has an element region located below a contact region between the electrode layer and the upper surface, and a peripheral voltage-resistant region located below a contact region between the insulating layer and the upper surface, The peripheral voltage-resistant region is a p-type voltage-resistant layer in contact with the insulating layer; an n-type voltage blocking layer in contact with the p-type voltage blocking layer from below; and The p-type voltage blocking layer is an upper p-type voltage-resistant layer in contact with the insulating layer; a lower p-type breakdown layer that is in contact with the upper p-type breakdown layer from below and has a p-type impurity concentration lower than that of the upper p-type breakdown layer; A semiconductor device having: (Configuration 2) 2. The semiconductor device according to configuration 1, wherein an activation rate of p-type impurities in the upper p-type voltage-blocking layer is lower than an activation rate of p-type impurities in the lower p-type voltage-blocking layer. (Configuration 3) 3. The semiconductor device according to configuration 2, wherein the activation rate of p-type impurities in the upper p-type voltage-breaking layer is 90% or less. (Configuration 4) 4. The semiconductor device according to any one of configurations 1 to 3, wherein a plurality of the p-type breakdown voltage layers are arranged at intervals in a direction from the element region toward the outer periphery of the semiconductor substrate. (Configuration 5) The semiconductor device according to any one of configurations 1 to 3, wherein a plurality of the lower p-type breakdown voltage layers are arranged at intervals below the upper p-type breakdown voltage layer in a direction from the element region toward the outer peripheral edge of the semiconductor substrate. (Configuration 6) the lower p-type breakdown voltage layer has a high-concentration p-type layer and a low-concentration p-type layer having a p-type impurity concentration lower than that of the high-concentration p-type layer, the high-concentration p-type layer and the low-concentration p-type layer are disposed adjacent to each other below the upper p-type breakdown voltage layer in a direction from the element region toward the outer periphery of the semiconductor substrate; The semiconductor device according to any one of configurations 1 to 3. (Configuration 7) 7. The semiconductor device according to any one of configurations 1 to 6, wherein the thickness of the upper p-type voltage-resistant layer is smaller than the thickness of the lower p-type voltage-resistant layer. (Configuration 8) 8. The semiconductor device according to any one of configurations 1 to 7, wherein the p-type voltage-resistant layer extends in an annular shape so as to surround the element region. (Configuration 9) A method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate made of a gallium nitride semiconductor, the semiconductor substrate having a specific region and a peripheral region located around the specific region, the peripheral region having an n-type breakdown voltage layer exposed on an upper surface of the semiconductor substrate; forming a lower p-type breakdown layer by implanting p-type impurities into the n-type breakdown layer; activating the p-type impurities in the lower p-type breakdown layer by annealing the semiconductor substrate; after the annealing, implanting p-type impurities into the n-type voltage blocking layer in a region between the upper surface and the lower p-type voltage blocking layer to form an upper p-type impurity layer exposed at the upper surface and having a higher p-type impurity concentration than the lower p-type voltage blocking layer; forming an insulating layer in contact with the upper p-type voltage blocking layer on the upper surface in the peripheral region; forming an electrode layer on the upper surface in the specific region; A manufacturing method comprising the steps of:

[0030] According to the second and third configurations, the upper p-type breakdown voltage layer is easily depleted, so that a high breakdown voltage can be achieved in the peripheral breakdown voltage region.

[0031] In any of the configurations 4 to 6, the p-type voltage-breaking layer can promote the extension of the depletion layer in the peripheral voltage-breaking region.

[0032] According to the seventh configuration, electric field concentration in the peripheral voltage-resistant region can be suppressed.

[0033] According to the ninth aspect, the activation rate of p-type impurities in the upper p-type voltage-breaking layer can be reduced, so that a high voltage-breaking property can be achieved in the peripheral voltage-breaking region.

[0034] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0035] 12: semiconductor substrate, 14: upper electrode layer, 16: insulating layer, 18: lower electrode layer, 20: element region, 22: peripheral voltage-resistant region, 50: p-type voltage-resistant layer, 50a: upper p-type voltage-resistant layer, 50b: lower p-type voltage-resistant layer, 60: n-type voltage-resistant layer

Claims

1. A semiconductor device, a semiconductor substrate (12) made of a gallium nitride semiconductor; an electrode layer (14) covering the upper surface of the semiconductor substrate; an insulating layer (16) covering the upper surface of the semiconductor substrate in a region surrounding the electrode layer; and the semiconductor substrate has an element region (20) located below a contact region between the electrode layer and the upper surface, and a peripheral voltage-resistant region (22) located below a contact region between the insulating layer and the upper surface, The peripheral voltage-resistant region is a p-type voltage-resistant layer (50) in contact with the insulating layer; an n-type voltage-resistant layer (60) in contact with the p-type voltage-resistant layer from below; and The p-type voltage blocking layer is an upper p-type voltage-resistant layer (50a) in contact with the insulating layer; a lower p-type voltage-resistant layer (50b) in contact with the upper p-type voltage-resistant layer from below and having a p-type impurity concentration lower than that of the upper p-type voltage-resistant layer; A semiconductor device having:

2. 2. The semiconductor device according to claim 1, wherein an activation rate of p-type impurities in said upper p-type voltage-blocking layer is lower than an activation rate of p-type impurities in said lower p-type voltage-blocking layer.

3. 3. The semiconductor device according to claim 2, wherein an activation rate of p-type impurities in said upper p-type voltage-breaking layer is 90% or less.

4. 4. The semiconductor device according to claim 1, wherein a plurality of said p-type breakdown voltage layers are arranged at intervals in a direction from said element region toward an outer peripheral edge of said semiconductor substrate.

5. The semiconductor device according to any one of claims 1 to 3, wherein a plurality of the lower p-type breakdown layers are arranged at intervals below the upper p-type breakdown layer in a direction from the element region toward the outer periphery of the semiconductor substrate.

6. the lower p-type breakdown voltage layer has a high-concentration p-type layer (51) and a low-concentration p-type layer (52) having a p-type impurity concentration lower than that of the high-concentration p-type layer, the high-concentration p-type layer and the low-concentration p-type layer are disposed adjacent to each other below the upper p-type breakdown voltage layer in a direction from the element region toward the outer periphery of the semiconductor substrate; The semiconductor device according to any one of claims 1 to 3.

7. 4. The semiconductor device according to claim 1, wherein the thickness of said upper p-type voltage-resistant layer is smaller than the thickness of said lower p-type voltage-resistant layer.

8. 4. The semiconductor device according to claim 1, wherein the p-type voltage-resistant layer extends in an annular shape so as to surround the element region.

9. A method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate made of a gallium nitride semiconductor, the semiconductor substrate having a specific region and a peripheral region located around the specific region, the peripheral region having an n-type breakdown voltage layer exposed on an upper surface of the semiconductor substrate; forming a lower p-type breakdown layer by implanting p-type impurities into the n-type breakdown layer; activating the p-type impurities in the lower p-type breakdown layer by annealing the semiconductor substrate; after the annealing, implanting p-type impurities into a region in the n-type voltage blocking layer between the upper surface and the lower p-type voltage blocking layer to form an upper p-type impurity layer exposed at the upper surface and having a higher p-type impurity concentration than the lower p-type voltage blocking layer; forming an insulating layer in contact with the upper p-type voltage blocking layer on the upper surface in the peripheral region; forming an electrode layer on the upper surface in the specific region; A manufacturing method comprising the steps of:

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