Gate drive circuit

Abstract

To provide a gate drive circuit that has achieved resonance suppression, loss reduction, and noise reduction.SOLUTION: The gate drive circuit drives semiconductor elements that are electrically connected in parallel and have gates, and includes: a charging circuit for charging the gates on the basis of a control command; a discharging circuit for discharging the gates on the basis of the control command; and a second charging circuit for additionally charging the gates in accordance with charging and discharging of the gates. The second charging circuit suppresses the discharging speed of the gates after the voltage between main circuit terminals of the semiconductor elements rises to a peak voltage during discharging of the gates.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a gate drive circuit. [Background technology]

[0002] In inverters mounted on electric vehicles, etc., as the switching frequency of power semiconductor elements increases, SiC-MOSFETs, which are majority carrier devices, are used as semiconductor switching elements. SiC-MOSFETs do not generate tail current at turn-off due to minority carriers like Si-IGBTs, so they can reduce switching loss and are suitable for high-frequency switching. They also contribute to the miniaturization of power conversion circuits and are compatible with Si-IGBTs in terms of drive system.

[0003] However, because SiC-MOSFETs are often used in multiple parallel connections due to the small chip area of ​​the semiconductor elements and the need for higher power, the inductance difference between the parallel-connected power semiconductor elements creates a resonance source between the power semiconductor elements during switching. This raises concerns about increased surge voltage and a deterioration in EMC, so there is a need to suppress resonance between power semiconductor elements and further reduce switching losses. In addition, when the current change rate during switching is large due to high-speed switching, surge voltage and ringing vibration generate electromagnetic noise from the switching elements, so there is a need to reduce this noise and avoid a decrease in inverter reliability.

[0004] As a configuration for avoiding a decrease in inverter reliability, for example, Patent Document 1 listed below discloses a power conversion circuit having a configuration that can avoid a decrease in the reliability of upper and lower arm switches when performing abnormality control. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2022-171419 Summary of the Invention [Problem to be solved by the invention]

[0006] The technology described in Patent Document 1 has a problem in that the switching speed is suppressed at a fast timing, which increases switching loss. In view of this, the present invention aims to provide a gate drive circuit that achieves resonance suppression, low loss, and low noise. [Means for solving the problem]

[0007] A gate drive circuit is provided which drives semiconductor elements electrically connected in parallel and having gates, the gate drive circuit comprising: a charging circuit which charges the gate based on a control command; a discharging circuit which discharges the gate; and a second charging circuit which additionally charges the gate in response to the charging and discharging of the gate, and the second charging circuit suppresses the discharge rate of the gate after the voltage between the main circuit terminals of the semiconductor element rises to a peak voltage during the discharging of the gate. [Effects of the Invention]

[0008] It is possible to provide a gate drive circuit that achieves resonance suppression, low loss, and low noise. [Brief explanation of the drawings]

[0009] [Figure 1] Diagram of an inverter circuit connected to a gate drive circuit. [Figure 2] FIG. 1 is a diagram of a gate drive circuit according to a first embodiment of the present invention. [Figure 3] 6A and 6B show a second charging circuit example and a modification of the gate drive circuit according to the first embodiment of the present invention. [Figure 4] 4 shows a turn-off waveform according to the first embodiment of the present invention. [Figure 5] 1 shows an example of a voltage detection circuit and example waveforms according to a first embodiment of the present invention. [Figure 6]FIG. 4 is a gate drive circuit diagram according to a second embodiment of the present invention. [Figure 7] A modified example of the second embodiment. [Figure 8] 10 shows an example of a gate drive waveform according to a second embodiment of the present invention. [Figure 9] FIG. 10 is a waveform diagram showing a gate driver turn-on according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and some omissions and simplifications have been made as appropriate for clarity of explanation. The present invention can be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0011] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0012] (First embodiment and overall configuration) (Figure 1) The inverter 100 includes a control circuit 10, a gate drive circuit 11, and a power semiconductor device 50. The gate drive circuit 11 includes a first gate drive circuit 11a and a second gate drive circuit 11b. The power semiconductor device 50 includes first power semiconductor elements 1a and 1b connected to the first gate drive circuit 11a, and second power semiconductor elements 2a and 2b connected to the second gate drive circuit 11b, with the first power semiconductor elements 1a and 1b forming a pair of arms. The first power semiconductor elements 1a and 1b and the second power semiconductor elements 2a and 2b are electrically connected in parallel to each other. The gate drive circuit 11 is driven based on a control command from the control circuit 10 to drive the power semiconductor elements 1 and 2. The power semiconductor elements are composed of semiconductor elements such as IGBTs, SiC-MOSFETs, and GaN-HEMTs. The illustrated power semiconductor elements 1 and 2 are MOSFETs.

[0013] In the first power semiconductor elements 1a and 1b, the main circuit high-voltage side terminal is a drain terminal, the main circuit low-voltage side terminal is a source terminal, and the control terminal is a gate terminal. If the power semiconductor elements are configured as IGBTs, the main circuit high-voltage side terminal is a collector terminal, and the main circuit low-voltage side terminal is an emitter terminal. Furthermore, the power semiconductor elements may be further connected in multiple parallel connections depending on the desired output current value. Furthermore, a configuration in which multiple power semiconductor devices 50 are connected in parallel may also be used.

[0014] The positive wiring is connected to a positive terminal 3 connected to a DC voltage source such as a battery (not shown). The negative wiring is connected to a negative terminal 4 connected to a DC voltage source such as a battery (not shown). This allows a DC voltage to be supplied to the power semiconductor device 50.

[0015] The positive wiring is connected to the drain terminals of the first power semiconductor elements 1a and 1b. The source terminals of the power semiconductor elements 1a and 1b are connected in parallel to the output terminal 7 and the drain terminals of the power semiconductor elements 2a and 2b. The source terminals of the power semiconductor elements 2a and 2b are connected to the negative wiring. The output terminal 7 of the power semiconductor elements is connected to a load such as a motor (not shown).

[0016] The gate terminal 5 and the source terminal 6 are connected to gate drive circuits 11a and 11b, respectively, which send drive power to the power semiconductor device 50. The gate drive circuits 11a and 11b are connected to a control circuit 10. The control circuit 10 outputs signals to turn on or off the power semiconductor elements 1a and 1b and the power semiconductor elements 2a and 2b via the gate drive circuits 11a and 11b, based on signals input from a higher-level control device such as a microcomputer (not shown).

[0017] By causing the power semiconductor elements 1a, 1b and the power semiconductor elements 2a, 2b to operate to be on or off, the power semiconductor device 50 converts a DC voltage input from a DC voltage source such as a battery (not shown) into an AC voltage and outputs the AC voltage to a load such as a motor via the output terminal 7.

[0018] (Figure 2) The circuit configuration of the gate drive circuit 11 will be described, focusing on the configuration of the first gate drive circuit 11a and the power semiconductor elements 1a and 1b in Fig. 1. The configuration described below is also applicable to other power semiconductor elements and gate drive circuits. The following description is an example in which the power semiconductors 1a and 1b and the switching element M1 are N-type MOSFETs, and the switching element M2 is a P-type MOSFET.

[0019] The gate drive circuit 11 includes a switching element M1, a switching element M2, a positive-side power supply V1, and a second charging circuit 20. The switching element M1 is a charging circuit that charges the gates of the power semiconductor elements 1a and 1b based on a control command from the control circuit 10. The switching element M2 is a discharging circuit that discharges the gates of the power semiconductor elements 1a and 1b. The second charging circuit 20 additionally charges the gates in response to the charging and discharging of the gates.

[0020] The positive power supply V1 of the gate drive circuit 11 is connected to the source terminal S1 of the switching element M1. The drain terminal D1 of the switching element M1 is connected to an on-gate resistor R1. The on-gate resistor R1 is connected to a backflow prevention diode Di1.

[0021] The diode Di1 is connected to a reverse current prevention diode Di2. The reverse current prevention diode Di2 is connected to an off-gate resistor R2. The off-gate resistor R2 is connected to a drain side terminal D2 of the switching element M2. A source side terminal S2 of the switching element M2 is connected to a source terminal 6 of the gate drive circuit 11. Note that the diodes Di1 and Di2 may be omitted.

[0022] One end of the on-gate resistor R1 and one end of the off-gate resistor R2 are connected to the gate terminal 5 of the gate drive circuit 11. The gate terminal G1 of the switching element M1 and the gate terminal G2 of the switching element M2 are connected to a signal terminal 21 of the gate drive circuit 11. The source terminal S2 of the switching element M2 is connected to the output terminal of the potential variable circuit. The second charging circuit 20 is connected to the gate terminal 5 of the gate drive circuit 11. In the gate drive circuit 11, the signal terminal 23 is a terminal that connects the control circuit 10 and the second charging circuit 20.

[0023] A gate terminal 5 of the gate drive circuit 11 is connected to gate terminals Gp of the power semiconductor elements 1a and 1b. A source terminal 6 of the gate drive circuit 11 is connected to source terminals Sp of the power semiconductor elements 1a and 1b. Although the gate drive circuit 11 has been described as being a voltage-driven type, it may also be a current-driven type.

[0024] In the above configuration, when a turn-on signal is input from the control circuit 10 to the signal terminal 21, an on-voltage command is input to the gate terminal G1 of the switching element M1, and when the switching element M1 is turned on, a potential VDD1 is supplied from the positive-side power supply V1 via the switching element M1, the diode Di1, and the on-gate resistor R1 to charge the gate-source capacitance of the power semiconductor elements 1a and 1b.

[0025] On the other hand, when a turn-off signal is input from the control circuit 10 to the signal terminal 21 and the switching element M2 is turned on, the gate-source capacitance of the power semiconductor elements 1a and 1b is discharged. At this time, the discharge speed of the gate charge of the power semiconductor elements 1a and 1b can be suppressed by temporarily turning on the second charging circuit 20 in accordance with the timing of the discharge of the gate-source capacitance of the power semiconductor elements 1a and 1b. This temporarily suppresses the change in gate voltage and reduces the switching speed.

[0026] In conventional power semiconductor elements 1a and 1b, the potential difference due to the source inductance difference and the difference in current change between each device at the end of turn-off fluctuated, resulting in a large-amplitude resonance source due to the high current change rate. However, by adopting the configuration of the present invention, the potential difference due to the source inductance difference that occurs between parallel semiconductor devices at the end of turn-off is reduced, thereby reducing the difference in the current change rate between each device and suppressing resonance without increasing switching loss. This achieves stable switching operation, high-speed switching, and low EMC.

[0027] (Figure 3) FIG. 3(a) shows an example of the configuration of a second charging circuit 20, which is a charging circuit, and FIG. 3(b) shows a modified example of FIG. 3(a). Note that the switching element M3 in FIG. 3(a) is a P-type MOSFET, and the switching element M4 in FIG. 3(b) is an N-type MOSFET. In the second charging circuit 20, the first power supply V2 is connected to the source terminal S3 of the switching element M3. The drain terminal D3 of the switching element M3 is connected to a resistor R3. The resistor R3 is connected to the output terminal 20b via a diode Di3. The input terminal 20a of the second charging circuit 20 is connected to the output terminal 30d of the voltage detection circuit 30 in FIG. 5, which will be described later.

[0028] When the voltage detection circuit 30 detects a predetermined voltage of the power semiconductor elements 1a and 1b and outputs an on signal to the input terminal 20a, the switching element M3 turns on, and the potential VDD2 is output from the first power supply V2 to the output terminal 20b. Note that the potential VDD2 output from the first power supply V2 may be different from the potential VDD1 output from the power supply V1 (Fig. 2), and the potential may be variable during operation.

[0029] Due to the potential output from the power supply in the second charging circuit 20, the gate charge can be charged at the timing when the gates of the power semiconductor elements 1a and 1b are discharged during turn-off, so the discharge speed of the gate charge of the power semiconductor elements 1a and 1b is suppressed.

[0030] The modified example shown in Fig. 3(b) is a configuration used when suppressing the discharge of the power semiconductor elements 1a and 1b according to the resistance value during turn-off. The first power supply V2 is connected to the source terminal S4 of the switching element M4. The drain terminal D4 of the switching element M4 is connected to the resistor R4. The resistor R4 is connected to the output terminal 20b via the diode Di4. When the voltage detection circuit 30 detects a predetermined voltage of the power semiconductor elements 1a and 1b and outputs an on signal to the input terminal 20a, the switching element M4 turns on, and the potential VSS2 is output from the first power supply V2 to the output terminal 20b. At this time, by setting the relationship between the resistance values of the resistor R2 (Fig. 2) and the resistor R4 as R2 < R4, the discharge of the power semiconductor elements 1a and 1b can be suppressed.

[0031] (Fig. 4) The solid lines (A) to (F) show waveforms when the power semiconductor elements 1a and 1b are turned off, and the dashed lines show waveforms in a conventional configuration. (A) shows the voltage waveform at the signal terminal 21 (FIG. 2), (B) shows the voltage waveform at the input terminal 20a (FIG. 3) of the second charging circuit 20, (C) shows the gate-source (GpSp) voltage waveform between the main circuit terminals of the power semiconductor elements 1a and 1b, (D) shows the drain-source (DpSp) voltage waveform of the power semiconductor elements 1a and 1b, (E) shows the drain-source (DpSp) current waveform of the power semiconductor elements 1a and 1b, and (F) shows the magnitude of the switching loss of the power semiconductor elements 1a and 1b. The waveforms will be explained below using the configurations shown in FIGS. 2 and 3.

[0032] At time t0, as shown in (A), a voltage command to change the power semiconductor elements 1a and 1b from on to off is input from the control circuit 10 to the signal terminal 21. As a result, the switching element M1 of the gate drive circuit 11 is turned off and the switching element M2 is turned on. As a result, the gate-source capacitance of the power semiconductor elements 1a and 1b begins to discharge, and as shown in (C), it can be seen that the gate-source voltage of the power semiconductor elements 1a and 1b begins to decrease from time t0.

[0033] At time t1, when the gate-source voltages of the power semiconductor elements 1a and 1b fall below the mirror voltage 13 as shown in (C), the drain-source voltages of the power semiconductor elements 1a and 1b start to increase as shown in (D).

[0034] At time t2, when the drain-source voltage of the power semiconductor elements 1a and 1b reaches the power supply voltage 12 as shown in (D), the drain-source current starts to decrease as shown in (E).

[0035] At time t3, as shown in (D), during gate discharge of the power semiconductor elements 1a and 1b, the drain-source voltage rises to a peak voltage and becomes a surge voltage. When the voltage detection circuit 30 detects this timing, an ON signal is input to the input terminal 20a of the second charging circuit 20, as shown in (B), turning on the second charging circuit 20. It can be seen that during the ON period of the second charging circuit 20, from time t3 to time t4, as shown in (C), the gate of the power semiconductor element 1 undergoing gate discharge is charged, thereby suppressing the gate discharge rate. This reduces the switching speed of the power semiconductor elements 1a and 1b, and suppresses the decrease in the gate-source voltage, maintaining it at a constant holding voltage 15.

[0036] Furthermore, as shown in (E), while the second charging circuit 20 is on, the decrease in the rate of change of the drain-source current of the power semiconductor element 1 is suppressed, and a tail current 16 flows between the drain and source of the power semiconductor elements 1a and 1b. This reduces the potential difference due to the source inductance difference between the parallel-connected semiconductor elements 1a and 1b shown in Fig. 1, and suppresses resonance of the drain-source voltage of the power semiconductor elements 1a and 1b.

[0037] At time t4, as shown in (B), an OFF signal is input to the input terminal 20a of the second charging circuit 20, turning off the second charging circuit 20. As a result, the gate-source voltage starts decreasing again from the holding voltage 15 as shown in (C).

[0038] At time t5, the gate-source voltages of the power semiconductor elements 1a and 1b, which have decreased again as shown in (C), fall below the threshold voltage 14, and the drain-source currents of the power semiconductor elements 1a and 1b become 0 as shown in (E). Through the above process, the turn-off that started at time t0 is completed.

[0039] The switching loss of the power semiconductor elements 1a and 1b that occurs during the above-mentioned turn-off is shown in (F) as switching loss 19 (the shaded area). The switching loss 19 that occurs from time t1 to time t5 is expressed as the integrated total value of the drain-source voltage and drain-source current of the power semiconductor elements 1a and 1b.

[0040] In the conventional configuration, in order to suppress the drain-source voltage of the power semiconductor elements 1a and 1b below the allowable voltage, the second charging circuit 20 was driven before time t3, as shown by the dashed line in (B), which slowed the switching speed of the power semiconductor elements 1a and 1b and increased switching losses. In contrast, in the present invention, the second charging circuit 20 is driven to suppress discharge of the gate voltage after the voltage between the main terminals of the parallel-connected power semiconductor elements 1a and 1b rises to a peak voltage at turn-off. This suppresses the resonant voltage source between the parallel-connected power semiconductor elements at turn-off, thereby reducing the increase in switching losses of the power semiconductor elements 1a and 1b compared to the conventional method without compromising noise reduction. This realizes stable switching operation that achieves high-speed switching, low EMC (low noise), and high efficiency.

[0041] (Figure 5) Fig. 5(a) shows an example of the configuration of a voltage detection circuit 30 that detects the voltage between the main terminals of parallel-connected power semiconductor elements 1a and 1b when turned off, and Fig. 5(b) shows an example of a gate drive waveform when using the voltage detection circuit 30. In Fig. 5(b), (A) shows an example of the waveform of the drain-source voltage of the power semiconductor elements 1a and 1b (Fig. 2), (B) shows an example of the waveform of voltage Vref when the drain-source voltage divided by resistors R1 and R2 in Fig. 5(a) is input to one end of comparator A1, (C) shows an example of the waveform of voltage Vpk when the drain-source voltage divided by resistors R1 and R2 in Fig. 5(a) is input to the other end of comparator A1 via diode Di1, (D) shows an example of the waveform of a control terminal 30c connected to the control circuit 10 (Fig. 2), and (E) shows an example of the waveform of an output terminal 30d connected to the second charging circuit 20 (Fig. 2). The waveforms will be described below using the configurations shown in FIGS. 2 and 3 above.

[0042] The voltage detection circuit 30 is connected to the drain terminal Dp and source terminal Sp of the power semiconductor elements 1a and 1b. The drain terminal Dp is connected to one end of a voltage dividing resistor R1, and the source terminal Sp is connected to one end of a voltage dividing resistor R2.

[0043] The other ends of the voltage-dividing resistors R1 and R2 are connected to one end of the comparator A1 and one end of the blocking diode Di1. The other end of the blocking diode Di1 is connected to the switching element M5, the capacitor C1, the discharge resistor R5, and the other end of the comparator A1, respectively.

[0044] The gate terminal of switching element M5 is connected to control terminal 30c. The output terminal 30d is connected to input terminal 20a of second charging circuit 20. The circuit configuration of voltage detection circuit 30 is not limited to the configuration shown in Fig. 5, and may be any configuration that detects the peak voltages of power semiconductor elements 1a and 1b and outputs an ON signal from output terminal 30d.

[0045] An example of a gate drive waveform when using the voltage detection circuit 30 shown in FIG. 5(b) will be described. At time t0, an OFF signal is input from the control circuit 10 to the control terminal 30c as shown in (D), causing the drain-source voltage to rise as shown in (A). As a result, the drain-source voltage Vref, which is input from the drain terminal Dp and the source terminal Sp to the voltage-dividing resistors R1 and R2 and then divided, is applied to one end of the comparator A1. The drain-source voltage Vref is also applied to the other end of the comparator A1 as the voltage Vpk via the diode Di1. While the drain-source voltage is rising, the voltage Vref and the voltage Vpk are at the same potential as shown in (B) and (C), so the comparator A1 outputs 0 to the output terminal 30d as shown in (E).

[0046] At time t1, as shown in (A), when the drain-source voltage reaches the peak voltage and starts to decrease, as shown in (B), the voltage Vref also starts to decrease following this. On the other hand, as shown in (C), the voltage Vpk, because it passes through the reverse-current prevention diode Di1, starts to decrease according to the time constant of the discharge resistor R5 and the capacitor C1 while maintaining the peak voltage. Therefore, the voltage between time t1 and time t2 is Vref < Vpk. As a result, as shown in (E), the comparator A1 outputs an on signal to the output terminal 30d, the second charging circuit 20 is driven, and the discharge of the power semiconductor elements 1a, 1b is suppressed.

[0047] At time t2, as shown in (D), an on signal is input from the control circuit 10 to the control terminal 30c at the timing (time t4) when the gate-source voltage in the aforementioned Figure 4(C) decreases. From this, as shown in (B) and (C), the voltage values become Vpk = Vref, and as shown in (E), the switching element M5 turns off and the comparator A1 outputs 0.

[0048] In this way, the driving of the second charging circuit 20 is controlled based on the detected value of the voltage between the main circuit terminals of the power semiconductor elements 1a, 1b detected by the voltage detection circuit 30. Note that the timing to turn off the switching element M5 can be arbitrarily determined on the control side. With such a configuration of the voltage detection circuit 30, it is possible to appropriately control the time to turn on and the time to turn off the second charging circuit 20 by detecting the peak voltage of the drain-source voltage.

[0049] (Second Embodiment) (Figure 6) In the following configuration of the second embodiment, the same parts as those in FIG. 2 will not be described. The gate drive circuit 11 has an active Miller clamp circuit 25. One end of the active Miller clamp circuit 25 is connected to the gate terminal 5, and the other end of the active Miller clamp circuit 25 is connected to the source terminal 6. The second charging circuit 20 is driven before the active Miller clamp circuit 25 is driven. The active Miller clamp circuit 25 clamps the gate voltages of the power semiconductor elements 1a and 1b to the off state after turning off, thereby maintaining the gate potential and source potential of the power semiconductor elements 1a and 1b at the same potential. This prevents erroneous turn-on of the power semiconductor elements 1a and 1b.

[0050] (Modification of the second embodiment) (Fig. 7, Fig. 8) The gate drive circuit 11 may be provided with a comparator A2 that compares the voltage at the drain terminal D1 of the switching element M1 with a reference voltage input from the control circuit 10 via the control terminal 24. When the voltage at the drain terminal D1 falls below the reference voltage, the comparator A2 outputs an ON signal to the gate signal of the active Miller clamp circuit 25, thereby driving the second charging circuit 20.

[0051] 8 illustrates gate drive waveforms including the active Miller clamp circuit 25 for a modified example of the second embodiment. Note that (A) shows an example of the waveform at the control terminal 23 of the gate drive circuit 11, (B) shows an example of the waveform at the control terminal 24 of the gate drive circuit 11, and (C) shows an example of the waveform of the gate-source voltage of the power semiconductor elements 1a and 1b.

[0052] At time t0, as shown in (A), an ON signal is output from the control circuit 10 to the control terminal 23, thereby driving the second charging circuit 20. At this time, as shown in (C), the gate-source voltages of the power semiconductors 1a and 1b decrease from the mirror voltage 13 and are maintained at the holding voltage 15, thereby suppressing discharge.

[0053] At time t1, as shown in (A), an OFF signal is output from control circuit 10 to control terminal 23, turning off second charging circuit 20. As a result, the gate-source voltages of power semiconductor elements 1a and 1b start to decrease from holding voltage 15 as shown in (C).

[0054] At time t2, the gate-source voltage falls below clamp voltage 17 as shown in (C), and as shown in (B), an ON signal is output from control circuit 10 to control terminal 24, turning on active mirror clamp circuit 25. After falling below clamp voltage 17, the gate-source voltage decreases to the source potential. The threshold voltage value of holding voltage 15 is determined so that the relationship is mirror voltage 13 > holding voltage 15 > clamp voltage 17.

[0055] With this configuration, the second charging circuit 20 is appropriately controlled to operate before the active Miller clamp circuit 25, which clamps the gate voltages of the power semiconductor elements 1a and 1b to the off state, thereby reducing the rate of change of current in the power semiconductor elements 1a and 1b by suppressing discharge, reducing the potential difference due to the source inductance difference, suppressing increases in switching loss, suppressing resonance, and preventing false turn-on.

[0056] (Third embodiment) (Figure 9) The configuration of the present invention can also be applied during turn-on. Such a configuration will be explained using the following waveforms. (A) shows an example of the voltage waveform at signal terminal 21 of gate drive circuit 11, (B) shows an example of the voltage waveform at input terminal 20a of second charging circuit 20, (C) shows an example of the voltage waveform between the gate and source of power semiconductor elements 1a and 1b, (D) shows an example of the voltage waveform between the drain and source of power semiconductor elements 2a and 2b (FIG. 1), which are the paired arms of power semiconductor elements 1a and 1b, (E) shows an example of the current waveform between the drain and source of power semiconductor elements 1a and 1b, and (F) shows the switching loss of power semiconductor elements 1a and 1b.

[0057] At time t0, as shown in (A), a turn-on voltage command is input from control circuit 10 to signal terminal 23, and as shown in (B), a voltage command to turn on second charging circuit 20 is input from control circuit 10 to input terminal 20a of second charging circuit 20. As a result, the gate-source voltage of power semiconductor element 1 begins to increase as shown in (C), but because gate drive circuit 11 and second charging circuit 20 are both driven, the gate charging speed increases between time t1 and time t2.

[0058] At time t1, when the value of the gate-source voltage of power semiconductor elements 1a and 1b, which increases as shown in (C), exceeds threshold voltage 14, the drain-source current of power semiconductor elements 1a and 1b begins to increase as shown in (E). Accordingly, the drain-source voltage of power semiconductor elements 2a and 2b begins to increase as shown in (D).

[0059] At time t2, the drain-source voltage of power semiconductor elements 2a and 2b becomes the allowable voltage 18, as shown in (D). This is detected by voltage detection circuit 30, which then outputs an OFF command to second charging circuit 20, turning off second charging circuit 20, as shown in (B). As a result, it can be seen that the increase in the gate-source voltage of power semiconductor elements 1a and 1b is suppressed between time t2 and time t3, as shown in (C). As shown in (D), the drain-source voltage of power semiconductor elements 2a and 2b becomes lower than the allowable voltage 18, and then becomes a constant voltage. Furthermore, as shown in (E), the drain-source current of power semiconductor elements 1a and 1b also becomes a constant voltage.

[0060] At time t3, as shown in (B), the gate-source voltage of the power semiconductor elements 1a and 1b increases again, indicating that the gate-source capacitance is being charged. At time t4, gate charging is completed, thereby ending the turn-on that began at time t0.

[0061] The timing at which an ON voltage command is input to input terminal 20a of second charging circuit 20 may be earlier than time t0. The timing at which an OFF voltage command is input to input terminal 20a may be later than time t2. The voltage applied between the gate and source of power semiconductor elements 1a, 1b when second charging circuit 20 is turned on is determined based on the ratio between ON gate resistance R1 of gate drive circuit 11 and charge / discharge gate resistance R3 of second charging circuit 20.

[0062] In this way, not only during turn-off but also during turn-on, the gate drive circuit 11 and second charging circuit 20 are turned on from time t0 to time t2, and only the second charging circuit 20 is turned off at time t2, thereby preventing the charging rate of the gate capacitance from increasing too much from time t2 to time t3. Also, compared to the conventional dashed line in which the on-gate resistance R1 is increased to keep the drain-source voltage below the allowable voltage 18, in the present invention, the period in which switching loss 19 occurs is from time t1 to time t4, which is a shorter period of loss occurrence than in the conventional case, and therefore the amount of loss can be reduced compared to the conventional case.

[0063] According to the embodiment of the present invention described above, the following advantageous effects are achieved.

[0064] (1) A gate drive circuit 11 for driving semiconductor elements electrically connected in parallel and having gates includes a charging circuit M1 that charges the gates of semiconductor elements 1a and 1b based on a control command, a discharging circuit M2 that discharges the gates, and a second charging circuit 20 that additionally charges the gates in response to the charging and discharging of the gates, and the second charging circuit 20 suppresses the discharge rate of the gates after the voltage between the main circuit terminals of semiconductor elements 1a and 1b rises to a peak voltage during gate discharging. This configuration provides a gate drive circuit that suppresses resonance, reduces loss, and reduces noise.

[0065] (2) A voltage detection circuit 30 is provided to detect the voltage between the main circuit terminals of the semiconductor elements 1a and 1b, and the driving of the second charging circuit 20 is controlled based on the detected value of the voltage between the main circuit terminals detected by the voltage detection circuit 30. This makes it possible to reliably suppress discharge when discharging the gates of the semiconductor elements 1a and 1b at turn-off.

[0066] (3) The active Miller clamp circuit 25 that clamps the gate voltage to the off state is provided, and the second charging circuit 20 is activated before the active Miller clamp circuit 25 is activated. This configuration makes it possible to suppress discharge of the semiconductor elements 1a and 1b when they are turned off, while also preventing erroneous turn-on.

[0067] (4) When the semiconductor elements 1a and 1b are in the ON state, the second charging circuit 20 is driven to increase the gate charging speed, and controls it based on the detection value of the voltage detection circuit 30. This reduces the switching loss of the semiconductor elements 1a and 1b when they are turned on.

[0068] The present invention is not limited to the above-described embodiments, and various modifications and combinations of other configurations are possible without departing from the spirit of the present invention. Furthermore, the present invention is not limited to those having all of the configurations described in the above-described embodiments, and includes those in which some of the configurations are omitted. [Explanation of symbols]

[0069] 1. First power semiconductor element 2 Second power semiconductor element 3 Positive terminal 4 Negative terminal 5 Gate terminal 6 Source terminal 7 Output terminal 8 Drain terminal 9 Control terminal 10 Control circuit 11 Gate drive circuit 12 Power supply voltage 13 Mirror Voltage 14 Threshold voltage 15 Holding voltage 16 Tail current 17 Clamping Voltage 18 Allowable voltage 19 Switching losses 20 Second charging circuit 20a Input terminal 20b Output terminal 21 Signal terminal 1 22 Signal terminal 2 23 Signal terminal 24 Control terminal (signal terminal) 25 Active Miller Clamp Circuit 30 Voltage detection circuit 30c control terminal 30d output terminal 50 Power semiconductor device 100 inverters A1, A2 Comparator

Claims

1. A gate drive circuit for driving semiconductor elements electrically connected in parallel and having gates, the gate drive circuit includes a charging circuit that charges the gate and a discharging circuit that discharges the gate based on a control command, and a second charging circuit that additionally charges the gate in response to the charging and discharging of the gate; The second charging circuit suppresses the discharge rate of the gate after the voltage between the main circuit terminals of the semiconductor element rises to a peak voltage during the discharge of the gate. Gate drive circuit.

2. 2. The gate drive circuit of claim 1, a voltage detection circuit for detecting a voltage between main circuit terminals of the semiconductor element; The driving of the second charging circuit is controlled based on the detected value of the voltage between the main circuit terminals detected by the voltage detection circuit. Gate drive circuit.

3. 2. The gate drive circuit of claim 1, an active Miller clamp circuit that clamps the voltage of the gate to an off state; The second charging circuit is activated before the active Miller clamp circuit is activated. Gate drive circuit.

4. 3. The gate drive circuit according to claim 2, The second charging circuit is driven to increase the charging speed of the gate when the semiconductor element is in an on-state, and controls the charging speed based on the detected value. Gate drive circuit.

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