Semiconductor device

Abstract

To reduce the threshold voltage of an LDMOSFET without lowering its off-state breakdown voltage of the LDMOSFET.SOLUTION: A semiconductor device has an offset drain region OD and a p-type well PWL. In the gate length direction of a gate electrode, a first distance between the offset drain region OD and a first portion P1 of the p-type well PWL is greater than a second distance between the offset drain region OD and a second portion P2 of the p-type well PWL. The semiconductor device has an n-type semiconductor region NR formed within a portion of an epitaxial layer EPI located between the offset drain region OD and a source region SR.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device including, for example, a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET). [Background technology]

[0002] Japanese Patent Application Laid-Open No. 2020-129597 (Patent Document 1) describes a technology related to a semiconductor device including an LDMOSFET. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-129597 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, in a semiconductor device including an LDMOSFET, it is desired to reduce the threshold voltage of the LDMOSFET without reducing the off-state breakdown voltage of the LDMOSFET.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] In one embodiment, a semiconductor device includes a p-type well having a first portion and a second portion, and an n-type semiconductor region formed in a semiconductor substrate and disposed between offset drain and source regions. [Effects of the Invention]

[0007] According to a semiconductor device including an LDMOSFET in one embodiment, the threshold voltage of the LDMOSFET can be reduced without reducing the off-state breakdown voltage of the LDMOSFET. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a diagram showing the configuration of a constant current source formed of a resistance element. [Figure 2] 2 is a graph showing current-voltage characteristics in the constant current source shown in FIG. [Figure 3] FIG. 1 is a diagram showing the configuration of a constant current source configured by combining a depletion-type MOSFET and a resistance element. [Figure 4] 4 is a graph showing current-voltage characteristics in the constant current source shown in FIG. 3. [Figure 5] FIG. 1 is a plan view showing an LDMOSFET according to a first related technique. [Figure 6] FIG. 6 is a cross-sectional view of the LDMOSFET taken along line AA in FIG. 5. [Figure 7] FIG. 6 is a cross-sectional view of the LDMOSFET taken along line BB in FIG. 5. [Figure 8] FIG. 6 is a cross-sectional view of the LDMOSFET taken along line CC in FIG. 5. [Figure 9] FIG. 10 is a plan view showing an LDMOSFET according to a second related technique. [Figure 10] FIG. 10 is a cross-sectional view of the LDMOSFET taken along line AA in FIG. 9. [Figure 11] FIG. 10 is a cross-sectional view of the LDMOSFET taken along line BB in FIG. 9. [Figure 12] FIG. 10 is a cross-sectional view of the LDMOSFET taken along line CC in FIG. [Figure 13] FIG. 1 is a plan view showing an LDMOSFET according to a first embodiment. [Figure 14] FIG. 14 is a cross-sectional view of the LDMOSFET taken along line AA in FIG. 13. [Figure 15] FIG. 14 is a cross-sectional view of the LDMOSFET taken along line BB in FIG. [Figure 16]FIG. 14 is a cross-sectional view of the LDMOSFET taken along line CC in FIG. [Figure 17] FIG. 10 is a plan view showing an LDMOSFET according to a modified example. [Figure 18] FIG. 18 is a cross-sectional view of the LDMOSFET taken along line AA in FIG. 17. [Figure 19] FIG. 18 is a cross-sectional view of the LDMOSFET taken along line BB in FIG. 17. [Figure 20] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 21] 21 is a diagram showing the manufacturing process of the semiconductor device following FIG. 20. [Figure 22] 22 is a diagram showing the manufacturing process of the semiconductor device following FIG. 21. [Figure 23] 23 is a diagram showing the manufacturing process of the semiconductor device following FIG. 22. [Figure 24] 24 is a diagram showing the manufacturing process of the semiconductor device following FIG. 23. [Figure 25] 25 is a diagram showing the manufacturing process of the semiconductor device following FIG. 24. [Figure 26] 10A and 10B are diagrams illustrating an example of the configuration of an opening for forming an n-type semiconductor region. [Figure 27] 10A and 10B are diagrams showing other configuration examples of openings for forming n-type semiconductor regions. [Figure 28] 10A and 10B are diagrams showing other configuration examples of the opening for forming the n-type semiconductor region. [Figure 29] FIG. 10 is a plan view showing an LDMOSFET according to a second embodiment. [Figure 30] FIG. 30 is a cross-sectional view of the LDMOSFET taken along line AA in FIG. 29. [Figure 31] FIG. 30 is a cross-sectional view of the LDMOSFET taken along line BB in FIG. 29. [Figure 32] FIG. 30 is a cross-sectional view of the LDMOSFET taken along line CC in FIG. 29. [Figure 33] FIG. 11 is a plan view showing an LDMOSFET according to a third embodiment. [Figure 34] FIG. 34 is a cross-sectional view of the LDMOSFET taken along line AA in FIG. 33. [Figure 35] FIG. 34 is a cross-sectional view of the LDMOSFET taken along line BB in FIG. 33. [Figure 36] FIG. 34 is a cross-sectional view of the LDMOSFET taken along line CC in FIG. 33. [Figure 37] 14 and 34, and (b) is a diagram showing the impurity profile in the epitaxial layer in the depth direction in FIGS. 15 and 35. [Figure 38] FIG. 1 is a diagram showing a main current and a sub-current flowing in a source region in an LDMOSFET having a p-type well and an n-type semiconductor region that are configured in a "ladder structure" having a first portion and a second portion. [Figure 39] 11 is a graph showing the current-voltage characteristics of a main current and the current-voltage characteristics of a sub-current in the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] In all the drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations thereof will be omitted. In addition, hatching may be used even in plan views to make the drawings easier to understand.

[0010] <The usefulness of depletion-type field-effect transistors> Known field effect transistors are depletion-type field effect transistors and enhancement-type field effect transistors. When a "depletion-type field effect transistor" is an n-channel field effect transistor, the "depletion-type field effect transistor" has a negative threshold voltage. On the other hand, when an "enhanced-type field effect transistor" is an n-channel field effect transistor, the "enhanced-type field effect transistor" has a positive threshold voltage. A "depletion-type field effect transistor" is also called a normally-on transistor. An "enhanced-type field effect transistor" is also called a normally-off transistor.

[0011] For example, a depletion-type field-effect transistor is used in a constant current source. Hereinafter, it will be described with reference to the drawings that the use of a depletion-type field-effect transistor in a constant current source can reduce the power consumption of a semiconductor device.

[0012] FIG. 1 is a diagram showing the configuration of a constant current source composed of a resistive element R. In FIG. 1, the resistive element R is electrically connected to a circuit. A power supply voltage VIN is applied to the circuit via the resistive element R. In this case, a current I (=VIN / R) is supplied to the circuit.

[0013] In the constant current source shown in Figure 1, the resistance value of the resistor element R must be set so that it can supply the current necessary for circuit operation even at the minimum product voltage Vmin of the power supply voltage VIN.

[0014] As shown in area "A" in Figure 2, in a constant current source made up of a resistor element R, when the magnitude of the power supply voltage VIN input to the resistor element R increases, the current flowing in the circuit increases. In other words, excessive current flows in the circuit, and in a constant current source made up of a resistor element R, the power consumption of the semiconductor device increases.

[0015] FIG. 3 is a diagram showing the configuration of a constant current source composed of a depletion-type MOSFET 10 and a resistor R. In FIG. 3, the depletion-type MOSFET 10 and the resistor R are electrically connected in a circuit. A power supply voltage VIN is applied to the circuit via the depletion-type MOSFET 10 and the resistor R. In this case, the power supply voltage VIN is applied to the drain of the depletion-type MOSFET 10. The resistor R is connected to the source of the depletion-type MOSFET 10.

[0016] The current supplied to the circuit from the constant current source configured in this manner depends on the current-voltage characteristics of the depletion-type MOSFET 10. Specifically, as shown in FIG. 4, the current supplied to the circuit from the constant current source increases in proportion to the magnitude of the power supply voltage V in a range where the power supply voltage V is small (linear region). In contrast, as shown in FIG. 4, the current supplied to the circuit from the constant current source remains almost constant regardless of the magnitude of the power supply voltage V in a range where the power supply voltage V is large (saturation region). Therefore, in the constant current source shown in FIG. 3, the current value hardly changes even if the power supply voltage V increases in the saturation region. Because excessive current does not flow in the circuit, a constant current source using the depletion-type MOSFET 10 can reduce the power consumption of a semiconductor device.

[0017] Here, in a constant current source using the depletion-type MOSFET 10, it is desirable to reduce the threshold voltage of the depletion-type MOSFET Q.

[0018] The reason why it is desirable to reduce the threshold voltage of the depletion-type MOSFET 10 will be explained below.

[0019] The depletion-type MOSFET 10, which is an n-channel MOSFET, has a negative threshold voltage. Increasing the absolute value of the negative threshold voltage of the depletion-type MOSFET 10 can increase the operating margin of a constant current source using the depletion-type MOSFET 10.

[0020] For example, suppose the threshold voltage of the depletion-mode MOSFET 10 is −0.3 V. Also, suppose the threshold voltage of the depletion-mode MOSFET 10 varies by ±200 mV due to process or temperature. In this case, the absolute value of the threshold voltage of the depletion-mode MOSFET 10 is smallest when the threshold voltage of the depletion-mode MOSFET 10 is −0.1 V. In contrast, the absolute value of the threshold voltage of the depletion-mode MOSFET 10 is largest when the threshold voltage of the depletion-mode MOSFET 10 is −0.5 V. The start-up time of the constant current source varies depending on whether the threshold voltage of the depletion-mode MOSFET 10 is −0.1 V or −0.5 V. For example, if the resistance of the resistor R is 300 kΩ, the maximum current value is 1.67 μA. On the other hand, the minimum current value is 333nA. This difference in current value causes variations in the startup time of the constant current source.

[0021] In this regard, let us assume that the threshold voltage of the depletion-mode MOSFET 10 is −0.6 V. Let us also assume that the threshold voltage of the depletion-mode MOSFET 10 varies by ±200 mV due to process or temperature. In this case, the absolute value of the threshold voltage of the depletion-mode MOSFET 10 is smallest when the threshold voltage of the depletion-mode MOSFET 10 is −0.4 V. In contrast, the absolute value of the threshold voltage of the depletion-mode MOSFET 10 is largest when the threshold voltage of the depletion-mode MOSFET 10 is −0.8 V. The difference between the maximum and minimum current values ​​when the threshold voltage of the depletion-mode MOSFET 10 varies between −0.4 V and −0.8 V is smaller than the difference between the maximum and minimum current values ​​when the threshold voltage of the depletion-mode MOSFET 10 varies between −0.1 V and −0.5 V. As a result, when the threshold voltage of the depletion-type MOSFET 10 varies between "-0.4V" and "-0.8V", the variation in the start-up time of the constant current source can be reduced more than when the threshold voltage of the depletion-type MOSFET 10 varies between "-0.1V" and "-0.5V".

[0022] From the above, it is desirable to reduce the threshold voltage of the depletion-type MOSFET 10 in order to reduce the variation in the start-up time of the constant current source.

[0023] <First Related Art> For example, a depletion-mode MOSFET used in a constant current source can be composed of an LDMOSFET. A first related technology relating to an LDMOSFET constituting a depletion-mode MOSFET will be described below. In this specification, the "first related technology" refers to a technology that is not publicly known, but has a problem discovered by the present inventor, and is the technology that forms the premise of this disclosure.

[0024] FIG. 5 is a plan view showing an LDMOSFET 100A according to the first related art.

[0025] In FIG. 5, the LDMOSFET 100A has a drain region DR, a trench region STI, an offset drain region OD, an epitaxial layer EPI, a p-type well PWL, an n-type semiconductor region NR, a body contact region PR, and a source region SR.

[0026] The trench region STI is formed between the drain region DR and the offset drain region OD. An epitaxial layer EPI is formed between the offset drain region OD and the p-type well PWL. A p-type well PWL is formed so as to be in contact with the epitaxial layer EPI. A body contact region PR and a source region SR are formed in the p-type well PWL. The body contact regions PR and the source regions SR are alternately arranged along the Y direction. The n-type semiconductor region NR is in contact with the offset drain region OD, the epitaxial layer EPI, the p-type well PWL, the body contact region PR, and the source region SR. In this manner, the drain region DR, the trench region STI, the offset drain region OD, the epitaxial layer EPI, the p-type well PWL, the n-type semiconductor region NR, the body contact region PR, and the source region SR are formed.

[0027] FIG. 6 is a cross-sectional view of the LDMOSFET taken along line AA in FIG.

[0028] 6 corresponds to a cross-sectional view of the gate electrode GE in the gate length direction, and shows the configuration of a semiconductor device SA1 including an LDMOSFET 100A.

[0029] In FIG. 6, the semiconductor device SA1 has a p-type semiconductor substrate SUB, an n-type buried layer NBL, an epitaxial layer EPI, a deep p-type well HPW, a p-type well PWL, an n-type well NWL, an offset drain region OD, a source region SR, a drain region DR, an n-type semiconductor region NR, a trench region STI, a deep trench region DTI, a gate insulating film GOX, a gate electrode GE, a sidewall spacer SW, an interlayer insulating film IL, a plug PLG1, a plug PLG2, a wiring WL1, and a wiring WL2.

[0030] The epitaxial layer EPI is formed on a p-type semiconductor substrate SUB. The epitaxial layer EPI is composed of a p-type semiconductor layer into which p-type impurities (acceptors) are introduced. An n-type buried layer NBL is formed between the p-type semiconductor substrate SUB and the epitaxial layer EPI. The n-type buried layer NBL is composed of an n-type semiconductor layer into which n-type impurities (donors) are introduced. The n-type buried layer NBL may be formed in the p-type semiconductor substrate SUB or in the epitaxial layer EPI.

[0031] The deep p-type well HPW is formed in the epitaxial layer EPI. The impurity concentration of the deep p-type well HPW is higher than that of the epitaxial layer EPI. The p-type well PWL is formed in the epitaxial layer EPI. The impurity concentration of the p-type well PWL is higher than that of the epitaxial layer EPI. The p-type well PWL is formed above the deep p-type well HPW and is separated from the deep p-type well HPW. The source region SR is formed in the p-type well PWL. The source region SR is composed of an n-type semiconductor region.

[0032] The n-type well NWL and the offset drain region OD are each formed in the epitaxial layer EPI. The offset drain region OD is composed of an n-type semiconductor region. The impurity concentration of the offset drain region OD is lower than the impurity concentration of the n-type well NWL. The offset drain region OD is separated from the p-type well PWL. The offset drain region OD is in contact with the n-type well NWL.

[0033] The trench region STI is formed in the offset drain region OD. The trench region STI includes a groove formed in the offset drain region OD and an insulating material filled in the groove. The drain region DR is formed in the offset drain region OD. The drain region DR is composed of an n-type semiconductor region. The drain region DR is in contact with the trench region STI. The impurity concentration of the drain region DR is higher than the impurity concentration of the offset drain region OD.

[0034] The n-type semiconductor region NR is formed in the epitaxial layer EPI. Specifically, the n-type semiconductor region NR is formed in the offset drain region OD, the p-type well PWL, and a portion of the epitaxial layer EPI located between the offset drain region OD and the p-type well PWL. The n-type semiconductor region NR is in contact with the source region SR. On the other hand, the n-type semiconductor region NR is separated from the trench region STI. However, the n-type semiconductor region NR may be in contact with the trench region STI.

[0035] The deep trench region DTI penetrates the epitaxial layer EPI and the n-type buried layer NBL and reaches the p-type semiconductor substrate SUB.

[0036] The gate insulating film GOX is formed on the n-type semiconductor region NR. The gate electrode GE is formed on the gate insulating film GOX and the trench region STI. The sidewall spacers SW are formed on the sidewalls of the gate electrode GE.

[0037] The interlayer insulating film IL is formed on the epitaxial layer EPI and covers the gate electrode GE. The plug PLG1 and the plug PLG2 each penetrate the interlayer insulating film IL. The plug PLG1 is in contact with the source region SR. This allows the plug PLG1 to be electrically connected to the source region SR. On the other hand, the plug PLG2 is in contact with the drain region DR. This allows the plug PLG2 to be electrically connected to the drain region DR.

[0038] The wiring WL1 and the wiring WL2 are each formed on an interlayer insulating film IL. The wiring WL1 is connected to a plug PLG1 and is electrically connected to the source region SR via the plug PLG1. The wiring WL2 is connected to a plug PLG2 and is electrically connected to the drain region DR via the plug PLG2. In this manner, the semiconductor device SA1 including the LDMOSFET 100A shown in FIG. 6 is configured.

[0039] FIG. 7 is a cross-sectional view of the LDMOSFET taken along line BB in FIG.

[0040] 7 corresponds to a cross-sectional view of the gate electrode GE in the gate length direction, and shows the configuration of a semiconductor device SA1 including an LDMOSFET 100A.

[0041] The configuration of the semiconductor device SA1 shown in FIG. 7 is almost the same as the configuration of the semiconductor device SA1 shown in FIG. 6, except that a body contact region PR is formed instead of the source region SR.

[0042] The body contact region PR is made of a p-type semiconductor region. The impurity concentration of the body contact region PR is higher than the impurity concentration of the p-type well PWL. The n-type semiconductor region NR is in contact with the body contact region PR.

[0043] The plug PLG3 is formed in the interlayer insulating film IL. The plug PLG3 is in contact with the body contact region PR and is electrically connected to the body contact region PR. The wiring WL3 is formed on the interlayer insulating film IL. The wiring WL3 is connected to the plug PLG3 and is electrically connected to the body contact region PR via the plug PLG3.

[0044] For example, the wiring WL1 shown in FIG. 6 and the wiring WL3 shown in FIG. 7 are electrically connected to each other. Therefore, the source region SR and the body contact region PR are electrically connected to each other. In other words, the same potential is supplied to the source region SR and the body contact region PR. In this manner, the semiconductor device SA1 including the LDMOSFET 100A shown in FIG. 7 is configured.

[0045] FIG. 8 is a cross-sectional view of the LDMOSFET taken along line CC in FIG.

[0046] Fig. 8 corresponds to a cross-sectional view of the gate electrode GE in the gate width direction, and shows the configuration of a semiconductor device SA1 including an LDMOSFET 100A.

[0047] As shown in Fig. 8, a p-type well PWL is formed on the epitaxial layer EPI. An n-type semiconductor region NR is formed on the p-type well PWL. A gate insulating film GOX is formed on the n-type semiconductor region NR. A gate electrode GE is formed on the gate insulating film GOX. In this manner, a semiconductor device SA1 including the LDMOSFET 100A shown in Fig. 8 is configured.

[0048] <Room for improvement in related technology 1> In the first related art, for example, as shown in FIG. 5, the threshold voltage of an LDMOSFET 100A can be reduced by forming an n-type semiconductor region NR. The LDMOSFET 100A is an n-channel MOSFET. The LDMOSFET 100A includes an accumulation layer made of an offset drain region OD and an n-type semiconductor region NR in a channel formation region directly below the gate electrode GE. Therefore, even when 0 V is applied to the gate electrode GE, a channel made of the accumulation layer and the n-type semiconductor region NR exists. Therefore, the LDMOSFET 100A is a depletion-type MOSFET with a negative threshold voltage.

[0049] When a negative voltage is applied to the gate electrode GE, an electrical repulsive force repels electrons in the n-type semiconductor region NR away from the channel formation region. Therefore, when a predetermined negative voltage is applied to the gate electrode GE, the n-type semiconductor region NR, which constitutes part of the channel, is depleted. The depleted n-type semiconductor region NR functions as an insulating region. Therefore, when a predetermined negative voltage is applied to the gate electrode GE, a channel is less likely to form. In other words, the LDMOSFET 100A is turned off when a gate voltage lower than the threshold voltage is applied to the gate electrode GE. The threshold voltage of the LDMOSFET 100A can be controlled by adjusting the impurity concentration of the n-type semiconductor region NR. In other words, the first related technique can reduce the threshold voltage of the LDMOSFET 100A by appropriately designing the impurity concentration of the n-type semiconductor region NR. For these reasons, the first related technique can reduce the threshold voltage of the LDMOSFET 100A.

[0050] In this regard, the n-type semiconductor region NR is formed by doping the epitaxial layer EPI and the p-type well PWL with n-type impurities. Each of the epitaxial layer EPI and the p-type well PWL is a p-type semiconductor region doped with p-type impurities.

[0051] Therefore, in order to form the n-type semiconductor region NR in the epitaxial layer EPI and the p-type well PWL, it is necessary to increase the dose of the n-type impurity introduced into the epitaxial layer EPI and the p-type well PWL.

[0052] In particular, in the first related technology, n-type impurities are introduced into both the epitaxial layer EPI and the p-type well PWL. Here, the p-type impurity concentration of the p-type well PWL is higher than the p-type impurity concentration of the epitaxial layer EPI. Therefore, in the first related technology, in order to form the n-type semiconductor region NR, n-type impurities are also introduced into the p-type well PWL, which has a higher p-type impurity concentration than the epitaxial layer EPI. As a result, the dose of n-type impurities is increased.

[0053] Here, the n-type impurities introduced to form the n-type semiconductor region NR are introduced not only into the epitaxial layer EPI and the p-type well PWL, but also into the offset drain region OD constituting the accumulation layer. Because the offset drain region OD is an n-type semiconductor region, when the n-type impurities are introduced into the offset drain region OD, the n-type impurity concentration in the offset drain region OD increases. As a result, for example, a location with a high electric field intensity occurs in the offset drain region OD. This causes the location with the high electric field intensity to become a hot spot (weak spot), reducing the breakdown voltage of the LDMOSFET 100A.

[0054] The offset drain region OD improves the breakdown voltage of the LDMOSFET 100A. Specifically, in the LDMOSFET 100A, the offset drain region OD, which has an impurity concentration lower than that of the drain region DR, is formed between the drain region DR and the channel formation region, thereby increasing the distance between the channel formation region and the drain region DR. As a result, the LDMOSFET 100A can ensure a sufficient breakdown voltage between the source region SR and the drain region DR. Furthermore, as shown in FIG. 6, in the LDMOSFET 100A, the trench region STI is formed in the offset drain region OD, thereby further increasing the distance between the channel formation region and the drain region DR, thereby further improving the breakdown voltage between the source region SR and the drain region DR. The LDMOSFET 100A is a MOSFET used in applications requiring an appropriate breakdown voltage. Therefore, in the LDMOSFET 100A, it is desirable to avoid a decrease in the breakdown voltage between the source region SR and the drain region DR.

[0055] That is, while the first related technique can reduce the threshold voltage of the LDMOSFET 100A, which is a depletion-type MOSFET, it may result in a decrease in the breakdown voltage of the LDMOSFET 100A.

[0056] <Description of the second related art> Next, a second related technique will be described.

[0057] In this specification, the "second related technology" is a technology that is not publicly known, but has a problem that the inventor has discovered, and is a technology that is the premise of the present disclosure.

[0058] FIG. 9 is a plan view showing an LDMOSFET 100B according to the second related technology.

[0059] In FIG. 9, the LDMOSFET 100B has a drain region DR, a trench region STI, an offset drain region OD, an epitaxial layer EPI, a p-type well PWL, a body contact region PR, and a source region SR.

[0060] The trench region STI is formed between the drain region DR and the offset drain region OD. The offset drain region OD is formed between the trench region STI and the epitaxial layer EPI. A p-type well PWL is formed in the epitaxial layer EPI. Specifically, the p-type well PWL has a first portion P1 and a second portion P2.

[0061] 9, a first distance in the X direction between a first portion P1 of the p-type well PWL and the offset drain region OD is greater than a second distance in the X direction between a second portion P2 of the p-type well PWL and the offset drain region OD. In this specification, such a structure of the p-type well PWL consisting of the first portion P1 and the second portion P2 may be referred to as a "ladder structure."

[0062] In plan view, the source region SR partially overlaps with the first portion P1 of the p-type well PWL. The body contact region PR is formed in the second portion P2 of the p-type well PWL. The body contact region PR and the source region SR are alternately arranged along the Y direction. In this manner, the drain region DR, trench region STI, offset drain region OD, epitaxial layer EPI, p-type well PWL, body contact region PR, and source region SR are formed.

[0063] FIG. 10 is a cross-sectional view of the LDMOSFET taken along line AA in FIG.

[0064] Fig. 10 corresponds to a cross-sectional view of the gate electrode GE in the gate length direction. Fig. 10 shows the configuration of a semiconductor device SA2 including an LDMOSFET 100B.

[0065] In FIG. 10, the semiconductor device SA2 has a p-type semiconductor substrate SUB, an n-type buried layer NBL, an epitaxial layer EPI, a deep p-type well HPW, a p-type well PWL, an n-type well NWL, an offset drain region OD, a source region SR, a drain region DR, a trench region STI, a deep trench region DTI, a gate insulating film GOX, a gate electrode GE, a sidewall spacer SW, an interlayer insulating film IL, a plug PLG1, a plug PLG2, a wiring WL1, and a wiring WL2.

[0066] 10, in the second related technology, the channel formation region immediately below the gate electrode GE is composed of an accumulation layer made of the offset drain region OD and an epitaxial layer EPI. That is, the first portion P1 of the p-type well PWL does not constitute the channel formation region. Therefore, the first portion P1 of the p-type well PWL is not included in the channel formation region located between the source region SR and the offset drain region OD.

[0067] FIG. 11 is a cross-sectional view of the LDMOSFET taken along line BB in FIG.

[0068] Fig. 11 corresponds to a cross-sectional view of the gate electrode GE in the gate length direction. Fig. 11 shows the configuration of a semiconductor device SA2 including an LDMOSFET 100B.

[0069] In FIG. 11, the semiconductor device SA2 has a p-type semiconductor substrate SUB, an n-type buried layer NBL, an epitaxial layer EPI, a deep p-type well HPW, a p-type well PWL, an n-type well NWL, an offset drain region OD, a body contact region PR, a drain region DR, a trench region STI, a deep trench region DTI, a gate insulating film GOX, a gate electrode GE, a sidewall spacer SW, an interlayer insulating film IL, a plug PLG2, a plug PLG3, a wiring WL2, and a wiring WL3.

[0070] 11, in the second related technology, the p-type well PWL has a "ladder structure," so that the second portion P2 of the p-type well PWL includes a portion located between the body contact region PR and the offset drain region OD. That is, the epitaxial layer EPI and a part of the second portion P2 of the p-type well PWL exist between the body contact region PR and the offset drain region OD.

[0071] The p-type well PWL has a "ladder structure." Therefore, as shown in FIG. 10, the first portion P1 of the p-type well PWL does not exist between the source region SR and the offset drain region OD. In contrast, as shown in FIG. 11, the second portion P2 of the p-type well PWL exists between the body contact region PR and the offset drain region OD.

[0072] FIG. 12 is a cross-sectional view of the LDMOSFET taken along line CC in FIG.

[0073] Fig. 12 corresponds to a cross-sectional view of the gate electrode GE in the gate width direction. Fig. 12 shows the configuration of a semiconductor device SA2 including an LDMOSFET 100B.

[0074] As shown in FIG. 12, the second portions P2 of the p-type well PWL are formed in the epitaxial layer EPI. Specifically, the second portions P2 of the p-type well PWL are formed at predetermined intervals in the epitaxial layer EPI. The gate insulating film GOX is formed on the epitaxial layer EPI. The gate insulating film GOX is formed on the second portions P2 of the p-type well PWL, but is not formed on the first portions P1 of the p-type well PWL. The gate electrode GE is formed on the gate insulating film GOX.

[0075] <Room for improvement in the second related technology> The second related technology employs a p-type well PWL having a "ladder structure." For example, in FIG. 10, there is no p-type well PWL between the offset drain region OD and the source region SR, but an epitaxial layer EPI exists. This reduces the threshold voltage of the LDMOSFET 100B.

[0076] The p-type well PWL and the epitaxial layer EPI are each composed of a p-type semiconductor region. The impurity concentration of the p-type well PWL is higher than that of the epitaxial layer EPI. Therefore, if not only the epitaxial layer EPI but also a p-type well PWL with a higher impurity concentration than the epitaxial layer EPI exists between the offset drain region OD and the source region SR, a higher gate voltage is applied to the gate electrode GE to form an inversion layer on the surface of the p-type well PWL. This increases the threshold voltage of the LDMOSFET 100B. In this regard, in the second related technology, there is no p-type well PWL between the offset drain region OD and the source region SR, but instead an epitaxial layer EPI with a lower p-type impurity concentration than the p-type well PWL exists. As a result, the threshold voltage of the LDMOSFET 100B can be reduced.

[0077] However, unlike the first related technology, the second related technology does not have an n-type semiconductor region NR that contributes to reducing the threshold voltage of the LDMOSFET 100B. As a result, in the second related technology, the p-type impurity concentration of the epitaxial layer EPI determines the threshold voltage of the LDMOSFET 100B. The threshold voltage of the LDMOSFET 100B can be reduced by reducing the p-type impurity concentration of the epitaxial layer EPI. However, because the impurity concentration of the epitaxial layer EPI is lower than the p-type impurity concentrations of other p-type semiconductor regions, there is a limit to how much the impurity concentration of the epitaxial layer EPI can be reduced. In other words, the second related technology is more difficult to reduce the threshold voltage of the LDMOSFET 100B than the first related technology. On the other hand, the first related technology may result in a decrease in the breakdown voltage of the LDMOSFET 100A.

[0078] From the above, in order to reduce the threshold voltage of the LDMOSFET while ensuring a sufficient breakdown voltage of the LDMOSFET, there is room for improvement in both the first related technique and the second related technique.

[0079] Therefore, the technical idea of ​​reducing the threshold voltage of an LDMOSFET while ensuring a sufficient breakdown voltage of the LDMOSFET will be explained.

[0080] <Basic philosophy> The basic idea is to form an n-type semiconductor region NR in the epitaxial layer EPI between the offset drain region OD and the source region SR to reduce the threshold voltage of the LDMOSFET. Furthermore, in the basic idea, a p-type well PWL having a p-type impurity concentration higher than the p-type impurity concentration of the epitaxial layer EPI is not formed between the offset drain region OD and the source region SR.

[0081] Between the offset drain region OD and the source region SR, there is no p-type well PWL, but rather an epitaxial layer EPI with a p-type impurity concentration lower than that of the p-type well PWL. Therefore, the n-type semiconductor region NR can be formed without increasing the amount of n-type impurities introduced. In other words, even if the n-type semiconductor region NR is formed, the dose of n-type impurities introduced into the offset drain region OD can be reduced. As a result, according to the basic concept, electric field concentration caused by n-type impurities introduced into the offset drain region OD can be suppressed. Therefore, according to the basic concept, even if the n-type semiconductor region NR is formed to reduce the threshold voltage of the LDMOSFET, a decrease in the breakdown voltage of the LDMOSFET can be suppressed. In other words, the basic concept allows the threshold voltage of the LDMOSFET to be reduced while ensuring a sufficient breakdown voltage of the LDMOSFET.

[0082] A first embodiment that embodies the basic concept will be described below.

[0083] <First Embodiment> <<Configuration of semiconductor device>> FIG. 13 is a plan view showing the LDMOSFET 100 according to the first embodiment.

[0084] In FIG. 13, the LDMOSFET 100 has a drain region DR, a trench region STI, an offset drain region OD, an epitaxial layer EPI, a p-type well PWL, an n-type semiconductor region NR, a body contact region PR, and a source region SR.

[0085] The trench region STI is formed between the drain region DR and the offset drain region OD. The offset drain region OD is formed between the trench region STI and the epitaxial layer EPI. A p-type well PWL is formed in the epitaxial layer EPI. Specifically, the p-type well PWL has a first portion P1 and a second portion P2. As shown in FIG. 13, a first distance in the X direction between the first portion P1 of the p-type well PWL and the offset drain region OD is greater than a second distance (the distance in the X direction) between the second portion P2 of the p-type well PWL and the offset drain region OD in the X direction. In this way, the p-type well PWL is configured as a "ladder structure" having the first portion P1 and the second portion P2. That is, in the "ladder structure" referred to in this specification, a first distance between the offset drain region OD and a first portion P1 of the p-type well PWL in the gate length direction (X direction) of the gate electrode GE is greater than a second distance between the offset drain region OD and a second portion P2 of the p-type well PWL in the gate length direction (X direction) of the gate electrode GE. The first portion P1 of the p-type well PWL and the second portion P2 of the p-type well PWL are adjacent to each other in the gate width direction of the gate electrode GE.

[0086] In plan view, a source region SR is formed so as to partially overlap a first portion P1 of the p-type well PWL. A body contact region PR is formed in a second portion P2 of the p-type well PWL. The body contact regions PR and the source regions SR are alternately arranged along the Y direction. The body contact region PR is in contact with the source region SR. The source region SR and the body contact region PR are adjacent to each other in the gate width direction (Y direction) of the gate electrode GE.

[0087] In this manner, the drain region DR, the trench region STI, the offset drain region OD, the epitaxial layer EPI, the p-type well PWL, the body contact region PR, and the source region SR are formed.

[0088] Furthermore, in the first embodiment, an n-type semiconductor region NR is formed in the epitaxial layer EPI. The n-type semiconductor region NR partially overlaps with the offset drain region OD. The n-type semiconductor region NR is in contact with the source region SR. On the other hand, the n-type semiconductor region NR is not formed in the first portion P1 of the p-type well PWL or in the second portion P2 of the p-type well PWL. In this manner, the drain region DR, trench region STI, offset drain region OD, epitaxial layer EPI, p-type well PWL, n-type semiconductor region NR, body contact region PR, and source region SR are formed.

[0089] FIG. 14 is a cross-sectional view of the LDMOSFET taken along line AA in FIG.

[0090] 14 corresponds to a cross-sectional view of the gate electrode GE in the gate length direction, and shows the configuration of a semiconductor device SA including an LDMOSFET 100.

[0091] In FIG. 14, the semiconductor device SA has a p-type semiconductor substrate SUB, an n-type buried layer NBL, an epitaxial layer EPI, a deep p-type well HPW, a first portion P1 of the p-type well PWL, an n-type well NWL, an offset drain region OD, a source region SR, a drain region DR, an n-type semiconductor region NR, a trench region STI, a deep trench region DTI, a gate insulating film GOX, a gate electrode GE, a sidewall spacer SW, an interlayer insulating film IL, a plug PLG1, a plug PLG2, a wiring WL1, and a wiring WL2.

[0092] The epitaxial layer EPI is formed on a p-type semiconductor substrate SUB. The epitaxial layer EPI is composed of a p-type semiconductor layer into which p-type impurities (acceptors) are introduced. An n-type buried layer NBL is formed between the p-type semiconductor substrate SUB and the epitaxial layer EPI. The n-type buried layer NBL is composed of an n-type semiconductor layer into which n-type impurities (donors) are introduced. The n-type buried layer NBL may be formed in the p-type semiconductor substrate SUB or in the epitaxial layer EPI.

[0093] The deep p-type well HPW is formed in the epitaxial layer EPI. The impurity concentration of the deep p-type well HPW is higher than that of the epitaxial layer EPI. The first portion P1 of the p-type well PWL is formed in the epitaxial layer EPI. The impurity concentration of the first portion P1 of the p-type well PWL is higher than that of the epitaxial layer EPI. The first portion P1 of the p-type well PWL is formed above the deep p-type well HPW and is separated from the deep p-type well HPW. The source region SR partially overlaps with the first portion P1 of the p-type well PWL. The source region SR is composed of an n-type semiconductor region. An LDD region may be formed in the source region SR.

[0094] 14, the first portion P1 of the p-type well PWL is arranged so as not to overlap with the gate electrode GE. In other words, the first portion P1 of the p-type well PWL is not formed in the channel formation region located below the gate electrode GE.

[0095] The n-type well NWL and the offset drain region OD are each formed in the epitaxial layer EPI. The offset drain region OD is composed of an n-type semiconductor region. The impurity concentration of the offset drain region OD is lower than the impurity concentration of the n-type well NWL. The offset drain region OD is separated from the first portion P1 of the p-type well PWL. The offset drain region OD is in contact with the n-type well NWL.

[0096] The trench region STI is formed in the offset drain region OD. The trench region STI includes a groove formed in the offset drain region OD and an insulating material filled in the groove. The drain region DR is formed in the offset drain region OD. The drain region DR is composed of an n-type semiconductor region. The drain region DR is in contact with the trench region STI. The impurity concentration of the drain region DR is higher than the impurity concentration of the offset drain region OD.

[0097] The n-type semiconductor region NR is formed in the epitaxial layer EPI. Specifically, the n-type semiconductor region NR is formed in the offset drain region OD and across a portion of the epitaxial layer EPI located between the offset drain region OD and the source region SR. The n-type semiconductor region NR is in contact with the source region SR. On the other hand, the n-type semiconductor region NR is separated from the trench region STI. However, the n-type semiconductor region NR may be in contact with the trench region STI.

[0098] As described above, in the first embodiment, the channel formation region located below the gate electrode GE is composed of an accumulation layer made of the offset drain region OD and an n-type semiconductor region NR formed in the epitaxial layer EPI. This n-type semiconductor region NR is arranged so as not to be formed in the first portion P1 of the p-type well PWL.

[0099] The deep trench region DTI penetrates the epitaxial layer EPI and the n-type buried layer NBL and reaches the p-type semiconductor substrate SUB.

[0100] A gate insulating film GOX is formed on the n-type semiconductor region NR. A gate electrode GE is formed on the gate insulating film GOX and the trench region STI. Sidewall spacers SW are formed on the side walls of the gate electrode GE. A channel formation region is located below the gate electrode GE. The channel formation region is composed of an accumulation layer made up of an offset drain region OD and the n-type semiconductor region NR.

[0101] The interlayer insulating film IL is formed on the epitaxial layer EPI and covers the gate electrode GE. The plug PLG1 and the plug PLG2 each penetrate the interlayer insulating film IL. The plug PLG1 is in contact with the source region SR. This allows the plug PLG1 to be electrically connected to the source region SR. On the other hand, the plug PLG2 is in contact with the drain region DR. This allows the plug PLG2 to be electrically connected to the drain region DR.

[0102] The wiring WL1 and the wiring WL2 are each formed on an interlayer insulating film IL. The wiring WL1 is connected to a plug PLG1 and is electrically connected to the source region SR via the plug PLG1. The wiring WL2 is connected to a plug PLG2 and is electrically connected to the drain region DR via the plug PLG2. In this manner, the semiconductor device SA including the LDMOSFET 100 shown in FIG. 14 is configured.

[0103] FIG. 15 is a cross-sectional view of the LDMOSFET taken along line BB in FIG.

[0104] Fig. 15 corresponds to a cross-sectional view of the gate electrode GE in the gate length direction. Fig. 15 shows the configuration of a semiconductor device SA including an LDMOSFET 100. Except for the fact that a body contact region PR is formed instead of the source region SR, the configuration of the semiconductor device SA shown in Fig. 15 is substantially the same as the configuration of the semiconductor device SA shown in Fig. 14.

[0105] The body contact region PR is made of a p-type semiconductor region, and the impurity concentration of the body contact region PR is higher than the impurity concentration of the p-type well PWL.

[0106] The second portion P2 of the p-type well PWL includes the body contact region PR and partially overlaps with the gate electrode GE.

[0107] The n-type semiconductor region NR is formed in the epitaxial layer EPI. Specifically, the n-type semiconductor region NR is formed in the offset drain region OD and in a portion of the epitaxial layer EPI located between the offset drain region OD and the second portion P2 of the p-type well PWL. The n-type semiconductor region NR is in contact with the second portion of the p-type well PWL. However, the n-type semiconductor region NR is arranged so as not to be formed in the second portion P2 of the p-type well PWL. As a result, the n-type semiconductor region NR is separated from the body contact region PR formed in the second portion P2 of the p-type well PWL.

[0108] The plug PLG3 is formed in the interlayer insulating film IL. The plug PLG3 is in contact with the body contact region PR and is electrically connected to the body contact region PR. The wiring WL3 is formed on the interlayer insulating film IL. The wiring WL3 is connected to the plug PLG3 and is electrically connected to the body contact region PR via the plug PLG3.

[0109] For example, the wiring WL1 shown in FIG. 14 and the wiring WL3 shown in FIG. 15 are electrically connected to each other. Therefore, the source region SR and the body contact region PR are electrically connected to each other. In other words, the same potential is supplied to the source region SR and the body contact region PR. In this manner, the semiconductor device SA including the LDMOSFET 100 shown in FIG. 15 is configured.

[0110] FIG. 16 is a cross-sectional view of the LDMOSFET taken along line CC in FIG.

[0111] 16 corresponds to a cross-sectional view of the gate electrode GE in the gate width direction, and shows the configuration of a semiconductor device SA including an LDMOSFET 100.

[0112] As shown in FIG. 16, the second portions P2 of the p-type well PWL are formed in the epitaxial layer EPI. Specifically, the second portions P2 of the p-type well PWL are formed at predetermined intervals in the epitaxial layer EPI. In the epitaxial layer EPI, an n-type semiconductor region NR is formed in a portion between the second portions P2 of the p-type well PWL adjacent to each other. A gate insulating film GOX is formed on the epitaxial layer EPI. Specifically, the gate insulating film GOX is formed on the second portions P2 of the p-type well PWL and on the n-type semiconductor region NR. A gate electrode GE is formed on the gate insulating film GOX.

[0113] The semiconductor device SA according to the first embodiment is configured as described above.

[0114] <<Modifications>> Fig. 17 is a plan view showing an LDMOSFET 100M according to a modification of the first embodiment. In Fig. 17, the LDMOSFET 100M includes a drain region DR, a trench region STI, an offset drain region OD, an epitaxial layer EPI, a p-type well PWL, an n-type semiconductor region NR, a body contact region PR, and a source region SR.

[0115] 13, the source region SR and the body contact region PR are adjacent to each other in the Y direction. That is, the source region SR and the body contact region PR are adjacent to each other in the gate width direction of the gate electrode GE.

[0116] 17, in this modification, the source region SR and the body contact region PR are adjacent to each other in the X direction. That is, the source region SR and the body contact region PR are adjacent to each other in the gate length direction of the gate electrode GE.

[0117] FIG. 18 is a cross-sectional view of the LDMOSFET taken along line AA in FIG.

[0118] Fig. 18 corresponds to a cross-sectional view of the gate electrode GE in the gate length direction. Fig. 18 shows the configuration of a semiconductor device SB including an LDMOSFET 100M.

[0119] In FIG. 18, the semiconductor device SB has a p-type semiconductor substrate SUB, an n-type buried layer NBL, an epitaxial layer EPI, a deep p-type well HPW, a first portion P1 of the p-type well PWL, an n-type well NWL, an offset drain region OD, a source region SR, a drain region DR, an n-type semiconductor region NR, a trench region STI, a deep trench region DTI, a gate insulating film GOX, a gate electrode GE, a sidewall spacer SW, an interlayer insulating film IL, a plug PLG1, a plug PLG2, a plug PLG3, a wiring WL, and a wiring WL2.

[0120] 18, the source region SR is formed in the epitaxial layer EPI so as to partially overlap with the first portion P1 of the p-type well PWL. On the other hand, the body contact region PR is formed in the first portion P1 of the p-type well PWL. The source region SR and the body contact region PR are in contact with each other.

[0121] The source region SR is connected to a plug PLG1. The body contact region PR is connected to a plug PLG3. The plug PLG1 and the plug PLG3 are each electrically connected to a wiring WL. As a result, the source region SR and the body contact region PR are electrically connected to each other. Therefore, the same potential is supplied to the source region SR and the body contact region PR.

[0122] FIG. 19 is a cross-sectional view of the LDMOSFET taken along line BB in FIG.

[0123] Fig. 19 corresponds to a cross-sectional view of the gate electrode GE in the gate length direction. Fig. 19 shows the configuration of a semiconductor device SB including an LDMOSFET 100M.

[0124] 19, the source region SR and the body contact region PR are formed in the second portion P2 of the p-type well PWL. The source region SR and the body contact region PR are in contact with each other.

[0125] The source region SR is connected to a plug PLG1. The body contact region PR is connected to a plug PLG3. The plug PLG1 and the plug PLG3 are each electrically connected to a wiring WL. As a result, the source region SR and the body contact region PR are electrically connected to each other. Therefore, the same potential is supplied to the source region SR and the body contact region PR.

[0126] The basic idea can be applied not only to the semiconductor device SA described in the first embodiment but also to the semiconductor device SB described in this modification.

[0127] <<Semiconductor Device Manufacturing Method>> Next, a method for manufacturing the semiconductor device SA in the first embodiment will be described with reference to Figures 20 to 25. Figures 20 to 25 are diagrams showing the manufacturing process of the semiconductor device SA, and show cross-sectional views corresponding to the AA and BB cross sections of Figure 13, respectively.

[0128] 20, using a general semiconductor manufacturing technique, an n-type buried layer NBL, a deep p-type well HPW, a first portion P1 of the p-type well PWL, a second portion P2 of the p-type well PWL, an n-type well NWL, and an offset drain region OD are formed in an epitaxial layer EPI formed on a p-type semiconductor substrate SUB. Note that the n-type buried layer NBL may be formed in the p-type semiconductor substrate SUB instead of in the epitaxial layer EPI.

[0129] 21, a resist film R1 is applied onto the epitaxial layer EPI. Then, the resist film R1 is patterned using photolithography to form openings OP in the resist film R1. Then, using the patterned resist film R1 as a mask, an n-type impurity (donor) such as phosphorus (P) or arsenic (As) is introduced into the epitaxial layer EPI exposed from the openings OP by ion implantation. Specifically, in the AA cross section, the n-type impurity is introduced into a portion of the offset drain region OD, a portion of the epitaxial layer EPI located between the offset drain region OD and the first portion P1 of the p-type well PWL, and a portion of the first portion P1 of the p-type well PWL.

[0130] In addition, in the cross section BB, n-type impurities are introduced into a part of the offset drain region OD, a part of the epitaxial layer EPI located between the offset drain region OD and the second portion P2 of the p-type well PWL, and a part of the second portion P2 of the p-type well PWL. As a result, in the cross section AA, an n-type semiconductor region NR is formed in a part of the offset drain region OD and a part of the epitaxial layer EPI located between the offset drain region OD and the first portion P1 of the p-type well PWL. In the cross section BB, an n-type semiconductor region NR is formed in a part of the offset drain region OD and a part of the epitaxial layer EPI located between the offset drain region OD and the second portion P2 of the p-type well PWL.

[0131] The n-type impurity is also introduced into a part of the first portion P1 of the p-type well PWL and a part of the second portion P2 of the p-type well PWL. However, since the amount of p-type impurity contained in the p-type well PWL is greater than the dose of the n-type impurity, no n-type semiconductor region NR is formed in the part of the first portion P1 of the p-type well PWL or in the part of the second portion P2 of the p-type well PWL. In contrast, the amount of p-type impurity contained in the epitaxial layer EPI is smaller than the dose of the introduced n-type impurity. Therefore, an n-type semiconductor region NR is formed in the epitaxial layer EPI. In other words, the n-type impurity is introduced in such a way that an n-type semiconductor region NR is formed in the epitaxial layer EPI while an n-type semiconductor region NR is not formed in the p-type well PWL.

[0132] Next, as shown in FIG. 22, a deep trench region DTI and a trench region STI are formed. The deep trench region DTI is formed by forming a trench from the upper surface of the epitaxial layer EPI, penetrating the p-type well PWL, the deep p-type well HPW, and the n-type buried layer NBL, to reach the p-type semiconductor substrate SUB, and then filling this trench with an insulating material. The trench region STI is formed by forming a trench in the offset drain region OD, and then filling this trench with an insulating material. Then, an insulating film IF is formed on the upper surface of the epitaxial layer EPI, for example, by using a thermal oxidation method. The insulating film IF is formed of, for example, a silicon oxide film.

[0133] Thereafter, a polysilicon film is formed on the insulating film IF. Next, the polysilicon film is patterned using photolithography and etching techniques. As a result, a gate electrode GE is formed as shown in FIG. 23. Then, the insulating film IF is patterned using the gate electrode GE as a mask to form a gate insulating film GOX. Next, although not shown, n-type impurities are introduced into the epitaxial layer EPI by ion implantation using the gate electrode GE as a mask. This forms an LDD region. Note that the LDD region does not necessarily have to be formed.

[0134] Next, as shown in Fig. 24, sidewall spacers SW are formed on the sidewalls of the gate electrode GE. Thereafter, as shown in Fig. 25, a drain region DR and a source region SR are formed in the AA cross section by using photolithography and ion implantation. Furthermore, a body contact region PR is formed in the BB cross section by using photolithography and ion implantation.

[0135] Subsequently, although not shown, an interlayer insulating film and wiring are formed using a general semiconductor manufacturing technique, and in this manner, the semiconductor device SA can be manufactured.

[0136] For example, in the first embodiment, to form the n-type semiconductor region NR, n-type impurities such as phosphorus (P) or arsenic (As) are introduced by ion implantation using a patterned resist film R1 as a mask, as shown in Fig. 21. At this time, a mask having openings surrounded by thick lines as shown in each of Figs. 26 to 28 below can be used.

[0137] 26 exposes a region where n-type impurities are introduced to form the n-type semiconductor region NR. As a result, n-type impurities are not introduced into regions where n-type impurities do not need to be introduced. As a result, by using the mask shown in FIG. 26, it is possible to suppress fluctuations in the characteristics of the LDMOSFET 100 that would otherwise be caused by introducing n-type impurities into regions where n-type impurities do not need to be introduced.

[0138] 27 exposes the region surrounded by the deep trench region DTI. As a result, variations in the formation of the n-type semiconductor region NR due to misalignment of the mask are suppressed. This makes it possible to suppress variations in the characteristics of the LDMOSFET 100 due to variations in the formation of the n-type semiconductor region NR.

[0139] 28 is larger than the opening shown in FIG. 26 and smaller than the opening shown in FIG. 27. N-type impurities are not introduced near the ends of the LDMOSFET 100 in the gate width direction (Y direction). In particular, when the mask having the opening shown in FIG. 28 is used, n-type impurities are not introduced into the corners of the epitaxial layer EPI, which are part of the region surrounded by the deep trench region DTI and are likely to cause a decrease in the breakdown voltage of the LDMOSFET 100. Therefore, by using the mask having the opening shown in FIG. 28, it is possible to suppress fluctuations in the characteristics of the LDMOSFET 100 due to misalignment of the mask in the gate length direction and a decrease in the breakdown voltage of the LDMOSFET 100 due to introduction of n-type impurities near the ends of the epitaxial layer EPI in the gate width direction.

[0140] <<Features of the First Embodiment>> The features of the first embodiment are as follows.

[0141] For example, as shown in FIG. 13, the p-type well PWL is configured with a "ladder structure" having a first portion P1 and a second portion P2.

[0142] For example, as shown in FIG. 14, an n-type semiconductor region NR is formed in a portion of the epitaxial layer EPI between the offset drain region OD and the source region SR.

[0143] As a result, the p-type well PWL is arranged so that the p-type well PWL is not formed between the offset drain region OD and the source region SR. That is, the p-type well PWL does not exist between the offset drain region OD and the source region SR, but the epitaxial layer EPI does. A p-type well PWL having a higher p-type impurity concentration than the epitaxial layer EPI is not formed between the offset drain region OD and the source region SR, which form the n-type semiconductor region NR. Therefore, in the first embodiment, when forming the n-type semiconductor region NR between the offset drain region OD and the source region SR, the n-type semiconductor region NR can be formed without increasing the dose of the n-type impurity.

[0144] That is, in the first embodiment, the p-type well PWL does not exist between the offset drain region OD and the source region SR, but the epitaxial layer EPI having a p-type impurity concentration lower than that of the p-type well PWL exists, so that the n-type semiconductor region NR can be formed without increasing the dose of the n-type impurity.

[0145] That is, to form the n-type semiconductor region NR, it is necessary to introduce n-type impurities that cancel out the p-type impurities already introduced into the p-type semiconductor region. Therefore, to form the n-type semiconductor region NR in the p-type well PWL having a higher p-type impurity concentration than the epitaxial layer EPI, the dose of n-type impurities must be larger than that required to form the n-type semiconductor region NR in the epitaxial layer EPI having a lower p-type impurity concentration than the p-type well PWL. In this regard, according to the first embodiment, since the epitaxial layer EPI is present but the p-type well PWL is not present between the offset drain region OD and the source region SR, the n-type semiconductor region NR can be formed without increasing the dose of n-type impurities. That is, even when the n-type semiconductor region NR is formed, the dose of n-type impurities introduced into the offset drain region OD can be reduced. Thus, according to the first embodiment, electric field concentration due to the n-type impurities introduced into the offset drain region OD can be suppressed. Therefore, according to the first embodiment, even when the n-type semiconductor region NR is formed to reduce the threshold voltage of the LDMOSFET 100, a decrease in the breakdown voltage of the LDMOSFET 100 can be suppressed.

[0146] <Embodiment 2> Next, a second embodiment will be described.

[0147] Except for the configuration of the n-type semiconductor region NR, the configuration of the second embodiment is almost the same as the configuration of the above-described first embodiment. Therefore, the following description will focus on the differences between the second embodiment and the first embodiment.

[0148] FIG. 29 is a plan view showing an LDMOSFET 200 according to the second embodiment.

[0149] 29, in the second embodiment, an n-type semiconductor region NR is formed in a part of the epitaxial layer EPI. For example, as shown in Fig. 29, the n-type semiconductor region NR is formed in a part of the epitaxial layer EPI located between the offset drain region OD and the source region SR in the X direction. In contrast, as shown in Fig. 29, the n-type semiconductor region NR is not formed in a part of the epitaxial layer EPI located between the offset drain region OD and the second portion P2 of the p-type well PWL in the X direction.

[0150] FIG. 30 is a cross-sectional view of the LDMOSFET 200 taken along line AA in FIG. 29. FIG. 30 is similar to FIG. 14. Therefore, the description of FIG. 30 will be omitted. FIG. 31 is a cross-sectional view of the LDMOSFET 200 taken along line BB in FIG. 29. As shown in FIG. 31, no n-type semiconductor region NR is formed in a portion of the epitaxial layer EPI in the X direction that is located between the offset drain region OD and the second portion P2 of the p-type well PWL. FIG. 32 is a cross-sectional view of the LDMOSFET 200 taken along line CC in FIG. 29. As shown in FIG. 32, an n-type semiconductor region NR is formed in a portion of the epitaxial layer EPI that is located between the second portions P2 of the p-type well PWL that are formed at a predetermined interval. In this manner, the semiconductor device SC according to the second embodiment is configured.

[0151] <<Features of the Second Embodiment>> In the second embodiment, too, an n-type semiconductor region NR is formed in a portion of the epitaxial layer EPI located between the offset drain region OD and the source region SR. That is, the n-type semiconductor region NR is formed in the channel formation region located below the gate electrode GE. This reduces the threshold voltage of the LDMOSFET 200. In particular, in the second embodiment, too, the p-type well PWL has a "ladder structure" having a first portion P1 and a second portion P2. Therefore, no p-type well PWL having a higher p-type impurity concentration than the p-type impurity concentration of the epitaxial layer EPI is formed between the offset drain region OD and the source region SR. This allows the n-type semiconductor region NR to be formed without increasing the dose of n-type impurities. This prevents the n-type impurity concentration of the offset drain region OD from becoming too high. In this way, in the second embodiment, too, the threshold voltage of the LDMOSFET 200 can be reduced without ensuring a sufficient breakdown voltage of the LDMOSFET 200.

[0152] On the other hand, in the second embodiment, the n-type semiconductor region NR is not formed in a portion of the epitaxial layer EPI located between the offset drain region OD and the second portion P2 of the p-type well PWL. As a result, in the second embodiment, the introduction of n-type impurities suppresses the formation of weak spots that contribute to a decrease in the breakdown voltage of the LDMOSFET 200. That is, in the second embodiment, the n-type semiconductor region NR is formed in a region that contributes to a decrease in the threshold voltage of the LDMOSFET 200, while the n-type semiconductor region NR is not formed in a region that is unlikely to contribute to a decrease in the threshold voltage of the LDMOSFET 200. Therefore, in the second embodiment, a decrease in the breakdown voltage of the LDMOSFET 200 due to the introduction of n-type impurities into unnecessary regions does not occur. That is, in the second embodiment, the threshold voltage of the LDMOSFET 200 can be reduced without generating weak spots that would cause a decrease in the breakdown voltage of the LDMOSFET 200.

[0153] <Third Embodiment> Next, a third embodiment will be described.

[0154] Except for the n-type semiconductor region NR, the configuration of the third embodiment is almost the same as the configuration of the above-described first embodiment. Therefore, the following description will focus on the differences between the third embodiment and the first embodiment.

[0155] FIG. 33 is a plan view showing an LDMOSFET 300 according to the third embodiment.

[0156] 33, in the third embodiment, the n-type semiconductor region NR is formed not only in a part of the epitaxial layer EPI but also in the second portion P2 of the p-type well PWL. For example, as shown in FIG. 33, the n-type semiconductor region NR is formed in a portion of the epitaxial layer EPI located between the offset drain region OD and the source region SR in the X direction. Also, as shown in FIG. 33, the n-type semiconductor region NR is formed in a portion of the epitaxial layer EPI located between the offset drain region OD and the second portion P2 of the p-type well PWL in the X direction, and in the second portion P2 of the p-type well PWL. That is, in the portion of the LDMOSFET 300 along the line AA in FIG. 33, the n-type semiconductor region NR is formed in a portion of the epitaxial layer EPI located between the offset drain region OD and the second portion P2 of the p-type well PWL. In addition, in the portion of the LDMOSFET 300 along the line BB in FIG. 33, an n-type semiconductor region NR is also formed in a portion of the epitaxial layer EPI located between the offset drain region OD and the second portion P2 of the p-type well PWL, and in the second portion P2 of the p-type well PWL.

[0157] Fig. 34 is a cross-sectional view of the LDMOSFET taken along line AA in Fig. 33. Fig. 34 is similar to Fig. 14. Therefore, the description of Fig. 34 will be omitted. Fig. 35 is a cross-sectional view of the LDMOSFET taken along line BB in Fig. 33. As shown in Fig. 35, n-type semiconductor regions NR are formed not only in a portion of the epitaxial layer EPI located between the offset drain region OD and the second portion P2 of the p-type well PWL, but also in the second portion P2 of the p-type well PWL. For this reason, in the third embodiment, the n-type impurity concentration of the n-type semiconductor region NR is higher than the p-type impurity concentration of the p-type well PWL.

[0158] Figure 36 is a cross-sectional view of the LDMOSFET taken along line CC in Figure 33. As shown in Figure 36, n-type semiconductor regions NR are formed in portions of the epitaxial layer EPI located between the second portions P2 of the p-type wells PWL formed at a predetermined interval and in the second portions P2 of the p-type wells PWL. Here, the p-type impurity concentration of the p-type wells PWL is higher than the p-type impurity concentration of the epitaxial layer EPI. Therefore, the n-type impurity concentration of the n-type semiconductor regions NR formed in the second portions P2 of the p-type wells PWL is lower than the n-type impurity concentration of the n-type semiconductor regions NR formed in the epitaxial layer EPI.

[0159] As described above, the semiconductor device SD according to the third embodiment is configured.

[0160] Next, the n-type impurity concentration of the n-type semiconductor region NR will be described.

[0161] Specifically, the relationship between the n-type impurity concentration of the n-type semiconductor region NR in the first embodiment, the n-type impurity concentration of the n-type semiconductor region NR in the third embodiment, and the n-type impurity concentration of the n-type semiconductor region NR in the first related art will be described.

[0162] FIG. 37(a) is a diagram showing an impurity profile in the epitaxial layer EPI in the depth direction in FIG. 14 showing the first embodiment and FIG. 34 showing the third embodiment.

[0163] 37(a), the horizontal axis represents the depth from the upper surface of the epitaxial layer EPI, and the vertical axis represents the impurity concentration of p-type impurities or n-type impurities.

[0164] In FIG. 37(a), the p-type impurity concentration of the epitaxial layer EPI is, for example, 1.3×10 15 (1 / cm 3 ) "(1)" indicates the n-type impurity profile of the n-type semiconductor region NR in the first embodiment shown in FIG. 14. "(2)" indicates the n-type impurity profile of the n-type semiconductor region NR in the third embodiment shown in FIG.

[0165] As shown in FIG. 37(a), the n-type impurity concentration of the n-type semiconductor region NR in the first embodiment and the n-type impurity concentration of the n-type semiconductor region NR in the third embodiment are both higher than the p-type impurity concentration of the epitaxial layer EPI. Furthermore, the n-type impurity concentration of the n-type semiconductor region NR in the first embodiment is lower than the n-type impurity concentration of the n-type semiconductor region NR in the third embodiment. Consequently, the dose of the n-type impurity introduced into the epitaxial layer EPI to form the n-type semiconductor region NR is lower in the first embodiment than in the third embodiment. Therefore, the dose of the n-type impurity introduced into the offset drain region OD can be reduced in the first embodiment than in the third embodiment. Therefore, the first embodiment is more likely to suppress a decrease in the breakdown voltage of the LDMOSFET caused by the introduction of the n-type impurity into the offset drain region OD than the third embodiment.

[0166] FIG. 37(b) is a diagram showing an impurity profile in the epitaxial layer EPI in the depth direction in FIG. 15 showing the first embodiment and FIG. 35 showing the third embodiment.

[0167] 37(b), the horizontal axis represents the depth from the upper surface of the epitaxial layer EPI, and the vertical axis represents the impurity concentration of p-type impurities or n-type impurities.

[0168] In FIG. 37(b), the p-type impurity concentration of the epitaxial layer EPI is, for example, 1.3×10 15 (1 / cm 3 The p-type impurity concentration of the p-type well PWL is, for example, 2×10 17 (1 / cm 3 ) or more and 4×10 17 (1 / cm 3 ) or less. Therefore, the p-type impurity concentration of the p-type well PWL is higher than the p-type impurity concentration of the epitaxial layer EPI. "(1)" shows the n-type impurity profile of the n-type semiconductor region NR in the first embodiment shown in FIG. 15. "(2)" shows the n-type impurity profile of the n-type semiconductor region NR in the third embodiment shown in FIG. 35. "(3)" shows the n-type impurity profile of the n-type semiconductor region NR in the first related technology shown in FIG. 7.

[0169] As shown in FIG. 37(b), the n-type impurity concentration of the n-type semiconductor region NR in the first embodiment and the n-type impurity concentration of the n-type semiconductor region NR in the third embodiment are both higher than the p-type impurity concentration of the epitaxial layer EPI. The n-type impurity concentration of the n-type semiconductor region NR in the first embodiment is lower than the p-type impurity concentration of the p-type well PWL. Therefore, the n-type semiconductor region NR in the first embodiment is not formed in the p-type well PWL. In contrast, the n-type impurity concentration of the n-type semiconductor region NR in the third embodiment is higher than the p-type impurity concentration of the p-type well PWL. Therefore, the n-type semiconductor region NR in the third embodiment is also formed in the p-type well PWL.

[0170] The n-type impurity concentration of the n-type semiconductor region NR in the first related technology is higher than the p-type impurity concentration of the p-type well PWL. Therefore, in the first related technology, the n-type semiconductor region NR is also formed in the p-type well PWL. Furthermore, the n-type impurity concentration of the n-type semiconductor region NR in the first related technology is higher than the n-type impurity concentration of the n-type semiconductor region NR in the third embodiment. Therefore, compared to the first related technology, the dose of n-type impurities introduced into the epitaxial layer EPI to form the n-type semiconductor region NR in the third embodiment is lower. Therefore, the third embodiment can reduce the dose of n-type impurities introduced into the offset drain region OD more than the first related technology. Therefore, the third embodiment is more likely to suppress a decrease in the breakdown voltage of the LDMOSFET caused by the introduction of n-type impurities into the offset drain region OD than the first related technology.

[0171] <<Features of the Third Embodiment>> FIG. 38 is a diagram showing a main current I1 and a sub-current I2 flowing from a drain region DR to a source region SR in an LDMOSFET having a p-type well PWL and an n-type semiconductor region NR, which are configured as a "ladder structure" having a first portion P1 and a second portion P2.

[0172] In Figure 38, the main current I1 shown by the solid line indicates the current flowing from the n-type semiconductor region NR formed in the portion of the epitaxial layer EPI located between the offset drain region (not shown in Figure 38) and the source region SR to the source region SR.

[0173] On the other hand, the sub-current I2 indicated by the dashed line represents the current flowing to the source region SR via the n-type semiconductor region NR formed in the portion of the epitaxial layer EPI located between the offset drain region (not shown in Figure 38) and the second portion P2 of the p-type well PWL and the n-type semiconductor region NR formed in the second portion P2 of the p-type well PWL.

[0174] In the third embodiment, an n-type semiconductor region NR is also formed in the second portion P2 of the p-type well PWL. Therefore, the sub-current I2 is larger than in a configuration in which the n-type semiconductor region NR is not formed in the second portion P2 of the p-type well PWL. Therefore, according to the third embodiment, the total current amount, which is the sum of the main current I1 and the sub-current I2, can be increased. In other words, according to the third embodiment, the current driving power of the LDMOSFET can be improved.

[0175] FIG. 39 is a diagram qualitatively illustrating that the total current amount, which is the sum of the main current I1 and the sub-current I2, can be increased in the third embodiment.

[0176] For example, in a configuration in which the n-type semiconductor region NR is not formed in the second portion P2 of the p-type well PWL (the configuration of the first embodiment), in order to flow the subcurrent I2, it is necessary to form an inversion layer in the second portion P2 of the p-type well PWL. That is, the threshold voltage for forming the inversion layer in the second portion P2 of the p-type well PWL is a positive voltage.

[0177] In contrast, in the configuration in which the n-type semiconductor region NR is formed in the second portion P2 of the p-type well PWL (the configuration of the third embodiment), the n-type semiconductor region NR is formed in the second portion P2 of the p-type well PWL, so the sub-current I2 can flow without forming an inversion layer in the second portion P2 of the p-type well PWL. That is, in the third embodiment, it is not necessary to apply a positive voltage to the gate electrode to flow the sub-current I2. That is, in the third embodiment, the sub-current I2 flows even if the gate voltage applied to the gate electrode is a negative voltage.

[0178] As a result, as shown in Fig. 39, the sub-current I2 flowing in the configuration of embodiment 3 is larger than the sub-current I2 flowing in the configuration of embodiment 1. Therefore, based on Fig. 39, according to embodiment 3, the total current amount combining the main current I1 and the sub-current I2 can be increased.

[0179] In the first embodiment, the modified example of the first embodiment, the second embodiment, and the third embodiment, a stacked structure including a semiconductor substrate SUB and an epitaxial layer EPI formed on the semiconductor substrate SUB is described, but the epitaxial layer EPI does not necessarily have to be formed.

[0180] When the epitaxial layer EPI is not formed, the n-type buried layer NBL, the deep p-type well HPW, the n-type well NWL, the drain region DR, the trench region STI, the deep trench region DTI, the offset drain region OD, the p-type well PWL, the n-type semiconductor region NR, the body contact region PR, and the source region SR are formed in the semiconductor substrate SUB. In addition, the gate insulating film GOX, the gate electrode GE, the sidewall spacer SW, the interlayer insulating film IL, the plugs PLG1, PLG2, PLG3, the wiring WL1, the wiring WL2, the wiring WL3, and the wiring WL are formed on the semiconductor substrate SUB.

[0181] Furthermore, when the epitaxial layer EPI is not formed, the first embodiment, the modified example of the first embodiment, the second embodiment, and the third embodiment can be understood by replacing the epitaxial layer EPI with the semiconductor substrate SUB.

[0182] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0183] DR drain region DTI Deep Trench Region EPI epitaxial layer GE gate electrode GOX gate insulating film HPW Deep p-type well IF insulating film IL Interlayer insulating film I1 Main current I2 Sub Current NBL n-type buried layer NR n-type semiconductor region NWL n-type well OD Offset drain region OP opening PLG1 plug PLG2 plug PLG3 plug PR body contact region PWL p-type well P1 Part 1 P2 2nd part R resistive element R1 resist film SA1 Semiconductor Device SA2 Semiconductor Device SB Semiconductor Device SC Semiconductor Device SD Semiconductor Devices SR Source Region STI trench area SUB p-type semiconductor substrate SW Sidewall Spacer WL wiring WL1 wiring WL2 wiring WL3 wiring 10 Depletion-type MOSFET 100 LDMOSFET 100A LDMOSFET 100B LDMOSFET 100M LDMOSFET 200 LDMOSFET 300 LDMOSFET

Claims

1. a semiconductor substrate of a first conductivity type; a first well of the first conductivity type formed in the semiconductor substrate, the first well having an impurity concentration higher than an impurity concentration of the semiconductor substrate, and the first well having a first portion and a second portion; an offset drain region formed in the semiconductor substrate, spaced apart from the first well, and having a second conductivity type opposite to the first conductivity type; a drain region of the second conductivity type formed in the offset drain region and having an impurity concentration higher than an impurity concentration of the offset drain region; a source region of the second conductivity type formed in the semiconductor substrate to partially overlap the first portion of the first well and spaced apart from the offset drain region; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film; Equipped with a first distance between the offset drain region and the first portion of the first well in a gate length direction of the gate electrode is greater than a second distance between the offset drain region and the second portion of the first well; The semiconductor device includes a first semiconductor region of the second conductivity type formed in a portion of the semiconductor substrate located between the offset drain region and the source region.

2. 2. The semiconductor device according to claim 1, The first semiconductor region is formed in a portion of the semiconductor substrate located between the offset drain region and the second portion of the first well.

3. 3. The semiconductor device according to claim 2, The first semiconductor region also extends into the first well.

4. 2. The semiconductor device according to claim 1, The first semiconductor region is arranged so as not to be formed within a portion of the semiconductor substrate located between the offset drain region and the second portion of the first well.

5. 2. The semiconductor device according to claim 1, The impurity concentration of the first semiconductor region is higher than the impurity concentration of the semiconductor substrate.

6. 6. The semiconductor device according to claim 5, The impurity concentration of the first semiconductor region is lower than the impurity concentration of the first well.

7. 6. The semiconductor device according to claim 5, The impurity concentration of the first semiconductor region is higher than the impurity concentration of the first well.

8. 2. The semiconductor device according to claim 1, the first conductivity type is p-type, the second conductivity type is n-type, the gate electrode is a gate electrode of an n-channel field effect transistor, The n-channel field effect transistor has a negative threshold voltage.

9. 2. The semiconductor device according to claim 1, the semiconductor device has a trench formed in the offset drain region; The groove is filled with an insulating material.

10. 2. The semiconductor device according to claim 1, The first portion of the first well and the second portion of the first well are adjacent to each other in the gate width direction of the gate electrode.

11. 2. The semiconductor device according to claim 1, The semiconductor device has a body contact region of the first conductivity type formed in the first well, having an impurity concentration higher than an impurity concentration of the first well, and in contact with the source region.

12. 12. The semiconductor device according to claim 11, The source region and the body contact region are adjacent to each other in the gate width direction of the gate electrode.

13. 12. The semiconductor device according to claim 11, The source region and the body contact region are adjacent to each other in the gate length direction of the gate electrode.

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