Semiconductor device

Abstract

To provide a semiconductor device including a dielectric layer with a high dielectric constant having a concave part or a pad spacer having a lower surface, which is additionally arranged on a gate structure for protecting the gate structure by covering.SOLUTION: A semiconductor device includes a substrate, a gate structure, an insulating spacer, a first pad, an insulating layer, and a dielectric layer with a high dielectric constant. The insulating spacer and the gate structure are arranged alternately on the substrate. The first pad is disposed on the insulating spacer. The insulating layer overlaps on the insulating spacer and the gate structure, and a part of the insulating layer overlapping on the gate structure includes a concave part. The dielectric layer with a high dielectric constant is disposed in the concave part and the lowest surface of the dielectric layer with a high dielectric constant is lower than the highest surface of the first pad. By disposing the dielectric layer with a high dielectric constant and / or the insulating layer, the generation of a defect in an upper structure of the gate structure can be prevented and the occurrence of a short-circuit problem between the gate structure and a metal mutual connection line disposed thereon can be avoided.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices that include gate structures. [Background technology]

[0002] As various electronic products continue to miniaturize, the design of semiconductor devices must also meet the demands for higher integration and density. Dynamic random access memories (DRAMs) with recessed gate structures can reduce current leakage in capacitor structures due to a longer carrier channel length in the same semiconductor substrate. Therefore, under the current mainstream development trend, they are gradually replacing DRAMs with simple planar gate structures. Generally, DRAMs with recessed gate structures include a large number of memory cells, which form an array area for storing data. Each memory cell includes a transistor component and a capacitor component connected in series to receive voltage signals from bit lines and word lines. To meet the demands for product features, it is still necessary to continue increasing the strength of memory cells in the array area. As a result, manufacturing processes and designs become increasingly important and complex. Therefore, conventional technologies or conventional structures need to be further improved to effectively improve the performance and reliability of associated memory devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,790,289 Summary of the Invention [Problem to be solved by the invention]

[0004] The object of the present invention is to provide a semiconductor device including a recessed high-k dielectric layer or a pad spacer with a lower surface that is additionally disposed on a gate structure to cover and protect the gate structure, thereby preventing defects from occurring in the upper structure of the gate structure and avoiding short circuit problems between the gate structure and the metal interconnection lines disposed thereon. [Means for solving the problem]

[0005] To achieve the above object, an embodiment of the present invention provides a semiconductor device including a substrate, a gate structure, an insulating spacer, a first pad, an insulating layer, and a high-k dielectric layer. The gate structure is disposed on the substrate. The insulating spacers and the gate structure are alternately disposed on the substrate. The first pad is disposed on the insulating spacer. The insulating layer overlies the insulating spacer and the gate structure, and a portion of the insulating layer overlying the gate structure has a recess. The high-k dielectric layer is disposed in the recess, and a bottom surface of the high-k dielectric layer is lower than a top surface of the first pad.

[0006] To achieve the above object, another embodiment of the present invention provides a semiconductor device including a substrate, a gate structure, an insulating spacer, a first spacer structure, a first pad, and a pad spacer. The substrate is defined by a first region and a second region. The gate structure is disposed on the substrate and is located in the first region. The first spacer structure is disposed on a sidewall of the gate structure. The insulating spacers and the gate structure are alternately disposed on the substrate and are located in the first region. Each of the first pads is disposed on the insulating spacer in the first region. Each of the pad spacers is disposed on a sidewall of a plurality of first pads in the first region. The lower surface of the pad spacer is lower than the upper surface of the first spacer structure.

[0007] These and other objects of the present invention will no doubt become obvious to those skilled in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

[0008] The accompanying drawings are intended to provide a better understanding of the embodiments and are included as part of the specification of this disclosure. These drawings and descriptions are used to explain the principles of the embodiments. It should be noted that all drawings are schematic and relative dimensions and scales have been adjusted for convenience of the drawings. Identical or similar features in different embodiments are marked with the same reference numerals. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view that schematically illustrates a semiconductor device according to a first embodiment of the present application; [Figure 2] 1 is a schematic diagram illustrating a method of forming a semiconductor device according to a preferred embodiment of the present application, which is a cross-sectional view that schematically illustrates the middle of a semiconductor device after a plug hole has been formed. [Figure 3] 1 is a schematic diagram illustrating a method of forming a semiconductor device according to a preferred embodiment of the present application, and is a cross-sectional view that schematically illustrates the middle of a semiconductor device after a metal material layer has been formed. [Figure 4] 1 is a schematic diagram illustrating a method of forming a semiconductor device according to a preferred embodiment of the present application, and is a cross-sectional view that schematically illustrates the middle of a semiconductor device after pads have been formed. [Figure 5] FIG. 1 is a schematic diagram illustrating a method of forming a semiconductor device according to a preferred embodiment of the present application, which is a cross-sectional view that schematically illustrates the middle of a semiconductor device after a first dielectric material layer has been formed. [Figure 6] FIG. 2 is a schematic diagram illustrating a method of forming a semiconductor device according to a preferred embodiment of the present application, which is a cross-sectional view that schematically illustrates the middle of the semiconductor device after a second dielectric material layer has been formed. [Figure 7] 1 is a schematic diagram illustrating a method of forming a semiconductor device according to a preferred embodiment of the present application, and is a cross-sectional view that schematically illustrates the middle of a semiconductor device after a capacitive dielectric layer has been formed. [Figure 8] FIG. 2 is a cross-sectional view that schematically illustrates a semiconductor device according to a second embodiment of the present application. [Figure 9] FIG. 10 is a cross-sectional view that schematically illustrates a semiconductor device according to a third embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0010] For a better understanding of the present disclosure, preferred embodiments will be described in detail. The preferred embodiments of the present disclosure are illustrated in the accompanying drawings with numbered elements. In addition, the technical features in the different embodiments described below can be substituted, recombined, or mixed with each other to construct another embodiment without departing from the spirit of the present disclosure.

[0011] Please refer to FIG. 1, which is a cross-sectional view schematically illustrating a semiconductor device according to a first embodiment of the present application. As shown in FIG. 1, the semiconductor device 10 includes a substrate 100, a gate structure 130, a plurality of insulating spacers 150, a plurality of first pads 160, an insulating layer 170, and a high-dielectric-constant material layer 184. The substrate 100 may be, for example, but not limited to, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed from any other suitable material. In one embodiment, the substrate 100 further includes a first region 101 having a relatively low integration level of components, such as a peripheral region of the semiconductor device 10, and a second region 102 having a relatively high integration level of components, such as a cell region of the semiconductor device 10. For example, but not limited to, the first region 101 and the second region 102 are disposed adjacent to each other. Furthermore, a plurality of shallow trench isolations (STIs) 110 and 120 are disposed in the first region 101 and the second region 102 of the substrate 100, and a plurality of active areas (AA, not shown) are defined in the substrate 100.

[0012] The gate structure 130 and insulating spacers 150 are disposed on the substrate 100 and are positioned in the first region 101. Here, two of the insulating spacers 150 are disposed on opposite sides of the corresponding ones of the gate structure 130. The first pad 160 is disposed on the insulating spacers 150 and is covered from above by an insulating layer 170. The insulating layer 170 also overlies the gate structure 130. A high-k material layer 184 further overlies the insulating layer 170. Note that the insulating layer 170 overlying the gate structure 130 has a recess R1, such that the high-k material layer 184 is partially disposed in the recess R1 and the bottom surface 184b of the high-k material layer 184 is lower than the top surface 160t of the first pad 160. Therefore, the upper structure of the gate structure 130 having a relatively wide line width can be protected by being successively covered by the insulating layer 170 and the high-dielectric-constant material layer 184. Therefore, the first pad 160 can be isolated from physical contact with the gate structure 130 to avoid potential short-circuit problems in metal interconnect lines disposed on the first pad 160, such as the contact structure 190.

[0013] In one embodiment, for example, the first pad 160 has a height H (not shown) in a direction perpendicular to the substrate 100. The bottom surface 184b of the high-k material layer 184 is preferably lower than the middle position of the high-k material layer 184, for example, ½H below the top surface 160t of the first pad 160, thereby ensuring that the high-k material layer 184 fully and effectively overlaps the first pad 160 and the gate structure 130 and avoids direct contact therebetween. The semiconductor device 10 further includes a dielectric layer 120 disposed under one of the gate structures 130 and a first spacer structure 140 disposed on an opposite sidewall of the gate structure 130. For example, the dielectric layer 120 includes an insulating material such as silicon oxide and functions as a gate dielectric layer for the gate structure 130. Each of the first spacer structures 140 is disposed between the gate structure 130 and a corresponding one of the insulating spacers 150 and functions as a gate spacer structure for the gate structure 130. To effectively insulate the gate structure 130 and the corresponding first pad 160, the upper surface 140t of the first spacer structure 140 is preferably higher than the upper surface of the gate structure 130. In one embodiment, the insulating layer 170 further includes a plurality of pad spacers 172 and a cover layer 174. For example, two of the pad spacers 172 are disposed on the sidewalls opposite to the corresponding first pads 160. Meanwhile, the pad spacers 172 each overlap the upper sidewall of the first spacer structure 140. The cover layer 174 conformally overlaps the pad spacers 172 and the first pads 160 in such a manner that the insulating layer 170 includes a recess R1 between adjacent pad spacers 172. The configuration is not limited thereto. Additionally, a plurality of contact structures 190 are disposed on the first pad 160 and comprise a low-resistivity metal material, such as aluminum (Al), copper (Cu), or tungsten (W), which serve as a first layer of metal interconnect lines for the semiconductor device 10, and the metal interconnect lines are electrically connected to other conductive structures subsequently disposed on the semiconductor device 10.

[0014] The semiconductor device 10 further includes a plurality of bit lines 230, a plurality of plugs 250, a plurality of second pads 260, and a capacitor structure 280, which are disposed in the second region 102. The bit lines 230 and the plugs 250 are alternately arranged on the substrate 100, and second spacer structures 240 are disposed between the bit lines 230 and the plugs 250. In one embodiment, the process of forming the bit lines 230 can be integrated with the process of forming the gate structures 130 in the first region 101. Thus, each of the bit lines 230 and the gate structures 130 includes, successively from bottom to top, a stack of a semiconductor layer 132, a barrier layer 134, and a metal layer 136, where the metal layer 136 in the bit lines 230 further has a cap layer 138 disposed thereon. The semiconductor layer 132 includes a semiconductor material such as, for example, doped polysilicon or doped amorphous silicon. The barrier layer 134 includes a conductive barrier material, such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide. The metal layer 136 includes, for example, copper, aluminum, tungsten, or other suitable conductive material with low resistivity. The cap layer 138 includes an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The materials are not limited to the above examples. The bit lines 230 are essentially disposed on the dielectric layer 220 and extend to the substrate 100 through corresponding bit line contacts (BLCs) 230a formed therebelow, and are electrically connected to corresponding active areas. In one embodiment, the dielectric layer 220 includes, for example, a silicon oxide layer 222, a silicon nitride layer 224, and a silicon oxide layer 226 stacked in sequence, resulting in an oxide-nitride-oxide (ONO) structure, but is not limited thereto. In another embodiment, the process of forming the second spacer structure 240 can be integrated with the process of the first spacer structure 140 arranged in the first region 101, so that each of the first spacer structure 140 and the second spacer structure 240 includes a first spacer 142, a second spacer 144 and a third spacer 146 arranged successively horizontally on the sidewalls of the gate structure 130 and the sidewalls of the bit line 230.The top surface of the second spacer structure 240 is, for example, flush with the top surface of the bit line 230 and higher than the top surface 140t of the first spacer structure 140 disposed in the first region 101. The first spacer 142 and the third spacer 146 include the same insulating material, such as, for example, silicon nitride and silicon carbonitride, while the second spacer 144 includes, for example, a different insulating material from that of the first spacer 142 and the third spacer 146. The second spacer 144 may be, but is not limited to, silicon oxide and silicon oxynitride.

[0015] The plug 250 includes an epitaxial material, such as silicon (Si), silicon phosphorus (SiP), silicon germanium (SiGe), or germanium (Ge), and serves as a storage node (SN) contact of the semiconductor device 10, which is in physical contact with the active area. A second pad 260 is disposed on the plug 250 as the storage node (SN) pad of the semiconductor device 10, and a capacitor structure 280 is disposed on the second pad 260. Specifically, two adjacent second pads 260 are separated from each other by an insulating layer 270, and a metal silicide layer 252 is further disposed between one of the second pads 260 and the corresponding one of the plug 250. The metal silicide layer 252 includes a metal silicide material, such as, but not limited to, cobalt disilicide (CoSi), titanium disilicide (TiSi), or nickel silicide (NiSi). In one embodiment, the process of forming the second pad 260 is integrated with the process of forming the first pad 160 disposed in the first region 101, such that the second pad 260 and the first pad 160 each include a sequentially stacked barrier layer 162 and metal layer 164. The barrier layer 162 includes a conductive barrier material such as, for example, titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaO), etc., and the metal layer 164 includes, for example, but is not limited to, copper, aluminum, tungsten, or other suitable low resistivity conductive material.

[0016] In one embodiment, each insulating layer 270 further includes a first dielectric layer 272 and a second dielectric layer 274 stacked in order, and the first dielectric layer 272 and the second dielectric layer 274 can have the same or different insulating materials, which can be selected from, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., and preferably includes silicon nitride. Furthermore, the process of forming the insulating layer 270 can also be integrated with the process of forming the insulating layer 170 disposed in the first region 101, so that the pad spacer 172 of the insulating layer 170 includes the same material as the first dielectric layer 272 and the cover layer 174 of the insulating layer 170 includes, but is not limited to, the same material as the second dielectric layer 274. The capacitor structure 280 includes a bottom electrode layer 282, a capacitor dielectric layer 284, and a top electrode layer 286, which are arranged in sequence to form a plurality of vertically extending capacitors that serve as storage nodes (SNs) of the semiconductor device 10 and are in physical contact with the underlying SN pads, i.e., second pads 260. The bottom electrode layer 282 includes, for example, titanium nitride. The top electrode layer 286 includes, for example, a titanium nitride and silicon germanium composite structure. The capacitor dielectric layer 284 includes, for example, but is not limited to, a high-k dielectric material selected from the group of metal oxides, such as hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO), titanium oxide (TiO), and zirconia-alumina-zirconia (ZAZ), preferably zirconia-alumina-zirconia. In a preferred embodiment, the process of forming the capacitor dielectric layer 284 may be integrated with the high-k material layer 184 disposed in the first region 101. For example, when the capacitor dielectric layer 284 is formed, the high-k material layer 184 is simultaneously formed in the first region 101, so that the capacitor dielectric layer 284 and the high-k material layer 184 comprise the same material.

[0017] In the above-described configuration, capacitor and transistor components (not shown) disposed in the second region 102 of the substrate 100 can form a minimum memory cell for receiving voltage information from the bit line 230 and the word line (not shown). As a result, the semiconductor device 10 in this embodiment can form a dynamic random access memory (DRAM) device and achieve improved operating performance. In this embodiment of the semiconductor device 10, a high-k material layer 184 and an insulating layer 170 disposed thereunder are additionally disposed on the gate structure 130 to cover and protect the upper structure of the gate structure 130, ensuring that the metal interconnection lines disposed in the first region 101 are electrically connected only to the first pad 160 without directly contacting the gate structure 130. Therefore, potential short-circuit problems can be avoided. Furthermore, the process of forming the high-k material layer 184 and the insulating layer 170 in the first region 101 can be accomplished simultaneously with the process of forming the specified components in the second region 102. Therefore, no additional operations or processes are required, and the semiconductor device 10 in this embodiment can be made with a more reliable structure and have satisfactory performance based on a simplified manufacturing process. Those skilled in the art will easily understand that the semiconductor device according to the present invention is not limited to the above and can have alternative forms as long as the resulting product meets actual requirements. Other embodiments or variations of the semiconductor device in this application are further described below. For simplicity, the following description will mainly focus on the differences between the embodiments and will not repeat similarities. In addition, the same components in various embodiments in this application will be labeled with the same reference numerals to facilitate mutual comparison between the various embodiments.

[0018] 1 , in another embodiment, the semiconductor device 10 may optionally include a substrate 100, a gate structure 130, an insulating spacer 150, a first spacer structure 140, a first pad 160, and a pad spacer 172. The gate structure 130 and the insulating spacer 150 are both disposed in the first region 101, and are arranged on the substrate 100 in a manner such that a plurality of insulating spacers 150 are disposed on both sides of one of the gate structures 130. One of the first spacer structures 140 is disposed on a sidewall of a corresponding one of the gate structures 130 and is interposed between the gate structure 130 and the insulating spacer 150. The first pads 160 are respectively disposed on the insulating spacers 150. In particular, the multiple pad spacers 172 are respectively disposed on the sidewalls of the first pads 160, while respectively overlapping the upper sidewalls of the first spacer structures 140 in such a manner that the lower surfaces 172b of the pad spacers 172 are lower than the upper surfaces 140t of the first spacer structures 140. Therefore, physical contact between the first pads 160 and the gate structures 130 can be effectively blocked by the respective pad spacers 172 to ensure that a subsequently formed metal interconnection line, e.g., a contact structure 190, is electrically connected only to the first pads 160 and does not contact the gate structures 130, thereby avoiding possible short-circuit problems.

[0019] In order to allow those skilled in the art to easily understand the semiconductor device 10 according to the present invention, the manufacturing process of the semiconductor device 10 according to the present application will be further described below.

[0020] 2 to 7, which are schematic diagrams illustrating a manufacturing process of a semiconductor device 10 according to a preferred embodiment of the present application. First, as shown in FIG. 2, a substrate 100 is prepared. Shallow trench isolations 110 and 120 are formed in a first region 101 and a second region 102 of the substrate 100, respectively, and active areas are defined in the first region 101 and the second region 102, respectively. In one embodiment, the shallow trench isolations 110 and 210 are formed, for example, but not limited to, by performing an etching process to form a plurality of trenches (not shown) in the substrate 100, and then filling the trenches with at least one insulating material, such as, for example, silicon oxide, silicon nitride, etc., to form the shallow trench isolations 110 and 210 flush with the top surface of the substrate 100.

[0021] Next, a plurality of buried word lines (not shown) are formed on the substrate 100 in the first region 101 and the second region 102. In one embodiment, the process of forming the buried word lines includes, but is not limited to, the following steps. For example, a plurality of trenches (not shown) are formed that can pass through the active area and the shallow trench isolation 210 simultaneously. Next, a dielectric layer (not shown) overlying the entire surface of the trench, a gate dielectric layer (not shown) overlying the surface of the lower half of the trench, a gate conductive layer (not shown) filling the lower half of the trench, and a cap layer (not shown) filling the upper half of the trench are formed in the trench. Furthermore, a dielectric layer 120 and a dielectric layer 220 are formed on the substrate 100 in the first region 101 and the second region 102, respectively. In one embodiment, the process of forming the dielectric layer 120 and the dielectric layer 220 includes, but is not limited to, the following steps. For example, the dielectric material layer may include a first silicon oxide material layer (not shown), a silicon nitride material layer (not shown), and a second silicon oxide material layer (not shown) formed and stacked in that order on the substrate 100 in the first region 101 and the second region 102. At least the second silicon oxide material layer and the silicon nitride material layer formed in the first region 101 of the substrate 100 are removed, such that the first silicon oxide material layer in the first region 101 of the substrate 100 forms the dielectric layer 120, and the dielectric material layer in the second region 102 of the substrate 100 forms the dielectric layer 220. Alternatively, in another embodiment, the dielectric material layer in the first region 101 of the substrate 100 can be completely removed, and then an additional dielectric layer 120 can be formed.

[0022] Thereafter, a plurality of gate stack structures 130a and a plurality of spaced-apart bit lines 230 are formed on the substrate 100 in the first region 101 and the second region 102 by a similar process. The gate stack structures 130a have a relatively wide line width compared to the bit lines 230, but are not limited thereto. In one embodiment, the process of forming the gate stack structures 130a and the bit lines 230 includes, but is not limited to, the following steps: First, a plurality of openings (not shown) penetrating the dielectric layer 220 and partially exposing the substrate 100 are formed in the second region 102, and a semiconductor material layer (not shown), for example, made of a semiconductor material including polysilicon or doped amorphous silicon, is formed in the first region 101 and the second region 102 to fill the openings. Meanwhile, a barrier material layer (not shown) including a conductive barrier material such as titanium and / or titanium nitride, or tantalum and / or tantalum oxide, a metal material layer (not shown) including a metal material with low resistivity such as tungsten, aluminum, or copper, and a cap material layer (not shown) including an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride are formed on the semiconductor material layer. Thereafter, as shown in FIG. 2, gate stack structures 130a, bit lines 230, and bit line plugs 230a disposed below some of the bit lines 230 are simultaneously formed by a patterning process. Thus, each of the gate stack structures 130a and the bit lines 230 includes a semiconductor layer 132, a barrier layer 134, a metal layer 136, and a cap layer 138, which are stacked in order from bottom to top.

[0023] 2, the first spacer structure 140 and the second spacer structure 240 are formed by the same process and each includes, for example, but not limited to, a first spacer 142 (including, for example, silicon nitride or silicon carbonitride), a second spacer 144 (including, for example, silicon oxide or silicon oxynitride), and a third spacer 146 (including, for example, silicon nitride or silicon carbonitride) stacked in sequence in the horizontal direction. The stacks are formed on sidewalls of the gate stack structure 130a and the bit line 230.

[0024] A deposition and etch-back process is then performed to provide insulating material between adjacent gate stack structures 130a and adjacent bit lines 230. The insulating material in the first region 101 forms insulating spacers 150. As shown in FIG. 2 , the insulating material between adjacent bit lines 230 is then removed by using a mask layer (not shown), and a plurality of plug holes 250a that partially expose the substrate 100 are formed in the second region 102. The mask layer is then completely removed.

[0025] 3, an epitaxial formation process is performed to form a plug 250 in the plug hole 250a in the second region 102, and a metal silicide formation process is performed on the plug 250 to form a metal silicide layer 252. In one embodiment, the plug 250 includes an epitaxial material such as, for example, silicon, silicon phosphorus, silicon germanium, or germanium. The metal silicide layer 252 includes a metal silicide material such as, for example, but not limited to, cobalt disilicide, titanium silicide, or nickel silicide. The plug 250 formed in this manner can be used as a storage node plug in the semiconductor device 10. Then, at least one deposition process is performed to simultaneously form a barrier material layer 162a, for example, including titanium and / or titanium nitride, or tantalum and / or tantalum oxide, and a metal material layer 164a, for example, including copper, aluminum, tungsten, or any other suitable metal material with low resistivity, on the substrate 100 in the first region 101 and the second region 102. In this configuration, a portion of the barrier material layer 162a conformally forms in the plug hole 250a, as shown in FIG. 2, and another portion of the barrier material layer 162a forms outside the plug hole 250a. The remaining space of the plug hole 250a is filled with a portion of the metal material layer 164a.

[0026] As shown in FIG. 4, the first pad 160 and the second pad 260 are formed on the substrate 100 in the first region 101 and the second region 102, respectively, by using another mask layer (not shown), which is then completely removed. For example, but not limited to, the first pad 160 has a height H in a direction perpendicular to the substrate 100. Note that the first pad 160 is formed on the insulating spacer 150 and the first spacer structure 140, and when the first pad 160 is formed, the cap layer 138 of the gate stack structure 130a is synchronously removed by adjusting etching parameters. As a result, the gate structure 130 is formed. On the other hand, the second pad 260 is partially formed on the bit line 230 and the second spacer structure 240 and partially formed in the plug hole 250a, as shown in FIG. 2, and is in physical contact with the metal silicide layer 252 to be electrically connected to the plug 250. In this manner, the second pad 260 can be formed as a storage node pad for the semiconductor device 10 .

[0027] 5, a deposition process is performed to form a first dielectric material layer 172a on the substrate 100 in the first region 101 and the second region 102. The first dielectric material layer 172a includes an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. The first dielectric material layer 172a integrally covers the first pad 160, the first spacer structure 140, and the gate structure 130 in the first region 101, and also integrally covers the second pad 260, the second spacer structure 240, and the bit line 230 in the second region 102.

[0028] 6 , the first dielectric material layer 172a formed in the first region 101 is partially removed by using another mask layer (not shown) to form pad spacers 172, which are then completely removed. The pad spacers 172 partially cover the sidewalls of the first pad 160 and partially cover the sidewalls of the upper half of the first spacer structure 140. In a preferred embodiment, the lower surface 172b of the pad spacer 172 is lower than the upper surface 140t of the first spacer structure 140, thus effectively blocking physical contact between the first pad 160 and the gate structure 130.

[0029] Another deposition process is then performed to form a second dielectric material layer 174a on the substrate 100 in the first region 101 and the second region 102. The second dielectric material layer 174a includes an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. In this configuration, the second dielectric material layer 174a formed in the first region 101 conformally covers the gate structure 130 and the pad spacers 172, which have a relatively wide linewidth, and a recess R1 exists between adjacent pad spacers 172. The lowermost end of the recess R1 is, for example, but not limited to, lower than the underside of the first pad 160. In this manner, the upper structure of the gate structure 130 is protected and covered when the second dielectric material layer 174a is formed to further block the first pad 160 and the gate structure 130 from physical contact. On the other hand, the second dielectric material layer 174a formed in the second region 102 just fills the remaining space between adjacent second pads 260 and presents a generally flat upper surface. In one embodiment, the first dielectric material layer 172a and the second dielectric material layer 174a preferably comprise different insulating materials. For example, if the first dielectric material layer 172a comprises silicon oxide or silicon oxynitride, the second dielectric material layer 174a may comprise, but is not limited to, silicon nitride or silicon carbonitride.

[0030] 7, a planarization process is performed on the second region 102 of the substrate 100 to partially remove the second dielectric material layer 174a and the first dielectric material layer 172a. After the planarization process, the second dielectric material layer 174a in the first region 101 forms the cover layer 174, which, together with the pad spacer 172 in the first region 101, forms the insulating layer 170 having the recess R1; on the other hand, the second dielectric material layer 174a and the first dielectric material layer 172a in the second region 102 form the second dielectric layer 274 and the first dielectric layer 272 having a U-shaped cross section, which jointly form the insulating layer 270. The top surface of the insulating layer 270 is flush with the top surface of the second pad 260.

[0031] A bottom electrode layer 282 is then formed on the insulating layer 270 and the second pad 260, physically contacting the top surface of the second pad 260. The bottom electrode layer 282 may comprise, for example, but not limited to, titanium nitride. A capacitor dielectric layer 284 is then formed on the bottom electrode layer 282, and may comprise, for example, a high-k dielectric material selected from the group consisting of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zinc oxide, titanium oxide, and zirconia-alumina-zirconia, with zirconia-alumina-zirconia being preferred. Note that once the capacitor dielectric layer 284 is formed, the capacitor dielectric layer 284 may extend into the first region 101 to cover the insulating layer 170. In this manner, the capacitor dielectric layer extending into the first region 101 forms the high-k material layer 184 in the recess R1, as shown in FIG. 1 . The bottom surface 184b of the high-k material layer 184 is lower than the top surface 160t of the first pad 160. That is, the high-k material layer 184 in the first region 101 is part of the capacitor dielectric layer that forms the capacitor dielectric layer 284 in the second region 102, and the process of forming the high-k material layer 184 in the first region 101 can be integrated with the process of forming the capacitor dielectric layer 284 in the second region 102 with the same material.

[0032] A top electrode layer 286 is then formed on the capacitor dielectric layer 284, such that the top electrode layer 286, the capacitor dielectric layer 284, and the bottom electrode layer 282 in the second region 102 together form a capacitor structure 280, as shown in FIG. 1, and a contact structure 190 is formed in the first region 101, as shown in FIG. 1, to create this embodiment of the semiconductor device 10. In this configuration, the vertical capacitor and transistor components (not shown) of the capacitor structure 280 formed in the second region 102 of the substrate 100 can form a minimum memory cell for receiving voltage information from the bit line 230 and the word line. Thus, the semiconductor device 10 in this embodiment can form a dynamic random access memory device to achieve improved operating performance.

[0033] According to the manufacturing process of the present embodiment, by integrating the processes for forming components in the first region 101 and the second region 102 of the substrate 100, the gate structure 130 and the bit line 230 having a relatively wide line width are formed in the first region 101 and the second region 102 by the same process. Furthermore, by integrating the processes for forming the insulating layer 170 in the first region 101 and the insulating layer 270 in the second region 102 and / or by integrating the processes for forming the high-k material layer 184 in the first region 101 and the capacitor dielectric layer 284 in the second region 102, the upper structure of the gate structure 130 is protected by the high-k material layer 184 and / or the insulating layer 170 formed in the first region 101, thereby avoiding direct contact between the first pad 160 and the gate structure 130 after the cap layer 138 in the first region 101 is removed. Under this operation, the manufacturing process of the semiconductor device in this embodiment can form the semiconductor device 10 having a highly reliable structure and satisfactory performance based on a simplified manufacturing process.

[0034] Please refer to Figure 8, which is a schematic cross-sectional view of a semiconductor device 30 according to a second embodiment of the present invention. The structure of the semiconductor device 30 in this embodiment is basically the same as that of the semiconductor device 10 in the previous embodiment shown in Figure 1, and the similarities will not be repeated herein. The main difference between the semiconductor device 30 in this embodiment and the semiconductor device 10 in the above-mentioned embodiment is that the cover layer 374 in this embodiment has a void 376 below the recess R1.

[0035] 8, the insulating layer 370 in this embodiment includes pad spacers 172 and a cover layer 374. The cover layer 374 conformally overlies the pad spacers 172, the first pad 160, and the gate structure 130 having a relatively wide linewidth, such that the cover layer 374 includes recesses (not shown) between adjacent pad spacers 172. A subsequently formed high-k material layer 384 further covers and partially closes the recesses, forming recesses R1 and voids 376, as shown in FIG. 8, where a portion of the high-k material layer 384 is also formed in and in direct contact with the voids 376, but it should be noted that this is not limiting.

[0036] In the above-described configuration of the semiconductor device 30 according to this embodiment, the upper structure of the gate structure 130 is also effectively protected because it is covered by the insulating layer 370 and / or the high-dielectric-constant material layer 384, which ensures that the metal interconnection line (such as the contact structure 190) disposed in the first region 101 is electrically connected only to the first pad 160 without contacting the gate structure 130. In this way, the short-circuit problem that may have been encountered in the prior art can be avoided. Therefore, a dynamic random access memory device including the semiconductor device 30 of this embodiment can be made with highly reliable structure and characteristics and has improved operating performance.

[0037] 9, which is a schematic cross-sectional view of a semiconductor device 50 according to a third embodiment of the present invention. The structure of the semiconductor device 50 in this embodiment is basically the same as that of the semiconductor device 10 in the above-described embodiment shown in FIG. 1, so similarities will not be repeated herein. The main difference between this embodiment of the semiconductor device 50 and the embodiment of the semiconductor device 10 is that the gate structure 530 in this embodiment has an upper recess 530a, and a cover layer 574 fills the recess 530a.

[0038] 9 , the insulating layer 570 in this embodiment includes a pad spacer 172 and a cover layer 574. The cover layer 574 conformally covers the pad spacer 172, the first pad 160, and the gate structure 530 having a relatively wide linewidth. The cover layer 574 includes a recess R1 between adjacent pad spacers 172. Note that in this embodiment, when the first dielectric material layer 172a disposed in the first region 101 is partially removed as shown in FIG. 5 , the etching conditions of the etch-back process are adjusted to partially remove the metal layer 136 of the gate structure 530 to form a recess 530a on the top of the gate structure 530. In this manner, the recess 530a can be formed between adjacent pad spacers 172. Optionally, but not limited to, the sidewalls of the recess 530a can be vertically aligned with the sidewalls of the pad spacer 172. A subsequently formed cover layer 574 is then filled into the recess 530 a to cover and protect the upper structure of the gate structure 530 .

[0039] In the above-described configuration of the semiconductor device 50 according to this embodiment, the upper structure of the gate structure 530 is also effectively protected because it is covered by the insulating layer 570 and / or the high-dielectric-constant material layer 184, which ensures that the metal interconnection line (such as the contact structure 190) disposed in the first region 101 is electrically connected only to the first pad 160 without contacting the gate structure 530. In this way, the short-circuit problem that may have been encountered in the prior art can be avoided. Therefore, a dynamic random access memory device including the semiconductor device 50 of this embodiment can be made with highly reliable structure and characteristics and has improved operating performance.

[0040] Overall, the manufacturing process of the semiconductor device according to the present invention integrates the processes of forming components in different regions. Through the simplified manufacturing process, the gate structure can be more effectively protected by blocking unwanted physical contact between the gate structure and the pad with a lower bottom pad spacer that is additionally disposed on the gate structure in the recessed high-k material layer or peripheral region. Therefore, defects that may occur in the structure above the gate structure can be prevented, and short-circuit problems that may occur between the gate structure and the metal interconnection line disposed thereon can be avoided.

[0041] Those skilled in the art will readily appreciate that numerous modifications and variations of the present device and method may be made while retaining the teachings of the present invention. Accordingly, the above disclosure should be considered limited only by the scope of the appended claims. [Explanation of symbols]

[0042] 10 Semiconductor Devices 30 Semiconductor Devices 50 Semiconductor Devices 100 boards 101 First Area 102 Second Area 110 Shallow Trench Isolation, STI 120 Shallow Trench Isolation, STI, Dielectric Layer 130 Gate Structure 130a Gate stack structure 132 Semiconductor layer 134 Barrier Layer 136 Metal layer 138 Cap Layer 140 first spacer structure 140t top surface 142 First spacer 144 Second Spacer 146 Third Spacer 150 Insulating spacer 160 First Pad 160t top surface 162 Barrier Layer 162a Barrier material layer 164 Metal layer 164a Metal material layer 170 Insulating Layer 172 Pad spacer 172a first dielectric material layer 172b Bottom side 174 Cover Layer 174a second dielectric material layer 184 High-permittivity material layer 184b Bottom surface 190 Contact structure 210 Shallow Trench Isolation 220 Dielectric Layer 222 silicon oxide layer 224 Silicon nitride layer 226 Silicon oxide layer 230 bit lines 230a Bit Line Contact, BLC, Bit Line Plug 240 Second Spacer Structure 250 plug 250a Spark Plug Hole 252 Metal silicide layer 260 Second Pad 270 Insulating Layer 272 First Dielectric Layer 274 Second Dielectric Layer 280 Capacitor Structure 282 Lower electrode layer 284 Capacitor Dielectric Layer 286 Upper electrode layer 370 Insulating Layer 374 Cover Layer 376 Void 384 High-permittivity material layer 530 Gate Structure 530a Upper recess, recess 570 Insulating Layer 574 Cover Layer

Claims

1. A substrate; a gate structure disposed on the substrate; a plurality of insulating spacers disposed on the substrate and positioned on opposite sides of the gate structure; a plurality of first pads disposed on the plurality of insulating spacers; an insulating layer overlying the plurality of insulating spacers and the gate structure, wherein a portion of the insulating layer overlying the gate structure has a recess; a high-k dielectric layer disposed in the recess, the bottom surface of the high-k dielectric layer being lower than the top surface of the first pad; A semiconductor device comprising:

2. The insulating layer is a plurality of pad spacers disposed on sidewalls of the plurality of first insulating spacers, the recesses being disposed between two adjacent ones of the plurality of pad spacers; a cover layer overlying the plurality of pad spacers; The semiconductor device of claim 1 further comprising:

3. The semiconductor device of claim 2 , wherein the cover layer comprises a void below the recess.

4. The semiconductor device of claim 3 , wherein the high-k dielectric layer covers the surfaces of the void.

5. The semiconductor device of claim 2 , wherein a top surface of the gate structure has a recess between adjacent two of the pad spacers, and the cover layer is further disposed in the recess.

6. a plurality of contact structures disposed on the plurality of first pads; a first spacer structure disposed between the gate structure and one of the insulating spacers, the first spacer structure having a top surface higher than a top surface of the gate structure; The semiconductor device of claim 1 further comprising:

7. 2. The semiconductor device of claim 1, wherein each of the first pads has a specified height in a direction perpendicular to the substrate, and the bottom surface of the high-k dielectric layer is lower than a position that is half the specified height from the top surface of the first pad.

8. a plurality of bit lines disposed on the substrate; a plurality of plugs disposed on the substrate and interleaved with the plurality of bit lines; a plurality of second pads disposed on the plurality of plugs; a capacitor structure disposed on the plurality of second pads and including, in order, a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer, wherein the capacitor dielectric layer and the high-k dielectric layer comprise the same material; and The semiconductor device of claim 1 further comprising:

9. a substrate defined by a first region and a second region; a gate structure disposed on the substrate and positioned in the first region; a plurality of insulating spacers disposed on the substrate and positioned on opposite sides of the gate structure; a first spacer structure disposed on a sidewall of the gate structure and interposed between the gate structure and one of the insulating spacers; a plurality of first pads disposed on the plurality of insulating spacers, respectively; a plurality of pad spacers respectively disposed on sidewalls of the plurality of first pads, the lower surfaces of the pad spacers being lower than the upper surface of the first spacer structures; A semiconductor device comprising:

10. a cover layer disposed on the plurality of pad spacers, the gate structure, and the plurality of first pads, the cover layer comprising a recess between adjacent two of the pad spacers over the gate structure; The semiconductor device of claim 9 further comprising:

11. a plurality of bit lines disposed on the substrate and positioned in the second region; a plurality of plugs disposed on the substrate and interleaved with the plurality of bit lines; a plurality of second pads disposed on the plurality of plugs; a capacitor structure disposed on the plurality of second pads, the capacitor structure comprising, in order, a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer, wherein at least a portion of the capacitor dielectric layer is disposed in the recess; and The semiconductor device of claim 10 further comprising:

12. 12. The semiconductor device of claim 11, wherein a lowermost surface of the portion of the capacitor dielectric layer is lower than a topmost surface of the first pad in the first region.

13. The semiconductor device of claim 11 , wherein the cover layer comprises a void below the recess.

14. The semiconductor device of claim 13 , wherein the portion of the capacitor dielectric layer covers a surface of the void.

15. an insulating layer overlying the plurality of bit lines and comprising a first dielectric layer and a second dielectric layer stacked in sequence, the first dielectric layer and the pad spacers comprising the same material; The semiconductor device of claim 11 further comprising:

16. 16. The semiconductor device of claim 15, wherein a top surface of the insulating layer is coplanar with a top surface of the second pad.

17. a plurality of contact structures disposed on the plurality of first pads; The semiconductor device of claim 10 further comprising:

18. 11. The semiconductor device of claim 10, wherein a top surface of the gate structure has a recess between adjacent two of the pad spacers, and the cover layer is further disposed in the recess.

19. 20. The semiconductor device of claim 18, wherein the top surface of the first spacer structure is higher than the top surface of the gate structure.

20. a plurality of second spacer structures, each disposed between one of the bit lines and an adjacent one of the plugs, the second spacer structures having a top surface flush with the top surface of the bit line and higher than the top surface of the first spacer structure; The semiconductor device of claim 11 further comprising:

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