Manufacturing method for integrated circuit device

Abstract

To provide a manufacturing method for an integrated circuit device whose electric characteristics and reliability are improved.SOLUTION: A manufacturing method for an integrated circuit device according to the present invention includes the steps of: preparing a substrate including a cell array region and a peripheral circuit region; forming a conductive layer on the cell array region and the peripheral circuit region; forming a capping insulating layer on the conductive layer; forming a direct contact and a bit line by using the capping insulating layer as an etching mask in the cell array region; forming a spacer structure covering both side walls of the direct contact and the bit line; forming an embedded contact between the direct contact and the bit line and between the adjacent bit lines; forming an insulating spacer covering the cell array region and the peripheral circuit region; and forming a gate structure by using the insulating spacer as the etching mask in the peripheral circuit region.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] The present invention relates to a method for fabricating integrated circuit devices, and more particularly to a method for fabricating integrated circuit elements including bit lines. [Background technology]

[0002] Downscaling of integrated circuit devices continues to reduce the size of the individual fine circuit patterns that implement the integrated circuit devices. Furthermore, as integrated circuit devices become more highly integrated, the width of bit lines becomes narrower, which increases the difficulty of the process for forming contacts between bit lines. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in view of the problems associated with the conventional methods for manufacturing integrated circuit devices, and an object of the present invention is to provide a method for manufacturing an integrated circuit device with improved electrical characteristics and reliability. [Means for solving the problem]

[0004] In order to achieve the above object, a method for manufacturing an integrated circuit device according to the present invention includes the steps of: preparing a substrate including a cell array region and a peripheral circuit region; forming a conductive layer on the cell array region and the peripheral circuit region; forming a capping insulating layer on the conductive layer; forming direct contacts and bit lines in the cell array region using the capping insulating layer as an etching mask; forming spacer structures covering both sidewalls of the bit lines and the direct contacts; forming buried contacts between the direct contacts and the bit lines and between adjacent bit lines; forming insulating spacers covering the cell array region and the peripheral circuit region; and forming gate structures in the peripheral circuit region using the insulating spacers as an etching mask.

[0005] In addition, to achieve the above object, a method for manufacturing an integrated circuit device according to the present invention includes the steps of: preparing a substrate including a cell array region and a peripheral circuit region; forming a conductive layer on the cell array region and the peripheral circuit region; forming a first capping layer consisting of a single film on the conductive layer; forming direct contacts, bit lines, and capping patterns disposed on the direct contacts and the bit lines in the cell array region using the first capping layer as an etching mask; forming spacer structures covering both sidewalls of the bit lines and the direct contacts; forming buried contacts between the direct contacts and the bit lines and between adjacent bit lines; forming insulating spacers covering the cell array region and the peripheral circuit region; and forming gate structures in the peripheral circuit region using the insulating spacers as an etching mask.

[0006] In addition, an integrated circuit device according to an embodiment of the present invention includes a substrate including a cell array region and a peripheral circuit region; bit lines extending in one direction parallel to an upper surface of the substrate on the cell array region of the substrate; direct contacts connected to active regions of the substrate within direct contact holes formed on the substrate; buried contacts disposed between the direct contacts and the bit lines or between adjacent bit lines; spacer structures covering both sidewalls of the bit lines and the direct contacts; a first capping pattern made of a single layer covering the bit lines; an insulating spacer covering the first capping pattern and the buried contacts; a gate structure disposed on the substrate on the peripheral circuit region of the substrate; and a contact plug disposed on a side of the gate structure. [Effects of the Invention]

[0007] According to the manufacturing method of the integrated circuit device of the present invention, the process of forming the second capping layer is performed after the process of forming the bit line, thereby preventing deterioration of the bit line that occurs during the process of forming the gate structure and the second capping layer that covers the gate structure, and improving the characteristics of the integrated circuit device. Furthermore, by performing the step of forming the gate structure after the steps of forming the bit line and buried contact, the electrical characteristics and reliability of the integrated circuit device are improved. Furthermore, by performing the gate structure formation process in the peripheral circuit region after the bit line formation process and buried contact formation process in the cell array region, the height of the first capping layer can be designed taking into consideration only the bit line formation process and buried contact formation process in the cell array region, and the height of the first capping layer can be adjusted to be lower than in the comparative example, thereby reducing the process difficulty. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a layout diagram showing a schematic configuration of an integrated circuit device according to an embodiment of the present invention. [Figure 2] FIG. 2 is an enlarged layout diagram of part II in FIG. [Figure 3A] FIG. 3 is a cross-sectional view taken along line AA' in FIG. 2. [Figure 3B] FIG. 3 is a cross-sectional view taken along line BB' in FIG. 2. [Figure 4] FIG. 3B is an enlarged cross-sectional view of a portion EX1 of FIG. 3A. [Figure 5A] 3 is a cross-sectional view for explaining a manufacturing method of an integrated circuit device according to an embodiment of the present invention, and corresponds to a cross section taken along line AA' in FIG. 2. FIG. [Figure 5B] 3 is a cross-sectional view for explaining the manufacturing method of the integrated circuit device according to the embodiment of the present invention, and corresponds to the cross section taken along the line BB' in FIG. 2. FIG. [Figure 6] 3 is a cross-sectional view for explaining a manufacturing method of an integrated circuit device according to an embodiment of the present invention, and corresponds to a cross section taken along line AA' in FIG. 2. FIG. [Figure 7A] 3 is a cross-sectional view for explaining a manufacturing method of an integrated circuit device according to an embodiment of the present invention, and corresponds to a cross section taken along line AA' in FIG. 2. FIG. [Figure 7B] 3 is a cross-sectional view for explaining the manufacturing method of the integrated circuit device according to the embodiment of the present invention, and corresponds to the cross section taken along the line BB' in FIG. 2. FIG. [Figure 8A] 3 is a cross-sectional view for explaining a manufacturing method of an integrated circuit device according to an embodiment of the present invention, and corresponds to a cross section taken along line AA' in FIG. 2. FIG. [Figure 8B] 3 is a cross-sectional view for explaining the manufacturing method of the integrated circuit device according to the embodiment of the present invention, and corresponds to the cross section taken along the line BB' in FIG. 2. FIG. [Figure 9A] 3 is a cross-sectional view for explaining a manufacturing method of an integrated circuit device according to an embodiment of the present invention, and corresponds to a cross section taken along line AA' in FIG. 2. FIG. [Figure 9B]3 is a cross-sectional view for explaining the manufacturing method of the integrated circuit device according to the embodiment of the present invention, and corresponds to the cross section taken along the line BB' in FIG. 2. FIG. [Figure 10A] 3 is a cross-sectional view for explaining a manufacturing method of an integrated circuit device according to an embodiment of the present invention, and corresponds to a cross section taken along line AA' in FIG. 2. FIG. [Figure 10B] 3 is a cross-sectional view for explaining the manufacturing method of the integrated circuit device according to the embodiment of the present invention, and corresponds to the cross section taken along the line BB' in FIG. 2. FIG. [Figure 11A] 3 is a cross-sectional view for explaining a manufacturing method of an integrated circuit device according to an embodiment of the present invention, and corresponds to a cross section taken along line AA' in FIG. 2. FIG. [Figure 11B] 3 is a cross-sectional view for explaining the manufacturing method of the integrated circuit device according to the embodiment of the present invention, and corresponds to the cross section taken along the line BB' in FIG. 2. FIG. [Figure 12A] 3 is a cross-sectional view for explaining a manufacturing method of an integrated circuit device according to an embodiment of the present invention, and corresponds to a cross section taken along line AA' in FIG. 2. FIG. [Figure 12B] 3 is a cross-sectional view for explaining the manufacturing method of the integrated circuit device according to the embodiment of the present invention, and corresponds to the cross section taken along the line BB' in FIG. 2. FIG. [Figure 13] 3 is a cross-sectional view for explaining a manufacturing method of an integrated circuit device according to an embodiment of the present invention, and corresponds to a cross section taken along line AA' in FIG. 2. FIG. [Figure 14A] 3 is a cross-sectional view for explaining a manufacturing method of an integrated circuit device according to an embodiment of the present invention, and corresponds to a cross section taken along line AA' in FIG. 2. FIG. [Figure 14B] 3 is a cross-sectional view for explaining the manufacturing method of the integrated circuit device according to the embodiment of the present invention, and corresponds to the cross section taken along the line BB' in FIG. 2. FIG. [Figure 15A]3 is a cross-sectional view for explaining a manufacturing method of an integrated circuit device according to an embodiment of the present invention, and corresponds to a cross section taken along line AA' in FIG. 2. FIG. [Figure 15B] 3 is a cross-sectional view for explaining the manufacturing method of the integrated circuit device according to the embodiment of the present invention, and corresponds to the cross section taken along the line BB' in FIG. 2. FIG. [Figure 16A] 3 is a cross-sectional view for explaining a manufacturing method of an integrated circuit device according to an embodiment of the present invention, and corresponds to a cross section taken along line AA' in FIG. 2. FIG. [Figure 16B] 3 is a cross-sectional view for explaining the manufacturing method of the integrated circuit device according to the embodiment of the present invention, and corresponds to the cross section taken along the line BB' in FIG. 2. FIG. [Figure 17A] 3 is a cross-sectional view for explaining a manufacturing method of an integrated circuit device according to an embodiment of the present invention, and corresponds to a cross section taken along line AA' in FIG. 2. FIG. [Figure 17B] 3 is a cross-sectional view for explaining the manufacturing method of the integrated circuit device according to the embodiment of the present invention, and corresponds to the cross section taken along the line BB' in FIG. 2. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Next, a specific example of an embodiment for carrying out a method for manufacturing an integrated circuit device according to the present invention will be described with reference to the drawings. The same reference numerals are used for the same components in the drawings, and redundant explanations relating thereto will be omitted.

[0010] FIG. 1 is a layout diagram showing the schematic configuration of an integrated circuit device according to an embodiment of the present invention, FIG. 2 is an enlarged layout diagram of part II of FIG. 1, FIG. 3A is a cross-sectional view taken along line A-A' of FIG. 2, FIG. 3B is a cross-sectional view taken along line B-B' of FIG. 2, and FIG. 4 is an enlarged cross-sectional view of part EX1 of FIG. 3A. 1 to 4, an integrated circuit device 100 includes a substrate 110 including a cell array area MCA and a peripheral circuit area PCA.

[0011] An isolation trench 112T is formed in the substrate 110, and an isolation film 112 is formed in the isolation trench 112T. The device isolation layers 112 define a plurality of first active regions AC1 in the substrate 110 in the cell array region MCA, and define a plurality of second active regions AC2 in the substrate 110 in the peripheral circuit region PCA. A plurality of first active regions AC1 on the cell array region MCA of the substrate 110 are arranged to have their major axes in a diagonal direction D1 with respect to the first direction X and the second direction Y, respectively. In the cell array region MCA of the substrate 110, a plurality of word lines WL extend parallel to each other in a first direction X across the first active regions AC1. A plurality of bit lines BL extend parallel to each other in the second direction Y on the plurality of word lines WL. A plurality of bit lines BL are arranged on the cell array area MCA. The plurality of bit lines BL are connected to the plurality of first active regions AC1 through direct contacts DC. In this specification, the first direction X is defined as a direction parallel to the top surface of the substrate 110, the second direction Y is defined as a direction intersecting the first direction X and parallel to the top surface of the substrate 110, and the vertical direction Z is defined as a direction perpendicular to the top surface of the substrate 110.

[0012] A plurality of buried contacts BC are formed between two adjacent bit lines BL among the plurality of bit lines BL. The buried contacts BC are arranged in a line along the first direction X and the second direction Y. A plurality of landing pads LP are formed on the plurality of buried contacts BC. The buried contacts BC and the landing pads LP serve to connect lower electrodes (not shown) of capacitors formed on the bit lines BL to the first active regions AC1. The landing pads LP are arranged so as to partially overlap the buried contacts BC, respectively.

[0013] Substrate 110 comprises silicon, for example, monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments, the substrate 110 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In one embodiment, the substrate 110 includes a conductive region, such as an impurity-doped well or impurity-doped structure. The element isolation film 112 includes an oxide film, a nitride film, or a combination thereof. In the cell array region MCA, a buffer film 114 is formed on a substrate 110. The buffer film 114 includes a first insulating film 114A and a second insulating film 114B. The first insulating film 114A and the second insulating film 114B each include an oxide film, a nitride film, or a combination thereof.

[0014] A plurality of direct contacts DC are formed in the plurality of direct contact holes DCH on the substrate 110 . The direct contacts DC are connected to the first active regions AC1. The plurality of direct contacts DC include doped polysilicon. For example, the direct contacts DC may include polysilicon containing a relatively high concentration of n-type impurities such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb).

[0015] A plurality of bit lines BL extend in the second direction Y on the substrate 110 and the plurality of direct contacts DC. The plurality of bit lines BL are connected to the first active region AC1 through direct contacts DC, respectively. Each of the plurality of bit lines BL includes a lower conductive pattern 132A, a middle conductive pattern 134A, and an upper conductive pattern 136A, which are sequentially stacked on the substrate 110. The lower conductive pattern 132A includes doped polysilicon. The intermediate conductive pattern 134A and the upper conductive pattern 136A may each include TiN, TiSiN, W, tungsten silicide, or a combination thereof. In an exemplary embodiment, the intermediate conductive pattern 134A is made of TiN, TiSiN, or a combination thereof, and the upper conductive pattern 136A includes W.

[0016] The plurality of bit lines BL are covered with the plurality of first capping patterns 142A, respectively. The first capping pattern 142A may be made of one of an oxide, a nitride, and an oxynitride. The first capping patterns 142A extend in the second direction Y on the bit lines BL. The first capping pattern 142A disposed on the bit line BL may be formed of a single layer without forming an interface. As will be described later, since an interface such as the second capping layer 174 is not formed in the first capping pattern 142A, deterioration of the bit line BL that occurs during the process of forming the gate structure PGT and the second capping layer 174 covering the gate structure PGT can be prevented, thereby improving the characteristics of the integrated circuit device 100.

[0017] Spacer structures 150 are disposed on both sidewalls of each of the plurality of bit lines BL. The spacer structures 150 extend in the second direction Y on both sidewalls of the bit lines BL, and a portion of the spacer structures 150 extends into the direct contact holes DCH to cover both sidewalls of the direct contacts DC. In the exemplary embodiment, the spacer structure 150 includes a first spacer layer 152 , a second spacer layer 154 , and a third spacer layer 156 . The first spacer layer 152 is conformally disposed on the sidewalls of the plurality of bit lines BL, the sidewalls of the plurality of first capping patterns 142A, and the inner wall of the direct contact hole DCH. A second spacer layer 154 and a third spacer layer 156 are sequentially disposed on the first spacer layer 152 . In one embodiment, the first spacer layer 152 and the third spacer layer 156 may comprise silicon nitride, and the second spacer layer 154 may comprise silicon oxide. In one embodiment, the first spacer layer 152 and the third spacer layer 156 may comprise silicon nitride, and the second spacer layer 154 may comprise air or a low-k dielectric material, where the term "air" refers to air or a space containing other gases present during the manufacturing process.

[0018] The buried insulating layer 158 surrounds the lower sidewall of the direct contact DC on the first spacer layer 152 and fills the remaining space of the direct contact hole DCH. The buried insulating layer 158 comprises silicon nitride, silicon oxynitride, silicon oxide, or a combination thereof. The direct contact DC is formed in a direct contact hole DCH formed in the substrate 110 and extends to a level higher than the upper surface of the substrate 110 . For example, the upper surface of the direct contact DC is disposed at the same level as the upper surface of the lower conductive pattern 132A, and the upper surface of the direct contact DC contacts the bottom surface of the intermediate conductive pattern 134A. In addition, the bottom surface of the direct contact DC is located at a level lower than the top surface of the substrate 110.

[0019] A plurality of insulating fences (not shown) and a plurality of buried contacts BC are arranged in a line along the second direction Y between the respective bit lines BL. Each of the plurality of buried contacts BC includes a lower contact conductive layer 162 , a metal silicide film 164 , and an upper contact conductive layer 166 . The plurality of buried contacts BC extend longitudinally in the vertical direction Z from the first recess space RS1 formed in the substrate 110. In the second direction Y, both side walls of each of the plurality of buried contacts BC are insulated from each other by a plurality of insulating fences. The insulating fences may include silicon nitride.

[0020] In an exemplary embodiment, the bottom contact conductive layer 162 comprises doped polysilicon. The metal silicide film 164 includes cobalt silicide, nickel silicide, or manganese silicide. The top contact conductive layer 166 comprises Ti, TiN, or a combination thereof. In other exemplary embodiments, the plurality of buried contacts BC may be made of Ti, TiN, Ta, TaN, Ru, Co, Mo, W, WN, TiSiN, WSiN, cobalt silicide, nickel silicide, tungsten silicide, and combinations thereof. In the exemplary embodiment, the vertical level of the upper surface of the buried contact BC is different from the vertical level of the upper surface of the first capping pattern 142A. For example, the vertical level of the upper surface of the buried contact BC is higher than the vertical level of the upper surface of the first capping pattern 142A.

[0021] The insulating spacer 172 covers the buried contact BC, the spacer structure 150, and the first capping pattern 142A. At this time, the insulating spacer 172 is formed to have a step. The vertical level of the bottom surface of the insulating spacer 172 in contact with the buried contact BC is different from the vertical level of the bottom surface of the insulating spacer 172 in contact with the first capping pattern 142A. For example, the insulating spacer 172 has a "┐" shape. In an exemplary embodiment, insulating spacers 172 comprise silicon nitride, silicon oxynitride, silicon oxide, or a combination thereof. A second capping layer 174 and an upper insulating layer 176 are sequentially disposed on the insulating spacer 172 .

[0022] The second capping layer 174 and the top insulating layer 176 comprise silicon nitride, silicon oxynitride, silicon oxide, or a combination thereof. A plurality of landing pads LP are formed on the plurality of buried contacts BC. The landing pad LP passes through the insulating spacer 172 , the second capping layer 174 and the upper insulating layer 176 . The landing pad LP is arranged so as to vertically overlap the buried contact BC. Although FIG. 3A shows the bottom surface of the landing pad LP as being coplanar with the bottom surface of the insulating spacer 172, this embodiment is not so limited. The landing pad LP is connected to a buried contact BC. The landing pad LP comprises a metal, a metal nitride, conductive polysilicon, or a combination thereof. For example, the landing pad LP may include W.

[0023] The landing pads LP may have a pattern shape of a plurality of islands in a plan view. The landing pads LP may have a shape whose horizontal cross-sectional area increases as they move away from each other in the vertical direction Z on the substrate 110. The landing pads LP cover the sidewalls of the insulating spacers 172 and the top surfaces of the first capping patterns 142A so as to vertically overlap portions of the bit lines BL. The landing pads LP are electrically isolated from one another by insulating spacers 172, a second capping layer 174, and an upper insulating layer 176 around the landing pads LP.

[0024] In the peripheral circuit area PCA, a gate structure PGT is disposed on the second active area AC2. The gate structure PGT includes a gate dielectric layer 116, a peripheral circuit gate electrode PG, and a gate capping pattern 142B, which are sequentially stacked on the second active region AC2. The gate dielectric film 116 may be made of at least one selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an ONO (oxide / nitride / oxide), or a high-k film having a higher dielectric constant than a silicon oxide film. The peripheral circuit gate electrode PG includes a lower conductive pattern 132B, an intermediate conductive pattern 134B, and an upper conductive pattern 136B. The materials constituting the lower conductive pattern 132B, the intermediate conductive pattern 134B, and the upper conductive pattern 136B are the same as the materials constituting the lower conductive pattern 132A, the intermediate conductive pattern 134A, and the upper conductive pattern 136A included in the bit line BL in the cell array region MCA, respectively. The gate capping pattern 142B may include a silicon nitride film.

[0025] Both side walls of the gate structure PGT are covered with gate spacers PGS. The gate spacer PGS includes an oxide film, a nitride film, or a combination thereof. The gate structure PGT and the gate spacer PGS are covered with a second capping layer 174 . The second capping layer 174 may include silicon nitride. An interlayer insulating film 149 is formed on the second capping layer 174 and around the gate structure PGT. The interlayer insulating film 149 includes, but is not limited to, TOSZ (Tonen SilaZene). The gate structure PGT, the second capping layer 174 and the interlayer insulating film 149 are covered with an upper insulating layer 176 . The upper insulating layer 176 may include silicon nitride.

[0026] In the peripheral circuit area PCA, a plurality of contact plugs CP are arranged, which penetrate the interlayer insulating film 149 and the second capping layer 174 in the vertical direction Z and extend to the second active area AC2 of the substrate 110. A plurality of contact plugs CP are disposed on both sides of the gate structure PGT. The contact plugs CP are the same as the buried contacts BC formed in the cell array region MCA. The contact plug CP includes Ti, TiN, or a combination thereof. Although not shown in the figure, a metal silicide film (not shown) may be interposed between the second active region AC2 and the contact plug CP. The metal silicide film may be made of cobalt silicide, nickel silicide, or manganese silicide.

[0027] 5A to 11B are cross-sectional views illustrating a method for manufacturing the integrated circuit device 100 according to the embodiment of the present invention. Specifically, Figures 5A, 6, 7A, 8A, 9A, 10A, and 11A are cross-sectional views corresponding to the cross section cut along line A-A' in Figure 2, and Figures 5B, 7B, 8B, 9B, 10B, and 11B are cross-sectional views corresponding to the cross section cut along line B-B' in Figure 2.

[0028] Referring to Figures 5A and 5B, in the cell array region MCA, a buffer layer 114 including a first insulating layer 114A and a second insulating layer 114B is formed on a substrate 110, and in the peripheral circuit region PCA, a gate dielectric layer 116 is formed on the substrate 110. Next, a lower conductive layer 132 is formed on the buffer layer 114 in the cell array region MCA and the gate dielectric layer 116 in the peripheral circuit region PCA. In an exemplary embodiment, the bottom conductive layer 132 comprises Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof. For example, the lower conductive layer 132 may include polysilicon.

[0029] Next, a first mask pattern (not shown) is formed on the lower conductive layer 132, and then the lower conductive layer 132 and the buffer film 114 exposed through the openings (not shown) of the first mask pattern in the cell array region MCA are etched, thereby etching the exposed portions of the substrate 110 and the device isolation film 112 to form direct contact holes DCH that expose the first active regions AC1 of the substrate 110. Next, the first mask pattern is removed, and direct contacts DC are formed in the direct contact holes DCH. In an exemplary process for forming the direct contact DC, a conductive layer is formed inside the direct contact hole DCH and on top of the lower conductive layer 132 to a thickness sufficient to fill the direct contact hole DCH, and the conductive layer is etched back so that the conductive layer remains only in the direct contact hole DCH. The conductive layer may include polysilicon.

[0030] Next, in the cell array region MCA and the peripheral circuit region PCA, the middle conductive layer 134, the upper conductive layer 136, and the capping insulating layer are sequentially formed on the lower conductive layer 132 and the direct contacts DC. The capping insulating layer includes a first capping layer 142 and a mask layer 144 . The middle conductive layer 134 and the top conductive layer 136 may each comprise TiN, TiSiN, W, tungsten silicide, or a combination thereof. In an exemplary embodiment, the first capping layer 142 and the mask layer 144 comprise materials that have an (etch) selectivity with respect to one another. The first capping layer 142 and the mask layer 144 may be comprised of an oxide, a nitride, an oxynitride, or a combination thereof. For example, the first capping layer 142 and the mask layer 144 may each include SiO2, SiN, ZrO, HfO, or a combination thereof.

[0031] In the method for manufacturing the integrated circuit device 100 according to the present invention, after the step of forming the bit lines BL and the buried contacts BC in the cell array area MCA, the step of forming the gate structure PGT in the peripheral circuit area PCA is performed. Therefore, the height of the capping insulating layer can be designed by taking into consideration only the processes of forming the bit lines BL and the buried contacts BC in the cell array region MCA. That is, the height of the capping insulating layer can be adjusted to be lower than that of the comparative example. For example, the height of the capping insulating layer can be reduced by about 43% compared to the comparative example, thereby reducing the process difficulty. For example, by reducing the height of the capping insulating layer used as an etching mask, line width roughness (LWR), aspect ratio, etc. can be improved, and process difficulty can be reduced.

[0032] Referring to FIG. 6, in the cell array region MCA, the mask layer 144 and the first capping layer 142 are patterned to form a mask pattern 144A and a first capping pattern 142A. In this process, the height of the mask pattern 144A is reduced from the height of the mask layer 144 (see FIG. 5A). Using the mask pattern 144A and the first capping pattern 142A as an etching mask, the upper conductive layer 136, the intermediate conductive layer 134, and the lower conductive layer 132 are etched to form a plurality of bit lines BL consisting of the lower conductive pattern 132A, the intermediate conductive pattern 134A, and the upper conductive pattern 136A. In the process of forming the plurality of bit lines BL, a portion of the sidewall of the direct contact DC is removed to expose a portion of the direct contact hole DCH.

[0033] Referring to FIGS. 7A and 7B, spacer structures 150 are formed on sidewalls of the plurality of bit lines BL and sidewalls of the direct contacts DC. The spacer structure 150 includes a first spacer layer 152 , a second spacer layer 154 , and a third spacer layer 156 . In this step, a buried insulating layer 158 is formed to fill the interior of the direct contact hole DCH. Also, a portion of the substrate 110 is removed to form a plurality of first recess spaces RS1 exposing the first active regions AC1 of the substrate 110 between the respective bit lines BL. A plurality of buried contacts BC are formed to fill the first recess spaces RS1 and the spaces between the bit lines BL. Each of the buried contacts BC includes a lower contact conductive layer 162, a metal silicide film 164, and an upper contact conductive layer 166. In this process, the upper side of the mask pattern 144A covering the bit lines BL and a portion of the upper side of the spacer structure 150 are also removed, and the vertical level of the mask pattern 144A is lowered. At this time, in the cell array region MCA, the upper surface of the mask pattern 144A and the upper surface of the buried contact BC form the same plane.

[0034] 8A and 8B, the mask layer 144 and the mask pattern 144A are removed in the cell array region MCA and the peripheral circuit region PCA. As a result, the upper surface of the first capping pattern 142A is exposed in the cell array region MCA, and the upper surface of the first capping layer 142 is exposed in the peripheral circuit region PCA. In the cell array region MCA, the top surface of the first capping pattern 142A is exposed, thereby forming a first opening OP1 above the bit line BL.

[0035] 9A and 9B, an insulating spacer 172 is formed to cover the cell array region MCA and the peripheral circuit region PCA. In the cell array region MCA, the insulating spacer 172 fills the first opening OP1 (see FIG. 8A). In the cell array region MCA and the peripheral circuit region PCA, the insulating spacer 172 conformally covers the first capping pattern 142A and the first capping layer 142.

[0036] 10A and 10B, in the peripheral circuit region PCA, the gate dielectric film 116, the lower conductive layer 132, the intermediate conductive layer 134, the upper conductive layer 136, and the lower capping layer 142 are patterned using the insulating spacers 172 as an etching mask to form a gate electrode PG consisting of a lower conductive pattern 132B, an intermediate conductive pattern 134B, and an upper conductive pattern 136B on the gate dielectric film 116, and a gate capping pattern 142B covering the gate electrode PG. Thereafter, gate spacers PGS are formed on both side walls of the gate structure PGT, which is a stacked structure of the gate dielectric film 116, the gate electrode PG, and the gate capping pattern 142B, and an ion implantation process is performed on both sides of the gate structure PGT to form source / drain regions in the second active region AC2. In this process, the vertical level of the insulating spacers 172 in the cell array area MCA is lowered.

[0037] Thereafter, a second capping layer 174 is formed to cover the insulating spacers 172 in the cell array region MCA and to cover the gate structures PGT and gate spacers PGS in the peripheral circuit region PCA. Next, in the peripheral circuit area PCA, an interlayer insulating film 149 is formed to fill the space around the gate structure PGT. At this time, the insulating spacer 172 is formed to have a step. The vertical level of the bottom surface of the insulating spacer 172 in contact with the buried contact BC is different from the vertical level of the bottom surface of the insulating spacer 172 in contact with the first capping pattern 142A. In an exemplary embodiment, insulating spacers 172 may include silicon nitride, silicon oxynitride, silicon oxide, or a combination thereof.

[0038] In an exemplary embodiment, the process of forming the second capping layer 174 is performed after the process of forming the bit line BL, thereby preventing deterioration of the bit line BL that occurs during the process of forming the gate structure PGT and the second capping layer 174 covering the gate structure PGT, and improving the characteristics of the integrated circuit device 100. Furthermore, since the process of forming the gate structure PGT is performed after the annealing process of the buried contact BC, the heat budget can be reduced and the characteristics of the integrated circuit device 100 can be improved. In addition, in the process of forming the gate structure PGT, the second capping layer 174 formed in the cell array region MCA can be used as an etching mask in the process of forming the landing pad LP, which will be described later.

[0039] Referring to Figures 11A and 11B, in the peripheral circuit region PCA, the interlayer insulating film 149 and the second capping layer 174 are etched to form a plurality of contact holes CPH that expose the second active region AC2 of the substrate 110, and a plurality of contact plugs CP that fill the plurality of contact holes CPH are formed. Next, an upper insulating layer 176 is formed to cover the second capping layer 174 in the cell array region MCA and the peripheral circuit region PCA. Next, a second opening OP2 is formed through the upper insulating layer 176, the second capping layer 174, and the insulating spacer 172. In the cell array region MCA, the second opening OP2 exposes a part of the buried contact BC.

[0040] Referring again to FIGS. 3A and 3B, a landing pad LP is formed to fill the second opening OP2. The process of forming the landing pad LP is performed by a damascene process, but is not limited to this. The landing pads LP are arranged in an island shape and are connected to the buried contacts BC, respectively. According to an embodiment of the present invention, the process of forming the gate structure PGT is performed after the process of forming the bit line BL and the buried contact BC, thereby improving the electrical characteristics and reliability of the integrated circuit device 100.

[0041] 12A to 17B are cross-sectional views illustrating a method for manufacturing an integrated circuit device 100 according to an embodiment of the present invention. Specifically, Figures 12A, 13, 14A, 15A, 16A, and 17A are cross-sectional views corresponding to the cross section cut along line A-A' in Figure 2, and Figures 12B, 14B, 15B, 16B, and 17B are cross-sectional views corresponding to the cross section cut along line B-B' in Figure 2. In describing FIGS. 12A to 17B, parts that are substantially the same as those described with reference to FIGS. 3A to 11B will be omitted, and differences will be mainly described.

[0042] Referring to Figures 12A and 12B, in the cell array region MCA, a buffer layer 114 including a first insulating layer 114A and a second insulating layer 114B is formed on a substrate 110, and in the peripheral circuit region PCA, a gate dielectric layer 116 is formed on the substrate 110. Next, a lower conductive layer 132 is formed on the buffer layer 114 in the cell array region MCA and the gate dielectric layer 116 in the peripheral circuit region PCA. Next, a portion of the substrate 110 and a portion of the isolation film 112 are etched to form a direct contact hole DCH exposing the first active region AC1 of the substrate 110. Next, a direct contact DC is formed in the direct contact hole DCH.

[0043] Next, in the cell array region MCA and the peripheral circuit region PCA, the middle conductive layer 134, the upper conductive layer 136, and the first capping layer 142 are sequentially formed on the lower conductive layer 132 and the direct contacts DC. The middle conductive layer 134 and the top conductive layer 136 may each comprise TiN, TiSiN, W, tungsten silicide, or a combination thereof. In an exemplary embodiment, the first capping layer 142 may consist of a single film. The first capping layer 142 may be comprised of an oxide, a nitride, an oxynitride, or a combination thereof. For example, the first capping layer 142 may include SiO2, SiN, ZrO, HfO, or a combination thereof.

[0044] In the method for manufacturing an integrated circuit device according to the present invention, after the step of forming the bit lines BL and the buried contacts BC in the cell array area MCA, the step of forming the gate structure PGT in the peripheral circuit area PCA is performed. Therefore, the height of the first capping layer 142 can be designed by taking into consideration only the processes of forming the bit lines BL and the buried contacts BC in the cell array region MCA. That is, the height of the first capping layer 142 can be adjusted to be lower than that of the comparative example. For example, the height of the first capping layer 142 can be reduced by about 43% compared to the comparative example, thereby reducing the process difficulty. For example, by reducing the height of the first capping layer 142 used as an etching mask, the line width roughness (LWR), aspect ratio, etc. can be improved, and the process difficulty can be reduced.

[0045] Referring to FIG. 13, in the cell array region MCA, the first capping layer 142 is patterned to form a first capping pattern 142A. In this process, the height of the first capping pattern 142A is reduced from the height of the first capping layer 142 (see FIG. 12A). Using the first capping pattern 142A as an etching mask, the upper conductive layer 136, the intermediate conductive layer 134, and the lower conductive layer 132 are etched to form a plurality of bit lines BL consisting of the lower conductive pattern 132A, the intermediate conductive pattern 134A, and the upper conductive pattern 136A. In the process of forming the plurality of bit lines BL, a portion of the sidewall of the direct contact DC is removed to expose a portion of the direct contact hole DCH.

[0046] Referring to FIGS. 14A and 14B, spacer structures 150 are formed on sidewalls of the plurality of bit lines BL and sidewalls of the direct contacts DC. The spacer structure 150 includes a first spacer layer 152 , a second spacer layer 154 , and a third spacer layer 156 . In this step, a buried insulating layer 158 is formed to fill the interior of the direct contact hole DCH. Also, a portion of the substrate 110 is removed to form a plurality of first recess spaces RS1 exposing the first active regions AC1 of the substrate 110 between the respective bit lines BL. A plurality of buried contacts BC are formed filling the first recess spaces RS1 and filling spaces between the bit lines BL, respectively. Each of the plurality of buried contacts BC includes a lower contact conductive layer 162 , a metal silicide film 164 , and an upper contact conductive layer 166 . In this process, the upper side of the first capping pattern 142A covering the bit line BL and a portion of the upper side of the spacer structure 150 are also removed, so that the vertical level of the first capping pattern 142A is lowered. In this case, in the cell array region MCA, the top surfaces of the first capping patterns 142A and the buried contacts BC are flush with each other.

[0047] Referring to FIGS. 15A and 15B, an insulating spacer 172 is formed to cover the cell array region MCA and the peripheral circuit region PCA. In the cell array region MCA and the peripheral circuit region PCA, the insulating spacer 172 conformally covers the first capping pattern 142A and the first capping layer 142.

[0048] 16A and 16B, in the peripheral circuit region PCA, the gate dielectric film 116, the lower conductive layer 132, the intermediate conductive layer 134, the upper conductive layer 136, and the lower capping layer 142 are patterned using the insulating spacers 172 as an etching mask to form a gate electrode PG consisting of a lower conductive pattern 132B, an intermediate conductive pattern 134B, and an upper conductive pattern 136B on the gate dielectric film 116, and a gate capping pattern 142B covering the gate electrode PG. Thereafter, gate spacers PGS are formed on both side walls of the gate structure PGT, which is a stacked structure of the gate dielectric film 116, the gate electrode PG, and the gate capping pattern 142B, and an ion implantation process is performed on both sides of the gate structure PGT to form source / drain regions in the second active region AC2. In this process, the vertical level of the insulating spacers 172 in the cell array area MCA is lowered. Thereafter, a second capping layer 174 is formed to cover the insulating spacers 172 in the cell array region MCA and to cover the gate structures PGT and gate spacers PGS in the peripheral circuit region PCA. Next, in the peripheral circuit area PCA, an interlayer insulating film 149 is formed to fill the space around the gate structure PGT. At this time, the insulating spacers 172 are formed conformally. The insulating spacer 172 conformally covers the upper surface of the buried contact BC and the first capping pattern 142A.

[0049] In an exemplary embodiment, the process of forming the second capping layer 174 is performed after the process of forming the bit line BL, thereby preventing deterioration of the bit line BL that occurs during the process of forming the gate structure PGT and the second capping layer 174 covering the gate structure PGT, and improving the characteristics of the integrated circuit device 100. Furthermore, since the process of forming the gate structure PGT is performed after the annealing process of the buried contact BC, the heat budget can be reduced and the characteristics of the integrated circuit device 100 can be improved. In addition, in the process of forming the gate structure PGT, the second capping layer 174 formed in the cell array region MCA can be used as an etching mask in the process of forming the landing pad LP, which will be described later.

[0050] Referring to Figures 16A and 16B, in the peripheral circuit region PCA, the interlayer insulating film 149 and the second capping layer 174 are etched to form a plurality of contact holes CPH that expose the second active region AC2 of the substrate 110, and a plurality of contact plugs CP that fill the plurality of contact holes CPH are formed. Next, an upper insulating layer 176 is formed to cover the second capping layer 174 in the cell array region MCA and the peripheral circuit region PCA. Next, a landing pad LP is formed through the upper insulating layer 176, the second capping layer 174, and the insulating spacer 172. The process of forming the landing pad LP is performed by a damascene process, but is not limited to this. The landing pads LP are arranged in an island shape and are connected to the buried contacts BC, respectively.

[0051] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0052] 100 Integrated circuit device 110 Substrate 112 Element isolation membrane 112T Isolation trench 114 Buffer Film 114A First insulating film 114B Second insulating film 116 Gate dielectric film 132A, 132B Lower conductive pattern 134A, 134B Intermediate conductive pattern 136A, 136B Upper conductive pattern 142 First capping layer 142A First Capping Pattern 142B Gate Capping Pattern 144 Mask Layer 149 Interlayer insulating film 150 Spacer Structure 152 First spacer layer 154 Second spacer layer 156 Third spacer layer 158 Buried insulating layer 162 Lower contact conductive layer 164 Metal silicide film 166 Upper contact conductive layer 172 Insulating spacer 174 Second Capping Layer 176 Upper insulating layer AC1 1st active area AC2 2nd active area BC Implantable Contacts BL Bit Line CP Contact Plug DC Direct Contact DCH Direct Contact Hole LP Landing Pad MCA cell array region PCA peripheral circuit area PG peripheral circuit gate electrode PGS Gate Spacer PGT Gate Structure RS1 First recess space WL Word Line

Claims

1. providing a substrate including a cell array region and a peripheral circuit region; forming a conductive layer on the cell array region and the peripheral circuit region; forming a capping insulating layer on the conductive layer; forming direct contacts and bit lines in the cell array region using the capping insulating layer as an etching mask; forming a spacer structure covering both sidewalls of the bit line and the direct contact; forming buried contacts between the direct contacts and the bit lines and between adjacent bit lines; forming an insulating spacer covering the cell array region and the peripheral circuit region; forming a gate structure in the peripheral circuit region using the insulating spacers as an etching mask.

2. The step of forming the capping insulating layer includes: forming a first capping layer on the conductive layer; 2. The method of claim 1, further comprising the step of: forming a mask layer on the first capping layer, the mask layer having a selectivity relative to the first capping layer.

3. 3. The method of claim 2, wherein forming the direct contact and the bit line comprises forming a first capping pattern and a mask pattern on the direct contact and the bit line.

4. 4. The method of claim 3, wherein the step of forming the buried contact includes forming the mask pattern so that an upper surface of the buried contact and an upper surface of the mask pattern are flush with each other.

5. forming the insulating spacer includes removing the mask pattern to expose the first capping pattern covering the bit line; 5. The method for manufacturing an integrated circuit device according to claim 4, wherein the insulating spacer is formed to have a step.

6. 2. The method of claim 1, wherein forming the gate structure comprises forming a second capping layer on the insulating spacer remaining in the cell array region, covering the gate structure.

7. 3. The method of claim 2, wherein the first capping layer and the masking layer comprise an oxide, a nitride, an oxynitride, or a combination thereof.

8. forming contact plugs on both sides of the gate structure in the peripheral circuit region; 7. The method of claim 6, further comprising the step of forming a landing pad connected to the buried contact and the contact plug.

9. The step of forming the landing pad includes: forming an upper insulating layer covering the gate structure and the second capping layer; forming a recess through the upper insulating layer, the second capping layer, and the insulating spacer; 9. The method of claim 8, further comprising forming the landing pad filling the recess.

10. providing a substrate including a cell array region and a peripheral circuit region; forming a conductive layer on the cell array region and the peripheral circuit region; forming a first capping layer consisting of a single layer on the conductive layer; forming direct contacts, bit lines, and capping patterns disposed on the direct contacts and the bit lines in the cell array region using the first capping layer as an etching mask; forming a spacer structure covering both sidewalls of the bit line and the direct contact; forming buried contacts between the direct contacts and the bit lines and between adjacent bit lines; forming an insulating spacer covering the cell array region and the peripheral circuit region; forming a gate structure in the peripheral circuit region using the insulating spacers as an etching mask.

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