Semiconductor device

Abstract

To provide a semiconductor device with a novel structure.SOLUTION: A semiconductor device includes a cell array executing product-sum operation of a first layer and product-sum operation of a second layer in an artificial neural network, a first circuit that inputs first data to the cell array, and a second circuit to which second data is output from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In a first period, a t-th (t is a natural number of 2 or more) piece of the first data is input to the first region from the first circuit, so that a t-th piece of the second data corresponding to the product-sum operation of the first layer is output to the second circuit. A (t-1)-th piece of the first data is input to the second region from the first circuit, so that a (t-1)-th piece of the second data corresponding to the product-sum operation of the second layer is output to the first circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] Currently, active development is underway on integrated circuits that mimic the workings of the human brain. These integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brainmorphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with significantly less power consumption than von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network with "neurons" and "synapses" is called an artificial neural network (ANN). By using an artificial neural network, it is possible to make inferences with accuracy comparable to or even exceeding that of humans. In an artificial neural network, the main operation is the weighted sum of neuron outputs, i.e., the sum-of-products operation.

[0005] Non-Patent Document 1 proposes a multiply-and-accumulate circuit using non-volatile memory elements. In this multiply-and-accumulate circuit, each memory element utilizes the subthreshold operation of a transistor having silicon in its channel formation region to output a current corresponding to the multiplication of data corresponding to a multiplier stored in each memory element and input data corresponding to a multiplicand. Furthermore, data corresponding to the multiply-and-accumulate operation is obtained by summing the currents output by the memory elements in each column. Because this multiply-and-accumulate circuit has internal memory elements, it is not necessary to read or write data from an external memory during multiplication and addition. This reduces the number of data transfers due to reads and writes, which is expected to reduce power consumption. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] X. Guo et al., “Fast, Energy-Efficient, Robust, and Reproducible Mixed-Signal Neuromorphic Classifier Based on Embedded NOR Flash Memory Technology” IEDM2017, pp.151-154. Summary of the Invention [Problem to be solved by the invention]

[0007] When a multiply-accumulate circuit performs a multiply-accumulate operation, power consumption may increase due to an increase in through current caused by miniaturization of transistors. In repetitive arithmetic processing such as a multiply-accumulate operation, it is important to improve not only the processing speed but also the processing capacity per unit of power.

[0008] Furthermore, by applying a display system equipped with a product-sum operation circuit to glasses-based AR (Augmented Reality) devices, it is possible to provide an advanced user experience that combines not only display functions but also sensor functions and AI processing functions. However, since such devices are expected to be powered by batteries, there are strict restrictions on power consumption. Therefore, the arithmetic unit that realizes such functions must be low-power.

[0009] An object of one embodiment of the present invention is to provide a semiconductor device or the like that has excellent arithmetic processing capability per unit power.An object of one embodiment of the present invention is to provide a semiconductor device or the like that has excellent low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device or the like that has a novel structure and is capable of performing product-sum operations.

[0010] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but it is sufficient that it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc. [Means for solving the problem]

[0011] One aspect of the present invention is a semiconductor device comprising: a cell array that performs a first layer product-sum operation and a second layer product-sum operation in an artificial neural network; a first circuit that inputs first data to the cell array; and a second circuit that outputs second data from the cell array, wherein the cell array has a plurality of cells, and the cell array has a first region and a second region; during a first period, the first region receives t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs t-th second data corresponding to the first layer product-sum operation to the second circuit; and the second region receives (t-1)-th first data from the first circuit and outputs (t-1)-th second data corresponding to the second layer product-sum operation to the second circuit.

[0012] One aspect of the present invention is an artificial neural network comprising a cell array that executes a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit that inputs first data to the cell array, and a second circuit that outputs second data from the cell array, wherein the cell array has a plurality of cells, the cell array having a first region and a second region, and wherein during a first period, the first region receives t-th (t is a natural number equal to or greater than 2) first data from the first circuit and outputs t-th second data corresponding to the product-sum operation of the first layer to the second region. the second region receives the (t-1)th first data from the first circuit and outputs the (t-1)th second data corresponding to the sum-of-products operation of the second layer to the second circuit; during a second period, the first region receives the (t+1)th first data from the first circuit and outputs the (t+1)th second data corresponding to the sum-of-products operation of the first layer to the second circuit; and the second region receives the tth first data from the first circuit and outputs the tth second data corresponding to the sum-of-products operation of the second layer to the second circuit.

[0013] In one aspect of the present invention, the semiconductor device is preferably such that the first data input to the second region is data obtained by performing a nonlinear operation on the second data output from the first region.

[0014] In one embodiment of the present invention, the semiconductor device preferably includes a third circuit to which the second data is output from the cell array, and the third circuit has a function of performing an operation based on a nonlinear function on the second data.

[0015] In one embodiment of the present invention, a semiconductor device is preferred in which a cell includes a first transistor, a second transistor, and a capacitor, wherein the first transistor has a function of holding a first potential corresponding to weight data provided to a gate of the second transistor via the first transistor when in an off state, the capacitor has a function of changing the first potential held at the gate of the second transistor to a second potential in response to a change in potential corresponding to first data provided to one electrode, and the second transistor has a function of outputting second data corresponding to the first data as an analog current to the other of the source and the drain.

[0016] In one aspect of the present invention, the semiconductor device is preferably such that the analog current is a current that flows when the second transistor operates in a subthreshold region.

[0017] In one embodiment of the present invention, the first transistor is preferably a semiconductor device including a semiconductor layer having a metal oxide in a channel formation region.

[0018] In one embodiment of the present invention, the metal oxide preferably contains In, Ga, and Zn.

[0019] In one embodiment of the present invention, the second transistors are preferably semiconductor devices each having a semiconductor layer containing silicon in a channel formation region.

[0020] One embodiment of the present invention is an electronic device including the semiconductor device, a driver circuit, a pixel circuit, a light-emitting element, and a light-receiving element, in which the pixel circuit has a function of controlling light emission of the light-emitting element, the driver circuit has a function of controlling the pixel circuit, the semiconductor device has a transistor included in a layer in which the pixel circuit is provided and a transistor included in a layer in which the driver circuit is provided, and the semiconductor device has a function of performing arithmetic processing using a current output by the light-receiving element as first data.

[0021] One embodiment of the present invention is an electronic device, in which the light-receiving element has an organic photodiode and the light-emitting element is an organic EL element.

[0022] One embodiment of the present invention is an electronic device, in which the light emitting element and the light receiving element are separated by a photolithography method.

[0023] Other aspects of the present invention will be described in the following embodiments and in the drawings. [Effects of the Invention]

[0024] According to one embodiment of the present invention, a semiconductor device or the like having excellent arithmetic processing performance per unit power can be provided. According to one embodiment of the present invention, a semiconductor device or the like having excellent low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device or the like having a novel structure and capable of performing product-sum operations can be provided.

[0025] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings of this specification. [Brief explanation of the drawings]

[0026] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 2]2A and 2B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 3] 3A and 3B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 4] 4A and 4B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 5] FIG. 5 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 7] FIG. 7 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 8] FIG. 8 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 9] FIG. 9 is a diagram illustrating a configuration example of a semiconductor device. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 11] 11A and 11B are diagrams illustrating a configuration example of a semiconductor device. [Figure 12] FIG. 12 is a diagram illustrating a configuration example of a semiconductor device. [Figure 13] 13A, 13B, and 13C are diagrams illustrating configuration examples of a semiconductor device. [Figure 14] 14A, 14B, 14C, and 14D are diagrams illustrating configuration examples of semiconductor devices. [Figure 15] 15A, 15B, and 15C are diagrams illustrating configuration examples of semiconductor devices. [Figure 16] FIG. 16 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 17] FIG. 17 is a diagram illustrating a configuration example of a semiconductor device. [Figure 18] 18A and 18B are diagrams illustrating an example of the configuration of a display device. [Figure 19] 19A and 19B are diagrams illustrating an example of the configuration of a display device. [Figure 20]FIG. 20 is a diagram illustrating an example of the configuration of a display device. [Figure 21] 21A and 21B are diagrams illustrating an example of the configuration of a display device. [Figure 22] 22A and 22B are diagrams illustrating an example of the configuration of a display device. [Figure 23] 23A, 23B, 23C, and 23D are diagrams illustrating configuration examples of a display device. [Figure 24] 24A and 24B are diagrams illustrating an example of the configuration of a display device. [Figure 25] 25A, 25B, 25C, and 25D are diagrams illustrating configuration examples of a display device. [Figure 26] 26A and 26B are diagrams illustrating an example of the configuration of a display device. [Figure 27] 27A to 27G are diagrams illustrating configuration examples of a display device. [Figure 28] FIG. 28 is a diagram illustrating an example of the configuration of a display device. [Figure 29] 29A and 29B are diagrams illustrating an example of the configuration of an electronic device. [Figure 30] 30A and 30B are diagrams illustrating an example of the configuration of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0027] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0028] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0029] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0030] In this specification, for example, the power supply potential VDD may be abbreviated to potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0031] Furthermore, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "_2", "_n", or "_m,n" may be added to the reference numeral. For example, the second wiring GL is written as wiring GL_2.

[0032] (Embodiment 1) A semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention can be used for arithmetic processing of an artificial neural network. As an example of the artificial neural network, a hierarchical neural network can be used.

[0033] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0034] 1 is a block diagram of a semiconductor device that combines a cell array and its peripheral circuits, which can perform the sum-of-products operation performed in the arithmetic processing of an artificial neural network (hereinafter sometimes referred to as a neural network). Note that the semiconductor device having the cell array and its peripheral circuits described in this embodiment is a circuit capable of sum-of-products operation, and may be referred to as an arithmetic circuit.

[0035] The semiconductor device MAC includes a circuit XCS, a circuit WCS, a circuit WSD, a cell array CA, and a circuit ITRZ. The cell array CA includes cells IM (also called memory cells) arranged in a matrix of m rows and n columns (m and n are natural numbers greater than or equal to 2).

[0036] The circuit XCS has a digital-to-analog (D / A) conversion circuit corresponding to each row of the cell array CA. The circuit XCS can supply analog signals corresponding to input data to the cells IM of each row of the cell array CA via signal lines X[1] to X[m]. The circuit XCS may be referred to as an X driver. The signal lines X[1] to X[m] may also be referred to as wirings XCL[1] to XCL[m].

[0037] The circuit XCS receives input data XDATA to be supplied to each row of the cell array CA. The input data XDATA is supplied to signal lines X[1] to X[m] at a predetermined timing according to a clock signal XCLK, a start pulse XSP, and a latch signal XLAT. For example, as shown in FIG. 2A, the circuit XCS includes a shift register SR1 and a latch circuit LAT1. The input data XDATA is assigned to each row according to the clock signal XCLK and start pulse XSP input to the shift register SR1 and is held in the latch circuit LAT1. The input data XDATA is then output to the signal lines X[1] to X[m] according to the timing of the latch signal XLAT.

[0038] The circuit WCS has a D / A conversion circuit corresponding to each column of the cell array CA and can supply analog signals corresponding to weight data from signal lines W[1] to W[n] to the cells IM of each column of the cell array CA. The circuit WCS is sometimes called a W driver. The signal lines W[1] to W[n] are sometimes called wirings WCL[1] to WCL[n].

[0039] The circuit WSD can supply signals for selecting rows to be written in the cell array CA from signal lines G[1] to G[m]. The circuit WSD may be referred to as a G driver. The signal lines G[1] to G[m] may be referred to as wirings WSL[1] to WSL[m].

[0040] The circuit ITRZ has an analog-to-digital (A / D) conversion circuit corresponding to each column of the cell array CA, and can acquire digital signals corresponding to the analog signals output from the cells IM of each column of the cell array CA to the signal lines Y[1] to Y[n]. The circuit ITRZ is sometimes called a Y driver. The signal lines Y[1] to Y[n] correspond to the signal lines W[1] to W[n], i.e., the wirings connected to the wirings WCL[1] to WCL[n].

[0041] The circuit ITRZ outputs output data YDATA acquired from each row of the cell array CA. The output data YDATA acquires analog signals from the signal lines Y[1] to Y[n] at predetermined timings based on a clock signal YCLK, a start pulse YSP, and a latch signal YLAT, and outputs the analog signals as digital output data YDATA. For example, as shown in FIG. 2B, the circuit ITRZ includes a shift register SR2, a latch circuit LAT2, and a switch SW_Y. The data on the signal lines Y[1] to Y[n] is held in the latch circuit LAT2. The data on the signal lines Y[1] to Y[n] held in the latch circuit LAT2 is output as output data YDATA when the switch SW_Y assigned to each column is turned on by the clock signal YCLK and start pulse YSP input to the shift register SR2.

[0042] Specific examples of the circuit XCS, the circuit WCS, the circuit WSD, the cell array CA, and the circuit ITRZ, and an example of their operation will be described in detail in the third embodiment.

[0043] Here, we will explain hierarchical neural networks. As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer. Figure 3A shows a network diagram of a three-layer perceptron, which is an example of a hierarchical neural network. In Figure 3A, the first layer corresponds to the input layer, the second layer corresponds to the intermediate layer, and the third layer corresponds to the output layer.

[0044] Each layer of the neural network has one or more neurons NU. In Figure 3A, the first layer has m neurons, the second layer has n neurons, and the third layer has p neurons (n, m, and p are natural numbers greater than or equal to 2).

[0045] In Fig. 3A, in the first layer, which is the input layer, data X1[1] to X1[m] are provided to m neurons. Data X1[1] to X1[m] are output from each neuron in the first layer to each neuron in the second layer. In Fig. 3A, in the third layer, which is the output layer, data X2[1] to X2[n] are provided to p neurons. The neurons in the output layer output data Y2[1] to Y2[p] obtained by performing a fully connected process between data X2[1] to X2[n] and weight data W2[1] to W2[n] (not shown).

[0046] The signals input and output to and from neurons in the second layer, which corresponds to the hidden layer, will be explained using Figure 3B. Figure 3B shows data X1[1] to X1[m] input from each neuron in the first layer and weight data W1[1] to W1[m] held by neurons in the second layer. Figure 3B also shows data Y1[1] to Y1[m] obtained by a multiply-and-accumulate operation of the input data X1[1] to X1[m] and weight data W1[1] to W1[m]. Data Y1[1] to Y1[m] is output to each neuron in the third layer as data X2[1], which has undergone nonlinear operation based on activation function f.

[0047] For example, for the t-th (t is a natural number equal to or greater than 2) data X1[1](t) through X1[m](t), each data is input and output in each layer of the neural network in Fig. 3A as shown in Fig. 4A. Also, for the (t-1)-th data X1[1](t-1) through X1[m](t-1), each data is input and output in each layer of the neural network in Fig. 3A as shown in Fig. 4B.

[0048] In this neural network, the tth input data X1[1](t) to X1[m](t) undergoes a multiply-and-accumulate operation Y1[j](t) = ΣW1[i,j]X1[i](t) and a nonlinear operation X2[j](t) = f(Y1[j](t)) in the second layer, which is the intermediate layer, and a multiply-and-accumulate operation Y2[k](t) = ΣW2[j,k]X2[j](t) in the third layer, which is the output layer. Similarly, for the input (t-1)th data X1[1](t-1) to X1[m](t-1), the second layer, which is the intermediate layer, performs a multiply-and-accumulate operation Y1[j](t-1) = ΣW1[i,j]X1[i](t-1) and a nonlinear operation X2[j](t-1) = f(Y1[j](t-1)). The third layer, which is the output layer, performs a multiply-and-accumulate operation Y2[k](t) = ΣW2[j,k]X2[j](t-1). The layers that perform the multiply-and-accumulate operation may be referred to as the first layer and the second layer. For example, the second layer, which is the intermediate layer, may be referred to as the first layer, and the third layer, which is the output layer, may be referred to as the second layer. Note that i, j, and k in each equation are natural numbers. The nonlinear operation is an operation using a nonlinear function f(X) on X. Examples of the nonlinear function f(X) include a sigmoid function and a ReLU function.

[0049] Fig. 5 is a diagram in which the areas of the cell array CA shown in Fig. 1 are divided according to the neural networks shown in Fig. 4A and Fig. 4B. In the hidden layer for the t-th data X1[1](t) to X1[m](t), the m-row, n-column product-sum operation Y1[j](t) = ΣW1[i,j]X1[i](t) is assigned to area L1, and in the output layer for the (t-1)-th data X1[1](t-1) to X1[m](t-1), the n-row, p-column product-sum operation Y2[k](t-1) = ΣW2[j,k]X2[j](t-1) is assigned to area L2.

[0050] By using the configuration of Figure 5, it is possible to perform product-sum operations in multiple layers of a neural network using a single cell array CA, thereby providing a low-power arithmetic processing device that can efficiently perform arithmetic processing.

[0051] Fig. 6 is a timing chart when the cell array CA shown in Fig. 1 is divided into regions and operated as shown in Fig. 5. In the following explanation, it is assumed that weight data W1[i,j] is stored in cell IM in the i-th row and j-th column (i = 1 to m, j = 1 to n) of cell array CA. It is also assumed that weight data W2[i,j] is stored in cell IM in the (m+i)-th row and (n+j)-th column (i = 1 to n, j = 1 to p) of cell array CA.

[0052] At time TX0, the t-th data X1[1](t) through X1[m](t) and the hidden layer nonlinear operation data X2[1](t-1) through X2[n](t-1) for the (t-1)th data X1[1](t-1) through X1[m](t-1) are sequentially input to the circuit XCS. The hidden layer nonlinear operation data X2[1](t-1) through X2[n](t-1) for the t-th data X1[1](t) through X1[m](t) and the (t-1)th data X1[1](t-1) through X1[m](t-1) are sequentially captured into the latch circuit of the circuit XCS in synchronization with the clock signal XCLK.

[0053] At time TX1, the t-th analog signal y1[1](t-1) = Σw1[i,1]x1[i](t-1) to y1[n](t-1) = Σw1[i,n]x1[i](t-1) and the (t-2)-th analog signal y2[1](t-2) = Σw2[j,1]x2[j](t-2) to y2[p](t-2) = Σw2[j,p]x1[j](t-2) are determined in each column of the cell array CA and supplied to signal lines Y[1] to Y[n] and Y[n+1] to Y[n+p]. The A / D conversion circuits corresponding to each column of the cell array CA generate the (t-1)th output data Y1[1](t-1) to Y1[n](t-1) and the (t-2)th output data Y2[1](t-2) to Y2[p](t-2) corresponding to the (t-1)th analog signal y1[1](t-1) to y1[n](t-1) and the (t-2)th analog signal y2[1](t-2) to y2[p](t-2).

[0054] At time TX2, by setting the latch signal YLAT to H level, the (t-1)th data Y1[1](t-1) to Y1[n](t-1) and the (t-2)th data Y2[1](t-2) to Y2[l](t-2) are taken into the latch circuit of circuit ITRZ and output sequentially in synchronization with the clock signal YCLK.

[0055] At time TX3, by setting the latch signal XLAT to H level, the D / A conversion circuit corresponding to each row of the cell array CA generates the t-th analog signals x1[1](t) to x1[m](t) corresponding to the t-th data X1[1](t) to X1[m](t), and the (t-1)-th analog signals x2[1](t-1) to x2[n](t-1) corresponding to the intermediate layer nonlinear operation data X2[1](t-1) to X2[n](t-1) for the (t-1)-th data X1[1](t-1) to X1[m](t-1), and these are supplied to the signal lines X[1] to X[m], X[m+1] to X[m+n].

[0056] During the period (first period) from time TX0 to time TX3, the (t-1)th data X1[1](t-1) to X1[m](t-1) are input to area L1 (first region) in Fig. 5, and thereby the (t-1)th data Y1[1](t-1) to Y1[n](t-1) corresponding to the product-sum operation of area L1 can be output. Also, during the period (first period) from time TX0 to time TX3, the (t-2)th data X2[1](t-2) to X2[m](t-2) are input to area L2 (second region) in Fig. 5, and thereby the (t-2)th data Y2[1](t-2) to Y2[n](t-2) corresponding to the product-sum operation of area L2 can be output.

[0057] At time TX4, the (t+1)th data X1[1](t+1) through X1[m](t+1) and the hidden layer nonlinear operation data X2[1](t) through X2[n](t) for the t-th data X1[1](t) through X1[m](t) are sequentially input to the circuit XCS. The (t+1)th data X1[1](t+1) through X1[m](t+1) and the hidden layer nonlinear operation data X2[1](t) through X2[n](t) for the t-th data X1[1](t) through X1[m](t) are sequentially captured into the latch circuit of the circuit XCS in synchronization with the clock signal XCLK.

[0058] At time TX5, the t-th analog signal y1[1](t) = Σw1[i,1]x1[i](t) to y1[n](t) = Σw1[i,n]x1[i](t) and the (t-1)-th analog signal y2[1](t-1) = Σw2[j,1]x2[j](t-1) to y2[p](t-1) = Σw2[j,p]x1[j](t-1) in each column of the cell array CA are determined and supplied to signal lines Y[1] to Y[n] and Y[n+1] to Y[n+p]. The A / D conversion circuits corresponding to each column of the cell array CA generate the tth output data Y1[1](t) to Y1[n](t) and the (t-1)th output data Y2[1](t-1) to Y2[p](t-1) corresponding to the tth analog signal y1[1](t) to y1[n](t) and the (t-1)th analog signal y2[1](t-1) to y2[p](t-1).

[0059] At time TX6, by setting the latch signal YLAT to H level, the t-th data Y1[1](t) to Y1[n](t) and the (t-1)-th data Y2[1](t-1) to Y2[l](t-1) are taken into the latch circuit of the circuit ITRZ and output sequentially in synchronization with the clock signal YCLK.

[0060] At time TX7, by setting the latch signal XLAT to H level, the D / A conversion circuit corresponding to each row of the cell array CA generates the (t+1)th analog signals x1[1](t+1) to x1[m](t+1) corresponding to the (t+1)th data X1[1](t+1) to X1[m](t+1), and the tth analog signals x2[1](t) to x2[n](t) corresponding to the intermediate layer nonlinear operation data X2[1](t) to X2[n](t) for the tth data X1[1](t) to X1[m](t), and these are supplied to the signal lines X[1] to X[m], X[m+1] to X[m+n] (not shown).

[0061] During the period from time TX4 to time TX7 (second period), the t-th data X1[1](t) to X1[m](t) are input to area L1 (first region) in Fig. 5, and t-th data Y1[1](t) to Y1[n](t) corresponding to the product-sum operation of area L1 can be output. Also, during the period from time TX4 to time TX7 (second period), the (t-1)th data X2[1](t-1) to X2[m](t-1) are input to area L2 (second region) in Fig. 5, and the (t-1)th data Y2[1](t-1) to Y2[n](t-1) corresponding to the product-sum operation of area L2 can be output.

[0062] Here, it is preferable to output the t-th data Y1[1](t) through Y1[n](t) in accordance with the cycle of the clock signal YCLK, and then execute a nonlinear operation X2[j](t)=f(Y1[j](t)) in the hidden layer corresponding to the t-th data, store the result of the nonlinear operation in a first-in-first-out (FIFO), and read out the nonlinear operation data X2[1](t) through X2[n](t) from the FIFO in accordance with the cycle of the clock signal XCLK. With this configuration, the operating speeds of the D / A conversion circuit and the A / D conversion circuit can be set to values ​​appropriate for each, thereby enabling reductions in power consumption, etc.

[0063] Furthermore, it is preferable to synchronize the period of the clock signal YCLK with the period of the clock signal XCLK, so that the timing of outputting the t-th data Y1[1](t) to Y1[n](t) and the timing of executing the nonlinear operation X2[j](t) = f(Y1[j](t)) in the intermediate layer corresponding to the t-th data are synchronized with the timing of inputting X2[j](t). This configuration eliminates the need for a mechanism such as a first-in-first-out (FIFO) to store the results of the nonlinear operation and read them out in synchronization with the clock signal XCLK, simplifying the configuration of the semiconductor device.

[0064] With the above configuration, a single cell array can perform product-sum operations equivalent to multiple layers of a neural network, providing a low-power processing device that can efficiently perform calculations.

[0065] (Embodiment 2) In this embodiment, a configuration different from that of the semiconductor device described in the above embodiment will be described. Note that the detailed description of the same configuration as in the first embodiment will be omitted, as the description is incorporated herein by reference.

[0066] In this embodiment, a case will be described in which calculations are performed in an example of the hierarchical neural network described in Fig. 3A of Embodiment 1. Fig. 7 shows, as an example, how, for the t-th (t is a natural number equal to or greater than 2) data X1[1](t) to X1[m](t), data X1[1](t) to X1[m](t) are input / output between the first and second layers of the neural network, and data X2[1](t) to X2[n](t) are input / output between the second and third layers of the neural network.

[0067] In this neural network, the t-th input data X1[1](t) through X1[m](t) undergoes a multiply-and-accumulate operation Y1[j](t) = ΣW1[i,j]X1[i](t) and a nonlinear operation X2[j](t) = f(Y1[j](t)) in the second layer (also referred to as the first layer), which is the intermediate layer, and a multiply-and-accumulate operation Y2[k](t) = ΣW2[j,k]X2[j](t) in the third layer (also referred to as the second layer), which is the output layer. Note that i, j, and k in each equation are natural numbers. The nonlinear operation is an operation using a nonlinear function f(X) on X. Examples of the nonlinear function f(X) include a sigmoid function and a ReLU function.

[0068] 8 is a diagram in which the area of ​​the cell array CA is divided corresponding to the neural network shown in FIG. 7. The cell array CA shown in FIG. 8 has (m+n) rows and (n+p) columns of cells IM connected to signal lines X[1] to X[m] and X[m+1] to X[m+n], and signal lines Y[1] to X[n] and X[n+1] to X[n+p]. In the cell array CA shown in FIG. 8, the t-th data X1[1](t) to X1[m](t) and the t-th data X2[1](t) to X2[n](t) are input to the signal lines X[1] to X[m+n]. In the cell array CA shown in FIG. 8, the t-th data Y1[1](t) to Y1[n](t) and the t-th data Y2[1](t) to Y2[p](t) are output to the signal lines Y[1] to Y[n+p]. That is, the m-row, n-column product-sum operation Y1[j](t) = ΣW1[i,j]X1[i](t) in the second layer, which is the intermediate layer for the t-th data X1[1](t) through X1[m](t), is assigned to area L1, and the n-row, p-column product-sum operation Y2[k](t) = ΣW2[j,k]X2[j](t) in the third layer, which is the output layer for the t-th data X2[1](t) through X2[n](t), is assigned to area L2.

[0069] Fig. 9 is a drive timing chart of a semiconductor device in which the cell array CA is divided into areas as in Fig. 8. It is assumed that weight data w1[i,j] is stored in cell IM in the i-th row and j-th column (i = 1 to m, j = 1 to n) of the cell array CA. It is also assumed that weight data w2[i,j] is stored in cell IM in the (m+i)-th row and (n+j)-th column (i = 1 to n, j = 1 to p) of the cell array CA.

[0070] At time TX10, analog signals x1[1](t) to x1[m](t) corresponding to the t-th data are supplied to signal lines X[1] to X[m]. In area L1 of cell array CA, an operation corresponding to a product-sum operation ΣW1[i,j]X1[i](t) of m rows and n columns is executed.

[0071] At time TX11, analog signals y1[1](t) = Σw1[i,1]x1[i](t) to y1[n](t) = Σw1[i,n]x1[i](t) of each column of area L1 of cell array CA are determined and supplied to signal lines Y[1] to Y[n].

[0072] At time TX12, analog signals x2[1](t) through x2[n](t) obtained by performing nonlinear operations on analog signals y1[1](t) through y1[n](t) are supplied to signal lines X[m+1] through X[m+n]. In area L2 of cell array CA, an operation equivalent to a product-sum operation Σw2[j,k]x2[j](t) of n rows and p columns is executed.

[0073] At time TX13, analog signals y2[1](t)=Σw2[j,1]x2[j](t) through y2[l](t)=Σw2[j,n]x2[j](t) for each column of area L2 of cell array CA are determined and supplied to signal lines Y[n+1] through Y[n+p]. Here, analog signals y2[1](t) through y2[p](t) correspond to the results of performing the arithmetic processing of the neural network in FIG. 7 on the t-th data.

[0074] At time TX20, analog signals x1[1](t+1) to x1[m](t+1) corresponding to the (t+1)th data are supplied to signal lines X[1] to X[m]. In area L1 of cell array CA, an operation corresponding to a product-sum operation Σw1[i,j]x1[i](t+1) of m rows and n columns is executed.

[0075] At time TX21, analog signals y1[1](t+1) = Σw1[i,1]x1[i](t+1) to y1[n](t+1) = Σw1[i,n]x1[i](t+1) of each column of area L1 of cell array CA are determined and supplied to signal lines Y[1] to Y[n].

[0076] At time TX22, analog signals x2[1](t+1) through x2[n](t+1) are generated by performing a nonlinear operation on analog signals y1[1](t+1) through y1[n](t+1), and the analog signals x2[1](t+1) through x2[n](t+1) are supplied to signal lines X[m+1] through X[m+n]. In area L2 of cell array CA, an operation equivalent to a product-sum operation Σw2[j,k]x2[j](t+1) of n rows and p columns is executed.

[0077] At time TX23, analog signals y2[1](t+1)=Σw2[j,1]x2[j](t+1) through y2[l](t+1)=Σw2[j,n]x2[j](t+1) for each column of area L2 of cell array CA are determined and supplied to signal lines Y[n+1] through Y[n+p]. Here, analog signals y2[1](t+1) through y2[l](t+1) correspond to the results of performing the neural network calculation process shown in FIG. 7 on the (t+1)th data.

[0078] 10 shows an example of peripheral circuits of a semiconductor device MAC2 including a cell array CA that enables the arithmetic processing of this embodiment. The semiconductor device MAC2 includes a circuit XCS, a circuit WCS, a circuit WSD, a cell array CA, a circuit ITRZ, and a circuit ACT. The cell array CA includes cells IM arranged in a matrix of (m+n) rows and (n+p) columns. The semiconductor device MAC of this embodiment differs from the semiconductor device MAC of the first embodiment in that a circuit ACT is provided between signal lines Y[1] to Y[n] and signal lines X[m+1] to X[m+n].

[0079] The circuit ACT has a circuit that performs a nonlinear calculation corresponding to each column of the cell array CA. The circuit ACT can acquire an analog signal that has undergone a nonlinear calculation corresponding to the analog signal output from each column of the cell array CA to the signal lines Y[1] to Y[n]. The circuit ACT can also supply the analog signal to the cells IM of each row of the cell array CA by outputting the analog signal to the signal lines X[m+1] to X[m+n].

[0080] It is preferable that the signal lines X[m+1] to X[m+n] be configured to selectively supply analog signals from the circuit ACT and the circuit XCS. It is also preferable that the signal lines Y[1] to Y[n] be configured to supply analog signals to the circuit ITRZ as well as the circuit ACT. This configuration allows the number of rows and columns of the areas L1 and L2 to be flexibly changed according to the configuration of the neural network to be processed. It is also possible to select the supply of analog signals from the circuit XCS or the circuit ACT to all of the signal lines X[1] to X[m+n], or to select a group of several of the signal lines. It is also possible to select the supply of analog signals from all of the signal lines Y[1] to Y[n+p] to the circuit ITRZ or the circuit ACT, or to select a group of several of the signal lines. Furthermore, the signal lines X[1] to X[m+n] and the signal lines Y[1] to Y[n+p] to which no analog signals are supplied can be electrically disconnected as appropriate using an analog switch or the like.

[0081] 11A shows an example of the configuration of a circuit ACT having a function of performing nonlinear calculations, in which two columns of a cell array CA are used as a pair when the weight data is positive and negative.

[0082] In the configuration shown in FIG. 11A, as shown in FIG. 11B, the paired signal lines Y P [j], Y N Analog current I flowing through [j] + , I - A configuration for performing nonlinear calculations according to the above will be described.

[0083] The analog current I shown in FIGS. 11A and 11B + is the current output from the column corresponding to the positive weight data. Also, the analog current I - is the current output from the column corresponding to the negative weight data. In the configuration shown in FIG. 11A, the circuit ACT + >I - , that is, when the net result of the multiply-and-accumulate operation is positive, (I + -I - ) is the analog current I RELU On the other hand, in the configuration shown in FIG. 11A, the circuit ACT outputs I + - , that is, when the net result of the multiply-and-accumulate operation is negative, the analog current I RELU In other words, an output equivalent to the result of performing a nonlinear operation using the ReLU function on the result of the sum-of-products operation can be obtained.

[0084] With the above configuration, it is possible to provide a low-power semiconductor device that can efficiently perform product-sum operations equivalent to multiple layers of a neural network using a single cell array without performing analog-to-digital or digital-to-analog conversion in between.

[0085] (Embodiment 3) ​In this embodiment, a configuration example of the cell array and its peripheral circuits described in the above embodiment will be described.

[0086] <Configuration example of cell array CA> 12 shows a configuration example of a semiconductor device that performs a product-sum operation of weight data that is positive or "0" and input data that is positive or "0". The semiconductor device MAC1 shown in FIG. 12 is a circuit that performs a product-sum operation of weight data that corresponds to the potential held in each cell and input data (first data) that is input, and calculates an activation function using intermediate data (second data) of the product-sum operation. Note that the weight data and input data can be, for example, analog data or multi-valued data (discrete data).

[0087] The semiconductor device MAC1 has a circuit WCS, a circuit XCS, a circuit WSD, a circuit SWS1, a circuit SWS2, a cell array CA, and circuits ITRZ[1] to ITRZ[n].

[0088] The cell array CA has cells IM[1,1] to IM[m,n] (where m is an integer greater than or equal to 1 and n is an integer greater than or equal to 1) and cells IMref[1] to IMref[m]. Each of cells IM[1,1] to IM[m,n] has a function of holding a potential corresponding to an amount of current according to weight data, and cells IMref[1] to IMref[m] have a function of supplying a potential corresponding to input data required for performing a product-sum operation with the held weight data to wirings XCL[1] to XCL[m].

[0089] In addition, the cell array CA in Figure 12 has n+1 cells arranged in a matrix in the row direction and m cells in the column direction, but the cell array CA may have any configuration as long as it has two or more cells arranged in a matrix in the row direction and two or more cells arranged in the column direction, and when the semiconductor devices MAC and MAC2 described in the above embodiments 1 and 2 are applied, it is sufficient to configure it so that cells IM corresponding to each region are provided.

[0090] Each of cells IM[1,1] to IM[m,n] has, for example, a transistor F1, a transistor F2, and a capacitance C5, and each of cells IMref[1] to IMref[m] has, for example, a transistor F1m, a transistor F2m, and a capacitance C5m.

[0091] In particular, it is preferable that the sizes (e.g., channel length, channel width, transistor configuration, etc.) of the transistors F1 included in each of the cells IM[1,1] to IM[m,n] are equal to each other, and it is also preferable that the sizes of the transistors F2 included in each of the cells IM[1,1] to IM[m,n] are equal to each other. It is also preferable that the sizes of the transistors F1m included in each of the cells IMref[1] to IMref[m] are equal to each other, and it is also preferable that the sizes of the transistors F2m included in each of the cells IMref[1] to IMref[m] are equal to each other. It is also preferable that the sizes of the transistors F1 and F1m are equal to each other, and it is also preferable that the sizes of the transistors F2 and F2m are equal to each other.

[0092] By making the transistor sizes equal to each other, the electrical characteristics of each transistor can be made approximately equal. Therefore, by making the size of the transistor F1 included in each of cells IM[1,1] to IM[m,n] equal and making the size of the transistor F2 included in each of cells IM[1,1] to IM[m,n] equal, each of cells IM[1,1] to IM[m,n] can perform approximately the same operation under the same conditions. Here, the same conditions refer to, for example, the input potentials to the source, drain, gate, etc. of transistor F1, the input potentials to the source, drain, gate, etc. of transistor F2, and the voltages input to each of cells IM[1,1] to IM[m,n]. Furthermore, by making the size of the transistor F1m included in each of cells IMref[1] to IMref[m] equal and making the size of the transistor F2m included in each of cells IMref[1] to IMref[m] equal, for example, the operation and results of the operation of cells IMref[1] to IMref[m] can be made approximately the same. They can perform substantially the same operation under the same conditions, which means, for example, the input potentials to the source, drain, gate, etc. of transistor F1m, the input potentials to the source, drain, gate, etc. of transistor F2m, and the voltages input to each of cells IMref[1] to IMref[m].

[0093] Unless otherwise specified, the transistors F1 and F1m are considered to ultimately operate in a linear region when they are on. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors are considered to include a voltage range in which they operate in a linear region. However, one embodiment of the present invention is not limited to this. For example, the transistors F1 and F1m may operate in a saturation region when they are on, or may operate in both the linear region and the saturation region.

[0094] Furthermore, unless otherwise specified, the transistors F2 and F2m are considered to operate in the subthreshold region (i.e., in the transistor F2 or the transistor F2m, the gate-source voltage is lower than the threshold voltage, more preferably, the drain current increases exponentially with the gate-source voltage). That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are considered to be within a voltage range in which they operate in the subthreshold region. Therefore, the transistors F2 and F2m are considered to operate such that an off-state current flows between the source and the drain.

[0095] For example, the transistor F1 and / or the transistor F1m is preferably a transistor (also referred to as an OS transistor) having a metal oxide (also referred to as an oxide semiconductor) in a channel formation region. The channel formation region of the transistor F1 and / or the transistor F1m is more preferably an oxide containing at least one of indium, gallium, and zinc. Instead of the oxide, an oxide containing at least one of indium, an element M (e.g., aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like) and zinc may be used.

[0096] By using OS transistors as the transistors F1 and / or F1m, leakage current of the transistors F1 and / or F1m can be suppressed, thereby reducing the power consumption of the semiconductor device. Specifically, when the transistors F1 and / or F1m are off, leakage current from the retention node to the wiring XCL or WCL can be significantly reduced, thereby reducing the number of refresh operations for the potential of the retention node. Furthermore, reducing the number of refresh operations can reduce the power consumption of the semiconductor device. Furthermore, by significantly reducing the leakage current from the retention node to the wiring WCL or XCL, the cell can retain the potential of the retention node for a long time, thereby improving the operation accuracy of the semiconductor device.

[0097] Furthermore, by using an OS transistor for the transistor F2 and / or the transistor F2m, the transistors can operate over a wide current range in the subthreshold region, thereby reducing current consumption. Furthermore, by using an OS transistor for the transistor F2 and / or the transistor F2m, the transistors can be manufactured simultaneously with the transistors F1 and F1m, which may shorten the manufacturing process of the semiconductor device. The transistors F2 and / or the transistor F2m can be transistors containing silicon in their channel formation regions (hereinafter referred to as Si transistors) other than OS transistors. Examples of silicon that can be used include amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, and single-crystal silicon.

[0098] Incidentally, when semiconductor devices and the like are highly integrated on a chip, the chip may generate heat due to the operation of the circuit. This heat increases the temperature of the transistor, which may change the characteristics of the transistor, resulting in a change in field-effect mobility or a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, so they are less likely to experience changes in field-effect mobility due to temperature changes and are less likely to experience a decrease in operating frequency. Therefore, by using OS transistors, it is easier to perform calculations, processing, and the like, even in high-temperature environments. Therefore, when configuring a semiconductor device that is resistant to heat generation due to operation, it is preferable to use OS transistors as the transistors.

[0099] In each of the cells IM[1,1] to IM[m,n], a first terminal of the transistor F1 is electrically connected to a gate of the transistor F2. A first terminal of the transistor F2 is electrically connected to a wiring VE. A first terminal of the capacitor C5 is electrically connected to the gate of the transistor F2.

[0100] In each of the cells IMref[1] to IMref[m], a first terminal of the transistor F1m is electrically connected to a gate of the transistor F2m, a first terminal of the transistor F2m is electrically connected to a wiring VE, and a first terminal of the capacitor C5m is electrically connected to the gate of the transistor F2m.

[0101] 12, back gates are illustrated for the transistors F1, F2, F1m, and F2m. Although the connection configuration of the back gates is not illustrated, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor having a back gate, the gate and back gate may be electrically connected to increase the on-state current of the transistor. That is, for example, the gate and back gate of the transistor F1 may be electrically connected, or the gate and back gate of the transistor F1m may be electrically connected. Furthermore, for example, in a transistor having a back gate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, a wiring may be provided to electrically connect the back gate of the transistor to an external circuit or the like, and a potential may be applied to the back gate of the transistor from the external circuit or the like.

[0102] 12 includes a back gate, the semiconductor device of one embodiment of the present invention is not limited thereto. For example, the transistors F1 and F2 in FIG. 12 may have a structure without a back gate, that is, may have a single-gate structure. Furthermore, some of the transistors may have a back gate, and other transistors may have a structure without a back gate.

[0103] 12 illustrates n-channel transistors as the transistors F1 and F2, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, some or all of the transistors F1 and F2 may be replaced with p-channel transistors. Note that when some or all of the transistors F1 and F2 are replaced with p-channel transistors, the voltage applied by the wiring, the potential of the node NN, the potential of the node NNref, and the like, which are described in the specification, etc., may be changed as necessary so that the transistors F1 and F2 operate as desired.

[0104] The above-described examples of changes to the structure and polarity of the transistors are not limited to transistors F1 and F2. For example, the structure or polarity may be changed in the same way for transistors F1m, F2m, transistors F3[1] to F3[n], and transistors F4[1] to F4[n], which will be described later, as well as transistors described elsewhere in the specification or shown in other drawings.

[0105] The wiring VE functions as a wiring for passing a current between the first terminal and the second terminal of each of the transistors F2 in the cells IM[1,1], IM[m,1], IM[1,n], and IM[m,n], and also as a wiring for passing a current between the first terminal and the second terminal of each of the transistors F2m in the cells IMref[1] and IMref[m]. As an example, the wiring VE functions as a wiring for supplying a constant voltage. The constant voltage may be, for example, a low-level potential or a ground potential.

[0106] In cell IM[1,1], the second terminal of transistor F1 is electrically connected to wiring WCL[1], and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In FIG. 12, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[1,1] is designated as node NN[1,1].

[0107] In cell IM[m,1], the second terminal of transistor F1 is electrically connected to wiring WCL[1], and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In FIG. 12, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[m,1] is designated as node NN[m,1].

[0108] In cell IM[1,n], the second terminal of transistor F1 is electrically connected to wiring WCL[n], and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[n], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In FIG. 12, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[1,n] is referred to as node NN[1,n].

[0109] In cell IM[m,n], the second terminal of transistor F1 is electrically connected to wiring WCL[n], and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[n], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In FIG. 12, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[m,n] is designated as node NN[m,n].

[0110] In cell IMref[1], the second terminal of transistor F1m is electrically connected to line XCL[1], and the gate of transistor F1m is electrically connected to line WSL[1]. The second terminal of transistor F2m is electrically connected to line XCL[1], and the second terminal of capacitor C5 is electrically connected to line XCL[1]. In FIG. 12, the connection point between the first terminal of transistor F1m, the gate of transistor F2m, and the first terminal of capacitor C5 in cell IMref[1] is referred to as node NNref[1].

[0111] In cell IMref[m], the second terminal of transistor F1m is electrically connected to line XCL[m], and the gate of transistor F1m is electrically connected to line WSL[m]. The second terminal of transistor F2m is electrically connected to line XCL[m], and the second terminal of capacitor C5 is electrically connected to line XCL[m]. In FIG. 12, the connection point between the first terminal of transistor F1m, the gate of transistor F2m, and the first terminal of capacitor C5 in cell IMref[m] is referred to as node NNref[m].

[0112] Note that the nodes NN[1,1] to NN[m,n] and the nodes NNref[1] to NNref[m] function as holding nodes for the respective cells.

[0113] In cells IM[1,1] to IM[m,n], for example, when transistor F1 is in the on state, transistor F2 is configured as a diode. When transistor F1 is in the on state and a current of magnitude I flows from wiring WCL to the second terminal of transistor F2, with the constant voltage provided by wiring VE as the ground potential (GND), the potential of the gate (node ​​NN) of transistor F2 is determined according to the current magnitude I. Since transistor F1 is in the on state, the potential of the second terminal of transistor F2 is ideally equal to the gate (node ​​NN) of transistor F2. By turning transistor F1 off, the potential of the gate (node ​​NN) of transistor F2 is maintained. This allows transistor F2 to pass a current of magnitude I between its source and drain, depending on the ground potential of the first terminal of transistor F2 and the potential of the gate (node ​​NN) of transistor F2. In this specification and the like, this operation is referred to as "setting (programming) the amount of current flowing between the source and drain of transistor F2 of cell IM to I."

[0114] The circuit SWS1 includes, for example, transistors F3[1] to F3[n]. A first terminal of the transistor F3[1] is electrically connected to the wiring WCL[1], a second terminal of the transistor F3[1] is electrically connected to the circuit WCS, and a gate of the transistor F3[1] is electrically connected to the wiring SWL1. A first terminal of the transistor F3[n] is electrically connected to the wiring WCL[n], a second terminal of the transistor F3[n] is electrically connected to the circuit WCS, and a gate of the transistor F3[n] is electrically connected to the wiring SWL1.

[0115] As each of the transistors F3[1] to F3[n], for example, a transistor applicable to the transistor F1 and / or the transistor F2 can be used. In particular, as each of the transistors F3[1] to F3[n], it is preferable to use an OS transistor.

[0116] The circuit SWS1 functions as a circuit that brings the circuit WCS and each of the wirings WCL[1] to WCL[n] into a conductive state or a non-conductive state.

[0117] The circuit SWS2 includes, for example, transistors F4[1] to F4[n]. A first terminal of the transistor F4[1] is electrically connected to the wiring WCL[1], a second terminal of the transistor F4[1] is electrically connected to the input terminal of the circuit ITRZ[1], and a gate of the transistor F4[1] is electrically connected to the wiring SWL2. A first terminal of the transistor F4[n] is electrically connected to the wiring WCL[n], a second terminal of the transistor F4[n] is electrically connected to the input terminal of the circuit ITRZ[n], and a gate of the transistor F4[n] is electrically connected to the wiring SWL2.

[0118] As each of the transistors F4[1] to F4[n], for example, a transistor applicable to the transistor F1 and / or the transistor F2 can be used. In particular, as each of the transistors F4[1] to F4[n], it is preferable to use an OS transistor.

[0119] The circuit SWS2 has a function of bringing the wiring WCL[1] and the circuit ITRZ[1] and the wiring WCL[n] and the circuit ITRZ[n] into a conductive state or a non-conductive state.

[0120] The circuit WCS has a function of supplying data to be stored in each cell of the cell array CA.

[0121] The circuit XCS is electrically connected to the wirings XCL[1] to XCL[m]. The circuit XCS has a function of supplying a current amount corresponding to reference data (to be described later) or input data to each of the cells IMref[1] to IMref[m] included in the cell array CA.

[0122] The circuit WSD is electrically connected to the wirings WSL[1] to WSL[m]. When writing weight data to the cells IM[1,1] to IM[m,n], the circuit WSD has a function of selecting a row of the cell array CA to which the weight data is to be written by supplying a predetermined signal to the wirings WSL[1] to WSL[m]. In other words, the wirings WSL[1] to WSL[m] function as write word lines.

[0123] For example, the circuit WSD is electrically connected to the wiring SWL1 and the wiring SWL2. The circuit WSD has a function of bringing the circuit WCS and the cell array CA into a conductive state or a non-conductive state by supplying a predetermined signal to the wiring SWL1, and a function of bringing the circuits ITRZ[1] to ITRZ[n] and the cell array CA into a conductive state or a non-conductive state by supplying a predetermined signal to the wiring SWL2.

[0124] Each of the circuits ITRZ[1] to ITRZ[n] has, for example, an input terminal and an output terminal. For example, the output terminal of the circuit ITRZ[1] is electrically connected to a wiring OL[1], and the output terminal of the circuit ITRZ[n] is electrically connected to a wiring OL[n].

[0125] Each of the circuits ITRZ[1] to ITRZ[n] has a function of receiving a current input to an input terminal, converting the current into a voltage corresponding to the amount of the current, and outputting the voltage from an output terminal. The voltage may be, for example, an analog voltage or a digital voltage. Each of the circuits ITRZ[1] to ITRZ[n] may include a semiconductor device that performs a function operation. In this case, for example, the semiconductor device may perform a function operation using the converted voltage, and the result of the operation may be output to the wirings OL[1] to OL[n].

[0126] In particular, when performing calculations on a hierarchical neural network, the nonlinear functions that can be used include, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, and a threshold function.

[0127] <Example of circuit WCS and circuit XCS configuration> An example of the configuration of the circuit WCS and the circuit XCS will be described.

[0128] First, the circuit WCS will be described. Fig. 13A is a block diagram showing an example of the circuit WCS. Note that Fig. 13A also shows a circuit SWS1, a transistor F3, a wiring SWL1, and a wiring WCL in order to show the electrical connection of the circuit WCS with peripheral circuits. The transistor F3 is any one of the transistors F3[1] to F3[n] included in the semiconductor device MAC1 of Fig. 12, and the wiring WCL is any one of the wirings WCL[1] to WCL[n] included in the semiconductor device MAC1 of Fig. 12.

[0129] 13A includes, as an example, a switch SWW. A first terminal of the switch SWW is electrically connected to a second terminal of the transistor F3, and a second terminal of the switch SWW is electrically connected to a wiring VINIL1. The wiring VINIL1 functions as a wiring that applies an initialization potential to the wiring WCL, and the initialization potential can be a ground potential (GND), a low-level potential, a high-level potential, or the like. Note that the switch SWW is turned on only when the initialization potential is applied to the wiring WCL, and is turned off otherwise.

[0130] The switch SWW may be, for example, an electrical switch such as an analog switch or a transistor. When a transistor is used as the switch SWW, the transistor may have the same structure as the transistors F1 and F2. In addition to an electrical switch, a mechanical switch may also be used.

[0131] 13A has a plurality of current sources CS. Specifically, the circuit WCS has K bits (2 Kvalue) (K is an integer equal to or greater than 1) as a current amount. In this case, the circuit WCS has a function of outputting 2 K The circuit WCS has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and two current sources CS that output information corresponding to the value of the K-th bit as a current. K-1 There are individual ones.

[0132] In FIG. 13A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS is electrically connected to the second terminal of the transistor F3 of the circuit SWS1. The terminal T2 of one current source CS is electrically connected to the wiring DW[1], and the terminals T2 of the two current sources CS are electrically connected to the wiring DW[2]. K-1 Each of the terminals T2 of the current sources CS is electrically connected to a wiring DW[K].

[0133] The multiple current sources CS in the circuit WCS each have the same constant current I Wut from the terminal T1. In reality, during the manufacturing stage of the semiconductor device MAC1, errors may occur due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the constant current I output from each of the terminals T1 of the multiple current sources CS is Wut The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal T1 of each of the multiple current sources CS included in the circuit WCS is Wut The following explanation will be given assuming that there is no error.

[0134] The wirings DW[1] to DW[K] are electrically connected to a current source CS and a constant current I Wut Specifically, for example, when a high-level potential is applied to the wiring DW[1], the current source CS electrically connected to the wiring DW[1] outputs a constant current IWut flows to the second terminal of the transistor F3, and when a low-level potential is applied to the wiring DW[1], the current source CS electrically connected to the wiring DW[1] flows as follows: Wut For example, when a high-level potential is applied to the wiring DW[2], the two current sources CS electrically connected to the wiring DW[2] output a total of 2I Wut When a constant current of 2I flows to the second terminal of the transistor F3 and a low-level potential is applied to the wiring DW[2], the current source CS electrically connected to the wiring DW[2] flows through the second terminal of the transistor F3. Wut For example, when a high-level potential is applied to the wiring DW[K], the 2 K-1 The current sources CS are K-1 I Wut When a constant current of 100 V flows to the second terminal of the transistor F3 and a low-level potential is applied to the wiring DW[K], the current source CS electrically connected to the wiring DW[K] has a total of 2 K-1 I Wut It does not output a constant current.

[0135] The current flowing from one current source CS electrically connected to the wiring DW[1] corresponds to the value of the first bit, the current flowing from two current sources CS electrically connected to the wiring DW[2] corresponds to the value of the second bit, and the amount of current flowing from K current sources CS electrically connected to the wiring DW[K] corresponds to the value of the Kth bit. Here, consider the circuit WCS when K is 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", a high-level potential is applied to the wiring DW[1] and a low-level potential is applied to the wiring DW[2]. At this time, a constant current I is supplied from the circuit WCS to the second terminal of the transistor F3 of the circuit SWS1. Wut Also, for example, when the value of the first bit is "0" and the value of the second bit is "1", a low level potential is applied to the wire DW[1] and a high level potential is applied to the wire DW[2]. At this time, a constant current of 2I flows from the circuit WCS to the second terminal of the transistor F3 of the circuit SWS1. WutAlso, for example, when the value of the first bit is "1" and the value of the second bit is "1", a high level potential is applied to the wires DW[1] and DW[2]. At this time, a constant current of 3I flows from the circuit WCS to the second terminal of the transistor F3 of the circuit SWS1. Wut Furthermore, for example, when the value of the first bit is "0" and the value of the second bit is "0", a low-level potential is applied to the wires DW[1] and DW[2]. At this time, no constant current flows from the circuit WCS to the second terminal of the transistor F3 of the circuit SWS1.

[0136] 13A illustrates the circuit WCS when K is an integer equal to or greater than 3, but when K is 1, the circuit WCS in FIG. 13A may be configured without a current source CS electrically connected to the wirings DW[2] to DW[K]. When K is 2, the circuit WCS in FIG. 13A may be configured without a current source CS electrically connected to the wirings DW[3] to DW[K].

[0137] Next, a specific example of the configuration of the current source CS will be described.

[0138] The current source CS1 shown in FIG. 14A is a circuit that can be applied to the current source CS included in the circuit WCS in FIG. 13A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.

[0139] A first terminal of the transistor Tr1 is electrically connected to the wiring VDDL, and a second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. A second terminal of the transistor Tr2 is electrically connected to the terminal T1, and a gate of the transistor Tr2 is electrically connected to the terminal T2. The terminal T2 is also electrically connected to the wiring DW.

[0140] The wiring DW is any one of the wirings DW[1] to DW[K] in FIG. 13A.

[0141] The line VDDL functions as a line that applies a constant voltage, which may be, for example, a high-level potential.

[0142] When the constant voltage applied by the wiring VDDL is set to a high-level potential, a high-level potential is input to the first terminal of the transistor Tr1. The potential of the second terminal of the transistor Tr1 is set to a potential lower than the high-level potential. At this time, the first terminal of the transistor Tr1 functions as a drain, and the second terminal of the transistor Tr1 functions as a source. Since the gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected, the gate-source voltage of the transistor Tr1 is 0V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current (drain current) in the subthreshold region current range flows between the first terminal and the second terminal of the transistor Tr1. When the transistor Tr1 is an OS transistor, the amount of this current is, for example, 1.0×10 -8 A or less, and 1.0 × 10 -12 A or less is more preferable, and 1.0 × 10 -15 It is more preferable that the current is less than or equal to I. Also, for example, it is more preferable that the current is in a range that increases exponentially with respect to the gate-source voltage. In other words, the transistor Tr1 functions as a current source for supplying a current in the current range when operating in the subthreshold region. Note that the current is the above-mentioned I Wut , or I, as described below. Xut is equivalent to

[0143] Transistor Tr2 functions as a switching element. When the potential of the first terminal of transistor Tr2 is higher than the potential of the second terminal of transistor Tr2, the first terminal of transistor Tr2 functions as a drain, and the second terminal of transistor Tr2 functions as a source. Because the back gate of transistor Tr2 and the second terminal of transistor Tr2 are electrically connected, the back gate-source voltage is 0 V. Therefore, when the threshold voltage of transistor Tr2 is within an appropriate range, transistor Tr2 is turned on when a high-level potential is input to the gate of transistor Tr2, and turned off when a low-level potential is input to the gate of transistor Tr2. Specifically, when transistor Tr2 is on, a current in the subthreshold region flows from the second terminal of transistor Tr1 to terminal T1. When transistor Tr2 is off, the current does not flow from the second terminal of transistor Tr1 to terminal T1.

[0144] Note that the circuit applicable to the current source CS included in the circuit WCS of FIG. 13A is not limited to the current source CS1 of FIG. 14A. For example, while the current source CS1 is configured such that the back gate of the transistor Tr2 is electrically connected to the second terminal of the transistor Tr2, the back gate of the transistor Tr2 may be electrically connected to a separate wiring. An example of such a configuration is shown in FIG. 14B. The current source CS2 shown in FIG. 14B is configured such that the back gate of the transistor Tr2 is electrically connected to a wiring VTHL. By electrically connecting the wiring VTHL to an external circuit or the like, the current source CS2 can apply a predetermined potential to the wiring VTHL via the external circuit or the like, thereby applying the predetermined potential to the back gate of the transistor Tr2. This allows the threshold voltage of the transistor Tr2 to be varied. In particular, increasing the threshold voltage of the transistor Tr2 can reduce the off-state current of the transistor Tr2.

[0145] For example, the current source CS1 has a configuration in which the back gate of the transistor Tr1 is electrically connected to the second terminal of the transistor Tr1, but a configuration in which a capacitor is used to maintain a voltage between the back gate of the transistor Tr2 and the second terminal of the transistor Tr2 is also possible. Such a configuration example is shown in FIG. 14C. The current source CS3 shown in FIG. 14C includes a transistor Tr3 and a capacitor C6 in addition to the transistors Tr1 and Tr2. The current source CS3 differs from the current source CS1 in that the second terminal of the transistor Tr1 is electrically connected to the back gate of the transistor Tr1 via the capacitor C6 and the back gate of the transistor Tr1 is electrically connected to the first terminal of the transistor Tr3. The current source CS3 also has a configuration in which the second terminal of the transistor Tr3 is electrically connected to the wiring VTL and the gate of the transistor Tr3 is electrically connected to the wiring VWL. The current source CS3 can apply a high-level potential to the wiring VWL to turn on the transistor Tr3, thereby establishing electrical continuity between the wiring VTL and the back gate of the transistor Tr1. At this time, a predetermined potential can be input to the back gate of transistor Tr1 from line VTL. Then, by applying a low-level potential to line VWL to turn off transistor Tr3, the capacitor C6 can maintain the voltage between the second terminal of transistor Tr1 and the back gate of transistor Tr1. In other words, by determining the voltage applied to the back gate of transistor Tr1 from line VTL, the threshold voltage of transistor Tr1 can be varied, and the threshold voltage of transistor Tr1 can be fixed by transistor Tr3 and capacitor C6.

[0146] Furthermore, for example, a circuit applicable to the current source CS included in the circuit WCS of Fig. 13A may be the current source CS4 shown in Fig. 14D. The current source CS4 is configured such that the back gate of the transistor Tr2 in the current source CS3 of Fig. 14C is electrically connected to the line VTHL instead of the second terminal of the transistor Tr2. In other words, the current source CS4, like the current source CS2 of Fig. 14B, can vary the threshold voltage of the transistor Tr2 depending on the potential provided by the line VTHL.

[0147] In the current source CS4, when a large current flows between the first and second terminals of the transistor Tr1, it is necessary to increase the on-current of the transistor Tr2 in order to pass that current from the terminal T1 to the outside of the current source CS4. In this case, the current source CS4 applies a high-level potential to the line VTHL to lower the threshold voltage of the transistor Tr2 and increase the on-current of the transistor Tr2, thereby allowing the large current flowing between the first and second terminals of the transistor Tr1 to flow from the terminal T1 to the outside of the current source CS4.

[0148] 14A to 14D as the current source CS included in the circuit WCS of Fig. 13A, the circuit WCS can output a current corresponding to K-bit weight data. The amount of the current can be, for example, the amount of current flowing between the first terminal and the second terminal within the range in which the transistor F1 operates in the subthreshold region.

[0149] 13A may be replaced by the circuit WCS shown in FIG. 13B. The circuit WCS in FIG. 13B has a configuration in which the current source CS in FIG. 14A is connected to each of the wirings DW[1] to DW[K]. When the channel width of the transistor Tr1[1] is w[1], the channel width of the transistor Tr1[2] is w[2], and the channel width of the transistor Tr1[K] is w[K], the ratio of the channel widths is w[1]:w[2]:w[K]=1:2:2. K-1Since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the circuit WCS shown in Fig. 13B can output a current according to K-bit weight data, just like the circuit WCS in Fig. 13A.

[0150] Note that the transistor Tr1 (including transistors Tr1[1] to Tr2[K]), the transistor Tr2 (including transistors Tr2[1] to Tr2[K]), and the transistor Tr3 can be, for example, a transistor that can be used for the transistor F1 and / or the transistor F2. In particular, it is preferable to use OS transistors as the transistor Tr1 (including transistors Tr1[1] to Tr2[K]), the transistor Tr2 (including transistors Tr2[1] to Tr2[K]), and the transistor Tr3.

[0151] Next, a specific example of the circuit XCS will be described.

[0152] 13C is a block diagram showing an example of the circuit XCS. In addition, in order to show the electrical connection of the circuit WCS with the peripheral circuits, the wiring XCL is also shown in FIG. 13C. The wiring XCL is any one of the wirings XCL[1] to XCL[m] included in the semiconductor device MAC1 of FIG. 12.

[0153] The circuit XCS shown in FIG. 13C includes, as an example, a switch SWX. A first terminal of the switch SWX is electrically connected to the wiring XCL and a plurality of current sources CS, and a second terminal of the switch SWX is electrically connected to the wiring VINIL2. The wiring VINIL2 functions as a wiring that applies an initialization potential to the wiring XCL, and the initialization potential can be a ground potential (GND), a low-level potential, a high-level potential, or the like. The initialization potential applied by the wiring VINIL2 may be equal to the potential applied by the wiring VINIL1. Note that the switch SWX is turned on only when the initialization potential is applied to the wiring XCL, and is turned off otherwise.

[0154] The switch SWX may be, for example, a switch applicable to the switch SWW.

[0155] The circuit configuration of the circuit XCS in FIG. 13C can be configured to be substantially the same as the circuit WCS in FIG. 14A. Specifically, the circuit XCS has a function of outputting reference data as a current amount and a function of outputting L bits (2 L In this case, the circuit XCS has a function of outputting the input data of 2 L The circuit XCS has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and two current sources CS that output information corresponding to the value of the Lth bit as a current. L-1 There are individual ones.

[0156] Incidentally, the reference data output as a current by the circuit XCS can be, for example, information in which the value of the first bit is "1" and the values ​​of the second and subsequent bits are "0".

[0157] In FIG. 13C, the terminal T2 of one current source CS is electrically connected to the wiring DX[1], and each of the terminals T2 of the two current sources CS is electrically connected to the wiring DX[2]. L-1 Each of the terminals T2 of the current sources CS is electrically connected to the wiring DX[L].

[0158] The multiple current sources CS in the circuit XCS are each set to the same constant current I Xut from the terminal T1. The wirings DX[1] to DX[L] are electrically connected to the current source CS and the XutThe circuit XCS functions as a wiring that transmits a control signal for outputting the L-bit information. That is, the circuit XCS has a function of causing a current amount corresponding to L-bit information transmitted from the wirings DX[1] to DX[L] to flow through the wiring XCL. Note that the control signals transmitted to the wirings DX[1] to DX[L] can be transmitted to each row by the shift register, latch circuit, or the like described in the first embodiment.

[0159] Specifically, consider the circuit XCS when L is set to 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", a high level potential is applied to the wire DX[1] and a low level potential is applied to the wire DX[2]. At this time, a constant current I is applied from the circuit XCS to the wire XCL. Xut Also, for example, when the value of the first bit is "0" and the value of the second bit is "1", a low level potential is applied to the wire DX[1] and a high level potential is applied to the wire DX[2]. At this time, a constant current of 2I flows from the circuit XCS to the wire XCL. Xut Also, for example, when the value of the first bit is "1" and the value of the second bit is "1", a high level potential is applied to the wiring DX[1] and the wiring DX[2]. At this time, a constant current of 3I flows from the circuit XCS to the wiring XCL. Xut flows. Also, for example, when the value of the first bit is "0" and the value of the second bit is "0", a low level potential is applied to the wires DX[1] and DX[2]. At this time, no constant current flows from the circuit XCS to the wire XCL. Note that in this specification and other places, this may be rephrased as a current of 0 flowing from the circuit XCS to the wire XCL. Also, when the current of 0, I Xut , 2I Xut , 3I Xut These can be input data output by the circuit XCS, and in particular, the amount of current I Xut can be the reference data output by the circuit XCS.

[0160] In addition, if an error occurs due to variations in the electrical characteristics of the transistors included in each current source CS of the circuit XCS, the constant current I output from each of the terminals T1 of the multiple current sources CS will Xut The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal T1 of each of the multiple current sources CS included in the circuit XCS is Xut The following explanation will be given assuming that there is no error.

[0161] 14A to 14D can be used as the current source CS of the circuit XCS, similar to the current source CS of the circuit WCS. In this case, the wiring DW shown in FIGS. 14A to 14D can be replaced with the wiring DX. This allows the circuit XCS to pass a current in the subthreshold current range through the wiring XCL as reference data or L-bit input data.

[0162] Furthermore, the circuit XCS in Fig. 13C can have the same circuit configuration as the circuit WCS shown in Fig. 13B. In this case, the circuit WCS shown in Fig. 13B can be replaced with the circuit XCS, the wiring DW[1] with the wiring DX[1], the wiring DW[2] with the wiring DX[2], the wiring DW[K] with the wiring DX[L], the switch SWW with the switch SWX, and the wiring VINIL1 with the wiring VINIL2.

[0163] <Example of circuit ITRZ configuration> Here, a configuration example of a circuit that can be applied to the circuits ITRZ[1] to ITRZ[n] included in the semiconductor device MAC1 in FIG. 12 will be described.

[0164] The circuit ITRZ1 shown in Fig. 15A is an example of a circuit that can be applied to the circuits ITRZ[1] to ITRZ[n] in Fig. 12. Note that Fig. 15A also illustrates a circuit SWS2, wiring WCL, wiring SWL2, and a transistor F4 in order to show the electrical connection of the circuit ITRZ1 with peripheral circuits. The wiring WCL is any one of the wirings WCL[1] to WCL[n] included in the semiconductor device MAC1 in Fig. 12, and the transistor F4 is any one of the transistors F4[1] to F4[n] included in the semiconductor device MAC1 in Fig. 12.

[0165] The circuit ITRZ1 in FIG. 15A is electrically connected to the wiring WCL via a transistor F4. The circuit ITRZ1 is also electrically connected to the wiring OL. The circuit ITRZ1 has a function of converting the amount of current flowing from the circuit ITRZ1 to the wiring WCL or the amount of current flowing from the wiring WCL to the circuit ITRZ1 into an analog voltage and outputting the analog voltage to the wiring OL. In other words, the circuit ITRZ1 has a current-voltage conversion circuit.

[0166] The circuit ITRZ1 in FIG. 15A includes, as an example, a resistor R5 and an operational amplifier OP1.

[0167] The inverting input terminal of the operational amplifier OP1 is electrically connected to the first terminal of the resistor R5 and the second terminal of the transistor F4. The non-inverting input terminal of the operational amplifier OP1 is electrically connected to the wiring VRL. The output terminal of the operational amplifier OP1 is electrically connected to the second terminal of the resistor R5 and the wiring OL.

[0168] The wiring VRL functions as a wiring that applies a constant voltage, which may be, for example, a ground potential (GND) or a low-level potential.

[0169] By configuring the circuit ITRZ1 as shown in Figure 15A, the amount of current flowing from the wiring WCL to the circuit ITRZ1 via the transistor F4, or the amount of current flowing from the circuit ITRZ1 to the wiring WCL via the transistor F4, can be converted into an analog voltage and output to the wiring OL.

[0170] In particular, by setting the constant voltage provided by the line VRL to ground potential (GND), the inverting input terminal of the operational amplifier OP1 becomes a virtual ground, and the analog voltage output to the line OL can be a voltage based on ground potential (GND).

[0171] Although the circuit ITRZ1 in FIG. 15A is configured to output an analog voltage, the circuit configuration applicable to the circuits ITRZ[1] to ITRZ[n] in FIG. 12 is not limited to this. For example, the circuit ITRZ1 may be configured to include an analog-to-digital conversion circuit ADC, as shown in FIG. 15B. Specifically, the circuit ITRZ2 in FIG. 15B is configured such that the input terminal of the analog-to-digital conversion circuit ADC is electrically connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, and the output terminal of the analog-to-digital conversion circuit ADC is electrically connected to the wiring OL. With this configuration, the circuit ITRZ2 in FIG. 15B can output a digital signal to the wiring OL. The digital signal output to the wiring OL can be converted into a serial signal by the shift register, latch circuit, switch, etc. described in the first embodiment and output to the outside.

[0172] In addition, in circuit ITRZ2, when the digital signal output to wiring OL is 1 bit (binary), circuit ITRZ2 may be replaced with circuit ITRZ3 shown in FIG. 15C. The circuit ITRZ3 in FIG. 15C has a configuration in which a comparator CMP1 is provided in the circuit ITRZ1 in FIG. 15A. Specifically, in circuit ITRZ3, the first input terminal of comparator CMP1 is electrically connected to the output terminal of operational amplifier OP1 and the second terminal of resistor R5, the second input terminal of comparator CMP1 is electrically connected to wiring VRL2, and the output terminal of comparator CMP1 is electrically connected to wiring OL. Wiring VRL2 functions as a wiring that provides a potential for comparing with the potential of the first terminal of comparator CMP1. With such a configuration, the circuit ITRZ3 in FIG. 15C can output a low-level potential or a high-level potential (binary digital signal) to wiring OL according to the magnitude of the voltage converted from the amount of current flowing between the source and drain of transistor F4 by the current-voltage conversion circuit and the voltage provided by wiring VRL2.

[0173] In addition, the circuits ITRZ[1] to ITRZ[n] applicable to the semiconductor device MAC1 in FIG. 12 are not limited to the circuits ITRZ1 to ITRZ3 shown in FIGS. 15A to 15C, respectively. For example, when using the semiconductor device MAC1 for the operation of a hierarchical neural network, it is preferable that the circuits ITRZ1 to ITRZ3 have a semiconductor device that performs a function operation. In addition, as the semiconductor device that performs a function operation, a semiconductor device such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function can be used.

[0174] Note that one embodiment of the present invention is not limited to the circuit configuration of the semiconductor device MAC1 described in this embodiment. The circuit configuration of the semiconductor device MAC1 can be changed depending on the situation. For example, the semiconductor device MAC1 may be changed to a configuration in which the circuit SWS1 is not provided, as in the semiconductor device MAC1A shown in FIG. 16. In the semiconductor device MAC1, the circuit SWS1 can stop the current flowing from the circuit WCS to the wirings WCL[1] to WCL[n]. In the semiconductor device MAC1A, however, the circuit WCS can stop the current flowing from the circuit WCS to the wirings WCL[1] to WCL[n]. Specifically, for example, when the circuit WCS of FIG. 13A is used as the circuit WCS included in the semiconductor device MAC1A and the current source CS1 of FIG. 14A is used as the current source CS, a low-level potential can be input to each of the wirings DW[1] to DW[K] and the switch SWW can be turned off. By operating the circuit WCS in this way, the current flowing from the circuit WCS to the wirings WCL[1] to WCL[n] can be stopped. In this way, by stopping the current flowing from the circuit WCS to the wirings WCL[1] to WCL[n], it is possible to perform an operation using the semiconductor device MAC1A instead of the semiconductor device MAC1.

[0175] <Example of semiconductor device operation> Next, an example of the operation of the semiconductor device MAC1 will be described.

[0176] 17 shows a timing chart of an operation example of the semiconductor device MAC1. The timing chart of FIG. 17 shows fluctuations in the potentials of the wiring SWL1, wiring SWL2, wiring WSL[i] (i is an integer of 1 to m-1), wiring WSL[i+1], wiring XCL[i], wiring XCL[i+1], node NN[i,j] (j is an integer of 1 to n-1), node NN[i+1,j], node NNref[i], and node NNref[i+1] between time T11 and time T23 and in the vicinity thereof. Furthermore, the timing chart of FIG. 17 also shows fluctuations in the amount of current I flowing between the first terminal and the second terminal of the transistor F2 included in the cell IM[i,j]. F2[i,j] and the current I flowing between the first and second terminals of transistor F2m included in cell IMref[i] F2m [i] and the current I flowing between the first and second terminals of transistor F2 included in cell IM[i+1,j] F2 [i+1,j] and the current I flowing between the first and second terminals of transistor F2m included in cell IMref[i+1] F2m The respective variations of [i+1] and are also shown.

[0177] It is to be noted that the circuit WCS of the semiconductor device MAC1 is the circuit WCS of FIG. 13A, and the circuit XCS of the semiconductor device MAC1 is the circuit XCS of FIG. 13C.

[0178] In this operation example, the potential of the wiring VE is set to the ground potential GND. Also, before time T11, the potentials of the nodes NN[i,j], NN[i+1,j], NNref[i], and NNref[i+1] are set to the ground potential GND as an initial setting. Specifically, for example, by setting the initialization potential of the wiring VINIL1 in FIG. 13A to the ground potential GND and turning on the switch SWW, the transistor F3, and the transistors F1 included in the cells IM[i,j] and IM[i+1,j], the potentials of the nodes NN[i,j] and NN[i+1,j] can be set to the ground potential GND. Furthermore, for example, by setting the initialization potential of the wiring VINIL2 in Figure 13C to the ground potential GND and turning on the switch SWX and the transistors F1m included in the cells IMref[i,j] and IMref[i+1,j], the potentials of the nodes NNref[i,j] and NNref[i+1,j] can be set to the ground potential GND.

[0179] Between time T11 and time T12, a high-level potential (denoted as High in FIG. 17) is applied to wiring SWL1, and a low-level potential (denoted as Low in FIG. 17) is applied to wiring SWL2. As a result, a high-level potential is applied to the gates of each of transistors F3[1] to F3[n], causing each of transistors F3[1] to F3[n] to be in an on state, and a low-level potential is applied to the gates of each of transistors F4[1] to F4[n], causing each of transistors F4[1] to F4[n] to be in an off state.

[0180] Also, between time T11 and time T12, a low-level potential is applied to wiring WSL[i] and wiring WSL[i + 1]. As a result, a low-level potential is applied to the gates of transistors F1 included in cells IM[i,1] to IM[i,n] in the i-th row of cell array CA and to the gate of transistor F1m included in cell IMref[i], causing each of transistors F1 and transistor F1m to be in an off state. Also, a low-level potential is applied to the gates of transistors F1 included in cells IM[i + 1,1] to IM[i + 1,n] in the (i + 1)-th row of cell array CA and to the gate of transistor F1m included in cell IMref[i + 1], causing each of transistors F1 and transistor F1m to be in an off state.

[0181] Also, between time T11 and time T12, a ground potential GND is applied to wiring XCL[i] and wiring XCL[i + 1]. Specifically, for example, when the wiring XCL described in FIG. 13C is each of wiring XCL[i] and wiring XCL[i + 1], by setting the potential for initializing wiring VINIL2 to the ground potential GND and turning on switch SWX, the potentials of wiring XCL[i] and wiring XCL[i + 1] can be set to the ground potential GND.

[0182] 13A corresponds to the wirings WCL[1] to WCL[K], and no weight data is input to the wirings DW[1] to DW[K]. Also, between time T11 and time T12, when the wiring WCL in FIG. 13A corresponds to the wirings WCL[1] to WCL[K], and no input data is input to the wirings DX[1] to DX[L], and when the wiring XCL in FIG. 13C corresponds to the wirings XCL[1] to XCL[K], and no input data is input to the wirings DX[1] to DX[L], respectively. Here, in the circuit WCS in FIG. 13A, a low-level potential is input to each of the wirings DW[1] to DW[K], and in the circuit XCS in FIG. 13C, a low-level potential is input to each of the wirings DX[1] to DX[L].

[0183] Furthermore, between time T11 and time T12, no current flows through the wiring WCL[j], the wiring XCL[i], and the wiring XCL[i+1]. F2 [i,j], I F2m [i]I F2 [i+1,j], I F2m [i+1] becomes 0.

[0184] Between time T12 and time T13, a high-level potential is applied to the wiring WSL[i]. As a result, a high-level potential is applied to the gate of the transistor F1 included in the cells IM[i,1] to IM[i,n] in the i-th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i], turning on the transistor F1 and the transistor F1m. Also, between time T12 and time T13, a low-level potential is applied to the wirings WSL[1] to WSL[m] other than the wiring WSL[i], turning off the transistor F1 included in the cells IM[1,1] to IM[m,n] other than the i-th row of the cell array CA and the transistor F1m included in the cells IMref[1] to IMref[m] other than the i-th row.

[0185] Furthermore, the ground potential GND has been applied to the wirings XCL[1] to XCL[m] continuously since before time T12.

[0186] Between time T13 and time T14, a current of a current amount I0[i,j] flows from the circuit WCS to the cell array CA via the transistor F3[j] as weight data. Specifically, when the wiring WCL shown in FIG. 13A is the wiring WCL[j], signals according to the weight data are input to each of the wirings DW[1] to DW[K], and a current I0[i,j] flows from the circuit WCS to the second terminal of the transistor F3[j]. In other words, the value of the K-bit signal input as weight data is set to α[i,j] (α[i,j] is set to a value between 0 and 2). K -1 or less), then I0[i,j]=α[i,j]×I Wut This becomes:

[0187] Note that when α[i,j] is 0, I0[i,j]=0, so strictly speaking, no current flows from circuit WCS to cell array CA via transistor F3[j]. However, in this specification, it may be stated that "a current of I0[i,j]=0 flows."

[0188] Between time T13 and time T14, there is a conductive state between the first terminal of transistor F1 included in cell IM[i,j] in the i-th row of cell array CA and wiring WCL[j], and there is a non-conductive state between the first terminal of transistor F1 included in cells IM[1,j] to IM[m,j] other than the i-th row of cell array CA and wiring WCL[j], so that a current of an amount I0[i,j] flows from wiring WCL[j] to cell IM[i,j].

[0189] Incidentally, when the transistor F1 included in the cell IM[i,j] is turned on, the transistor F2 included in the cell IM[i,j] is configured as a diode connection. Therefore, when a current flows from the wiring WCL[j] to the cell IM[i,j], the potentials of the gate of the transistor F2 and the second terminal of the transistor F2 become approximately equal. This potential is determined by the amount of current flowing from the wiring WCL[j] to the cell IM[i,j] and the potential of the first terminal of the transistor F2 (GND in this case). In this operation example, when a current of the amount I0[i,j] flows from the wiring WCL[j] to the cell IM[i,j], the potential of the gate of the transistor F2 (node ​​NN[i,j]) becomes V g [i,j]. That is, in transistor F2, the gate-source voltage is V g [i,j]-GND, and the amount of current I0[i,j] is set as the current flowing between the first terminal and the second terminal of the transistor F2.

[0190] Here, the threshold voltage of transistor F2 is V th When [i,j] is used, the amount of current I0[i,j] when transistor F2 operates in the subthreshold region can be written as follows:

[0191]

number

[0192] In addition, I a is V g [i,j] is V th [i,j] is the drain current when J is a correction coefficient determined by temperature, device structure, etc.

[0193] In addition, between time T13 and time T14, the circuit XCS supplies the wire XCL[i] with the current amount I ref0Specifically, when the wiring XCL shown in FIG. 13C is the wiring XCL[i], a high-level potential is input to the wiring DX[1] and a low-level potential is input to each of the wirings DX[2] to DX[K], and a current I flows from the circuit XCS to the wiring XCL[i]. ref0 In other words, I ref0 =I Xut This becomes:

[0194] Between time T13 and time T14, the first terminal of the transistor F1m included in the cell IMref[i] is in a conductive state with the wiring XCL[i], so that a current I ref0 A current of flows.

[0195] As with cell IM[i,j], when transistor F1m included in cell IMref[i] is turned on, transistor F2m included in cell IMref[i] is configured as a diode connection. Therefore, when current flows from wiring XCL[i] to cell IMref[i], the potentials of the gate of transistor F2m and the second terminal of transistor F2m become approximately equal. This potential is determined by the amount of current flowing from wiring XCL[i] to cell IMref[i] and the potential of the first terminal of transistor F2m (here, GND), etc. In this operation example, the amount of current I flows from wiring XCL[i] to cell IMref[i]. ref0 As a result of this current flowing, the gate of transistor F2 (node ​​NNref[i]) is V gm [i], and the potential of the wiring XCL[i] at this time is also V gm [i]. That is, in transistor F2m, the gate-source voltage is V gm [i]-GND, and the current flowing between the first and second terminals of transistor F2m is I ref0 is set.

[0196] Here, the threshold voltage of transistor F2m is V thm When [i] is set, the amount of current I when transistor F2m operates in the subthreshold region isref0 can be written as in the following equation (1.2). Note that the correction coefficient J is assumed to be the same as that of transistor F2 included in cell IM[i,j]. For example, the device structure and size (channel length, channel width) of the transistors are assumed to be the same. Furthermore, although the correction coefficient J for each transistor varies due to manufacturing variations, it is assumed that the variations are suppressed to a level that allows the discussion below to be carried out with sufficient accuracy for practical use.

[0197]

number

[0198] Here, the weight coefficient w[i,j], which is weight data, is defined as in the following equation (1.3).

[0199]

number

[0200] Therefore, equation (1.1) can be rewritten as the following equation (1.4).

[0201]

number

[0202] The current I output from the current source CS of the circuit WCS in Figure 13A Wut and the current I output by the current source CS of the circuit XCS in Figure 13C. Xut If and are equal, then w[i,j]=α[i,j]. That is, I Wut And, I Xut When and are equal, α[i,j] corresponds to the value of the weight data, so I Wut And, I Xut Preferably, and are equal to each other.

[0203] Between time T14 and time T15, a low-level potential is applied to the wiring WSL[i], which applies a low-level potential to the gates of the transistors F1 included in the cells IM[i,1] to IM[i,n] in the i-th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i], turning off the transistors F1 and F1m.

[0204] When the transistor F1 included in the cell IM[i,j] is turned off, the capacitance C5 is charged with V, which is the difference between the potential of the gate of the transistor F2 (node ​​NN[i,j]) and the potential of the wiring XCL[i]. g [i,j]-V gm [i] is held. Also, by turning off the transistor F1 included in the cell IMref[i], the capacitance C5m holds 0, which is the difference between the potential of the gate (node ​​NNref[i]) of the transistor F2m and the potential of the wiring XCL[i]. Note that the voltage held by the capacitance C5m is a voltage (here, for example, V ds In this case, the potential of the node NNref[i] is V ds This can be thought of as the sum of the potentials.

[0205] 13C is the line XCL[i], the potential of the line XCL[i] can be set to the ground potential GND by setting the initialization potential of the line VINIL2 to the ground potential GND and turning on the switch SWX.

[0206] Therefore, the potentials of nodes NN[i,1] to NN[i,n] change due to capacitive coupling by capacitance C5 contained in each of cells IM[i,1] to IM[i,n] in the i-th row, and the potential of node NNref[i] changes due to capacitive coupling by capacitance C5m contained in cell IMref[i].

[0207] The amount of change in the potential of the nodes NN[i,1] to NN[i,n] is the potential obtained by multiplying the amount of change in the potential of the wiring XCL[i] by a capacitive coupling coefficient determined by the configuration of each of the cells IM[i,1] to IM[i,n] included in the cell array CA. The capacitive coupling coefficient is calculated based on the capacitance of the capacitor C5, the gate capacitance of the transistor F2, the parasitic capacitance, etc. In each of the cells IM[i,1] to IM[i,n], when the capacitive coupling coefficient due to the capacitor C5 is p, the potential of the node NN[i,j] of the cell IM[i,j] is calculated by multiplying the potential at the time between time T14 and time T15 by p(V gm [i]-GND) decreases.

[0208] Similarly, when the potential of the wiring XCL[i] changes, the potential of the node NNref[i] also changes due to the capacitive coupling by the capacitance C5m included in the cell IMref[i]. If the capacitive coupling coefficient of the capacitance C5m is p, the same as the capacitance C5, the potential of the node NNref[i] of the cell IMref[i] changes from the potential between time T14 and time T15 to p(V gm 17, p=1 is set as an example. Therefore, the potential of the node NNref[i] becomes GND between time T15 and time T16.

[0209] As a result, the potential of the node NN[i,j] of the cell IM[i,j] drops, so that the transistor F2 is turned off. Similarly, the potential of the node NNref[i] of the cell IMref[i] drops, so that the transistor F2m is also turned off. Therefore, between time T15 and time T16, F2 [i,j], I F2mEach of [i] is 0.

[0210] Between time T16 and time T17, a high-level potential is applied to the wiring WSL[i+1]. As a result, a high-level potential is applied to the gate of the transistor F1 included in the cells IM[i+1,1] to IM[i+1,n] in the i+1th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i+1], turning on the transistor F1 and the transistor F1m. Also, between time T16 and time T17, a low-level potential is applied to the wirings WSL[1] to WSL[m] except for the wiring WSL[i+1]. Therefore, the transistor F1 included in the cells IM[1,1] to IM[m,n] other than the i+1th row of the cell array CA and the transistor F1m included in the cells IMref[1] to IMref[m] other than the i+1th row of the cell array CA are turned off.

[0211] Furthermore, the ground potential GND has been applied to the wirings XCL[1] to XCL[m] continuously since before time T16.

[0212] Between time T17 and time T18, a current of a current amount I0[i+1,j] flows from the circuit WCS to the cell array CA via the transistor F3[j] as weight data. Specifically, when the wiring WCL shown in FIG. 13A is the wiring WCL[j+1], signals according to the weight data are input to each of the wirings DW[1] to DW[K], and a current I0[i+1,j] flows from the circuit WCS to the second terminal of the transistor F3[j]. In other words, the value of the K-bit signal input as weight data is set to α[i+1,j] (α[i+1,j] is between 0 and 2). K -1 or less.) I0[i+1,j]=α[i+1,j]×I Wut This becomes:

[0213] Note that when α[i+1,j] is 0, I0[i+1,j]=0, so strictly speaking, no current flows from circuit WCS to cell array CA via transistor F3[j]. However, in this specification, as in the case of I0[i,j]=0, it may be stated that "a current of I0[i+1,j]=0 flows."

[0214] At this time, there is a conductive state between the first terminal of transistor F1 included in cell IM[i+1,j] in the i+1th row of cell array CA and wiring WCL[j], and there is a non-conductive state between the first terminal of transistor F1 included in cells IM[1,j] to IM[m,j] other than the i+1th row of cell array CA and wiring WCL[j], so a current of an amount I0[i+1,j] flows from wiring WCL[j] to cell IM[i+1,j].

[0215] Incidentally, when transistor F1 included in cell IM[i+1,j] is turned on, transistor F2 included in cell IM[i+1,j] is configured as a diode. Therefore, when current flows from wiring WCL[j] to cell IM[i+1,j], the potentials of the gate of transistor F2 and the second terminal of transistor F2 become approximately equal. This potential is determined by the amount of current flowing from wiring WCL[j] to cell IM[i+1,j] and the potential of the first terminal of transistor F2 (here, GND). In this operation example, when a current of a current amount I0[i+1,j] flows from wiring WCL[j] to cell IM[i+1,j], the potential of the gate of transistor F2 (node ​​NN[i+1,j]) becomes V g [i+1,j]. That is, in transistor F2, the gate-source voltage is V g [i+1,j]-GND, and the amount of current I0[i+1,j] is set as the current flowing between the first terminal and the second terminal of the transistor F2.

[0216] Here, the threshold voltage of transistor F2 is V thWhen [i+1,j] is used, the amount of current I0[i+1,j] when transistor F2 operates in the subthreshold region can be expressed as follows: (1.5) Note that the correction coefficient is J, which is the same as that of transistor F2 included in cell IM[i,j] and transistor F2m included in cell IMref[i].

[0217]

number

[0218] In addition, between time T17 and time T18, the circuit XCS supplies the wire XCL[i+1] with the current amount I ref0 Specifically, as in the period from time T13 to time T14, when the wiring XCL shown in FIG. 13C is the wiring XCL[i+1], a high-level potential is input to the wiring DX[1] and a low-level potential is input to each of the wirings DX[2] to DX[K], and a current I flows from the circuit XCS to the wiring XCL[i+1]. ref0 =I Xut is playing.

[0219] Between time T17 and time T18, a state of conduction is established between the first terminal of the transistor F1m included in the cell IMref[i+1] and the wiring XCL[i+1], so that a current I ref0 A current of flows.

[0220] As with cell IM[i+1,j], when transistor F1m included in cell IMref[i+1] is turned on, transistor F2m included in cell IMref[i+1,j] is configured as a diode connection. Therefore, when current flows from wiring XCL[i+1] to cell IMref[i+1], the potentials of the gate of transistor F2m and the second terminal of transistor F2m become approximately equal. This potential is determined by the amount of current flowing from wiring XCL[i+1] to cell IMref[i+1] and the potential of the first terminal of transistor F2m (here, GND). In this operation example, a current amount I flows from wiring XCL[i+1] to cell IMref[i+1]. ref0 The current flowing through the transistor F2 gate (node ​​NNref[i+1]) is V gm [i+1], and the potential of the wiring XCL[i+1] at this time is also V gm [i+1]. That is, in transistor F2m, the gate-source voltage is V gm [i+1]-GND, and the current flowing between the first and second terminals of transistor F2m is I ref0 is set.

[0221] Here, the threshold voltage of transistor F2m is V thm When [i+1,j], the amount of current I when transistor F2m operates in the subthreshold region is ref0 can be written as the following equation (1.6): Note that the correction coefficient J is the same as that of the transistor F2 included in the cell IM[i+1,j].

[0222]

number

[0223] Here, the weight coefficient w[i+1,j], which is weight data, is defined as follows:

[0224]

number

[0225] Therefore, equation (1.5) can be rewritten as equation (1.6) below.

[0226]

number

[0227] The current I output from the current source CS of the circuit WCS in Figure 13A Wut and the current I output by the current source CS of the circuit XCS in Figure 13C. Xut If and are equal, then w[i+1,j]=α[i+1,j]. That is, I Wut And, I Xut When and are equal, α[i+1,j] corresponds to the value of the weight data, so I Wut And, I Xut Preferably, and are equal to each other.

[0228] Between time T18 and time T19, a low-level potential is applied to the wiring WSL[i+1], which applies a low-level potential to the gates of the transistors F1 included in the cells IM[i+1,1] to IM[i+1,n] in the i+1th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i+1], turning off the transistors F1 and F1m.

[0229] When the transistor F1 included in the cell IM[i+1,j] is turned off, the capacitance C5 is charged with V, which is the difference between the potential of the gate of the transistor F2 (node ​​NN[i+1,j]) and the potential of the wiring XCL[i+1]. g [i+1,j]-V gm[i+1] is held. Also, by turning off the transistor F1 included in the cell IMref[i+1], the capacitor C5m holds 0, which is the difference between the potential of the gate (node ​​NNref[i+1]) of the transistor F2m and the potential of the wiring XCL[i+1]. Note that the voltage held by the capacitor C5m is a voltage (here, for example, V ds In this case, the potential of the node NNref[i+1] is V ds This can be thought of as the sum of the potentials.

[0230] 13C is the wiring XCL[i+1], the potential for initialization of the wiring VINIL2 can be set to the ground potential GND by turning on the switch SWX.

[0231] Therefore, the potentials of nodes NN[i,1] to NN[i+1,n] change due to capacitive coupling by capacitance C5 contained in each of cells IM[i+1,1] to IM[i+1,n] in the i+1th row, and the potential of node NNref[i+1] changes due to capacitive coupling by capacitance C5m contained in cell IMref[i+1].

[0232] The change in the potential of the nodes NN[i+1,1] to NN[i+1,n] is calculated by multiplying the change in the potential of the wiring XCL[i+1] by a capacitive coupling coefficient determined by the configuration of each of the cells IM[i+1,1] to IM[i+1,n] included in the cell array CA. The capacitive coupling coefficient is calculated based on the capacitance of the capacitor C5, the gate capacitance of the transistor F2, the parasitic capacitance, etc. In each of the cells IM[i+1,1] to IM[i+1,n], when the capacitive coupling coefficient of the capacitor C5 is set to p, which is the same as the capacitive coupling coefficient of the capacitor C5 in each of the cells IM[i,1] to IM[i,n], the potential of the node NN[i+1,j] of the cell IM[i+1,j] is calculated by multiplying the change in the potential of the wiring XCL[i+1] by p(V gm [i+1]-GND) decreases.

[0233] Similarly, when the potential of the wiring XCL[i+1] changes, the potential of the node NNref[i+1] also changes due to the capacitive coupling by the capacitance C5m included in the cell IMref[i+1]. If the capacitive coupling coefficient of the capacitance C5m is p, like the capacitance C5, the potential of the node NNref[i+1] of the cell IMref[i+1] changes from the potential between time T18 and time T19 to p(V gm 17, p=1 is used as an example. Therefore, the potential of the node NNref[i+1] becomes GND between time T20 and time T21.

[0234] As a result, the potential of the node NN[i+1,j] of the cell IM[i+1,j] drops, so that the transistor F2 is turned off. Similarly, the potential of the node NNref[i+1] of the cell IMref[i+1] drops, so that the transistor F2m is also turned off. Therefore, between time T19 and time T20, F2 [i+1,j], I F2m Each of [i+1] is 0.

[0235] Between time T20 and time T21, a low-level potential is applied to the wiring SWL1, so that a low-level potential is applied to the gates of the transistors F3[1] to F3[n], turning off the transistors F3[1] to F3[n].

[0236] Between time T21 and time T22, a high-level potential is applied to the wiring SWL2, so that a high-level potential is applied to the gates of the transistors F4[1] to F4[n], turning on the transistors F4[1] to F4[n].

[0237] Between time T22 and time T23, the circuit XCS outputs the current amount I ref0 x[i] times x[i]I ref0 Specifically, for example, when the wiring XCL shown in FIG. 13C is the wiring XCL[i], a high-level potential or a low-level potential is input to each of the wirings DX[1] to DX[K] according to the value of x[i], and a current of x[i]I flows from the circuit XCS to the wiring XCL[i]. ref0 =x[i]I Xut In this example, x[i] corresponds to the value of the input data. At this time, the potential of the wiring XCL[i] varies from 0 to V gm [i]+ΔV[i].

[0238] When the potential of the wiring XCL[i] changes, the potentials of the nodes NN[i,1] to NN[i,n] also change due to the capacitive coupling of the capacitor C5 included in each of the cells IM[i,1] to IM[i,n] in the i-th row of the cell array CA. Therefore, the potential of the node NN[i,j] of the cell IM[i,j] is V g [i,j]+pΔV[i].

[0239] Similarly, when the potential of the wiring XCL[i] changes, the potential of the node NNref[i] also changes due to the capacitive coupling of the capacitance C5m included in the cell IMref[i]. Therefore, the potential of the node NNref[i] of the cell IMref[i] is V gm [i]+pΔV[i].

[0240] As a result, between time T22 and time T23, the amount of current I1[i,j] flowing between the first terminal and the second terminal of the transistor F2 and the amount of current I ref1 [i,j] can be written as follows:

[0241]

number

[0242]

number

[0243] From equations (1.9) and (1.10), x[i] can be expressed by the following equation (1.11).

[0244]

number

[0245] Therefore, equation (1.9) can be rewritten as the following equation (1.12).

[0246]

number

[0247] In other words, the amount of current flowing between the first and second terminals of transistor F2 included in cell IM[i,j] is proportional to the product of the weight coefficient w[i,j], which is weight data, and the input data x[i].

[0248] In addition, between time T22 and time T23, the circuit XCS outputs the current amount I ref0 x[i+1] is x[i+1] times I ref0 Specifically, for example, when the wiring XCL shown in FIG. 13C is the wiring XCL[i+1], a high-level potential or a low-level potential is input to each of the wirings DX[1] to DX[K] depending on the value of x[i+1], and a current of x[i+1]I flows from the circuit XCS to the wiring XCL[i+1]. ref0 =x[i+1]I Xut In this example, x[i+1] corresponds to the value of the input data. At this time, the potential of the wiring XCL[i+1] changes from 0 to V gm [i+1]+ΔV[i+1].

[0249] As the potential of the wiring XCL[i+1] changes, the potentials of the nodes NN[i+1,1] to NN[i+1,n] also change due to capacitive coupling by the capacitor C5 included in each of the cells IM[i+1,1] to IM[i+1,n] in the i+1th row of the cell array CA. Therefore, the potential of the node NN[i+1,j] of the cell IM[i+1,j] is V g [i+1,j]+pΔV[i+1].

[0250] Similarly, when the potential of the wiring XCL[i+1] changes, the potential of the node NNref[i+1] also changes due to the capacitive coupling of the capacitance C5m included in the cell IMref[i+1]. Therefore, the potential of the node NNref[i+1] of the cell IMref[i+1] is V gm [i+1]+pΔV[i+1].

[0251] As a result, between time T22 and time T23, the amount of current I1[i+1,j] flowing between the first terminal and the second terminal of the transistor F2 and the amount of current I ref1 [i+1,j] can be written as follows:

[0252]

number

[0253]

number

[0254] From equations (1.13) and (1.14), x[i+1] can be expressed by the following equation (1.15).

[0255]

number

[0256] Therefore, equation (1.13) can be rewritten as the following equation (1.16).

[0257]

number

[0258] In other words, the amount of current flowing between the first and second terminals of transistor F2 included in cell IM[i+1,j] is proportional to the product of the weight data w[i+1,j] and the input data x[i+1].

[0259] Here, consider the total amount of current flowing from the circuit ITRZ[j] to the cells IM[i,j] and IM[i+1,j] via the transistor F4[j] and the wiring WCL[j]. Let I S If [j], then I S [j] can be expressed by the following equation (1.17) using equations (1.12) and (1.16).

[0260]

number

[0261] Therefore, the amount of current output from circuit ITRZ[j] is proportional to the sum of the weighting coefficients w[i,j] and w[i+1,j], which are the weighting data, and the input data x[i] and x[i+1].

[0262] In the above example of operation, the sum of the currents flowing through the cells IM[i,j] and IM[i+1,j] is considered, but the sum of the currents flowing through the cells IM[1,j] to IM[m,j] may also be considered. In this case, equation (1.17) can be rewritten as the following equation (1.18):

[0263]

number

[0264] Therefore, even in the case of the semiconductor device MAC1 having three or more rows and two or more columns of cell arrays CA, it is possible to perform the product-sum operation as described above. In this case, the semiconductor device MAC1 selects one of the multiple columns as the current amount I ref0 , and xI ref0 By using a cell that holds a multiply-accumulate signal, it is possible to simultaneously execute the multiply-accumulate operation for the remaining number of columns among the multiple columns. In other words, by increasing the number of columns in the cell array, it is possible to provide a semiconductor device that realizes high-speed multiply-accumulate operation.

[0265] The above-described example of operation of the semiconductor device MAC1 is suitable for calculating the sum of products of positive weight data and positive input data.

[0266] Although the transistors included in the semiconductor device MAC1 are OS transistors or Si transistors in this embodiment, one embodiment of the present invention is not limited thereto. The transistors included in the semiconductor device MAC1 may be, for example, transistors including Ge or the like in a channel formation region, transistors including a compound semiconductor such as gallium nitride in a channel formation region, transistors including carbon nanotubes in a channel formation region, or transistors including an organic semiconductor in a channel formation region.

[0267] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0268] (Fourth embodiment) In this embodiment, a display device including the semiconductor device described above will be described. By including a semiconductor device capable of performing arithmetic processing of an artificial neural network, the display device can be a display device capable of performing arithmetic processing with excellent arithmetic efficiency. In addition, in this embodiment, a top view schematic diagram of a light-emitting element and its cross-sectional schematic diagram, a configuration example of the light-emitting element, a configuration example of the light-emitting element and the light-receiving element, and a configuration example of a cross-sectional view of the display device will be described.

[0269] <Example of display device configuration> Fig. 18A is a perspective view of display device 10. In display device 10 shown in Fig. 18A, the configuration of layers 20, 50, and 60 provided between substrates 11 and 12 is shown. Fig. 18A also shows display section 13, light receiving section 14, and input / output terminals 15 in layer 60.

[0270] A layer 20 is provided on the substrate 11. For example, the layer 20 includes a driver circuit 30 and an arithmetic circuit 40. The layer 20 includes a transistor 21 (also referred to as a Si transistor) having silicon in a channel formation region 22. For example, the substrate 11 is a silicon substrate. A silicon substrate is preferable because it has higher thermal conductivity than a glass substrate.

[0271] The transistor 21 can be, for example, a transistor having single crystal silicon in a channel formation region. In particular, when a transistor having single crystal silicon in a channel formation region is used as a transistor provided in the layer 20, the on-state current of the transistor can be increased. Therefore, it is preferable because the circuit included in the layer 20 can be driven at high speed. Furthermore, a transistor having single crystal silicon in a channel formation region can be formed by microfabrication to have a channel length of 3 nm to 10 nm. Therefore, it is possible to provide a dedicated arithmetic circuit 40 such as an artificial neural network (hereinafter sometimes referred to as a neural network) and / or a driver circuit 30, as well as an accelerator such as a CPU or a GPU, an application processor, or the like. The arithmetic circuit 40 can be any of the semiconductor devices described in any of the above Embodiments 1 to 3.

[0272] The driving circuit 30 includes, for example, a gate driver circuit, a source driver circuit, etc. The gate driver circuit, the source driver circuit, etc. can be arranged to overlap the display unit 13 and / or the light receiving unit 14. Therefore, compared to when the driving circuit 30 and the display unit 13 are arranged side by side, the width of the non-display area (also called a frame) existing on the periphery of the display unit 13 of the display device 10 can be made extremely narrow, thereby realizing a compact display device 10. Furthermore, when the driving circuit 30 is arranged on the periphery of the display unit 13 of the display device 10, the gate driver circuit and the source driver circuit are arranged together on the periphery, but the driving circuit 30 can be divided into multiple parts and arranged in the area overlapping with the display unit 13.

[0273] The arithmetic circuit 40 includes the semiconductor device described in any of the first to third embodiments. Therefore, it is possible to perform product-sum calculations in an artificial neural network, such as inference processing based on a hierarchical neural network, such as a deep neural network (DNN) or a convolutional neural network (CNN). Since the arithmetic circuit 40 can perform product-sum calculations using minute currents corresponding to analog voltage values, it can perform calculations using minute currents flowing through the light-receiving element 62 as input data. This is effective for reducing the circuit area, reducing power consumption, and improving calculation efficiency. The light-receiving element 62 is an element that converts optical signals into electrical signals, and is also called a photoelectric conversion element.

[0274] A layer 50 is provided on the layer 20. The layer 50 includes a pixel circuit portion 51P including a plurality of pixel circuits 51 and a cell array CA including a plurality of cells IM. The layer 50 includes a transistor 52 (also referred to as an OS transistor) having a metal oxide (also referred to as an oxide semiconductor) in a channel formation region 54. The layer 50 can be stacked on the layer 20. Alternatively, the layer 50 can be formed on a separate substrate and then bonded to the separate substrate.

[0275] The OS transistor 52 preferably has a channel formation region formed of an oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc. Such an OS transistor has a very low off-state current. Therefore, it is preferable to use an OS transistor, particularly as a transistor provided in the pixel circuit 51 and the cell IM, because analog data written to the pixel circuit 51 and the cell IM can be retained for a long period of time.

[0276] A layer 60 is provided on the layer 50. A substrate 12 is provided on the layer 60. The substrate 12 is preferably a light-transmitting substrate or a layer made of a light-transmitting material. The layer 60 includes a display section 13 having a plurality of light-emitting elements 61 and a light-receiving section 14 having a plurality of light-receiving elements 62. The layer 60 can be configured to be stacked on the layer 50. The light-emitting element 61 can be, for example, an organic electroluminescence element (also referred to as an organic EL element). However, the light-emitting element 61 is not limited thereto, and an inorganic EL element made of an inorganic material can also be used. Note that "organic EL element" and "inorganic EL element" are sometimes collectively referred to as "EL element." The light-emitting element 61 may include an inorganic compound such as quantum dots. For example, quantum dots can be used in the light-emitting layer to function as a light-emitting material. Furthermore, by using, for example, an organic photodiode as the light-receiving element 62, some of the manufacturing processes for the organic electroluminescence element can be performed.

[0277] 18A , the display device 10 of one embodiment of the present invention can have a stacked structure including a light-emitting element 61, a pixel circuit 51, and a driver circuit 30. This allows the pixel circuits 51 to be arranged at extremely high density, thereby achieving extremely high pixel resolution. Because of its extremely high resolution, the display device 10 can be suitably used in VR devices such as head-mounted displays or glasses-type AR devices. For example, even in a configuration in which the display portion of the display device 10 is viewed through an optical component such as a lens, the display device 10 has an extremely high-resolution display portion, so that the pixels are not visible even when the display portion is enlarged with the lens, thereby providing a highly immersive display.

[0278] 18A , the display device 10 of one embodiment of the present invention can have a stacked configuration of the light-receiving element 62, the cell array CA, and the arithmetic circuit 40. This allows for efficient arithmetic processing using a minute current output from the light-receiving element 62 as input data. Furthermore, the display device 10 can have a configuration in which the light-receiving unit 14 is located close to the display unit 13. This allows images to be viewed by the user's eyes, and images of the user's eyes and / or their surroundings to be captured. Furthermore, the cell IM of the cell array CA can retain analog data written in response to a minute current for a long period of time. Furthermore, the arithmetic circuit 40, which performs product-sum calculations using a minute current, can perform calculations with high arithmetic efficiency.

[0279] 18B shows a block diagram of each component of the layers 20, 50, and 60 in FIG. 18A. The driving circuit 30 in the layer 20 outputs signals GS and DS (for example, GS is a signal for driving a gate line, and DS is a signal corresponding to image data) for controlling the pixel circuit section 51P in the layer 50. The pixel circuit section 51P in the layer 50 supplies a current I corresponding to image data to a light emitting element 61 (not shown) in the display section 13 in the layer 60. EL The light emitting element 61 (not shown) in the display unit 13 on the layer 60 outputs a current I EL The light is emitted in accordance with the image, and the user can visually recognize the image.

[0280] In the block diagram shown in FIG. 18B, a light receiving element 62 (not shown) in the light receiving section 14 in the layer 60 captures an image around the display device 10, and a current I PS It outputs the current I PS is output to the cell array CA in the layer 50 and the arithmetic circuit 40 in the layer 20. The cell array CA in the layer 50 receives the current I PS , and a signal D corresponding to a product-sum operation in response to a control signal from the arithmetic circuit 40 in the layer 20. MAC to the arithmetic circuit 40 in the layer 20. The arithmetic circuit 40 in the layer 20 can perform inference processing based on a neural network ANN.

[0281] The layer 50 provided on the layer 20 may have a two-layer or more structure. For example, as shown in FIG. 19A, layers 50_1 and 50_2 having OS transistors may be provided. The layer 20 may also have a two-layer or more structure by a bonding process or the like. For example, as shown in FIG. 19B, layers 20_1 and 20_2 having Si transistors may be provided instead of the layers 50 and 20. The layers 20_1 and 20_2 having Si transistors may be bonded together by connecting electrodes (not shown) provided as TSVs (Through Silicon Vias) with microbumps 23 or the like.

[0282] <Three-dimensional structures of sensors and semiconductor devices> Next, a three-dimensional structure will be described when a semiconductor device capable of performing calculations using the output of a sensor such as a light receiving element provided in a part of the display device is provided in the display device 10. The display device 10 shown in Fig. 20 has a layer PDL, a layer ERL, a layer CCL, and a layer PHL. The layers CCL and PHL are provided with the respective components of the semiconductor device MAC1 or MAC1A described above. The circuit PTC provided in the layer CCL has circuits PTR[1] to PTR[m].

[0283] The circuit PTR[1] has a function of bringing the wiring EIL[1] and the wiring XCL[1] into a conductive state or a non-conductive state. Similarly, the circuit PTR[i] has a function of bringing the wiring EIL[i] and the wiring XCL[i] into a conductive state or a non-conductive state, and the circuit PTR[m] has a function of bringing the wiring EIL[m] and the wiring XCL[m] into a conductive state or a non-conductive state. In other words, each of the circuits PTR[1] to PTR[m] functions as a switching element.

[0284] Since the display device 10 shown in FIG. 20 is shown as a three-dimensional structure, arrows indicating the x, y, and z directions are added to FIG. 20. Note that the x, y, and z directions are shown as directions that are perpendicular to each other, as an example. In this specification, one of the x, y, and z directions may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0285] The layer CCL is located above the layer PHL, the layer ERL is located above the layer CCL, and the layer PDL is located above the layer ERL. In other words, the layers PHL, CCL, ERL, and PDL are stacked in this order in the z direction.

[0286] The layer PDL has a sensor array SCA, for example. The sensor array SCA has a plurality of electrodes and a plurality of sensors. In Fig. 20, for example, electrodes DNK[1] to DNK[m] (where m is an integer greater than or equal to 1) are shown as the plurality of electrodes, and sensors SNC[1] to SNC[m] are shown as the plurality of sensors. In addition, for example, m electrodes DNK are arranged in a matrix on the layer PDL, and sensors SNC[1] to SNC[m] are provided on the electrodes DNK[1] to DNK[m], respectively.

[0287] 20, the layer PDL shows only the symbols of the electrodes DNK[1], DNK[i] (where i is an integer between 1 and m), and DNK[m] among the electrodes DNK[1] to DNK[m]. Also, the layer PDL shows only the symbols of the sensors SNC[1], SNC[i], and SNC[m] among the sensors SNC[1] to SNC[m].

[0288] The sensors SNC[1] to SNC[m] convert sensed information into current values ​​and output the current values. The electrodes DNK[1] to DNK[m] function as terminals for outputting the current values ​​in the sensors SNC[1] to SNC[m]. For example, a light-receiving element can be used as the sensor SNC. By using a light-receiving element as the sensors SNC[1] to SNC[m], the layer PDL can be used as part of the image sensor. In this case, it is desirable that the range of light intensity that the light-receiving element can sense includes the intensity of light irradiated in the environment in which the light-receiving element is used. FIG. 20 shows a display device 10 employing a sensor SNC having a photodiode PD as the light-receiving element. The photodiode PD is preferably an organic light-emitting diode that can be provided in the same layer as the light-emitting element.

[0289] The circuit configuration of the sensor SNC[i] may be such that one of the input terminal or output terminal of the photodiode PD included in the sensor SNC[i] is electrically connected to the wiring EIL[i] via the electrode DNK[i]. The circuit configuration of the sensor SNC[i] may be such that a switch that cuts off the power supply to temporarily stop the sensor SNC[i] is provided. A light-emitting element (not shown) for displaying information may be provided on the same layer as the sensor SNC[i].

[0290] The layer ERL has wirings EIL[1] to EIL[m]. In the layer ERL shown in FIG. 20, the wirings EIL[1], EIL[i], and EIL[m] are shown by selecting the symbols of the wirings EIL[1] to EIL[m].

[0291] The wiring EIL[1] is electrically connected to the electrode DNK[1] on the layer PDL. The wiring EIL[i] is electrically connected to the electrode DNK[i] on the layer PDL. The wiring EIL[m] is electrically connected to the electrode DNK[m] on the layer PDL.

[0292] Specifically, for example, when viewed from above the display device 10 (viewing in the opposite direction of the z-axis arrow shown in Figure 20), plugs (sometimes called contact holes, etc.) are provided at the points where each of the electrodes DNK[1] to DNK[m] intersects with the wiring EIL[1] to EIL[m], electrically connecting each of the electrodes DNK[1] to DNK[m] to each of the wiring EIL[1] to EIL[m].

[0293] Therefore, when information is sensed in each of the sensors SNC[1] to SNC[m], the wiring EIL[1] to EIL[m] function as a path through which a current flows in an amount corresponding to the information output by each of the sensors SNC[1] to SNC[m].

[0294] Note that the layer PDL is preferably configured such that the sensors SNC[1] to SNC[m] can sequentially perform sensing, respectively, and current can sequentially flow through the wirings EIL[1] to EIL[m]. In this case, for example, the layer PDL may be configured to include signal lines for selecting the sensors SNC[1] to SNC[m], and signals or the like may be sequentially sent to the signal lines to operate the sensors SNC[1] to SNC[m] sequentially.

[0295] Furthermore, when the sensors SNC[1] to SNC[m] are light receiving elements configured with photodiodes or the like, the layer PDL of the display device 10 may be configured, for example, so that the output terminal (cathode) of the photodiode is electrically connected to the electrode DNK. Alternatively, as another configuration example, the layer PDL of the display device 10 may be configured so that the input terminal (anode) of the photodiode is electrically connected to the electrode DNK.

[0296] Furthermore, when the sensors SNC[1] to SNC[m] are light-receiving elements configured with photodiodes or the like, for example, by providing a filter that irradiates only one of the sensors SNC[1] to SNC[m] with light, the sensors SNC[1] to SNC[m] can be operated sequentially. Since there are m sensors SNC, there are m types of filters that irradiate only one sensor SNC with light. In addition, if a filter that does not irradiate any of the sensors SNC[1] to SNC[m] with light is provided, the number of filters becomes m+1. When light is irradiated onto the layer PDL, the sensors SNC[1] to SNC[m] can perform sensing sequentially by sequentially switching such filters.

[0297] Furthermore, when the sensors SNC[1] to SNC[m] are light receiving elements configured with photodiodes or the like, for example, the display device 10 may be configured to individually irradiate the sensors SNC[1] to SNC[m] with light. By configuring the sensors SNC[1] to SNC[m] to individually irradiate with light, the sensors SNC[1] to SNC[m] can be sequentially irradiated with light, and the sensors SNC[1] to SNC[m] can sequentially perform sensing.

[0298] The layer CCL includes, for example, a circuit PTC and a cell array CA. The layer PHL includes, for example, a circuit XCS, a circuit WCS, a circuit WSD, a circuit ITS, a circuit SWS1, and a circuit SWS2. As shown in FIG. 20, the cell array CA can be configured to be located above the circuit XCS, the circuit WCS, the circuit WSD, the circuit ITS, the circuit SWS1, and the circuit SWS2, which correspond to the peripheral circuits of the cell array CA.

[0299] The cell array CA has a plurality of cells, each of which has a function of holding weight data for performing a product-sum operation and a function of multiplying the weight data by input data.

[0300] The cell array CA is also electrically connected to a plurality of wirings. Specifically, for example, FIG. 20 shows a configuration in which the cell array CA is electrically connected to wirings WCL[1] to WCL[n] (where n is an integer equal to or greater than 1), wirings WSL[1] to WSL[m], and wirings XCL[1] to XCL[m]. In particular, the wirings WCL[1] to WCL[n] electrically connect the circuit SWS1 and the circuit SWS2. That is, the circuit SWS1 can be said to be electrically connected to the circuit SWS2 via the cell array CA by the wirings WCL[1] to WCL[n]. In FIG. 20, the wirings WSL[1] to WSL[m], wirings XCL[1] to XCL[m], and wirings WCL[1] to WCL[n] extend in the z-direction.

[0301] Furthermore, each of the cells in the cell array CA is electrically connected to one of the lines WCL[1] through WCL[n], one of the lines WSL[1] through WSL[m], and one of the lines XCL[1] through XCL[m]. Therefore, the cells included in the cell array CA are arranged in a matrix of at least m rows and n columns.

[0302] The circuit WCS has a function of supplying current to the wirings WCL[1] to WCL[n] in an amount corresponding to the weight data, and therefore is electrically connected to each of the wirings WCL[1] to WCL[n] via the circuit SWS1.

[0303] The circuit SWS1 has a function of bringing the circuit WCS into electrical continuity or non-conduction between the circuit WCS and each of the wirings WCL[1] to WCL[n].

[0304] The circuit WSD is electrically connected to the wirings WSL[1] to WSL[m]. When writing weight data to a cell included in the cell array CA, the circuit WSD has a function of selecting a row of the cell array CA to which the weight data is to be written by supplying a predetermined signal to the wirings WSL[1] to WSL[m]. In other words, the wirings WSL[1] to WSL[m] function as write word lines.

[0305] The circuit XCS is electrically connected to the wirings XCL[1] to XCL[m]. The circuit XCS has a function of supplying a current to the wirings XCL[1] to XCL[m] in an amount corresponding to reference data (to be described later) or in an amount corresponding to input data.

[0306] The circuit PTC includes circuits PTR[1] to PTR[m]. A first terminal of the circuit PTR[1] is electrically connected to a wiring XCL[1], a first terminal of the circuit PTR[i] is electrically connected to a wiring XCL[i], and a first terminal of the circuit PTR[m] is electrically connected to a wiring XCL[m].

[0307] In addition, the second terminal of the circuit PTR[1] is electrically connected to the wiring EIL[1] of the layer ERL, the second terminal of the circuit PTR[i] is electrically connected to the wiring EIL[i] of the layer ERL, and the second terminal of the circuit PTR[m] is electrically connected to the wiring EIL[m] of the layer ERL.

[0308] Specifically, for example, when viewed from above on the display device 10, plugs or the like are provided at the points where the second terminals of the circuits PTR[1] to PTR[m] intersect with the wirings EIL[1] to EIL[m], respectively, to electrically connect the second terminals of the circuits PTR[1] to PTR[m] with the wirings EIL[1] to EIL[m], respectively.

[0309] The circuit PTR[1] has a function of bringing the wiring EIL[1] and the wiring XCL[1] into a conductive state or a non-conductive state. Similarly, the circuit PTR[i] has a function of bringing the wiring EIL[i] and the wiring XCL[i] into a conductive state or a non-conductive state, and the circuit PTR[m] has a function of bringing the wiring EIL[m] and the wiring XCL[m] into a conductive state or a non-conductive state. In other words, each of the circuits PTR[1] to PTR[m] functions as a switching element.

[0310] The circuit ITS has a function of acquiring the amount of current flowing through the wirings WCL[1] to WCL[n] and outputting a result according to the amount of current to the wirings OL[1] to OL[n]. Therefore, the circuit ITS is electrically connected to each of the wirings WCL[1] to WCL[n] via the circuit SWS2. The circuit ITS is also electrically connected to each of the wirings OL[1] to OL[n].

[0311] The circuit SWS2 has a function of bringing the circuit ITS into a conductive state or a non-conductive state between the circuit ITS and each of the wirings WCL[1] to WCL[n].

[0312] 20, the wirings EIL[1] to EIL[m] preferably extend along the x-direction. That is, the direction in which the wirings EIL[1] to EIL[m] extend is preferably substantially parallel to the wirings XCL[1] to XCL[m] when viewed in the y-direction, and more preferably parallel. Furthermore, for example, the wirings EIL[1] to EIL[m] preferably extend substantially parallel to the wirings XCL[1] to XCL[m] included in the layer CCL when viewed from above, and more preferably parallel.

[0313] As described above, by applying the display device 10 shown in Fig. 20, the location of the sensor array SCA on the display device including the arithmetic circuit (layer CCL) can be determined almost freely. Therefore, for example, the sensor array SCA can be disposed at or near the center of the display device when viewed from above. Furthermore, the layout of the arithmetic circuit included in the layer CCL does not depend on the location of the sensor array SCA, which increases the degree of freedom in the layout of the arithmetic circuit and its surrounding wiring.

[0314] <Three-dimensional structure of driving circuits, pixel circuits, and light-emitting elements> 21A and 21B show an example of the configuration of pixel circuit 51 and light-emitting element 61 connected to pixel circuit 51, as shown in Fig. 18A. Fig. 21A is a diagram showing the connection of each element, and Fig. 21B is a diagram schematically showing the hierarchical relationship between layer 20 including drive circuit 30, layer 50 including multiple transistors that pixel circuit 51 has, and layer 60 including light-emitting element 61.

[0315] 21A and 21B include a pixel circuit 51 including a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The number of transistors, the number of capacitors, and the electrical connections between elements in the pixel circuit 51 are not limited to those shown in FIGS. 21A and 21B , and other configurations may be used. The transistors 52A, 52B, and 52C may be OS transistors. Each of the OS transistors 52A, 52B, and 52C preferably includes a back gate electrode. In this case, the back gate electrode may be configured to receive the same signal as the gate electrode, or a signal different from that of the gate electrode.

[0316] The transistor 52B includes a gate electrode electrically connected to the transistor 52A, a first electrode electrically connected to the light-emitting element 61, and a second electrode electrically connected to a wiring ANO. The wiring ANO is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0317] The transistor 52A has a first terminal electrically connected to the gate electrode of the transistor 52B, a second terminal electrically connected to the wiring SL functioning as a source line, and a gate electrode. The transistor 52A has a function of controlling the conductive state or non-conductive state based on the potential of the wiring GL1 functioning as a gate line.

[0318] The transistor 52C has a first terminal electrically connected to the wiring V0, a ​​second terminal electrically connected to the light-emitting element 61, and a gate electrode. The transistor 52C has a function of controlling the conductive state or non-conductive state based on the potential of the wiring GL2 that functions as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting a current flowing through the pixel circuit 51 to the drive circuit 30 or the arithmetic circuit 40.

[0319] The capacitor 53 includes a conductive film electrically connected to the gate electrode of the transistor 52B and a conductive film electrically connected to the second electrode of the transistor 52C.

[0320] The light-emitting element 61 includes a first electrode electrically connected to the first electrode of the transistor 52B and a second electrode electrically connected to a wiring VCOM. The wiring VCOM is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0321] This makes it possible to control the intensity of light emitted by the light-emitting element 61 in accordance with an image signal applied to the gate electrode of the transistor 52B. Also, the reference potential of the wiring V0 applied via the transistor 52C can suppress variations in the gate-source voltage of the transistor 52B.

[0322] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting element 61 to the outside. The current output to the wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter or the like and output to the arithmetic circuit 40 or the like.

[0323] Note that the light-emitting element described in one embodiment of the present invention refers to a self-luminous light-emitting element such as an organic light-emitting element (also referred to as an OLED (organic light-emitting diode)). Note that the light-emitting element electrically connected to the pixel circuit can be a self-luminous light-emitting element such as an LED (light-emitting diode), a micro LED, a QLED (quantum-dot light-emitting diode), or a semiconductor laser.

[0324] In the configuration shown in FIG. 21B as an example, the wiring electrically connecting the pixel circuits 51 and the drive circuit 30 can be shortened, thereby reducing the wiring resistance of the wiring. This allows data to be written at high speed, thereby enabling the display device 10 to be driven at high speed. This allows a sufficient frame period to be ensured even if the display device 10 has a large number of pixel circuits 51, thereby increasing the pixel density of the display device 10. Furthermore, increasing the pixel density of the display device 10 increases the resolution of the image displayed by the display device 10. For example, the pixel density of the display device 10 can be set to 1000 ppi or more, 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 10 can be used as a display device for AR or VR, for example, and can be suitably applied to electronic devices in which the display unit is close to the user, such as a head-mounted display.

[0325] 21A and 21B may be provided with the arithmetic circuit 40, the cell array CA, and the photodiode PD, which is a light-receiving element, respectively, as described in the third embodiment. Therefore, the display device 10 may be configured to include an arithmetic circuit and a drive circuit, a pixel circuit and a cell array, a light-emitting element, and a light-receiving element.

[0326] As described above, the display device 10 of one embodiment of the present invention can have a stacked structure including the light-emitting element 61, the pixel circuit 51, and the driver circuit 30, thereby enabling an extremely high pixel aperture ratio (effective display area ratio). Furthermore, the pixel circuits 51 can be arranged at extremely high density, enabling extremely high pixel resolution. Because of its extremely high resolution, the display device 10 can be suitably used for VR devices such as head-mounted displays or glasses-type AR devices. For example, even in a configuration in which the display portion of the display device 10 is viewed through an optical component such as a lens, the display device 10 has an extremely high-resolution display portion, and therefore, pixels are not visible even when the display portion is enlarged with the lens, enabling highly immersive display.

[0327] Furthermore, the display device 10 of one embodiment of the present invention can have a stacked structure including the light-receiving element 62, the cell array CA, and the arithmetic circuit 40. Therefore, the display device 10 can perform arithmetic processing with high arithmetic efficiency using a minute current output from the light-receiving element 62 as input data. Furthermore, the display device 10 can have a structure in which the light-receiving unit 14 is located close to the display unit 13. This allows the user to view an image with their eyes and capture images of the user's eyes and / or their surroundings. Furthermore, the cell IM of the cell array CA can retain analog data written in response to a minute current for a long period of time. Furthermore, the arithmetic circuit 40, which performs a product-sum operation using a minute current, can perform arithmetic processing with high arithmetic efficiency.

[0328] <Top view and cross-sectional view of the light-emitting element> 22A is a schematic top view illustrating a configuration example in which a light-emitting element and a light-receiving element are arranged in one pixel in a display device 10 according to one embodiment of the present invention. The display device 10 includes a plurality of light-emitting elements 61R that emit red light, a plurality of light-emitting elements 61G that emit green light, a plurality of light-emitting elements 61B that emit blue light, and a plurality of light-receiving elements 62. In FIG. 22A, in order to easily distinguish between the light-emitting elements 61, the light-emitting regions of the light-emitting elements 61 are labeled with R, G, and B. Furthermore, the light-receiving regions of the light-receiving elements 62 are labeled with PD.

[0329] The light-emitting elements 61R, 61G, 61B, and the light-receiving elements 62 are arranged in a matrix. FIG. 22A shows an example in which the light-emitting elements 61R, 61G, and 61B are arranged in the X direction, and the light-receiving elements 62 are arranged below them. FIG. 22A also shows an example in which the light-emitting elements 61 emitting light of the same color are arranged in the Y direction intersecting the X direction. In the display device 10 shown in FIG. 22A, a pixel 80 can be configured by, for example, a sub-pixel having the light-emitting element 61R, a sub-pixel having the light-emitting element 61G, and a sub-pixel having the light-emitting element 61B arranged in the X direction, and a sub-pixel having the light-receiving element 62 provided below these sub-pixels.

[0330] The light-emitting elements 61R, 61G, and 61B are preferably EL elements such as organic light-emitting diodes (OLEDs) or quantum-dot light-emitting diodes (QLEDs). Examples of light-emitting materials included in the EL elements include fluorescent materials, phosphorescent materials, inorganic compounds (quantum dot materials, etc.), and thermally activated delayed fluorescence (TADF) materials. The TADF material may be a material that is in thermal equilibrium between a singlet excited state and a triplet excited state. Such TADF materials have a short emission lifetime (excitation lifetime), which can suppress a decrease in the efficiency of the light-emitting elements in the high-brightness range.

[0331] For example, a pn-type or pin-type photodiode can be used as the light receiving element 62. The light receiving element 62 functions as a photoelectric conversion element that detects light incident on the light receiving element 62 and generates an electric charge. The amount of electric charge generated is determined based on the amount of incident light.

[0332] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound as the light receiving element 62. Organic photodiodes can be easily made thin, lightweight, and large in area, and have a high degree of freedom in shape and design, making them applicable to a variety of display devices.

[0333] In one embodiment of the present invention, an organic EL element is used as the light-emitting element 61, and an organic photodiode is used as the light-receiving element 62. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL element. The organic EL elements and the organic photodiode are preferably separated from each other by photolithography. This allows the distance between the light-emitting elements and the organic photodiode to be narrowed, thereby realizing a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0334] 22A shows a common electrode 81 and a connection electrode 82. Here, the connection electrode 82 is electrically connected to the common electrode 81. The connection electrode 82 is provided outside the display section in which the light-emitting elements 61 and the light-receiving elements 62 are arranged. Also in FIG. 22A, the common electrode 81 having an area overlapping with the light-emitting elements 61, the light-receiving elements 62, and the connection electrode 82 is shown by a dashed line.

[0335] The connection electrodes 82 can be provided along the periphery of the display unit. For example, they may be provided along one side of the periphery of the display unit, or they may be provided over two or more sides of the periphery of the display unit. That is, if the top surface of the display unit has a rectangular shape, the top surface of the connection electrodes 82 can have a strip-like, L-shaped, U-shaped (square bracket-shaped), quadrangular, or the like shape.

[0336] Fig. 22B is a schematic top view showing an example of the configuration of display device 10, which is a modification of display device 10 shown in Fig. 22A. Display device 10 shown in Fig. 22B differs from display device 10 shown in Fig. 22A in that it includes a light-emitting element 61IR that emits infrared light. Light-emitting element 61IR can emit, for example, near-infrared light (light with a wavelength of 750 nm or more and 1300 nm or less).

[0337] 22B, in addition to light-emitting elements 61R, 61G, and 61B, a light-emitting element 61IR is arranged in the X direction, and a light-receiving element 62 is arranged below them. The light-receiving element 62 has a function of detecting infrared light.

[0338] Fig. 23A is a cross-sectional view corresponding to dashed-dotted line A1-A2 in Fig. 22A, and Fig. 23B is a cross-sectional view corresponding to dashed-dotted line B1-B2 in Fig. 22A. Fig. 23C is a cross-sectional view corresponding to dashed-dotted line C1-C2 in Fig. 22A, and Fig. 23D is a cross-sectional view corresponding to dashed-dotted line D1-D2 in Fig. 22A. The light-emitting element 61R, the light-emitting element 61G, the light-emitting element 61B, and the light-receiving element 62 are provided on a substrate 83. Furthermore, when the display device 10 has a light-emitting element 61IR, the light-emitting element 61IR is provided on the substrate 83.

[0339] In this specification and the like, for example, when it is said that "B is on A" or "B is below A," A and B do not necessarily have to have an area where they contact each other.

[0340] 23A shows an example of the cross-sectional configuration of the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B, and FIG.

[0341] The light-emitting element 61R has a pixel electrode 84R, a hole injection layer 85R, a hole transport layer 86R, a light-emitting layer 87R, an electron transport layer 88R, a common layer 89, and a common electrode 81. The light-emitting element 61G has a pixel electrode 84G, a hole injection layer 85G, a hole transport layer 86G, a light-emitting layer 87G, an electron transport layer 88G, a common layer 89, and a common electrode 81. The light-emitting element 61B has a pixel electrode 84B, a hole injection layer 85B, a hole transport layer 86B, a light-emitting layer 87B, an electron transport layer 88B, a common layer 89, and a common electrode 81. The light-receiving element 62 has a pixel electrode 84PD, a hole transport layer 86PD, a light-receiving layer 90, an electron transport layer 88PD, a common layer 89, and a common electrode 81.

[0342] In the following description, when describing matters common to the hole injection layer 85R, the hole injection layer 85G, the hole injection layer 85B, etc., it may be referred to as the hole injection layer 85. When describing matters common to the hole transport layer 86R, the hole transport layer 86G, the hole transport layer 86B, the hole transport layer 86PD, etc., it may be referred to as the hole transport layer 86. When describing matters common to the light-emitting layer 87R, the light-emitting layer 87G, the light-emitting layer 87B, etc., it may be referred to as the light-emitting layer 87. When describing matters common to the electron transport layer 88R, the electron transport layer 88G, the electron transport layer 88B, the electron transport layer 88PD, etc., it may be referred to as the electron transport layer 88.

[0343] The common layer 89 functions as an electron injection layer in the light-emitting element 61. On the other hand, the common layer 89 functions as an electron transport layer in the light-receiving element 62. Therefore, the light-receiving element 62 does not need to have the electron transport layer 88PD.

[0344] The hole injection layer 85, the hole transport layer 86, the electron transport layer 88, and the common layer 89 can also be referred to as functional layers.

[0345] The pixel electrode 84, the hole injection layer 85, the hole transport layer 86, the light-emitting layer 87, and the electron transport layer 88 can be provided separately for each element. The common layer 89 and the common electrode 81 are provided in common to the light-emitting element 61R, the light-emitting element 61G, the light-emitting element 61B, and the light-receiving element 62.

[0346] 23A, the light-emitting element 61 and the light-receiving element 62 may have a hole-blocking layer and an electron-blocking layer. The light-emitting element 61 and the light-receiving element 62 may also have a layer containing a bipolar substance (a substance with high electron-transporting and hole-transporting properties) or the like.

[0347] A gap is provided between the common layer 89 and the insulating layer 92, which will be described later. This prevents the common layer 89 from coming into contact with the side surfaces of the light-emitting layer 87, the light-receiving layer 90, the hole-transporting layer 86, and the hole-injecting layer 85. This prevents short circuits in the light-emitting element 61 and the light-receiving element 62.

[0348] The voids are more easily formed, for example, as the distance between the light-emitting layers 87 becomes shorter. For example, the voids can be suitably formed when the distance is 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less.

[0349] 23A illustrates a configuration in which, from bottom to top, a pixel electrode 84, a hole injection layer 85, a hole transport layer 86, a light-emitting layer 87, an electron transport layer 88, a common layer 89 (electron injection layer), and a common electrode 81 are provided in the light-emitting element 61. Also, in FIG. 23B, a configuration in which, from bottom to top, a pixel electrode 84PD, a hole transport layer 86PD, a light-receiving layer 90, an electron transport layer 88PD, a common layer 89, and a common electrode 81 are provided in the light-receiving element 62. However, this is not a limitation of this embodiment. For example, the light-emitting element 61 may be provided, from bottom to top, with a pixel electrode, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, a hole injection layer, and a common electrode, and the light-receiving element 62 may be provided, from bottom to top, with a pixel electrode, an electron transport layer, a light-receiving layer, a hole transport layer, and a common electrode. In this case, the hole injection layer of the light-emitting element 61 can be a common layer, and the common layer can be provided between the hole transport layer and the common electrode of the light-receiving element 62. Also, in the light-emitting element 61, the electron injection layer can be separated for each element.

[0350] In the following description, the electron transport layer is assumed to be provided above the hole transport layer. However, the following description can also be applied to the case where the electron transport layer is provided below the hole transport layer, for example, by replacing "electrons" with "holes" and "holes" with "electrons."

[0351] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound and a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0352] The hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light emitting layer. The hole transport layer is a layer that contains a hole transporting material. Examples of the hole transporting material include 10 -6 cm 2 A material having a hole mobility of 1 / Vs or more is preferred. Note that other materials can also be used as long as they have a higher hole transporting property than electron transporting property. As the hole transporting material, a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, a furan derivative, etc.) or an aromatic amine (a compound having an aromatic amine skeleton), is preferred.

[0353] The electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light emitting layer. The electron transport layer is a layer that contains an electron transporting material. The electron transporting material is a material having a molecular weight of 1×10 -6 cm 2A substance having an electron mobility of 1 / Vs or more is preferred. Note that other substances can also be used as long as they have a higher electron transporting property than holes. Examples of electron-transporting materials that can be used include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, and metal complexes having a thiazole skeleton, as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and π-electron-deficient heteroaromatic compounds including nitrogen-containing heteroaromatic compounds.

[0354] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer and contains a material with high electron injection properties. Examples of the material with high electron injection properties include alkali metals, alkaline earth metals, and compounds thereof. Examples of the material with high electron injection properties include a composite material containing an electron transport material and a donor material (electron donor material).

[0355] Examples of the electron injection layer include lithium, cesium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF), 8-(quinolinolato)lithium (abbreviation: Liq), 2-(2-pyridyl)phenolatolithium (abbreviation: LiPP), 2-(2-pyridyl)-3-pyridinolatolithium (abbreviation: LiPPy), 4-phenyl-2-(2-pyridyl)phenolatolithium (abbreviation: LiPPP), and lithium oxide (LiO x ), alkali metals such as cesium carbonate, alkaline earth metals, or compounds thereof can be used.

[0356] Alternatively, the electron injection layer may be formed using a material having electron transport properties. For example, a compound having an unshared electron pair and an electron-deficient heteroaromatic ring may be used as the material having electron transport properties. Specifically, a compound having at least one of a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring), and a triazine ring may be used.

[0357] The organic compound having an unshared electron pair preferably has a lowest unoccupied molecular orbital (LUMO) of -3.6 eV to -2.3 eV. Generally, the highest occupied molecular orbital (HOMO) level and the LUMO level of an organic compound can be estimated by cyclic voltammetry (CV), photoelectron spectroscopy, optical absorption spectroscopy, inverse photoelectron spectroscopy, or the like.

[0358] Examples of organic compounds with lone electron pairs include 4,7-diphenyl-1,10-phenanthroline (abbreviated as BPhen), 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviated as NBPhen), diquinoxalino[2,3-a:2',3'-c]phenazine (abbreviated as HATNA), and 2,4,6-tris[3'-(pyridin-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviated as TmPPPyTz). NBPhen has a higher glass transition temperature (Tg) and better heat resistance than BPhen.

[0359] The light-emitting layer is a layer containing a light-emitting substance. The light-emitting layer can contain one or more light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0360] Examples of the light-emitting material include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0361] Examples of fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0362] Examples of phosphorescent materials include organometallic complexes (particularly iridium complexes) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton; organometallic complexes (particularly iridium complexes) having a phenylpyridine derivative having an electron-withdrawing group as a ligand; platinum complexes; and rare earth metal complexes.

[0363] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). One or more organic compounds may be a hole-transporting material or an electron-transporting material, or both. Alternatively, a bipolar material or a TADF material may be used as the one or more organic compounds.

[0364] The light-emitting layer preferably contains, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. This configuration allows for efficient light emission using Exciplex-Triplet Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, the energy transfer becomes smooth, allowing for efficient light emission. This configuration simultaneously enables high efficiency, low-voltage operation, and long life of the light-emitting element.

[0365] The light-emitting layer 87R of the light-emitting element 61R contains a light-emitting organic compound that emits light having an intensity in at least the red wavelength range. The light-emitting layer 87G of the light-emitting element 61G contains a light-emitting organic compound that emits light having an intensity in at least the green wavelength range. The light-emitting layer 87B of the light-emitting element 61B contains a light-emitting organic compound that emits light having an intensity in at least the blue wavelength range. The light-receiving layer 90 of the light-receiving element 62 contains an organic compound that has detection sensitivity in the wavelength range of visible light, for example.

[0366] A conductive film that is translucent to visible light is used for either the pixel electrode 84 or the common electrode 81, and a conductive film that is reflective is used for the other. By making the pixel electrode 84 translucent and the common electrode 81 reflective, the display device 10 can be made into a bottom-emission display device. On the other hand, by making the pixel electrode 84 reflective and the common electrode 81 translucent, the display device 10 can be made into a top-emission display device. Note that by making both the pixel electrode 84 and the common electrode 81 translucent, the display device 10 can also be made into a dual-emission display device.

[0367] Furthermore, the light-emitting element 61 preferably has a micro-optical resonator (microcavity) structure, which allows the light emitted from the light-emitting layer 87 to resonate between the pixel electrode 84 and the common electrode 81, thereby intensifying the light emitted from the light-emitting element 61.

[0368] When the light-emitting element 61 has a microcavity structure, it is preferable that one of the common electrode 81 and the pixel electrode 84 is an electrode having both light-transmitting and reflective properties (semi-transmissive / semi-reflective electrode), and the other of the common electrode 81 and the pixel electrode 84 is an electrode having reflective properties (reflective electrode). Here, the semi-transmissive / semi-reflective electrode can have a laminated structure of a reflective electrode and an electrode having transparency to visible light (also called a transparent electrode). The transparent electrode can be referred to as an optical adjustment layer.

[0369] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode for the light emitting element 61 that has a transmittance of 40% or more for visible light (light with a wavelength of 400 nm or more and less than 750 nm). The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes is 1×10 -2 When a light-emitting element that emits near-infrared light is used in the display device, the transmittance and reflectance of these electrodes for near-infrared light (light with a wavelength of 750 nm or more and 1300 nm or less) are preferably within the above-mentioned ranges.

[0370] An insulating layer 92 is provided to cover the end portions of the pixel electrodes 84R, 84G, 84B, and 84PD. The end portions of the insulating layer 92 are preferably tapered. Note that the insulating layer 92 does not have to be provided if it is not necessary.

[0371] For example, the hole injection layer 85R, the hole injection layer 85G, the hole injection layer 85B, and the hole transport layer 86PD each have a region in contact with the upper surface of the pixel electrode 84 and a region in contact with the surface of the insulating layer 92. In addition, the end of the hole injection layer 85R, the end of the hole injection layer 85G, the end of the hole injection layer 85B, and the end of the hole transport layer 86PD are located on the insulating layer 92.

[0372] 23A, between light-emitting elements 61 emitting light of different colors, a gap is provided, for example, between two light-emitting layers 87. In this manner, for example, light-emitting layer 87R, light-emitting layer 87G, and light-emitting layer 87B are preferably provided so as not to be in contact with one another. This makes it possible to preferably prevent current from flowing through two adjacent light-emitting layers 87, thereby preventing unintended light emission. This makes it possible to increase the contrast of display device 10, thereby improving the display quality of display device 10.

[0373] A protective layer 91 is provided on the common electrode 81. The protective layer 91 has the function of preventing impurities such as water from diffusing from above into each light-emitting element.

[0374] The protective layer 91 may have, for example, a single-layer structure or a multilayer structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, the protective layer 91 may be made of a semiconductor material such as indium gallium oxide or indium gallium zinc oxide.

[0375] In this specification and the like, a silicon oxynitride film refers to a film whose composition contains more oxygen than nitrogen, and a silicon nitride oxide film refers to a film whose composition contains more nitrogen than oxygen.

[0376] Alternatively, a laminated film of an inorganic insulating film and an organic insulating film may be used as the protective layer 91. For example, a configuration in which an organic insulating film is sandwiched between a pair of inorganic insulating films is preferable. Furthermore, it is preferable that the organic insulating film functions as a planarizing film. This allows the upper surface of the organic insulating film to be flat, improving the coverage of the inorganic insulating film thereon and enhancing the barrier properties. Furthermore, since the upper surface of the protective layer 91 is flat, when a structure (e.g., a color filter, a touch sensor electrode, a lens array, etc.) is provided above the protective layer 91, the influence of uneven shapes caused by the structure below can be reduced, which is preferable.

[0377] 23A and 23B, if the insulating layer 92 is not provided, the spacing between the light-emitting elements can be narrowed. For example, FIGS. 24A and 24B illustrate diagrams in which the insulating layer 92 is omitted. The region 92R between the light-emitting elements in FIGS. 24A and 24B may have an insulating layer containing an organic material. For example, the region 92R may be filled with an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimideamide resin, a silicone resin, a siloxane resin, a benzocyclobutene resin, a phenolic resin, or a precursor of these resins. The region 92R may also be filled with a photosensitive resin. A photoresist may be used as the photosensitive resin. The photosensitive resin may be a positive-type material or a negative-type material.

[0378] 23C shows an example of a cross-sectional configuration of the display device 10 in the Y direction, specifically showing an example of a cross-sectional configuration of the light-emitting element 61R and the light-receiving element 62. Note that the light-emitting element 61G and the light-emitting element 61B can also be arranged in the Y direction in the same manner as the light-emitting element 61R.

[0379] 23D shows a connection portion 93 where the connection electrode 82 and the common electrode 81 are electrically connected. In the connection portion 93, the common electrode 81 is provided in contact with the connection electrode 82, and a protective layer 91 is provided to cover the common electrode 81. In addition, an insulating layer 92 is provided to cover the end of the connection electrode 82.

[0380] <Configuration example of light-emitting element> As shown in FIG. 25A, the light-emitting element has an EL layer 686 between a pair of electrodes (electrode 672 and electrode 688). The EL layer 686 can be composed of multiple layers such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can have, for example, a layer containing a substance with high electron-injecting properties (electron-injecting layer) and a layer containing a substance with high electron-transporting properties (electron-transporting layer). The light-emitting layer 4411 contains, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with high hole-injecting properties (hole-injecting layer) and a layer containing a substance with high hole-transporting properties (hole-transporting layer).

[0381] A structure including the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 25A is referred to as a single structure in this specification.

[0382] 25B shows a modification of the EL layer 686 included in the light-emitting element shown in Fig. 25A. Specifically, the light-emitting element shown in Fig. 25B includes a layer 4430-1 on an electrode 672, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and an electrode 688 on the layer 4420-2. For example, when the electrode 672 is an anode and the electrode 688 is a cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. 25B , it is possible to efficiently inject carriers into light-emitting layer 4411 and increase the efficiency of carrier recombination in light-emitting layer 4411.

[0383] As shown in FIG. 25C, a configuration in which a plurality of light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between layer 4420 and layer 4430 is also a variation of the single structure.

[0384] Furthermore, as shown in Figure 25D, a configuration in which multiple light-emitting units (EL layer 686a, EL layer 686b) are connected in series via an intermediate layer (charge generation layer) 4440 is referred to as a tandem structure in this specification. Note that, although the configuration shown in Figure 25D is referred to as a tandem structure in this specification, the present invention is not limited to this, and for example, the tandem structure may also be referred to as a stack structure. Note that by using a tandem structure, a light-emitting element capable of emitting light with high brightness can be obtained.

[0385] 25C and 25D, the layer 4420 and the layer 4430 may have a laminated structure made up of two or more layers, as shown in FIG. 25B.

[0386] Furthermore, a structure in which each light-emitting element produces a different emission color (here, blue (B), green (G), and red (R)) is sometimes called an SBS (Side By Side) structure.

[0387] Furthermore, when comparing the above-mentioned single and tandem structures with the SBS structure, the order of decreasing power consumption is SBS, tandem, and single. If you want to keep power consumption low, the SBS structure is preferable. On the other hand, the single and tandem structures are preferable because their manufacturing processes are simpler than those of the SBS structure, allowing for lower manufacturing costs or higher manufacturing yields.

[0388] The color of light emitted from the light-emitting element can be red, green, blue, cyan, magenta, yellow, white, or the like, depending on the material constituting the EL layer 686. Furthermore, the color purity can be further improved by providing the light-emitting element with a microcavity structure.

[0389] A light-emitting element that emits white light preferably has a structure in which two or more types of light-emitting materials are contained in the light-emitting layer. To obtain white light emission, light-emitting materials can be selected so that the respective emissions of the two or more light-emitting materials have a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary colors, a light-emitting element that emits white light as a whole can be obtained. The same applies to a light-emitting element having three or more light-emitting layers.

[0390] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0391] <Configuration example of light emitting element and light receiving element> A display device according to one embodiment of the present invention is a top-emission display device that emits light in a direction opposite to a substrate on which a light-emitting element is formed. In this embodiment, a display device including a top-emission light-emitting element and a light-receiving element will be described as an example.

[0392] In this specification, unless otherwise specified, even when describing a configuration having a plurality of elements (e.g., light-emitting elements, light-emitting layers), when describing matters common to each element, the alphabet will be omitted. For example, when describing matters common to light-emitting layer 383R and light-emitting layer 383G, etc., they may be referred to as light-emitting layer 383.

[0393] A display device 380A shown in FIG. 26A has a light receiving element 370PD, a light emitting element 370R that emits red (R) light, a light emitting element 370G that emits green (G) light, and a light emitting element 370B that emits blue (B) light.

[0394] Each light-emitting element has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, ​​a light-emitting layer, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 stacked in this order. Light-emitting element 370R has a light-emitting layer 383R, light-emitting element 370G has a light-emitting layer 383G, and light-emitting element 370B has a light-emitting layer 383B. Light-emitting layer 383R contains a light-emitting material that emits red light, light-emitting layer 383G contains a light-emitting material that emits green light, and light-emitting layer 383B contains a light-emitting material that emits blue light.

[0395] The light emitting element is an electroluminescent element that emits light toward the common electrode 375 when a voltage is applied between the pixel electrode 371 and the common electrode 375 .

[0396] The light receiving element 370PD has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, ​​an active layer 373, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 stacked in this order.

[0397] The light receiving element 370PD is a photoelectric conversion element that receives light incident from outside the display device 380A and converts it into an electrical signal.

[0398] In this embodiment, in both the light-emitting element and the light-receiving element, the pixel electrode 371 functions as an anode and the common electrode 375 functions as a cathode. In other words, by applying a reverse bias between the pixel electrode 371 and the common electrode 375 and driving the light-receiving element, the light-receiving element can detect light incident on the light-receiving element, generate electric charges, and extract the electric charges as a current.

[0399] In the display device of this embodiment, an organic compound is used for the active layer 373 of the light-receiving element 370PD. The layers of the light-receiving element 370PD other than the active layer 373 can be configured in common with the light-emitting element. Therefore, by simply adding a step of forming the active layer 373 to the manufacturing process of the light-emitting element, the light-receiving element 370PD can be formed in parallel with the formation of the light-emitting element. Furthermore, the light-emitting element and the light-receiving element 370PD can be formed on the same substrate. Therefore, the light-receiving element 370PD can be built into the display device without significantly increasing the number of manufacturing steps.

[0400] In the display device 380A, the light receiving element 370PD and the light emitting element have a common configuration, except that the active layer 373 of the light receiving element 370PD and the light emitting layer 383 of the light emitting element are fabricated separately. However, the configuration of the light receiving element 370PD and the light emitting element is not limited to this. The light receiving element 370PD and the light emitting element may have layers fabricated separately from each other, in addition to the active layer 373 and the light emitting layer 383. It is preferable that the light receiving element 370PD and the light emitting element have one or more layers used in common (common layers). This allows the light receiving element 370PD to be incorporated into the display device without significantly increasing the number of manufacturing steps.

[0401] A conductive film that transmits visible light is used for the electrode from which light is extracted, between the pixel electrode 371 and the common electrode 375. It is preferable to use a conductive film that reflects visible light for the electrode from which light is not extracted.

[0402] The light-emitting element included in the display device of this embodiment preferably has a micro-optical resonator (microcavity) structure. Therefore, one of a pair of electrodes included in the light-emitting element preferably has an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other preferably has an electrode that is reflective to visible light (reflective electrode). When the light-emitting element has a microcavity structure, light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0403] The semi-transmitting / semi-reflective electrode can have a laminated structure of a reflective electrode and an electrode that is transparent to visible light (also called a transparent electrode).

[0404] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode with a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the light emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the resistivity of these electrodes is 1×10 -2 When the light-emitting element emits near-infrared light (light with a wavelength of 750 nm or more and 1300 nm or less), the transmittance or reflectance of these electrodes for near-infrared light preferably satisfies the above-mentioned numerical range, similar to the transmittance or reflectance for visible light.

[0405] The light-emitting element has at least a light-emitting layer 383. The light-emitting element may further have, in addition to the light-emitting layer 383, a layer containing a substance having a high hole-injecting property, a substance having a high hole-transporting property, a hole-blocking material, a substance having a high electron-transporting property, a substance having a high electron-injecting property, an electron-blocking material, a bipolar substance (a substance having a high electron-transporting property and a high hole-transporting property), or the like.

[0406] For example, the light-emitting element and the light-receiving element may have one or more layers of the hole injection layer, hole transport layer, electron transport layer, and electron injection layer in common, or the light-emitting element and the light-receiving element may have one or more layers of the hole injection layer, hole transport layer, electron transport layer, and electron injection layer formed differently from each other.

[0407] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound or a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0408] In a light-emitting element, the hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light-emitting layer. In a light-receiving element, the hole transport layer is a layer that transports holes generated in the active layer based on incident light to the anode. The hole transport layer is a layer that contains a hole transport material. The hole transport material is a material having a concentration of 1×10 -6 cm 2 A material having a hole mobility of 1 / Vs or more is preferred. Note that other materials can also be used as long as they have a higher hole transporting property than electron transporting property. As the hole transporting material, a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, a furan derivative, etc.) or an aromatic amine (a compound having an aromatic amine skeleton), is preferred.

[0409] In a light-emitting element, the electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light-emitting layer. In a light-receiving element, the electron transport layer is a layer that transports electrons generated in the active layer based on incident light to the cathode. The electron transport layer is a layer that contains an electron transporting material. The electron transporting material is a material having a concentration of 1×10 -6 cm 2A substance having an electron mobility of 1 / Vs or more is preferred. Note that other substances can also be used as long as they have a higher electron transporting property than holes. Examples of electron-transporting materials that can be used include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, and metal complexes having a thiazole skeleton, as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and π-electron-deficient heteroaromatic compounds including nitrogen-containing heteroaromatic compounds.

[0410] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer and contains a material with high electron injection properties. Examples of the material with high electron injection properties include alkali metals, alkaline earth metals, and compounds thereof. Examples of the material with high electron injection properties include a composite material containing an electron transport material and a donor material (electron donor material).

[0411] The light-emitting layer 383 is a layer containing a light-emitting substance. The light-emitting layer 383 can contain one or more light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0412] Examples of light-emitting materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0413] Examples of fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0414] Examples of phosphorescent materials include organometallic complexes (particularly iridium complexes) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton; organometallic complexes (particularly iridium complexes) having a phenylpyridine derivative having an electron-withdrawing group as a ligand; platinum complexes; and rare earth metal complexes.

[0415] The light-emitting layer 383 may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a hole-transporting material and an electron-transporting material can be used. Furthermore, as the one or more organic compounds, a bipolar material or a TADF material can be used.

[0416] The light-emitting layer 383 preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. This structure allows efficient emission using Exciplex-Triplet Energy Transfer (ExTET), which is energy transfer from an exciplex to a light-emitting substance (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting substance, the energy transfer becomes smooth, allowing efficient emission. This structure simultaneously enables high efficiency, low-voltage operation, and long life of the light-emitting element.

[0417] As a combination of materials that form an exciplex, it is preferable that the HOMO level (highest occupied molecular orbital level) of the hole-transporting material is equal to or higher than the HOMO level of the electron-transporting material. It is also preferable that the LUMO level (lowest unoccupied molecular orbital level) of the hole-transporting material is equal to or higher than the LUMO level of the electron-transporting material. The LUMO level and HOMO level of the material can be derived from the electrochemical properties (reduction potential and oxidation potential) of the material measured by cyclic voltammetry (CV).

[0418] The formation of exciplexes can be confirmed, for example, by comparing the emission spectra of the hole-transporting material, the electron-transporting material, and the mixed film of these materials and observing the phenomenon that the emission spectrum of the mixed film is shifted to longer wavelengths than the emission spectra of each material (or has a new peak at longer wavelengths). Alternatively, it can be confirmed by comparing the transient photoluminescence (PL) of the hole-transporting material, the transient PL of the electron-transporting material, and the mixed film of these materials and observing differences in transient response, such as the transient PL lifetime of the mixed film having a longer-lived component or a larger proportion of delayed components than the transient PL lifetimes of the individual materials. The above-mentioned transient PL can also be interpreted as transient electroluminescence (EL). In other words, the formation of exciplexes can also be confirmed by comparing the transient EL of the hole-transporting material, the transient EL of the electron-transporting material, and the mixed film of these materials and observing differences in transient response.

[0419] The active layer 373 includes a semiconductor. Examples of the semiconductor include an inorganic semiconductor such as silicon and an organic semiconductor including an organic compound. In this embodiment, an example in which an organic semiconductor is used as the semiconductor included in the active layer 373 is shown. By using an organic semiconductor, the light-emitting layer 383 and the active layer 373 can be formed by the same method (for example, vacuum evaporation), which is preferable because a common manufacturing device can be used.

[0420] The active layer 373 has an n-type semiconductor material, such as fullerene (e.g., C 60 , C 70Examples of electron-accepting organic semiconductor materials include fullerene derivatives and other fullerenes. Fullerenes have a soccer ball-like shape, which is energetically stable. Fullerenes have deep (low) HOMO and LUMO levels. Because fullerenes have a deep LUMO level, they have extremely high electron-accepting (acceptor) properties. Normally, when the π-electron conjugation (resonance) spreads on a plane, as in benzene, the electron-donating (donor) properties increase, but fullerenes have a spherical shape, so they have high electron-accepting properties despite the large spread of π-electrons. High electron-accepting properties allow charge separation to occur quickly and efficiently, making them useful as light-receiving elements. C 60 , C 70 Both have a wide absorption band in the visible light region, especially C 70 is C 60 It is preferable because it has a larger π-electron conjugated system and a broad absorption band in the long wavelength region compared to [6,6]-Phenyl-C71-butyric acid methyl ester (abbreviation: PC70BM), [6,6]-Phenyl-C61-butyric acid methyl ester (abbreviation: PC60BM), and 1',1'',4',4''-Tetrahydro-di[1,4]methanonaphthaleno[1,2:2',3',56,60:2'',3''][5,6]fullerene-C60 (abbreviation: ICBA).

[0421] Furthermore, examples of n-type semiconductor materials include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, naphthalene derivatives, anthracene derivatives, coumarin derivatives, rhodamine derivatives, triazine derivatives, and quinone derivatives.

[0422] Examples of the p-type semiconductor material of the active layer 373 include electron-donating organic semiconductor materials such as copper(II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), zinc phthalocyanine (ZnPc), tin phthalocyanine (SnPc), and quinacridone.

[0423] Examples of p-type semiconductor materials include carbazole derivatives, thiophene derivatives, furan derivatives, compounds having an aromatic amine skeleton, etc. Examples of p-type semiconductor materials include naphthalene derivatives, anthracene derivatives, pyrene derivatives, triphenylene derivatives, fluorene derivatives, pyrrole derivatives, benzofuran derivatives, benzothiophene derivatives, indole derivatives, dibenzofuran derivatives, dibenzothiophene derivatives, indolocarbazole derivatives, porphyrin derivatives, phthalocyanine derivatives, naphthalocyanine derivatives, quinacridone derivatives, polyphenylenevinylene derivatives, polyparaphenylene derivatives, polyfluorene derivatives, polyvinylcarbazole derivatives, polythiophene derivatives, etc.

[0424] The HOMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the HOMO level of the electron-accepting organic semiconductor material, and the LUMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the LUMO level of the electron-accepting organic semiconductor material.

[0425] It is preferable to use a spherical fullerene as the electron-accepting organic semiconductor material and a planar organic semiconductor material as the electron-donating organic semiconductor material. Molecules with similar shapes tend to aggregate together, and when molecules of the same type aggregate, the energy levels of their molecular orbitals become close, which can improve carrier transport properties.

[0426] For example, the active layer 373 is preferably formed by co-evaporating an n-type semiconductor and a p-type semiconductor, or alternatively, the active layer 373 may be formed by laminating an n-type semiconductor and a p-type semiconductor.

[0427] The light-emitting element and the light-receiving element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting element and the light-receiving element can be formed by a method such as vapor deposition (including vacuum vapor deposition), a transfer method, a printing method, an inkjet method, or a coating method.

[0428] For example, polymer compounds such as poly(3,4-ethylenedioxythiophene) / poly(styrenesulfonic acid) (PEDOT / PSS) and inorganic compounds such as molybdenum oxide and copper iodide (CuI) can be used as hole-transporting materials, and inorganic compounds such as zinc oxide (ZnO) can be used as electron-transporting materials.

[0429] Furthermore, a polymer compound such as Poly[[4,8-bis[5-(2-ethylhexyl)-2-thienyl]benzo[1,2-b:4,5-b']dithiophene-2,6-diyl]-2,5-thiophenediyl[5,7-bis(2-ethylhexyl)-4,8-dioxo-4H,8H-benzo[1,2-c:4,5-c']dithiophene-1,3-diyl]]polymer (abbreviated as PBDB-T) or a PBDB-T derivative, which functions as a donor, can be used for the active layer 373. For example, a method of dispersing an acceptor material in PBDB-T or a PBDB-T derivative can be used.

[0430] Furthermore, three or more types of materials may be mixed in the active layer 373. For example, in order to expand the wavelength range, a third material may be mixed in addition to an n-type semiconductor material and a p-type semiconductor material. In this case, the third material may be a low-molecular-weight compound or a high-molecular-weight compound.

[0431] Display device 380B shown in FIG. 26B differs from display device 380A in that light receiving element 370PD and light emitting element 370R have the same configuration.

[0432] The light receiving element 370PD and the light emitting element 370R have the active layer 373 and the light emitting layer 383R in common.

[0433] Here, it is preferable that light receiving element 370PD has the same configuration as a light emitting element that emits light of a longer wavelength than the light to be detected. For example, light receiving element 370PD configured to detect blue light can have the same configuration as one or both of light emitting element 370R and light emitting element 370G. For example, light receiving element 370PD configured to detect green light can have the same configuration as light emitting element 370R.

[0434] By using a common structure for the light-receiving element 370PD and the light-emitting element 370R, the number of film-forming steps and the number of masks can be reduced compared to a structure in which the light-receiving element 370PD and the light-emitting element 370R have separate layers, thereby reducing the manufacturing steps and manufacturing costs of the display device.

[0435] Furthermore, by using a common configuration for the light receiving element 370PD and the light emitting element 370R, the margin for misalignment can be narrowed compared to a configuration in which the light receiving element 370PD and the light emitting element 370R have separate layers. This allows for an increased pixel aperture ratio and improved light extraction efficiency of the display device. This also extends the life of the light emitting element. Furthermore, the display device can display high brightness. Furthermore, it also allows for higher resolution of the display device.

[0436] Light-emitting layer 383R includes a light-emitting material that emits red light. Active layer 373 includes an organic compound that absorbs light with a wavelength shorter than red (for example, one or both of green light and blue light). Active layer 373 preferably includes an organic compound that does not easily absorb red light and absorbs light with a wavelength shorter than red. This allows red light to be extracted efficiently from light-emitting element 370R, and light-receiving element 370PD to detect light with a wavelength shorter than red with high accuracy.

[0437] Furthermore, in the display device 380B, an example is shown in which the light emitting element 370R and the light receiving element 370PD have the same configuration, but the light emitting element 370R and the light receiving element 370PD may have optical adjustment layers of different thicknesses.

[0438] 27A and 27B includes a light receiving / emitting element 370SR that emits red (R) light and has a light receiving function, a light emitting element 370G, and a light emitting element 370B. The configuration of the light emitting element 370G and the light emitting element 370B can be based on the configuration of the display device 380A described above.

[0439] The light emitting / receiving element 370SR has, stacked in this order, a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, ​​an active layer 373, a light emitting layer 383R, an electron transport layer 384, an electron injection layer 385, and a common electrode 375. The light emitting / receiving element 370SR has the same configuration as the light emitting element 370R and the light receiving element 370PD exemplified in the display device 380B.

[0440] 27A shows a case where the light emitting / receiving element 370SR functions as a light emitting element. In FIG. 27A, an example is shown in which the light emitting element 370B emits blue light, the light emitting element 370G emits green light, and the light emitting / receiving element 370SR emits red light.

[0441] Fig. 27B shows a case where the light receiving / emitting element 370SR functions as a light receiving element. Fig. 27B shows an example where the light receiving / emitting element 370SR receives blue light emitted by the light emitting element 370B and green light emitted by the light emitting element 370G.

[0442] The light emitting element 370B, the light emitting element 370G, and the light emitting / receiving element 370SR each have a pixel electrode 371 and a common electrode 375. In this embodiment, a case will be described in which the pixel electrode 371 functions as an anode and the common electrode 375 functions as a cathode. The light emitting / receiving element 370SR is driven by applying a reverse bias between the pixel electrode 371 and the common electrode 375, so that the light emitting / receiving element 370SR can detect light incident on the light emitting / receiving element 370SR, generate electric charges, and extract the charges as a current.

[0443] The light emitting / receiving element 370SR can be said to have a configuration in which an active layer 373 is added to a light emitting element. In other words, the light emitting / receiving element 370SR can be formed in parallel with the formation of the light emitting element by simply adding a step of forming the active layer 373 to the manufacturing process of the light emitting element. Furthermore, the light emitting element and the light emitting / receiving element can be formed on the same substrate. Therefore, it is possible to provide the display unit with either or both of an imaging function and a sensing function without significantly increasing the manufacturing process.

[0444] There are no limitations on the stacking order of the light-emitting layer 383R and the active layer 373. Figures 27A and 27B show an example in which the active layer 373 is provided on the hole-transport layer 382, ​​and the light-emitting layer 383R is provided on the active layer 373. The stacking order of the light-emitting layer 383R and the active layer 373 may be reversed.

[0445] Furthermore, the light emitting / receiving element may not have at least one layer selected from the hole injection layer 381, the hole transport layer 382, ​​the electron transport layer 384, and the electron injection layer 385. The light emitting / receiving element may also have other functional layers such as a hole blocking layer and an electron blocking layer.

[0446] In the light emitting / receiving element, a conductive film that transmits visible light is used for the electrode on the light extraction side, and a conductive film that reflects visible light is preferably used for the electrode on the non-light extraction side.

[0447] The functions and materials of the layers constituting the light emitting / receiving element are similar to those of the layers constituting the light emitting element and the light receiving element, and therefore detailed description thereof will be omitted.

[0448] 27C to 27G show examples of the stacked structure of the light emitting and receiving element.

[0449] The light emitting / receiving element shown in FIG. 27C has a first electrode 377, a hole injection layer 381, a hole transport layer 382, ​​a light emitting layer 383R, an active layer 373, an electron transport layer 384, an electron injection layer 385, and a second electrode 378.

[0450] FIG. 27C shows an example in which a light-emitting layer 383R is provided on a hole-transporting layer 382, ​​and an active layer 373 is laminated on the light-emitting layer 383R.

[0451] As shown in FIGS. 27A to 27C, the active layer 373 and the light emitting layer 383R may be in contact with each other.

[0452] A buffer layer is preferably provided between the active layer 373 and the light-emitting layer 383R. In this case, the buffer layer preferably has hole-transporting and electron-transporting properties. For example, a bipolar substance is preferably used for the buffer layer. Alternatively, the buffer layer may be at least one layer selected from a hole-injection layer, a hole-transporting layer, an electron-transporting layer, an electron-injection layer, a hole-blocking layer, and an electron-blocking layer. FIG. 27D shows an example in which a hole-transporting layer 382 is used as the buffer layer.

[0453] By providing a buffer layer between the active layer 373 and the light-emitting layer 383R, it is possible to suppress the transfer of excitation energy from the light-emitting layer 383R to the active layer 373. In addition, the buffer layer can be used to adjust the optical path length (cavity length) of the microcavity structure. Therefore, a light-emitting / receiving element having a buffer layer between the active layer 373 and the light-emitting layer 383R can obtain high light-emitting efficiency.

[0454] FIG. 27E shows an example of a laminated structure in which a hole transport layer 382-1, an active layer 373, a hole transport layer 382-2, and an emitting layer 383R are laminated in this order on a hole injection layer 381. The hole transport layer 382-2 functions as a buffer layer. The hole transport layer 382-1 and the hole transport layer 382-2 may contain the same material or different materials. Alternatively, a layer that can be used as the buffer layer described above may be used instead of the hole transport layer 382-2. Alternatively, the positions of the active layer 373 and the emitting layer 383R may be interchanged.

[0455] 27F differs from the light emitting / receiving element shown in Fig. 27A in that it does not have the hole transport layer 382. In this way, the light emitting / receiving element may not have at least one layer among the hole injection layer 381, the hole transport layer 382, ​​the electron transport layer 384, and the electron injection layer 385. The light emitting / receiving element may also have other functional layers such as a hole blocking layer or an electron blocking layer.

[0456] The light emitting / receiving device shown in FIG. 27G differs from the light emitting / receiving device shown in FIG. 27A in that it does not have an active layer 373 and a light emitting layer 383R, but has a layer 389 that serves as both a light emitting layer and an active layer.

[0457] The layer that serves as both the light-emitting layer and the active layer can be, for example, a layer containing three materials: an n-type semiconductor that can be used for the active layer 373, a p-type semiconductor that can be used for the active layer 373, and a light-emitting substance that can be used for the light-emitting layer 383R.

[0458] It is preferable that the lowest energy absorption band in the absorption spectrum of the mixed material of n-type and p-type semiconductors does not overlap with the maximum peak in the emission spectrum (PL spectrum) of the luminescent substance, and it is more preferable that they are sufficiently separated from each other.

[0459] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0460] <Example of cross-sectional view configuration> 28 is a cross-sectional view showing a configuration example of the display device 10. The display device 10 has a configuration in which a transistor 310 having a channel formed in a substrate 301 and a transistor 320 having a channel formed in a semiconductor layer containing a metal oxide are stacked.

[0461] An insulating layer 261 is provided to cover the transistor 310, and a conductive layer 251 is provided over the insulating layer 261. An insulating layer 262 is provided to cover the conductive layer 251, and a conductive layer 252 is provided over the insulating layer 262. The conductive layers 251 and 252 each function as wirings. An insulating layer 263 and an insulating layer 332 are provided to cover the conductive layer 252, and a transistor 320 is provided over the insulating layer 332. An insulating layer 265 is provided to cover the transistor 320, and a capacitor 240 is provided over the insulating layer 265. The capacitor 240 and the transistor 320 are electrically connected by a plug 274.

[0462] The transistor 320 can be used as a transistor that forms a pixel circuit or a transistor that forms a memory cell. The transistor 310 can be used as a transistor that forms a memory cell, a transistor that forms a driver circuit for driving the pixel circuit, or a transistor that forms an arithmetic circuit. The transistors 310 and 320 can be used as transistors that form various circuits such as an arithmetic circuit or a memory circuit.

[0463] The transistor 310 has a channel formation region in a substrate 301. The substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as one of a source and a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311 and functions as an insulating layer.

[0464] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0465] The transistor 320 is a transistor in which a metal oxide (also referred to as an oxide semiconductor) is used for a semiconductor layer in which a channel is formed.

[0466] The transistor 320 includes a semiconductor layer 321 , an insulating layer 323 , a conductive layer 324 , a pair of conductive layers 325 , an insulating layer 326 , and a conductive layer 327 .

[0467] The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 301 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 321 toward the insulating layer 332. The insulating layer 332 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0468] A conductive layer 327 is provided over the insulating layer 332, and an insulating layer 326 is provided to cover the conductive layer 327. The conductive layer 327 functions as a first gate electrode of the transistor 320, and part of the insulating layer 326 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 326 that is in contact with the semiconductor layer 321. The top surface of the insulating layer 326 is preferably planarized.

[0469] The semiconductor layer 321 is provided over the insulating layer 326. The semiconductor layer 321 preferably includes a metal oxide (also referred to as an oxide semiconductor) film having semiconductor properties. The semiconductor layer 321 preferably includes a metal oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc. An OS transistor using such a metal oxide for a channel formation region has a characteristic of extremely low off-state current. Therefore, it is preferable to use an OS transistor as a transistor provided in a pixel circuit because analog data written to the pixel circuit can be retained for a long period of time. Similarly, it is preferable to use an OS transistor as a transistor used in a memory cell because analog data written to the memory cell can be retained for a long period of time.

[0470] A pair of conductive layers 325 is provided over and in contact with the semiconductor layer 321 and functions as a source electrode and a drain electrode.

[0471] An insulating layer 328 is provided to cover top surfaces and side surfaces of the pair of conductive layers 325 and side surfaces of the semiconductor layer 321, and an insulating layer 264 is provided over the insulating layer 328. The insulating layer 328 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 264 or the like to the semiconductor layer 321 and prevents oxygen from being released from the semiconductor layer 321. The insulating layer 328 can be formed using an insulating film similar to the insulating layer 332.

[0472] An opening is provided in the insulating layer 328 and the insulating layer 264, reaching the semiconductor layer 321. An insulating layer 323 and a conductive layer 324 are buried inside the opening and are in contact with the side surfaces of the insulating layer 264, the insulating layer 328, and the conductive layer 325, as well as the top surface of the semiconductor layer 321. The conductive layer 324 functions as a second gate electrode, and the insulating layer 323 functions as a second gate insulating layer.

[0473] The upper surfaces of the conductive layer 324, the insulating layer 323, and the insulating layer 264 are planarized so that their heights are approximately the same, and insulating layers 329 and 265 are provided to cover them.

[0474] The insulating layer 264 and the insulating layer 265 function as interlayer insulating layers. The insulating layer 329 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 265 or the like to the transistor 320. The insulating layer 329 can be formed using an insulating film similar to the insulating layer 328 and the insulating layer 332.

[0475] A plug 274 electrically connected to one of the pair of conductive layers 325 is provided so as to be embedded in the insulating layer 265 , the insulating layer 329 , and the insulating layer 264 .

[0476] Capacitor 240 has conductive layer 241, conductive layer 245, and insulating layer 243 positioned therebetween. Conductive layer 241 functions as one electrode of capacitor 240, conductive layer 245 functions as the other electrode of capacitor 240, and insulating layer 243 functions as a dielectric of capacitor 240.

[0477] The conductive layer 241 is provided over the insulating layer 261 and is buried in the insulating layer 254. The conductive layer 241 is electrically connected to one of the source and drain of the transistor 310 by a plug 271 buried in the insulating layer 261. The insulating layer 243 is provided to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping with the conductive layer 241 with the insulating layer 243 interposed therebetween.

[0478] An insulating layer 255 is provided to cover the capacitor 240, and a light emitting element 61, a light receiving element 62, and the like are provided on the insulating layer 255. A protective layer 91 is provided on the light emitting element 61 and the light receiving element 62, and a substrate 420 is bonded to the upper surface of the protective layer 91 by a resin layer 419. The substrate 420 can be a light-transmitting substrate.

[0479] The pixel electrode 84 of the light-emitting element 61 and the pixel electrode 84PD of the light-receiving element 62 are electrically connected to either the source or drain of the transistor 310 by a plug 256 embedded in the insulating layer 255, a conductive layer 241 embedded in the insulating layer 254, and a plug 271 embedded in the insulating layer 261.

[0480] By using this configuration, it is possible to arrange the OS transistors that make up the pixel circuits and cells directly below the light-receiving elements and light-emitting elements, and it is also possible to arrange driving circuits, arithmetic circuits, etc., making it possible to miniaturize a display device with high performance.

[0481] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0482] (Embodiment 5) In one embodiment of the present invention, an electronic device to which the display device of one embodiment of the present invention can be applied is described. The electronic device according to one embodiment of the present invention can also be suitably used as a wearable electronic device for VR and AR applications.

[0483] Fig. 29A is a perspective view of a goggle-type electronic device 100, which is an example of a wearable electronic device. The electronic device 100 shown in Fig. 29A illustrates a state in which a pair of display devices 10_L and 10_R are provided in a housing 101. The housing 101 is equipped with an acceleration sensor such as a gyro sensor, which can detect the orientation of the user's head and display an image according to that orientation.

[0484] In this specification and the like, when describing matters common to the display devices 10_L and 10_R, or when there is no need to distinguish between them, the display device 10 may simply be referred to as "display device 10." The display device 10 described in the above embodiment is applicable to the display devices 10_L and 10_R illustrated in FIG. 29A.

[0485] As described in the above embodiment 4, the display device 10 of one embodiment of the present invention can have a stacked structure of a light-emitting element, a pixel circuit, and a driver circuit, thereby enabling an extremely high pixel aperture ratio (effective display area ratio). Furthermore, the pixel circuits can be arranged at extremely high density, enabling extremely high pixel resolution. Because of its extremely high resolution, the display device 10 can be suitably used for VR devices such as head-mounted displays or glasses-type AR devices. For example, even in a configuration in which the display portion of the display device 10 is viewed through an optical component such as a lens, the display device 10 has an extremely high-resolution display portion, and therefore, pixels are not visible even when the display portion is enlarged by the lens, enabling highly immersive display.

[0486] As described in the above embodiment 4, the display device 10 of one embodiment of the present invention can have a stacked structure of a light-receiving element, a cell array, and an arithmetic circuit. Therefore, the display device 10 can perform arithmetic processing with high computational efficiency using a minute current output from the light-receiving element as input data. Furthermore, the display device 10 can be configured such that the light-receiving element is located close to the display unit. This allows the user to view an image with their eyes, and captures an image of the user's eyes and / or their surroundings. Therefore, the display device 10 can be configured to perform inference processing based on a neural network using image data as input data. Furthermore, the cells of the cell array can retain analog data written in response to a minute current for a long period of time. Furthermore, the arithmetic circuit that performs product-sum calculations using a minute current can perform computation with high computational efficiency.

[0487] FIG. 29B is a perspective view showing the back, bottom, and right side of the electronic device 100 described in FIG. 29A.

[0488] 29B, the housing 101 of the electronic device 100 includes, as an example, a mounting portion 106, a buffer member 107, and a pair of lenses 108 in addition to the pair of display devices 10_L and 10_R. The display units 13 of the pair of display devices 10_L and 10_R are each provided at a position inside the housing 101 where they can be viewed through the lenses 108.

[0489] The light receiving units 14 of the pair of display devices 10_L and 10_R are provided at positions where they can acquire information about the user's eyes and their surroundings. The acquisition of information about the user's eyes and their surroundings by the light receiving units 14 may be performed through a lens 108 inside the housing 101 or may be performed without using the lens 108.

[0490] 29B is provided with an input terminal 109 and an output terminal 110. A cable can be connected to input terminal 109 for supplying an image signal (image data) from a video output device or the like, or for supplying power for charging a battery provided within housing 101. Output terminal 110 functions as, for example, an audio output terminal, and can be connected to earphones, headphones, or the like.

[0491] Furthermore, the housing 101 preferably has a mechanism for adjusting the left-right positions of the lens 108 and the display devices 10_L and 10_R so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that the housing 101 has a mechanism for adjusting the focus by changing the distance between the lens 108 and the display devices 10_L and 10_R.

[0492] The cushioning member 107 is a portion that comes into contact with the user's face (forehead, cheeks, etc.). The cushioning member 107 makes close contact with the user's face, thereby preventing light leakage and enhancing the sense of immersion. It is preferable to use a soft material for the cushioning member 107 so that it can come into close contact with the user's face when the user wears the electronic device 100. Using such a material is preferable because it feels good on the skin and does not make the user feel cold when worn in cold seasons, etc. It is preferable to make the components that come into contact with the user's skin, such as the cushioning member 107 or the wearing part 106, removable, as this makes cleaning or replacement easier.

[0493] The electronic device according to one embodiment of the present invention may further include earphones 106A. The earphones 106A have a communication unit (not shown) and have a wireless communication function. The earphones 106A can output audio data using the wireless communication function. The earphones 106A may have a vibration mechanism in order to function as bone conduction earphones. The earphones 106A may be connected to the wearing unit 106 directly or via a wire.

[0494] 30A is a perspective view of a glasses-type electronic device 100A, which is another example of a wearable electronic device. The electronic device 100A shown in FIG. 30A includes a pair of display devices 10_L and 10_R in a housing 101.

[0495] The electronic device 100A can project an image displayed on the display unit 13 of the display devices 10_L and 10_R onto a display area 104 of the optical member 103. Furthermore, because the optical member 103 is translucent, the user can see the image displayed in the display area 104 superimposed on a transmitted image visually recognized through the optical member 103. Therefore, the electronic device 100A is an electronic device capable of AR display.

[0496] Furthermore, although not shown, the housing 101 is provided with a connector to which a wireless receiver or a cable can be connected, and a video signal or the like can be supplied to the housing 101. Furthermore, by providing the housing 101 with an acceleration sensor such as a gyro sensor, the direction of the user's head can be detected and an image corresponding to that direction can be displayed in the display area 104.

[0497] Next, a method for projecting an image onto display area 104 of electronic device 100A will be described with reference to Fig. 30B. Display device 10, lens 111, and reflector 112 are provided inside housing 101. In addition, a portion of optical member 103 corresponding to display area 104 has reflecting surface 113 that functions as a half mirror.

[0498] Light 115 emitted from display device 10 passes through lens 111 and is reflected by reflector 112 toward optical member 103. Inside optical member 103, light 115 is repeatedly totally reflected at the end surface of optical member 103 and reaches reflecting surface 113, whereby an image is projected onto reflecting surface 113. This allows the user to view both light 115 reflected by reflecting surface 113 and transmitted light 116 that has passed through optical member 103 (including reflecting surface 113).

[0499] 30B shows an example in which the reflector 112 and the reflecting surface 113 each have a curved surface. This allows for greater freedom in optical design and allows for a thinner optical member 103 than when these surfaces are flat. Note that the reflector 112 and the reflecting surface 113 may also be flat.

[0500] A member having a mirror surface, preferably one with high reflectivity, can be used as the reflector 112. Furthermore, a half mirror utilizing reflection from a metal film may be used as the reflecting surface 113, but the transmittance of the transmitted light 116 can be increased by using a prism or the like utilizing total reflection.

[0501] Here, it is preferable that the housing 101 has a mechanism for adjusting the distance between the lens 111 and the display device 10 or the angle therebetween. This makes it possible to adjust the focus, enlarge or reduce the image, etc. For example, the lens 111 or the display device 10, or both, may be configured to be movable in the direction of the optical axis.

[0502] Furthermore, it is preferable that the housing 101 has a mechanism that can adjust the angle of the reflector 112. By changing the angle of the reflector 112, it is possible to change the position of the display area 104 where an image is displayed. This makes it possible to position the display area 104 in an optimal position according to the position of the user's eyes.

[0503] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0504] <Additional notes regarding the present specification etc.> The above-described embodiments and the respective components in the embodiments will be described below with additional notes.

[0505] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0506] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or with the content (or even a part of the content) described in one or more other embodiments.

[0507] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0508] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0509] In addition, in the block diagrams in this specification, components are classified by function and shown as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where a single circuit is involved in multiple functions, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0510] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0511] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0512] Furthermore, in this specification and the like, terms such as "electrode" or "wiring" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0513] Furthermore, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0514] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0515] In this specification, a switch refers to a device that has the function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has the function of selecting and switching a path for a current to flow.

[0516] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0517] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0518] In this specification, "A and B are connected" includes not only a direct connection between A and B, but also an electrical connection between A and B. Here, "A and B are electrically connected" means that when an object having some kind of electrical effect exists between A and B, it enables the exchange of electrical signals between A and B.

[0519] In this specification, etc., a device fabricated using a metal mask or FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or FMM may be referred to as a device with an MML (metal maskless) structure.

[0520] In this specification, a structure in which different light-emitting layers are created for each color light-emitting element (here, blue (B), green (G), and red (R)), or in which the light-emitting layers are painted differently, may be referred to as an SBS (Side By Side) structure. In this specification, a light-emitting element that can emit white light may be referred to as a white light-emitting element. In addition, a white light-emitting element can be combined with a colored layer (for example, a color filter) to form a light-emitting element that displays full color.

[0521] Furthermore, light-emitting elements can be broadly classified into a single structure and a tandem structure. A single-structure element has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, two or more light-emitting layers may be selected so that the light emitted from each of the two or more light-emitting layers has a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration that emits white light from the entire light-emitting element can be obtained. The same applies to light-emitting elements having three or more light-emitting layers.

[0522] A tandem-structured element preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light, light from the light-emitting layers of the light-emitting units may be combined to obtain white light. The structure for obtaining white light is the same as that of the single-structure element. In a tandem-structured element, it is preferable to provide an intermediate layer such as a charge-generating layer between the light-emitting units.

[0523] Furthermore, when comparing the above-mentioned white light-emitting element (single structure or tandem structure) with a light-emitting element having an SBS structure, the light-emitting element having an SBS structure can reduce power consumption compared to the white light-emitting element. If you want to keep power consumption low, it is preferable to use a light-emitting element having an SBS structure. On the other hand, the manufacturing process of a white light-emitting element is simpler than that of a light-emitting element having an SBS structure, so it is preferable because it can reduce manufacturing costs or increase manufacturing yields. [Explanation of symbols]

[0524] CA: cell array, IM: cell, ITRZ: circuit, MAC: semiconductor device, WCS: circuit, WSD: circuit, XCLK: clock signal, XCS: circuit, XDATA: input data, XLAT: latch signal, XSP: start pulse, YCLK: clock signal, YDATA: output data, YLAT: latch signal, YSP: start pulse

Claims

[Claim 1] The artificial neural network includes a cell array that performs a first layer product-sum operation and a second layer product-sum operation, a first circuit that inputs first data to the cell array, and a second circuit that outputs second data from the cell array, The cell array has a plurality of cells, the cell array has a first region and a second region; In the first period, the first region receives the t-th (t is a natural number equal to or greater than 2) first data from the first circuit and outputs the t-th second data corresponding to the product-sum operation of the first layer to the second circuit; The second region receives the (t-1)th first data from the first circuit and outputs the (t-1)th second data corresponding to the product-sum operation of the second layer to the second circuit.

Images