Semiconductor device, method for manufacturing semiconductor device, and electronic device

Abstract

To achieve a high-performance semiconductor device.SOLUTION: A semiconductor device 1A includes a substrate 10 and a barrier layer 30A provided on a surface side 10a of the substrate. The barrier layer 30A has an opening 31A provided with a gate electrode 40. An Al-containing nitride semiconductor is used for the barrier layer 30A, an Al composition of the Al-containing nitride semiconductor decreasing from a substrate 10 side toward a surface 30a side. The barrier layer 30A includes a first layer 32 containing Al at a first concentration, and a second layer 33 provided between the substrate 10 and the first layer 32 and containing Al at a second concentration that is higher than the first concentration of the first layer 32. The first layer 32 has a first opening 32a forming a part of the opening 31A of the barrier layer 30A. The second layer 33 has a second opening 33a communicating with the first opening 32a and having an opening width smaller than that of the first opening, the second opening forming a part of the opening 31A of the barrier layer 30A. The opening 31A is provided with a slanted gate electrode 40 to suppress electric field concentration.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device. [Background technology]

[0002] For example, with regard to nitride semiconductor devices, a technology is known in which an aluminum-free nitride semiconductor layer is formed at a lower film formation temperature toward the surface side, and a recess having an inclined sidewall with a wider opening width toward the surface side is formed in the nitride semiconductor layer by etching (Patent Document 1).

[0003] Furthermore, with regard to a field effect compound semiconductor device, a technology is known in which a multilayer structure film having two or more layers with different compositions or densities is formed as an insulating film, and a gate opening including a step corresponding to the number of layers in the multilayer structure film is formed in the insulating film by etching (Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-164437 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-72962 Summary of the Invention [Problem to be solved by the invention]

[0005] In semiconductor devices, performance degradation of the semiconductor device may be caused by phenomena resulting from the configuration of the region in which the electrode is provided, such as electric field concentration at the edge of the gate electrode on the drain electrode side when a high voltage is applied to the drain electrode.

[0006] In one aspect, the present invention aims to realize a high-performance semiconductor device. [Means for solving the problem]

[0007] In one aspect, a semiconductor device is provided, including a substrate; a first layer provided on a first surface of the substrate, containing a first element at a first concentration, and having a first opening; and a second layer provided between the first surface of the substrate and the first layer, containing the first element at a second concentration different from the first concentration, and having a second opening that communicates with the first opening of the first layer and has an opening width smaller than that of the first opening.

[0008] In another aspect, there are provided a method for manufacturing the semiconductor device as described above, and an electronic device including the semiconductor device as described above. [Effects of the Invention]

[0009] In one aspect, it becomes possible to realize a high-performance semiconductor device. [Brief explanation of the drawings]

[0010] [Figure 1] 1A to 1C are diagrams illustrating a first example of a semiconductor device according to a first embodiment. [Figure 2] 2A to 2C are diagrams illustrating a barrier layer of the semiconductor device according to the first embodiment. [Figure 3] 1A to 1C are diagrams (part 1) illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] 1A to 1C are diagrams (part 2) illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] 5A to 5C are diagrams illustrating a second example of the semiconductor device according to the first embodiment. [Figure 6] 10A and 10B are diagrams illustrating an example of a simulation result of an electric field strength distribution in a semiconductor device. [Figure 7] 10A to 10C are diagrams illustrating a third example of the semiconductor device according to the first embodiment. [Figure 8] 5A to 5C are diagrams illustrating another example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 1 is a diagram (part 1) for explaining the electric field strength distribution of various semiconductor devices. [Figure 10] FIG. 10 is a diagram (part 2) for explaining the electric field strength distribution of various semiconductor devices. [Figure 11] 10A and 10B are diagrams illustrating an example of a barrier layer of a semiconductor device according to a second embodiment. [Figure 12] 10A to 10C are diagrams (part 1) illustrating an example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 13] 10A and 10B are diagrams (part 2) illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 14] 10A to 10C are diagrams illustrating an example of a semiconductor package according to a third embodiment. [Figure 15] FIG. 10 is a diagram illustrating an example of a power factor correction circuit according to a fourth embodiment. [Figure 16] FIG. 10 is a diagram illustrating an example of a power supply device according to a fifth embodiment. [Figure 17] FIG. 13 is a diagram illustrating an example of an amplifier according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] [First embodiment] First, a first example of the semiconductor device according to the first embodiment will be described. 1A and 1B are diagrams illustrating a first example of a semiconductor device according to a first embodiment. Fig. 1A is a schematic cross-sectional view of a main part of the example of the semiconductor device. Fig. 1B is an enlarged view of part P in Fig. 1A and shows an example of the relationship between the thickness of the barrier layer and the Al composition.

[0012] 1A and 1B, a semiconductor device 1A is an example of a semiconductor device including a high electron mobility transistor (HEMT). The semiconductor device 1A includes a substrate 10, an insulating film 20, a barrier layer 30A, a gate electrode 40, a source electrode 50, and a drain electrode 60.

[0013] The substrate 10 includes an electron transit layer 11 and an electron supply layer 12 . A nitride semiconductor, for example, gallium nitride (GaN), which is a nitride of gallium (Ga), is used for the electron transit layer 11. In addition to GaN, nitride semiconductors such as aluminum gallium nitride (AlGaN) and indium gallium nitride (InGaN) may also be used for the electron transit layer 11.

[0014] AlGaN is GaN in which a portion of the Ga atoms is replaced with aluminum (Al), and can be considered an Al-containing Ga nitride. InGaN is GaN in which a portion of the Ga atoms is replaced with indium (In), and can be considered an In-containing Ga nitride.

[0015] The electron transit layer 11 is formed on a predetermined base substrate (not shown) by, for example, metal organic chemical vapor deposition (MOCVD) or metal organic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), etc. The base substrate on which the electron transit layer 11 is formed may be made of various materials such as silicon carbide (SiC), GaN, silicon (Si), sapphire, diamond, etc.

[0016] The electron supply layer 12 includes a nitride semiconductor such as AlGaN. In addition to AlGaN, the electron supply layer 12 may include nitride semiconductors such as indium aluminum gallium nitride (InAlGaN) and indium aluminum nitride (InAlN).

[0017] InAlGaN is GaN in which part of the Ga is substituted with In and Al, and can be said to be a nitride of Ga containing In and Al. Also, InAlN is AlN in which part of the Al is substituted with In, and can be said to be a nitride of Al containing In.

[0018] The electron supply layer 12 is provided on one surface, for example, the group III polar surface side, of the electron transit layer 11. The electron supply layer 12 is formed on the one surface of the electron transit layer 11 by MOCVD or the like.

[0019] Here, the electron transit layer 11 and the electron supply layer 12 are made of nitride semiconductors with different band gaps. The electron supply layer 12 is made of a nitride semiconductor with a larger band gap than the electron transit layer 11. A two-dimensional electron gas (2DEG) region 70 is generated in the electron transit layer 11 due to spontaneous polarization of the nitride semiconductor of the electron supply layer 12 and piezoelectric polarization generated in the electron supply layer 12 due to strain caused by the difference in lattice constant between the nitride semiconductor of the electron transit layer 11 and the electron supply layer 12. The electron transit layer 11 and the electron supply layer 12 are made of nitride semiconductors in such a combination that the 2DEG region 70 is generated in the electron transit layer 11.

[0020] Although not shown, a layer such as AlN may be provided as an initial layer between the electron transit layer 11 and the underlying substrate on which it is formed, a layer such as AlGaN may be provided as a buffer layer, or a layer such as GaN doped with iron (Fe) may be provided. In addition, a layer such as AlN or AlGaN may be provided as a back barrier layer between the electron transit layer 11 and the underlying substrate to achieve a quantum confinement structure. A layer such as AlGaN or InGaN may be provided as a spacer layer between the electron transit layer 11 and the electron supply layer 12. A layer such as GaN may be provided as a cap layer on the side of the electron supply layer 12 opposite the electron transit layer 11. The substrate 10 of the semiconductor device 1A may include one or more of the initial layer, buffer layer, spacer layer, back barrier layer, cap layer, etc., in addition to the electron transit layer 11 and the electron supply layer 12.

[0021] 1A and 1B, the insulating film 20 is provided on one surface 10a of the substrate 10. The surface 10a of the substrate 10 is also referred to as the "first surface." In the example of FIGS. 1A and 1B, the surface 10a of the substrate 10 is the surface of the electron supply layer 12 opposite to the electron transit layer 11.

[0022] Various insulating materials are used for the insulating film 20. As an example, the insulating film 20 includes silicon nitride (SiN). In this case, the SiN of the insulating film 20 may contain elements such as hydrogen (H). For example, the SiN of the insulating film 20 may be amorphous SiN (also called "a-SiN") containing H at a concentration of 0.6×10 22 / cm 3 The following a-SiN is used.

[0023] The insulating film 20 containing a-SiN containing H is formed on the surface 10a side of the substrate 10 by using a low pressure chemical vapor deposition (LPCVD) method, an MOCVD method, or the like. The thickness of the insulating film 20 is set to, for example, 5 nm or less. The density of the insulating film 20 is set to, for example, 2.8 g / cm 3 It is set to the above.

[0024] The insulating film 20 is provided between the substrate 10 and the gate electrode 40 and functions as a gate insulating film. The insulating film 20 also functions as an etching stopper when forming, by etching, an opening 31A in the barrier layer 30A where the gate electrode 40 is to be provided.

[0025] 1(A) and 1(B), the barrier layer 30A is provided on the surface 20a of the insulating film 20, opposite to the substrate 10 side. The barrier layer 30A provided on the surface 20a side of the insulating film 20 can also be said to be the barrier layer 30A provided on the surface 10a side of the substrate 10. Hereinafter, the insulating film 20 side or the surface 20a side of the insulating film 20 will also be referred to as the substrate 10 side or the surface 10a side of the substrate 10.

[0026] The barrier layer 30A has an opening 31A extending from a surface 30a opposite to the insulating film 20 (or the substrate 10) to the insulating film 20. The opening 31A has a shape in which the opening width decreases from the surface 30a toward the insulating film 20. The insulating film 20 functions as an etching stopper when forming the opening 31A by etching.

[0027] The barrier layer 30A is made of a nitride semiconductor, for example, a nitride semiconductor containing Al (Al-containing nitride semiconductor). The Al contained in the barrier layer 30A is also referred to as the "first element." The barrier layer 30A is made of an amorphous nitride semiconductor. As shown in FIG. 1B, the barrier layer 30A is made of a nitride semiconductor having a gradient Al composition, in which the Al composition decreases from the insulating film 20 side (or the substrate 10 side) toward the surface 30a side. As an example, the barrier layer 30A is made of amorphous AlGaN (also referred to as "a-AlGaN") having a gradient Al composition, in which the Al composition decreases from the insulating film 20 side toward the surface 30a side. In addition to a-AlGaN, the barrier layer 30A may also be made of a nitride semiconductor having a gradient Al composition, such as amorphous InAlGaN or InAlN.

[0028] As will be described later, the opening 31A in the barrier layer 30A is formed by forming a through-hole by dry etching using a chlorine (Cl)-based gas, and then wet etching using potassium hydroxide (KOH).

[0029] Here, as described above, a nitride semiconductor such as a-AlGaN having a graded Al composition is used for the barrier layer 30A. When a nitride semiconductor having a graded Al composition is wet etched using KOH, the etching rate is faster in regions with a lower Al composition than in regions with a higher Al composition. Therefore, by using a nitride semiconductor having a graded Al composition in which the Al composition decreases toward the surface 30a for the barrier layer 30A, an opening 31A whose opening width decreases from the surface 30a toward the insulating film 20 is formed by wet etching using KOH.

[0030] As shown in FIGS. 1A and 1B, a gate electrode 40 is provided in an opening 31A in a barrier layer 30A. The gate electrode 40 can also be said to be provided on the surface 20a side of the insulating film 20 or the surface 10a side of the substrate 10. The opening 31A in the barrier layer 30A has a shape in which the opening width increases from the insulating film 20 side toward the surface 30a side. The gate electrode 40 provided in the opening 31A has a shape in which the width increases from the insulating film 20 side toward the surface 30a side. The gate electrode 40 can also be said to have a slant structure or a slant gate electrode structure. The gate electrode 40 may have a shape in which a portion is provided within the opening 31A and another portion is provided on the surface 30a.

[0031] The gate electrode 40 is made of a metal material. For example, the gate electrode 40 is made of a laminate having Ni (nickel) and gold (Au) provided thereon. The gate electrode 40 is formed by a deposition method or the like. The gate electrode 40 is provided on the surface 10a side of the substrate 10 via an insulating film 20 such as a-SiN. The insulating film 20 functions as a gate insulating film. The gate electrode 40 has a MIS (Metal Insulator Semiconductor) gate structure. The use of the MIS gate structure suppresses the occurrence of gate leakage current flowing from the gate electrode 40 to the substrate 10.

[0032] As shown in FIGS. 1A and 1B, a source electrode 50 and a drain electrode 60 are provided on both sides of the gate electrode 40 on the surface 10a side of the substrate 10. A metal material is used for the source electrode 50 and the drain electrode 60. For example, a laminate having tantalum (Ta) or titanium (Ti) and Al provided thereon is used for the source electrode 50 and the drain electrode 60. The source electrode 50 and the drain electrode 60 are formed using a vapor deposition method or the like.

[0033] The source electrode 50 and the drain electrode 60, for example, penetrate the barrier layer 30A and the insulating film 20 and are connected to the substrate 10. The source electrode 50 and the drain electrode 60 may, for example, be connected to the electron supply layer 12 of the substrate 10, or may penetrate the electron supply layer 12 and be connected to the electron transit layer 11. A contact layer (regrowth layer) using a nitride semiconductor such as n-type GaN or n-type AlGaN may be provided at the portion of the electron supply layer 12 or the electron transit layer 11 to which the source electrode 50 and the drain electrode 60 are connected.

[0034] In order to increase the breakdown voltage of the semiconductor device 1A, the gate electrode 40 may be disposed closer to the source electrode 50 than to the drain electrode 60, ie, in an asymmetrical arrangement. When the semiconductor device 1A having the above configuration is in operation, a predetermined voltage (potential difference) is applied between the source electrode 50 and the drain electrode 60, and a predetermined voltage (gate voltage) is applied to the gate electrode 40. The electric field effect caused by the voltage applied to the gate electrode 40 controls the amount of charge passing through the 2DEG region 70 immediately below the gate electrode 40 between the source electrode 50 and the drain electrode 60, thereby controlling the output drain current. In this way, the transistor function of the semiconductor device 1A is realized.

[0035] In the semiconductor device 1A, the gate electrode 40 is provided in an opening 31A in the barrier layer 30A, the opening width of which increases from the insulating film 20 side toward the surface 30a side. This results in the gate electrode 40 having a slanted structure in which the width increases from the insulating film 20 side toward the surface 30a side. The slanted gate electrode 40 has a shape in which a surface (also referred to as an "inclined surface") 45 that faces the surface 20a of the insulating film 20 (or the surface 10a of the substrate 10) via the barrier layer 30A, originating from a portion in contact with the insulating film 20, extends toward the drain electrode 60 while being spaced apart from the surface 20a (or the surface 10a). The shape of the gate electrode 40 or the opening 31A in which it is provided prevents a relatively high electric field from being concentrated near an edge 41 of the gate electrode 40 on the drain electrode 60 side (also referred to as a "drain-side edge") on the drain electrode 60 side during operation of the semiconductor device 1A.

[0036] Generally, a relatively high voltage is applied to the drain electrode side during operation of a semiconductor device. In this case, a phenomenon in which a relatively high electric field is concentrated near the drain-side edge of the gate electrode, known as electric field concentration, can occur. If the electric field concentration at the drain-side edge of the gate electrode exceeds the limit of the material in the vicinity, the semiconductor device may be destroyed.

[0037] In contrast, the semiconductor device 1A having the above configuration has a slanted gate electrode 40 whose width increases from the insulating film 20 side toward the surface 30a of the barrier layer 30A. This reduces electric field concentration near the drain-side edge 41 of the gate electrode 40. As a result, the material near the drain-side edge 41 is prevented from reaching a breakdown field, and breakdown of the semiconductor device 1A is prevented. This realizes a high-performance semiconductor device 1A in which performance degradation due to breakdown is suppressed.

[0038] In general, in a semiconductor device having a Schottky gate structure, when a forward bias (positive) gate voltage is applied during operation, a phenomenon called gate leakage current, in which current leaks from the gate electrode to the source electrode, may occur. When such a gate leakage current occurs in a semiconductor device, the maximum drain current may become smaller.

[0039] In contrast, in the semiconductor device 1A having the above configuration, an insulating film 20 such as a-SiN is interposed between the gate electrode 40 and the substrate 10. This suppresses the occurrence of gate leakage current during operation of the semiconductor device 1A, and also suppresses the decrease in maximum drain current caused by the gate leakage current. Therefore, a high-performance semiconductor device 1A in which performance degradation caused by the gate leakage current is suppressed is realized.

[0040] According to the above configuration, a high-performance semiconductor device 1A is realized in which performance degradation due to electric field concentration and gate leakage current is suppressed. Here, the barrier layer 30A will be further described.

[0041] In the above-described semiconductor device 1A, the barrier layer 30A can be considered to have the following configuration. 2 is a diagram illustrating the barrier layer of the semiconductor device according to the first embodiment, which is a schematic cross-sectional view of a main part near an opening in the barrier layer.

[0042] As described above, in the semiconductor device 1A, the insulating film 20 is provided on the surface 10a side of the substrate 10, and the barrier layer 30A is provided on the surface 20a side of the insulating film 20. The barrier layer 30A is provided to have a gradient Al composition, in which the Al composition decreases from the insulating film 20 side toward the surface 30a side. For example, the barrier layer 30A is an a-AlGaN layer having such a gradient Al composition. The barrier layer 30A having a gradient Al composition is formed by continuously or stepwise adjusting the supply amount of the Al source (e.g., trimethylaluminum) during growth of a-AlGaN or the like using the MOCVD method so that it decreases toward the surface 30a side.

[0043] The barrier layer 30A can also be considered to have a configuration in which multiple layers are stacked in the thickness direction. For ease of explanation, FIG. 2 illustrates the barrier layer 30A as having a configuration in which, from the surface 30a side, two layers, a first layer 32 and a second layer 33 made of a-AlGaN or the like, are stacked. That is, the first layer 32 and the second layer 33 are each a part of the barrier layer 30A. For example, the barrier layer 30A is formed such that the Al concentrations (amount of Al per unit volume) of the first layer 32 and the second layer 33 are higher in the first layer 32 than in the second layer 33.

[0044] Here, the Al composition of the first layer 32 and the second layer 33 may be set to be constant within each layer. Alternatively, the Al composition of the first layer 32 and the second layer 33 does not have to be constant within each layer, and may be set to have a gradient Al composition in which the Al composition decreases toward the surface 30a within each layer. By setting the Al composition of the first layer 32 and the second layer 33 in this manner, the Al concentration contained in each layer becomes lower in the order of the first layer 32 < the second layer 33.

[0045] The first layer 32 and the second layer 33 have a first opening 32a and a second opening 33a, respectively. The first opening 32a and the second opening 33a are in communication with each other. The first opening 32a and the second opening 33a are each part of the opening 31A of the barrier layer 30A. The opening widths of the first opening 32a and the second opening 33a are in the order of first opening 32a > second opening 33a.

[0046] Here, the Al composition of the barrier layer 30A decreases from the insulating film 20 side toward the face 30a side. Therefore, the etching rate during wet etching using KOH increases from the insulating film 20 side toward the face 30a side. Therefore, the opening widths of the first opening 32a and the second opening 33a formed by wet etching using KOH are in the order of first opening 32a > second opening 33a.

[0047] From this perspective, the barrier layer 30A can be considered to have a configuration including a first layer 32 and a second layer 33 containing the first element Al at different concentrations. Here, the first layer 32 is a layer provided on the surface 10a side of the substrate 10, containing a first concentration of Al, and having a first opening 32a. The second layer 33 is provided between the surface 10a of the substrate 10 and the first layer 32, containing a second concentration of Al higher than the first concentration, and having a second opening 33a that communicates with the first opening 32a of the first layer 32 and has a smaller opening width than the first opening 32a.

[0048] The second layer 33 before the second opening 33a is formed is also referred to as the "third layer," and the first layer 32 before the first opening 32a is formed is also referred to as the "fourth layer." By wet etching using KOH, the first opening is formed in the fourth layer to form the first layer, and the second opening is formed in the third layer to form the second layer.

[0049] 2, for convenience, the barrier layer 30A is described as including two layers, the first layer 32 and the second layer 33. However, the number of layers included in the barrier layer 30A is not limited to two, and may be three or more. Even when the barrier layer 30A includes three or more layers, any two of the layers can be considered to have the same relationship as the first layer 32 and the second layer 33 described above.

[0050] Next, an example of a method for manufacturing the semiconductor device 1A described above will be described. 3 and 4 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 3(A) and 3(B) and Figures 4(A) and 4(B) each show a schematic cross-sectional view of a main part of an example of a manufacturing process of a semiconductor device.

[0051] First, a structure as shown in FIG. 3(A) is formed, that is, a structure in which a barrier layer 30A is formed on a substrate 10 via an insulating film 20. The substrate 10 is formed by growing the electron transit layer 11, the electron supply layer 12, and the like on a predetermined base substrate (not shown) using a method such as MOCVD. For example, GaN is formed as the electron transit layer 11, and AlGaN is formed as the electron supply layer 12. The thickness of the electron transit layer 11 is set to be in the range of 100 nm to 200 nm, for example. The thickness of the electron supply layer 12 is set to be in the range of 5 nm to 30 nm, for example. Note that the substrate 10 can also be obtained by forming one or more of the following layers, such as an initial layer, a buffer layer, a spacer layer, a back barrier layer, and a cap layer, in addition to the electron transit layer 11 and the electron supply layer 12, using predetermined nitride semiconductors.

[0052] An insulating film 20 is formed on the surface 10a of the substrate 10 by using LPCVD, MOCVD, or the like. For example, a-SiN is formed as the insulating film 20. When forming a-SiN by LPCVD or MOCVD, the formation temperature is set to, for example, a range of 780°C to 850°C. As a result, the insulating film 20 is a-SiN containing H, and the concentration of H contained therein is 0.6×10 22 / cm 3and density is 2.8 g / cm 3 The a-SiN having the above structure is formed. The etching rate of such a-SiN with a Cl-based gas is about 1 / 10 of the etching rate of a-AlGaN of the barrier layer 30A formed as described below with a Cl-based gas. The thickness of the insulating film 20 is set to 5 nm or less, for example, in the range of 4 nm to 5 nm.

[0053] A barrier layer 30A is formed on the surface 20a of the insulating film 20 by MOCVD or the like. For example, a-AlGaN having a gradient Al composition, in which the Al composition decreases from the insulating film 20 side (substrate 10 side) toward the surface 30a side of the barrier layer 30A, is formed as the barrier layer 30A. The a-AlGaN having a gradient Al composition is formed by continuously or stepwise adjusting the supply amount of Al source (e.g., trimethylaluminum) during growth so that it decreases toward the surface 30a side of the barrier layer 30A. The thickness of the barrier layer 30A is set to, for example, a range of 10 nm to 100 nm.

[0054] After forming a structure in which a barrier layer 30A is formed on the substrate 10 via an insulating film 20, as shown in FIG. 3B, a resist 80 having an opening 80a in a region where a gate electrode 40 is to be formed is formed on the barrier layer 30A. Using this resist 80 as a mask, the barrier layer 30A in the opening 80a is dry-etched using a Cl-based gas. As a result, as shown in FIG. 3B, a through-hole 31Aa is formed in the barrier layer 30A, reaching the insulating film 20. The insulating film 20 has a lower etching rate with a Cl-based gas than the barrier layer 30A. The insulating film 20 thus functions as an etching stopper when the through-hole 31Aa is formed in the barrier layer 30A by dry etching. After the through-hole 31Aa is formed, the resist 80 is removed.

[0055] After the through-hole 31Aa is formed in the barrier layer 30A, as shown in FIG. 4A, a resist 81 having an opening 81a is formed on the barrier layer 30A in a region encompassing the through-hole 31Aa and its periphery (the periphery on the side where the source electrode 50 and the drain electrode 60 are to be formed). Using the resist 81 as a mask, the barrier layer 30A at the opening 81a is wet-etched using KOH. This wet etching widens the opening width of the through-hole 31Aa in the barrier layer 30A. When wet-etching the barrier layer 30A with a gradient Al composition, the etching rate is faster in regions with a lower Al composition (Al concentration) than in regions with a higher Al composition. Therefore, as shown in FIG. 4A, in the barrier layer 30A with a gradient Al composition where the Al composition decreases toward the surface 30a, an opening 31A whose opening width decreases from the surface 30a toward the insulating film 20 is formed by wet-etching using KOH. After the opening 31A is formed, the resist 81 is removed.

[0056] 2. In this case, the portion of the barrier layer 30A before the wet etching, which is the second layer 33 before the second opening 33a is formed, can be referred to as the "third layer," and the portion of the first layer 32 before the first opening 32a is formed can be referred to as the "fourth layer."

[0057] After the opening 31A is formed in the barrier layer 30A, the gate electrode 40, the source electrode 50, and the drain electrode 60 are formed as shown in FIG. 4(B). For example, the barrier layer 30A and the insulating film 20 in the area where the source electrode 50 and the drain electrode 60 are to be formed are removed by etching, and a laminate of Ta or Ti and Al is deposited in that area using a vapor deposition method to form the source electrode 50 and the drain electrode 60.

[0058] Furthermore, a stack of Ni and Au is deposited by evaporation in the opening 31A of the barrier layer 30A to form the gate electrode 40. The opening 31A in the barrier layer 30A has a shape in which the opening width increases from the insulating film 20 side toward the surface 30a side. By forming the gate electrode 40 in such an opening 31A, the gate electrode 40 is formed with a slant structure in which the width increases from the insulating film 20 side toward the surface 30a side. That is, the gate electrode 40 is formed with a slant structure in which an inclined surface 45 of the gate electrode 40, which faces the surface 20a of the insulating film 20 across the barrier layer 30A, extends toward the source electrode 50 side and the drain electrode 60 side while being spaced away from the surface 20a.

[0059] For example, a semiconductor device 1A as shown in FIG. 4(B) is manufactured by the above steps. The source electrode 50 and the drain electrode 60 may be formed on the surface 10a of the substrate 10 after the substrate 10 is formed but before the insulating film 20 and the barrier layer 30A are formed. In this case, the insulating film 20 and the barrier layer 30A are formed on the surface 10a of the substrate 10 on which the source electrode 50 and the drain electrode 60 have been formed, according to the example of FIG. 3(A). At this time, the insulating film 20 and the barrier layer 30A may be formed so as to cover the source electrode 50 and the drain electrode 60 on the surface 10a of the substrate 10. Alternatively, the source electrode 50 and the drain electrode 60 may be formed after the substrate 10 and the insulating film 20 are formed but before the barrier layer 30A is formed. In this case, the source electrode 50 and the drain electrode 60 are formed on the surface 10a of the substrate 10 from which part of the insulating film 20 has been removed, and then the barrier layer 30A is formed according to the example of FIG. 3(A). At this time, the barrier layer 30A may be formed so as to cover the source electrode 50 and the drain electrode 60. Thereafter, the through-hole 31Aa is formed according to the example of Fig. 3(B), the opening 31A is formed according to the example of Fig. 4(A), and the gate electrode 40 is formed according to the example of Fig. 4(B). In this manner, the semiconductor device 1A may be manufactured.

[0060] One possible method for forming the slant gate electrode 40 is to carve and form a barrier layer formed on the insulating film 20 on the substrate 10 using a YAG (Yttrium Aluminum Garnet) laser or the like to form an opening whose width increases from the insulating film 20 side toward the surface of the barrier layer. However, this method requires a long time for carving using a YAG laser or the like, and can significantly reduce the productivity of semiconductor devices equipped with the slant gate electrode 40.

[0061] In contrast, in the manufacturing method of the semiconductor device 1A described above, a barrier layer having a gradient Al composition, in which the Al composition decreases from the insulating film 20 side toward the surface 30a side, is formed as the barrier layer 30A. Then, by utilizing the fact that the etching rate in regions with low Al composition (Al concentration) is faster than in regions with high Al composition (Al concentration) during wet etching using KOH, an opening 31A whose opening width decreases from the surface 30a side toward the insulating film 20 side is formed by wet etching. The insulating film 20 functions as an etching stopper during this wet etching and during the dry etching performed prior to it. A gate electrode 40 is formed in the opening 31A thus formed in the barrier layer 30A. The gate electrode 40 formed in the opening 31A has a slant structure.

[0062] The above-described method for manufacturing the semiconductor device 1A using etching makes it possible to efficiently produce the semiconductor device 1A that includes the slanted gate electrode 40 and that can suppress electric field concentration and resulting breakdown near the drain-side edge 41. Furthermore, the insulating film 20 used as an etching stopper can also be used as a gate insulating film. Therefore, the above-described method for manufacturing the semiconductor device 1A makes it possible to efficiently produce the semiconductor device 1A that can suppress the occurrence of gate leakage current and the resulting decrease in maximum drain current.

[0063] According to the above manufacturing method, it is possible to efficiently manufacture a high-performance semiconductor device 1A in which performance degradation due to electric field concentration and gate leakage current is suppressed. Next, a second example of the semiconductor device according to the first embodiment will be described.

[0064] 5A and 5B are diagrams illustrating a second example of the semiconductor device according to the first embodiment. Fig. 5A is a schematic cross-sectional view of a main part of the example of the semiconductor device. Fig. 5B is an enlarged view of part Q in Fig. 5A and shows an example of the relationship between the thickness of the barrier layer and the Al composition.

[0065] In the semiconductor device 1B shown in FIGS. 5(A) and 5(B), the gate electrode 40 has a portion 42 (also referred to as a "rising portion") that extends so as to rise from the surface 20a of the insulating film 20. The gate electrode 40 of the semiconductor device 1B has an inclined surface 45 that starts from the rising portion 42 and faces the surface 20a of the insulating film 20 (or the surface 10a of the substrate 10) with the barrier layer 30B interposed therebetween, and extends toward the source electrode 50 and the drain electrode 60 while being spaced apart from the surface 20a (or the surface 10a). The semiconductor device 1B differs from the semiconductor device 1A (FIGS. 1(A) and 1(B)) in that it has a gate electrode 40 having such a shape.

[0066] The semiconductor device 1B includes a barrier layer 30B having an opening 31B in which a gate electrode 40 having a shape as shown in FIGS. 5A and 5B is to be provided. The barrier layer 30B has a portion 36 in which a rising portion 42 of the gate electrode 40 is to be provided. The barrier layer 30B further has a portion 37 in which an inclined surface 45 of the gate electrode 40, which faces the surface 20a of the insulating film 20 via the barrier layer 30B, extends toward the source electrode 50 and the drain electrode 60 while being spaced apart from the surface 20a. As shown in FIG. 5B, a nitride semiconductor such as a-AlGaN is formed in the portion 36 so as to have a relatively high Al composition. Similar to the barrier layer 30A, a nitride semiconductor such as a-AlGaN is formed in the portion 37 so as to have a graded Al composition. That is, as shown in FIG. 5(B), the portion 37 is formed of a nitride semiconductor such as a-AlGaN so as to have a gradient Al composition in which the Al composition at the boundary with the rising portion 42 is at its maximum and decreases from the insulating film 20 side toward the surface 30a side.

[0067] The opening 31B in the barrier layer 30B is formed by dry etching followed by wet etching using KOH, as described above for forming the opening 31A in the barrier layer 30A (e.g., FIGS. 3B and 4A). In wet etching using KOH, the etching rate is faster in regions with a low Al composition (Al concentration) than in regions with a high Al concentration. Therefore, in the barrier layer 30B having the above-described Al composition, an opening whose width decreases from the surface 30a toward the insulating film 20 is formed in the portion 37. An opening whose width at the boundary with the portion 36 extends to the insulating film 20 is formed in the portion 36. By maintaining a relatively high Al composition at the boundary between the portions 36 and 37, the opening in the portion 36 is prevented from widening. This results in the formation of the opening 31B having the shape shown in FIGS. 5A and 5B.

[0068] In the semiconductor device 1B, the gate electrode 40 is formed in the opening 31B of the barrier layer 30B having the shape described above. As a result, the gate electrode 40 is formed, which has a rising portion 42 on the surface 20a of the insulating film 20 and extends from the rising portion 42 toward the source electrode 50 and the drain electrode 60 while being spaced apart from the surface 20a of the insulating film 20.

[0069] From the same perspective as described above with reference to FIG. 2, the barrier layer 30B of the semiconductor device 1B can be considered to have a configuration including at least a "first layer" and a "second layer" containing the first element Al at different concentrations. Here, the first layer is a layer provided on the surface 10a side of the substrate 10, containing a first concentration of Al, and having a "first opening." The second layer is provided between the surface 10a of the substrate 10 and the first layer, containing a second concentration of Al higher than the first concentration, and having a "second opening" that communicates with the first opening of the first layer and has a smaller opening width than the first opening. The second layer before the second opening is formed is the "third layer," and the first layer before the first opening is formed is the "fourth layer."

[0070] Next, the results of simulating the electric field intensity in the semiconductor device 1A described in the first example and the semiconductor device 1B described in the second example will be described. FIG. 6 is a diagram illustrating an example of a simulation result of the electric field intensity distribution in a semiconductor device.

[0071] 6 shows an example of a simulation result of the electric field strength distribution when the voltage (drain voltage) Vd applied to the drain electrode 60 is set to 50 V and the voltage (gate voltage) Vg applied to the gate electrode 40 is set to −5 V. In Fig. 6, the electric field strength distribution of the semiconductor device 1A in which the gate electrode 40 does not have the rising portion 42 is shown by a solid line (denoted as "no rising portion"), and the electric field strength distribution of the semiconductor device 1B in which the gate electrode 40 has the rising portion 42 is shown by a dotted line (denoted as "with rising portion").

[0072] 6, the semiconductor device 1A (without rising portion indicated by a solid line) reduces electric field concentration at the position corresponding to the drain-side edge 41 of the gate electrode 40 compared to the semiconductor device 1B (with rising portion indicated by a dotted line). Therefore, from the viewpoint of reducing the electric field concentration at the position corresponding to the drain-side edge 41 of the gate electrode 40, it is preferable to reduce the height of the rising portion 42 of the gate electrode 40 (the height from the surface 20a of the insulating film 20).

[0073] Next, a third example of the semiconductor device according to the first embodiment will be described. 7A and 7B are diagrams illustrating a third example of the semiconductor device according to the first embodiment. Each of Fig. 7A and Fig. 7B is a schematic cross-sectional view of a main part of an example of the semiconductor device.

[0074] 7(A) includes a gate electrode 40 with a slanted structure in which the width increases from the insulating film 20 side toward the surface 30a side. The gate electrode 40 of the semiconductor device 1C has an inclined surface 45 that faces the surface 20a of the insulating film 20 via the barrier layer 30C and extends toward the drain electrode 60 while being spaced apart from the surface 20a. The semiconductor device 1C differs from the semiconductor device 1A (FIGS. 1(A) and 1(B)) in that it includes a gate electrode 40 having such a shape.

[0075] The barrier layer 30C of the semiconductor device 1C is made of a nitride semiconductor such as a-AlGaN. Similar to the barrier layer 30A, the barrier layer 30C has a gradient Al composition, in which the Al composition decreases from the insulating film 20 side toward the surface 30a side. The barrier layer 30C has an opening 31C whose opening width increases from the insulating film 20 side toward the surface 30a side. The opening 31C is provided so as to extend from the surface 20a of the insulating film 20 toward the surface 30a side and toward the drain electrode 60 side out of the source electrode 50 side and the drain electrode 60 side. A gate electrode 40 is provided in this opening 31C, resulting in a slanted gate electrode 40 extending from a position connected to the surface 20a of the insulating film 20 toward the surface 30a side and the drain electrode 60 side, as shown in FIG. 7A .

[0076] Furthermore, the semiconductor device 1D shown in FIG. 7(B) differs from the semiconductor device 1C shown in FIG. 7(A) in that the gate electrode 40 has a rising portion 42 that extends upward from the surface 20a of the insulating film 20.

[0077] The barrier layer 30D of the semiconductor device 1D is made of a nitride semiconductor such as a-AlGaN. The barrier layer 30D has a relatively high Al composition in a region where the rising portion 42 of the gate electrode 40 is provided, and a gradient Al composition in the region above that. The barrier layer 30D has an opening 31D whose opening width decreases from the surface 30a toward the insulating film 20 and extends from there to the insulating film 20 with approximately the same opening width. The gate electrode 40 is provided in this opening 31D, resulting in a slanted gate electrode 40 having the rising portion 42 on the surface 20a of the insulating film 20 and extending from the rising portion 42 toward the surface 30a and the drain electrode 60, as shown in FIG. 7(B).

[0078] From the same perspective as described above with reference to FIG. 2, the barrier layer 30C of the semiconductor device 1C and the barrier layer 30D of the semiconductor device 1D can each be considered to have a configuration including at least a "first layer" and a "second layer" containing the first element Al at different concentrations. The first layer is a layer provided on the surface 10a of the substrate 10, containing a first concentration of Al, and having a "first opening." The second layer is provided between the surface 10a of the substrate 10 and the first layer, containing a second concentration of Al higher than the first concentration, and having a "second opening" that communicates with the first opening in the first layer and has a smaller opening width than the first opening. The second layer before the second opening is formed is the "third layer," and the first layer before the first opening is formed is the "fourth layer."

[0079] Electric field concentration is likely to occur near the drain-side edge 41 of the gate electrode 40. In the semiconductor devices 1C and 1D, the gate electrode 40 is provided so as to extend toward the surface 30a and toward the drain electrode 60 side out of the source electrode 50 side and the drain electrode 60 side. This prevents electric field concentration near the drain-side edge 41 of the gate electrode 40 in the semiconductor devices 1C and 1D.

[0080] Furthermore, in the semiconductor devices 1C and 1D, the gate electrode 40 is provided so as to extend from a position connected to the insulating film 20 toward the drain electrode 60 side out of the source electrode 50 side and the drain electrode 60 side. Therefore, compared to a case where the gate electrode 40 is provided so as to extend toward both the source electrode 50 side and the drain electrode 60 side, it is possible to extend the gate electrode 40 toward the drain electrode 60 while being closer to the source electrode 50. Alternatively, it is possible to narrow the distance between the source electrode 50 and the drain electrode 60, which are arranged so as to sandwich the gate electrode 40. The semiconductor devices 1C and 1D make it possible to realize an asymmetric arrangement of the gate electrodes 40 while suppressing an increase in size, or to narrow the distance between the source electrode 50 and the drain electrode 60 to achieve miniaturization.

[0081] Next, an example of a method for manufacturing the semiconductor device 1C and the semiconductor device 1D described above will be described. 8A and 8B are diagrams illustrating another example of the method for manufacturing the semiconductor device according to the first embodiment. Each of Fig. 8A and Fig. 8B is a schematic cross-sectional view of a main part of an example of the manufacturing process of the semiconductor device.

[0082] 8(A) and 8(B) show an example in which the semiconductor device 1C (FIG. 7(A)) is manufactured. In manufacturing the semiconductor device 1C, a structure is prepared in which a barrier layer 30C is formed on a substrate 10 with an insulating film 20 interposed therebetween, as shown in FIG. 8(A), following the example of FIGS. 3(A) and 3(B) described for manufacturing the semiconductor device 1A (FIG. 1(A), etc.). That is, a structure is prepared in which the insulating film 20 is formed on the surface 10a of the substrate 10, the barrier layer 30C is formed on the surface 20a of the insulating film 20, and a through-hole 31Ca is formed in the barrier layer 30C. Then, as shown in FIG. 8(A), a resist 82 having an opening 82a in a region encompassing a part of the through-hole 31Ca and its periphery (the periphery on the side of the region where the drain electrode 60 is formed) is formed on the barrier layer 30C.

[0083] Using this resist 82 as a mask, the barrier layer 30C at the opening 82a is wet-etched using KOH. This wet etching widens the opening width of the through-hole 31Ca in the barrier layer 30C toward one side (the region where the drain electrode 60 is to be formed). When wet-etching the barrier layer 30C having a gradient Al composition, the etching rate is faster in a region with a low Al composition (Al concentration) than in a region with a high Al composition. Therefore, as shown in FIG. 8(B), in the barrier layer 30C having a gradient Al composition where the Al composition decreases toward the surface 30a, wet-etching using KOH forms an opening 31C whose opening width decreases from the surface 30a toward the insulating film 20. After the opening 31C is formed, the resist 82 is removed.

[0084] After the opening 31C in the barrier layer 30C is formed, the source electrode 50 and the drain electrode 60 are formed on the substrate 10, and the gate electrode 40 is formed in the opening 31C in the barrier layer 30C, according to the example of Fig. 4(B) above. In this way, the semiconductor device 1C (Fig. 7(A)) is manufactured.

[0085] While the fabrication of the semiconductor device 1C has been described above as an example, when fabricating the semiconductor device 1D (FIG. 7B), a barrier layer 30D is formed on the insulating film 20 on the substrate 10. The barrier layer 30D has a relatively high Al composition in the region where the rising portion 42 of the gate electrode 40 is to be formed, and a gradient Al composition in the region above that. After the formation of the barrier layer 30D, as in the examples of FIGS. 8A and 8B, a resist 82 having an opening 82a is formed, and wet etching using KOH is performed, and an opening 31D is formed by utilizing the difference in etching rate due to the Al composition. Then, as in the example of FIG. 4B, a source electrode 50 and a drain electrode 60 are formed on the substrate 10, and a gate electrode 40 is formed in the opening 31D of the barrier layer 30D. In this manner, the semiconductor device 1D is fabricated.

[0086] In manufacturing the semiconductor devices 1C and 1D, the source electrode 50 and the drain electrode 60 may be formed on the surface 10a of the substrate 10 after the substrate 10 is formed and before the insulating film 20 and the barrier layer 30C or 30D are formed. Alternatively, the source electrode 50 and the drain electrode 60 may be formed on the surface 10a of the substrate 10 from which part of the insulating film 20 has been removed, after the substrate 10 and the insulating film 20 are formed and before the barrier layer 30C or 30D is formed.

[0087] In the above description, an example has been described in which a-SiN containing H is used as the insulating film 20. In addition, the insulating film 20 of the semiconductor devices 1A-1D is not limited to a-SiN containing H, and various insulating materials can be used as long as they can function as an etching stopper and a gate insulating film.

[0088] Next, the electric field strength distribution of various semiconductor devices will be further described. 9 and 10 are diagrams for explaining the electric field strength distribution of various semiconductor devices. Each of Fig. 9(A) to Fig. 9(D) shows an example of a semiconductor device model. Fig. 10 shows an example of the electric field strength distribution.

[0089] 9(A) to 9(D) are used for the simulation of the electric field strength. Each of the semiconductor device models M1 to M4 includes a barrier layer 30 and a gate electrode 40 provided on an insulating film 20 on a substrate 10, and a drain electrode 60 provided on the substrate 10. The gate electrode 40 is provided in an opening 31 formed in the barrier layer 30.

[0090] The semiconductor device model M1 shown in Figure 9(A) has a gate electrode 40 with a T-shaped structure, which has a rising portion 42 extending from the insulating film 20 and an overhanging portion 43 facing the insulating film 20 (or the substrate 10) via the barrier layer 30.

[0091] 9(B) includes a gate electrode 40 having a slant structure in which an inclined surface 45 facing the insulating film 20 via the barrier layer 30 extends toward the drain electrode 60 while being spaced apart from the insulating film 20. The gate electrode 40 of the semiconductor device model M2 has a shape in which the inclined surface 45 is inclined at a certain angle with respect to the insulating film 20 and extends a relatively short length toward the drain electrode 60.

[0092] 9(C) includes a gate electrode 40 having a slant structure in which an inclined surface 45 facing the insulating film 20 via the barrier layer 30 extends toward the drain electrode 60 while being spaced apart from the insulating film 20. The gate electrode 40 of the semiconductor device model M3 has a shape in which the inclined surface 45 is inclined at a certain angle with respect to the insulating film 20 and extends a relatively long length toward the drain electrode 60.

[0093] 9(D) includes a gate electrode 40 having a slant structure in which an inclined surface 45 facing the insulating film 20 via the barrier layer 30 extends toward the drain electrode 60 while being spaced apart from the insulating film 20. The gate electrode 40 of the semiconductor device model M4 has a shape in which the inclined surface 45 is concavely curved and inclined with respect to the insulating film 20, and extends a relatively long distance toward the drain electrode 60.

[0094] An example of the results of a simulation of the electric field strength distribution performed on the semiconductor device models M1-M4 is shown in Fig. 10. Fig. 10 shows the electric field strength distributions superimposed on each other when the positions of the drain-side edges 41 of the gate electrodes 40 in the semiconductor device models M1-M4 are aligned.

[0095] As shown in Figure 10, in a semiconductor device model M1 in which the gate electrode 40 has a T-shaped structure, a relatively strong electric field concentration occurs at a position corresponding to the drain side edge 41 of the gate electrode 40 and the edge (also called the "eaves edge") 44 of its eaves portion 43 on the drain electrode 60 side.

[0096] In contrast, in semiconductor device models M2-M4 in which the gate electrode 40 has a slant structure, the electric field concentration is alleviated at a position corresponding to the drain-side edge 41 of the gate electrode 40, and further, the electric field concentration is alleviated at a position corresponding to the overhanging edge 44 of the T-shaped structure. Furthermore, in semiconductor device models M3-M4 in which the length of the inclined surface 45 of the gate electrode 40 is relatively long, the electric field tends to be more dispersed than in semiconductor device model M2 in which the length is relatively short. In semiconductor device model M4 in which the inclined surface 45 of the gate electrode 40 is curved, the electric field tends to be more dispersed than in semiconductor device model M3 in which the inclined surface 45 is not curved.

[0097] By forming the gate electrode 40 in a slanted structure, it is possible to suppress localized strong electric field concentration compared to a T-shaped structure, and furthermore, by changing the shape of the slanted gate electrode 40, it is possible to change the position and strength of the electric field. Gate electrodes 40 having various shapes can be realized by adjusting the graded Al composition (Al composition distribution or Al concentration distribution) of the barrier layer 30 on which the gate electrode 40 is provided, and by adjusting the shape of the opening 31 formed in the barrier layer 30 by etching.

[0098] For example, the position of the drain-side edge 41 of the gate electrode 40 is set, and the position of the end 46 on the surface 30a on the drain electrode 60 side or the distance between the end 46 and the drain electrode 60 is set. Furthermore, the thickness of the barrier layer 30 is set. This determines the extension amount of the inclined surface 45 of the gate electrode 40 toward the drain electrode 60. Whether the inclined surface 45 of the gate electrode 40 is inclined at a constant angle or curved is adjusted by the gradient Al composition, i.e., Al concentration distribution, of the barrier layer 30 at that thickness. Adjusting the Al concentration distribution of the barrier layer 30 adjusts the shape of the opening 31 formed by etching, and the shape of the gate electrode 40 formed in the opening 31, i.e., the slope type (constant angle or curved) of the inclined surface 45, is adjusted.

[0099] [Second embodiment] Fig. 11 is a diagram illustrating an example of a barrier layer of a semiconductor device according to the second embodiment. Fig. 11 is a schematic cross-sectional view of a main part of an example of the barrier layer. Fig. 11 illustrates the barrier layer provided on a substrate with an insulating film interposed therebetween.

[0100] A barrier layer 100 as shown in FIG. 11 may be provided on the surface 10a side of the substrate 10 with an insulating film 20 interposed therebetween. The barrier layer 100 shown in FIG. 11 has a first layer 110 and a second layer 120. The first layer 110 is provided on the surface 20a side of the insulating film 20. The second layer 120 is provided between the surface 20a of the insulating film 20 and the first layer 110.

[0101] The first layer 110 is made of an insulating material containing a relatively high concentration of H, such as a-SiN. For example, the first layer 110 contains H at a concentration of 1.4×10 22 / cm 3 The following a-SiN is used. The concentration of H contained in the first layer 110 is set to be higher than the concentration of H contained in the second layer 120. The thickness of the first layer 110 is set to be in the range of 5 nm to 30 nm, for example.

[0102] The second layer 120 is made of an insulating material containing a relatively low concentration of H, such as a-SiN. For example, the second layer 120 contains H at a concentration of 1.0×10 22 / cm 3 The following a-SiN is used. The concentration of H contained in the second layer 120 is set to be lower than the concentration of H contained in the first layer 110. The thickness of the second layer 120 is set to be in the range of 5 nm to 30 nm, for example.

[0103] The first layer 110 and the second layer 120 are formed on the surface 10a side of the substrate 10 using a plasma enhanced chemical vapor deposition (PECVD) method and annealing.

[0104] For example, a-SiN is formed on the surface 20a of the insulating film 20 formed on the surface 10a side of the substrate 10 using the PECVD method, and the a-SiN is then annealed at a relatively high temperature of 600° C. to form the second layer 120. The second layer 120 formed in this manner (the second layer 120 before the formation of the second opening 121 described below) is also referred to as the “third layer.”

[0105] On the formed second layer 120, a-SiN is formed using the PECVD method, and the a-SiN is further annealed at a relatively low temperature of 350° C. to form the first layer 110. The first layer 110 formed in this manner (the first layer 110 before the formation of the first opening 111 described below) is also referred to as the “fourth layer.”

[0106] The higher the annealing temperature, the lower the H content of a-SiN. Therefore, by annealing a-SiN formed using the PECVD method as described above at a relatively high temperature of 600°C, the second layer 120 containing a-SiN with a relatively low concentration of H is formed. By annealing a-SiN formed using the PECVD method at a relatively low temperature of 350°C, the first layer 110 containing a-SiN with a relatively high concentration of H is formed.

[0107] In this manner, the barrier layer 100 is formed, which includes the first layer 110 (or the fourth layer) and the second layer 120 (or the third layer). Note that H contained in the first layer 110 and the second layer 120 of the barrier layer 100 is also referred to as the "first element."

[0108] Next, an example of a method for manufacturing a semiconductor device using the above-described barrier layer 100 will be described. 12 and 13 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. Figures 12(A) and 12(B) and Figures 13(A) and 13(B) each show a schematic cross-sectional view of a main part of an example of a manufacturing process of a semiconductor device.

[0109] First, a structure as shown in FIG. 12(A) is formed, that is, a structure in which a barrier layer 100 is formed on a substrate 10 via an insulating film 20. The substrate 10 is formed by growing the electron transit layer 11, the electron supply layer 12, and the like on a predetermined base substrate (not shown) using a method such as MOCVD. For example, GaN is formed as the electron transit layer 11, and AlGaN is formed as the electron supply layer 12. The thickness of the electron transit layer 11 is set to be in the range of 100 nm to 200 nm, for example. The thickness of the electron supply layer 12 is set to be in the range of 5 nm to 30 nm, for example. Note that the substrate 10 can also be obtained by forming one or more of the following layers, such as an initial layer, a buffer layer, a spacer layer, a back barrier layer, and a cap layer, in addition to the electron transit layer 11 and the electron supply layer 12, using predetermined nitride semiconductors.

[0110] An insulating film 20 is formed on the surface 10a of the substrate 10 by using LPCVD, MOCVD, or the like. For example, a-SiN is formed as the insulating film 20. When forming a-SiN by LPCVD or MOCVD, the formation temperature is set to, for example, a range of 780°C to 850°C. As a result, the insulating film 20 is a-SiN containing H, and the concentration of H contained therein is 0.6×10 22 / cm 3 and density is 2.8 g / cm 3 The a-SiN having the above thickness is formed. The thickness of the insulating film 20 is set to 5 nm or less, for example, in the range of 4 nm to 5 nm. The a-SiN of the insulating film 20 is formed so as to have a lower concentration of H contained therein than the barrier layer 100 formed as described below.

[0111] A barrier layer 100 is formed on the surface 20a of the insulating film 20 by using the PECVD method and annealing. For example, as described above, a-SiN is formed on the surface 20a of the insulating film 20 by using the PECVD method, and the a-SiN is then annealed at a relatively high temperature of 600°C to form the second layer 120 (also referred to as the "third layer"). The thickness of the second layer 120 is set to, for example, a range of 5 nm to 30 nm. The second layer 120 thus formed has a H concentration of 1.0×10 22 / cm 3 The following is the result.

[0112] On the formed second layer 120, a-SiN is formed by PECVD, and the a-SiN is further annealed at a relatively low temperature of 350°C to form the first layer 110 (also referred to as the "fourth layer"). The thickness of the first layer 110 is set to, for example, a range of 5 nm to 30 nm. The first layer 110 thus formed has a H concentration of 1.4 x 10 22 / cm 3 The following is the result.

[0113] As a result, a barrier layer 100 is formed that includes a first layer 110 containing a-SiN with a relatively high concentration of H contained therein and a second layer 120 containing a-SiN with a relatively low concentration of H contained therein.

[0114] After forming a structure in which a barrier layer 100 is formed on a substrate 10 with an insulating film 20 interposed therebetween, a resist 83 having an opening 83a in a region where a gate electrode 40 is to be formed is formed on the barrier layer 100, as shown in Fig. 12(B). Using this resist 83 as a mask, the barrier layer 100 in the opening 83a is dry-etched using a fluorine (F)-based gas.

[0115] Here, the insulating film 20 is made of a-SiN containing a lower concentration of H than the a-SiN of the barrier layer 100. The etching rate of a-SiN containing a relatively low concentration of H with an F-based gas is slower than that of a-SiN containing a relatively high concentration of H. Therefore, the barrier layer 100 containing a relatively high concentration of H is etched using the insulating film 20 containing a relatively low concentration of H as an etching stopper.

[0116] 12(B), the barrier layer 100 is etched using the insulating film 20 as an etching stopper, whereby a through hole 130a reaching the insulating film 20 is formed in the barrier layer 100. That is, a first through hole 111a penetrating the first layer 110 is formed in the barrier layer 100, and a second through hole 121a communicating with the first through hole 111a and penetrating the second layer 120 is formed, thereby forming the through hole 130a reaching the insulating film 20. After the through hole 130a is formed, the resist 83 is removed.

[0117] 13(A), after the through-hole 130a is formed in the barrier layer 100, a resist 84 having an opening 84a in a region encompassing the through-hole 130a and its periphery (the periphery on the side of the region where the source electrode 50 and the drain electrode 60 are to be formed) is formed on the barrier layer 100. Using this resist 84 as a mask, the barrier layer 100 at the opening 84a is wet-etched using ammonium fluoride (NHF) and hydrogen fluoride (HF).

[0118] Here, the barrier layer 100 has a first layer 110 containing a-SiN with a relatively high concentration of H and a second layer 120 containing a-SiN with a relatively low concentration of H. The a-SiN with a relatively high concentration of H has a faster etching rate with NHF and HF than the a-SiN with a relatively low concentration of H. Therefore, when the barrier layer 100 is wet-etched using NHF and HF, the first layer 110 is more easily etched than the second layer 120. Furthermore, the insulating film 20 is made of a-SiN with an even lower concentration of H than the second layer 120. Therefore, when the barrier layer 100 is wet-etched using NHF and HF, the insulating film 20 functions as an etching stopper.

[0119] By etching the barrier layer 100 in this manner using the insulating film 20 as an etching stopper, as shown in FIG. 13A, an opening 130 is formed in the barrier layer 100, the opening width of which decreases from the surface 100a opposite to the insulating film 20 side toward the insulating film 20 side. That is, in the first layer 110, the opening width of the first through hole 111a increases to form a first opening 111. In the second layer 120, the opening width of the second through hole 121a increases to form a second opening 121. The first opening 111 and the second opening 121 form the opening 130 in the barrier layer 100. After the opening 130 is formed, the resist 84 is removed.

[0120] After the opening 130 is formed in the barrier layer 100, the gate electrode 40, the source electrode 50, and the drain electrode 60 are formed as shown in FIG. 13(B). For example, the barrier layer 100 and the insulating film 20 in the area where the source electrode 50 and the drain electrode 60 are to be formed are removed by etching, and a laminate of Ta or Ti and Al is deposited in that area using a vapor deposition method to form the source electrode 50 and the drain electrode 60.

[0121] Furthermore, a stack of Ni and Au is deposited by evaporation in the opening 130 of the barrier layer 100, to form the gate electrode 40. The opening 130 of the barrier layer 100 has a shape in which the opening width increases from the insulating film 20 side toward the surface 100a side. By forming the gate electrode 40 in such an opening 130, the gate electrode 40 is formed with a slant structure in which the width increases from the insulating film 20 side toward the surface 100a side. That is, the gate electrode 40 is formed with a slant structure in which an inclined surface 45 of the gate electrode 40, which faces the surface 20a of the insulating film 20 across the barrier layer 100, extends toward the source electrode 50 side and the drain electrode 60 side while being spaced apart from the surface 20a of the insulating film 20.

[0122] For example, a semiconductor device 1E as shown in FIG. 13(B) is manufactured by the above steps. The source electrode 50 and the drain electrode 60 may be formed on the surface 10a of the substrate 10 after the substrate 10 is formed and before the insulating film 20 and the barrier layer 100 are formed. In this case, the insulating film 20 and the barrier layer 100 are formed on the surface 10a of the substrate 10 on which the source electrode 50 and the drain electrode 60 have been formed, according to the example of FIG. 12(A). At this time, the insulating film 20 and the barrier layer 100 may be formed so as to cover the source electrode 50 and the drain electrode 60 on the surface 10a of the substrate 10. Alternatively, the source electrode 50 and the drain electrode 60 may be formed after the substrate 10 and the insulating film 20 are formed and before the barrier layer 100 is formed. In this case, the source electrode 50 and the drain electrode 60 are formed on the surface 10a of the substrate 10 from which part of the insulating film 20 has been removed, and then the barrier layer 100 is formed according to the example of FIG. 12(A). At this time, the barrier layer 100 may be formed so as to cover the source electrode 50 and the drain electrode 60. Thereafter, the through-hole 130a is formed according to the example of Fig. 12(B), the opening 130 is formed according to the example of Fig. 13(A), and the gate electrode 40 is formed according to the example of Fig. 13(B). In this manner, the semiconductor device 1E may be manufactured.

[0123] In the manufacturing method of the semiconductor device 1E described above, a barrier layer 100 is formed having a first layer 110 containing a-SiN with a relatively high concentration of H and a second layer 120 containing a-SiN with a relatively low concentration of H. Then, utilizing the fact that the etching rate of a high-H concentration region is faster than that of a low-H concentration region during wet etching using NHF and HF, an opening 130 whose opening width narrows from the surface 100a toward the insulating film 20 is formed by wet etching. The insulating film 20 functions as an etching stopper during this wet etching and during the dry etching performed prior to it. A gate electrode 40 is formed in the opening 130 thus formed in the barrier layer 100. The gate electrode 40 formed in the opening 130 has a slant structure.

[0124] According to the above-described method for manufacturing the semiconductor device 1E using etching, it is possible to efficiently obtain the semiconductor device 1E that includes the gate electrode 40 having a slanted structure and that can suppress electric field concentration and resulting breakdown near the drain-side edge 41. Furthermore, the insulating film 20 used as an etching stopper can also be used as a gate insulating film. Therefore, according to the above-described method for manufacturing the semiconductor device 1E, it is possible to efficiently obtain the semiconductor device 1E that can suppress the occurrence of gate leakage current and the resulting decrease in maximum drain current.

[0125] According to the above manufacturing method, it is possible to efficiently manufacture a high-performance semiconductor device 1E in which performance degradation due to electric field concentration and gate leakage current is suppressed. Although the barrier layer 100 having a two-layer structure consisting of the first layer 110 and the second layer 120 has been exemplified here, the number of layers in the barrier layer is not limited to this. Even in the case of a barrier layer having a three-layer or more layer structure, it is possible to obtain a configuration similar to that of the semiconductor device 1E by using a barrier layer that contains a higher concentration of H than the insulating film 20 and has an H concentration distribution in which the concentration is higher on the surface 100a side than on the insulating film 20 side. That is, it is possible to obtain a semiconductor device that includes a barrier layer having an opening whose opening width decreases from the surface 100a side toward the insulating film 20 side, and a slanted gate electrode 40 provided in the opening.

[0126] In the above description, an example has been described in which a-SiN containing H is used as the insulating film 20. In addition, the insulating film 20 of the semiconductor device 1E is not limited to a-SiN containing H, and various insulating materials can be used as long as they can function as an etching stopper and a gate insulating film.

[0127] In the semiconductor device 1E, the position and strength of the electric field can be changed by changing the shape of the slanted gate electrode 40. The gate electrode 40 having various shapes can be realized by adjusting the H concentration distribution in the barrier layer 100 on which the gate electrode 40 is provided and by adjusting the shape of the opening 31 formed in the barrier layer 100 by etching.

[0128] For example, the position of the drain-side edge 41 of the gate electrode 40 is set, and the position of the end of the surface 100a on the drain electrode 60 side or the distance between the end and the drain electrode 60 is set. Furthermore, the thickness of the barrier layer 100 is set. This determines the extension amount of the inclined surface 45 of the gate electrode 40 toward the drain electrode 60. Then, the number of layers and the thickness of each layer in the barrier layer 100 having that thickness, in which the H concentration increases toward the surface 100a, are set. This adjusts the shape of the opening 130 formed by etching, and the shape of the gate electrode 40 formed in the opening 130 is adjusted.

[0129] The first and second embodiments have been described above. The semiconductor devices 1A-1E described above can be applied to various electronic devices. As an example, the following describes cases where a semiconductor device having the above configuration is applied to a semiconductor package, a power factor correction circuit, a power supply device, and an amplifier.

[0130] [Third embodiment] Here, an example of application of a semiconductor device having the above-described configuration to a semiconductor package will be described as a third embodiment.

[0131] Fig. 14 is a diagram illustrating an example of a semiconductor package according to the third embodiment, which diagrammatically shows a plan view of a main part of the example of the semiconductor package. 14 is an example of a discrete package. The semiconductor package 200 includes, as an example, the semiconductor device 1A (FIGS. 1A and 1B, etc.) as described in the first embodiment, a lead frame 210 on which the semiconductor device 1A is mounted, and a resin 220 that seals them.

[0132] The semiconductor device 1A is mounted on a die pad 210a of a lead frame 210 using, for example, a die attach material or the like (not shown). The semiconductor device 1A is provided with a pad 40a connected to the gate electrode 40, a pad 50a connected to the source electrode 50, and a pad 60a connected to the drain electrode 60. The pads 40a, 50a, and 60a are connected to a gate lead 211, a source lead 212, and a drain lead 213 of the lead frame 210, respectively, using wires 230 made of Au, Al, or the like. The lead frame 210, the semiconductor device 1A mounted thereon, and the wires 230 connecting them are sealed with resin 220 so that portions of the gate lead 211, the source lead 212, and the drain lead 213 are exposed.

[0133] An external connection electrode connected to the source electrode 50 may be provided on the surface of the semiconductor device 1A opposite to the surface on which the pad 40a connected to the gate electrode 40 and the pad 60a connected to the drain electrode 60 are provided. The external connection electrode may be connected to the die pad 210a connected to the source lead 212 using a conductive bonding material such as solder.

[0134] For example, a semiconductor package 200 can be obtained using the semiconductor device 1A described in the first embodiment. In the semiconductor device 1A described above, a barrier layer including a first layer and a second layer containing a predetermined first element at different concentrations is provided on a substrate, with an insulating film serving as an etching stopper and gate insulating film interposed therebetween. An opening whose width narrows toward the insulating film side is formed in the barrier layer by utilizing the difference in etching rates between the first and second layers, and a gate electrode is provided in the opening. The gate electrode provided in the opening has a slant structure. This realizes a high-performance semiconductor device 1A in which performance degradation due to electric field concentration and gate leakage current is suppressed. A semiconductor package 200 can be realized using such a semiconductor device 1A.

[0135] Although the semiconductor device 1A is used as an example here, it is possible to obtain a semiconductor package in the same manner using other semiconductor devices 1B-1E and the like. [Fourth embodiment] Here, an example of application of a semiconductor device having the above-described configuration to a power factor correction circuit will be described as a fourth embodiment.

[0136] Fig. 15 is a diagram illustrating an example of a power factor correction circuit according to the fourth embodiment, showing an equivalent circuit diagram of the example of the power factor correction circuit. The power factor correction (PFC) circuit 300 shown in FIG. 15 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360, and an AC power supply 370 (AC).

[0137] In the PFC circuit 300, a drain electrode of a switch element 310 is connected to an anode terminal of a diode 320 and one terminal of a choke coil 330. A source electrode of the switch element 310 is connected to one terminal of a capacitor 340 and one terminal of a capacitor 350. The other terminal of the capacitor 340 is connected to the other terminal of the choke coil 330. The other terminal of the capacitor 350 is connected to the cathode terminal of the diode 320. A gate driver is connected to the gate electrode of the switch element 310. An AC power supply 370 is connected between both terminals of the capacitor 340 via a diode bridge 360, and a DC power supply (DC) is taken out between both terminals of the capacitor 350.

[0138] For example, the semiconductor device 1A-1E or the like is used as the switch element 310 of a PFC circuit 300 having such a configuration. In the semiconductor device 1A-1E or the like, a barrier layer including a first layer and a second layer containing a predetermined first element at different concentrations is provided on a substrate via an insulating film that serves as an etching stopper and gate insulating film. An opening whose width narrows toward the insulating film side is formed in the barrier layer by utilizing the difference in etching rates between the first layer and the second layer, and a gate electrode is provided in the opening. The gate electrode provided in the opening has a slant structure. This realizes a high-performance semiconductor device 1A-1E or the like that suppresses performance degradation due to electric field concentration and gate leakage current. The PFC circuit 300 is realized using such a semiconductor device 1A-1E or the like.

[0139] [Fifth embodiment] Here, an example in which a semiconductor device having the above-described configuration is applied to a power supply device will be described as a fifth embodiment.

[0140] Fig. 16 is a diagram illustrating an example of a power supply device according to the fifth embodiment, showing an equivalent circuit diagram of the example of the power supply device. The power supply device 400 shown in FIG. 16 includes a primary side circuit 410, a secondary side circuit 420, and a transformer 430 provided between the primary side circuit 410 and the secondary side circuit 420.

[0141] The primary side circuit 410 includes the PFC circuit 300 as described in the fourth embodiment, and an inverter circuit, for example, a full-bridge inverter circuit 440, connected between both terminals of the capacitor 350 of the PFC circuit 300. The full-bridge inverter circuit 440 includes a plurality of (for example, four in this case): a switch element 441, a switch element 442, a switch element 443, and a switch element 444.

[0142] The secondary side circuit 420 includes a plurality of switch elements, three of which are a switch element 421, a switch element 422, and a switch element 423, as an example. For example, the semiconductor device 1A-1E described above may be used for the switch element 310 of the PFC circuit 300 and the switch elements 441-444 of the full-bridge inverter circuit 440 included in the primary-side circuit 410 of a power supply device 400 having such a configuration. For example, typical silicon metal-insulator-semiconductor (Si) field-effect transistors may be used for the switch elements 421-423 of the secondary-side circuit 420 of the power supply device 400. In the semiconductor device 1A-1E described above, a barrier layer including a first layer and a second layer containing a predetermined first element at different concentrations is provided on a substrate via an insulating film that serves as an etching stopper and gate insulating film. An opening whose width narrows toward the insulating film side is formed in the barrier layer by utilizing the difference in etching rates between the first and second layers, and a gate electrode is provided in the opening. The gate electrode provided in the opening has a slant structure. This allows for the realization of a high-performance semiconductor device 1A-1E that suppresses performance degradation due to electric field concentration and gate leakage current. The power supply device 400 is realized using such semiconductor devices 1A-1E.

[0143] [Sixth embodiment] Here, an example of application of the semiconductor device having the above-described configuration to an amplifier will be described as a sixth embodiment.

[0144] Fig. 17 is a diagram illustrating an example of an amplifier according to the sixth embodiment, showing an equivalent circuit diagram of the example amplifier. The amplifier 500 shown in FIG. 17 includes a digital predistortion circuit 510, a mixer 520, a mixer 530, and a power amplifier 540.

[0145] The digital predistortion circuit 510 compensates for nonlinear distortion in the input signal. The mixer 520 mixes the input signal SI, for which nonlinear distortion has been compensated, with an AC signal. The power amplifier 540 amplifies the signal resulting from mixing the input signal SI with the AC signal. In the amplifier 500, for example, by switching a switch, the output signal SO can be mixed with the AC signal in the mixer 530 and sent to the digital predistortion circuit 510. The amplifier 500 can be used as a high-frequency amplifier or a high-power amplifier.

[0146] The power amplifier 540 of the amplifier 500 having such a configuration uses the semiconductor device 1A-1E or the like. In the semiconductor device 1A-1E or the like, a barrier layer including a first layer and a second layer containing a predetermined first element at different concentrations is provided on a substrate via an insulating film that serves as an etching stopper and gate insulating film. An opening whose width narrows toward the insulating film side is formed in the barrier layer by utilizing the difference in etching rates between the first layer and the second layer, and a gate electrode is provided in the opening. The gate electrode provided in the opening has a slant structure. This realizes a high-performance semiconductor device 1A-1E or the like that suppresses performance degradation due to electric field concentration and gate leakage current. The amplifier 500 is realized using such a semiconductor device 1A-1E or the like.

[0147] Various electronic devices to which the semiconductor devices 1A-1E and the like are applied (such as the semiconductor package 200, PFC circuit 300, power supply device 400, and amplifier 500 described in the third to sixth embodiments) can be mounted in various electronic devices or electronic devices, such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio equipment, measuring devices, inspection devices, manufacturing equipment, transmitters, receivers, and radar devices.

[0148] The following additional notes are provided regarding the above-described embodiment. (Appendix 1) A substrate, a first layer provided on a first surface side of the substrate, containing a first element at a first concentration, and having a first opening; a second layer provided between the first surface of the substrate and the first layer, containing the first element at a second concentration different from the first concentration, and having a second opening communicating with the first opening of the first layer and having an opening width smaller than that of the first opening; 10. A semiconductor device comprising:

[0149] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the first layer and the second layer are amorphous. (Supplementary Note 3) The semiconductor device according to Supplementary Note 1, wherein the first layer and the second layer each contain the first element and include a nitride of a second element different from the first element.

[0150] (Supplementary Note 4) The first element is aluminum, and the second element is gallium, 4. The semiconductor device of claim 3, wherein the first concentration of the first element is lower than the second concentration. (Supplementary Note 5) The first element is hydrogen, and the second element is silicon; 4. The semiconductor device of claim 3, wherein the first concentration of the first element is higher than the second concentration.

[0151] (Supplementary Note 6) An insulating film is provided between the first surface and the second layer, 2. The semiconductor device according to claim 1, wherein the second opening of the second layer communicates with the insulating film. (Supplementary Note 7) A barrier layer is provided on the first surface side of the substrate, and has an opening whose opening width increases from the substrate side toward an opposite side to the substrate side, the first layer and the second layer are each part of the barrier layer; 2. The semiconductor device of claim 1, wherein the first opening in the first layer and the second opening in the second layer are each part of the opening in the barrier layer.

[0152] (Supplementary Note 8) A gate electrode provided in the opening of the barrier layer; a drain electrode provided on the first surface side of the substrate and separated from the gate electrode; Including, 8. The semiconductor device according to claim 7, wherein the opening has a shape such that a surface of the gate electrode that faces the first surface via the barrier layer extends toward the drain electrode while being spaced apart from the first surface.

[0153] (Supplementary Note 9) A step of forming a first layer containing a first element at a first concentration and having a first opening on a first surface side of a substrate; forming a second layer between the first surface of the substrate and the first layer, the second layer containing the first element at a second concentration different from the first concentration, the second layer having a second opening communicating with the first opening of the first layer and having a smaller opening width than the first opening; A method for manufacturing a semiconductor device, comprising:

[0154] (Supplementary Note 10) Before forming the first layer and the second layer, forming a third layer containing the first element at the second concentration on the first surface side of the substrate; forming a fourth layer containing the first element at the first concentration on a side of the third layer opposite to the substrate; Including, forming the first layer includes etching the fourth layer to form the first opening, thereby forming the first layer having the first opening; 10. The method for manufacturing a semiconductor device according to claim 9, wherein the step of forming the second layer includes the step of forming the second layer having the second opening by etching the third layer to form the second opening.

[0155] (Supplementary Note 11) The method for manufacturing a semiconductor device according to Supplementary Note 9, wherein the first layer and the second layer are amorphous. (Appendix 12) The method for manufacturing a semiconductor device according to Appendix 9, wherein the first layer and the second layer each contain the first element and a nitride of a second element different from the first element.

[0156] (Supplementary Note 13) The first element is aluminum, and the second element is gallium, 13. The method for manufacturing a semiconductor device according to claim 12, wherein the first concentration of the first element is lower than the second concentration.

[0157] (Supplementary Note 14) The first element is hydrogen, and the second element is silicon; 13. The method of claim 12, wherein the first concentration of the first element is higher than the second concentration.

[0158] (Supplementary Note 15) A step of forming an insulating film between the first surface and the second layer, 10. The method for manufacturing a semiconductor device according to claim 9, wherein the step of forming the second layer includes the step of forming the second layer having the second opening communicating with the insulating film.

[0159] (Supplementary Note 16) A step of forming a barrier layer on the first surface side of the substrate, the barrier layer having an opening whose opening width increases from the substrate side toward an opposite side to the substrate side, 10. The method for manufacturing a semiconductor device according to claim 9, wherein the step of forming the barrier layer includes the step of forming the first layer and the step of forming the second layer.

[0160] (Supplementary Note 17) A step of forming a gate electrode in the opening of the barrier layer; forming a drain electrode on the first surface side of the substrate, the drain electrode being separated from the gate electrode; Including, 17. The method for manufacturing a semiconductor device according to claim 16, wherein the step of forming the barrier layer includes a step of forming the barrier layer having the opening, the opening having a shape such that a surface of the gate electrode facing the first surface with the barrier layer interposed therebetween extends toward the drain electrode while being spaced apart from the first surface.

[0161] (Appendix 18) A substrate; a first layer provided on a first surface side of the substrate, containing a first element at a first concentration, and having a first opening; a second layer provided between the first surface of the substrate and the first layer, containing the first element at a second concentration different from the first concentration, and having a second opening communicating with the first opening of the first layer and having an opening width smaller than that of the first opening; An electronic device comprising a semiconductor device including: [Explanation of symbols]

[0162] 1A, 1B, 1C, 1D, 1E Semiconductor device 10 Substrate 10a, 20a, 30a, 100a side 11 Electron transit layer 12 Electron supply layer 20 insulating film 30, 30A, 30B, 30C, 30D, 100 Barrier layer 31, 31A, 31B, 31C, 31D, 80a, 81a, 82a, 83a, 84a, 130 opening 31Aa, 31Ca, 130a through hole 32, 110 1st layer 32a, 111 1st opening 33, 120 2nd layer 33a, 121 2nd opening 36, 37 parts 40 gate electrode 40a, 50a, 60a pads 41 Drain side edge 42 Rising section 43 Eaves 44 Eaves edge 45 Slope 46 Termination 50 Source electrode 60 drain electrode 70 2DEG area 80, 81, 82, 83, 84 Resist 111a 1st through hole 121a 2nd through hole 200 Semiconductor Packages 210 Lead Frame 210a die pad 211 Gate Lead 212 Source Read 213 Drain Lead 220 Resin 230 Wire 300 PFC circuit 310, 421, 422, 423, 441, 442, 443, 444 Switch elements 320 Diode 330 Choke Coil 340, 350 capacitors 360 Diode Bridge 370 AC power supply 400 power supply 410 Primary circuit 420 Secondary circuit 430 transformer 440 Full-bridge inverter circuit 500 Amplifier 510 Digital Pre-Distortion Circuit 520, 530 Mixer 540 Power Amplifier M1, M2, M3, M4 Semiconductor Device Models

Claims

1. A substrate; a first layer provided on a first surface side of the substrate, containing a first element at a first concentration and having a first opening; a second layer provided between the first surface of the substrate and the first layer, containing the first element at a second concentration different from the first concentration, and having a second opening communicating with the first opening of the first layer and having an opening width smaller than that of the first opening; 10. A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the first layer and the second layer are amorphous.

3. The semiconductor device according to claim 1 , wherein the first layer and the second layer each contain the first element and include a nitride of a second element different from the first element.

4. the first element is aluminum and the second element is gallium; The semiconductor device according to claim 3 , wherein the first concentration of the first element is lower than the second concentration.

5. the first element is hydrogen and the second element is silicon; The semiconductor device according to claim 3 , wherein the first concentration of the first element is higher than the second concentration.

6. an insulating film provided between the first surface and the second layer; The semiconductor device according to claim 1 , wherein the second opening of the second layer communicates with the insulating film.

7. a barrier layer provided on the first surface side of the substrate, the barrier layer having an opening whose opening width increases from the substrate side toward an opposite side to the substrate side; the first layer and the second layer are each part of the barrier layer; The semiconductor device according to claim 1 , wherein the first opening in the first layer and the second opening in the second layer are each a part of the opening in the barrier layer.

8. a gate electrode provided in the opening of the barrier layer; a drain electrode provided on the first surface side of the substrate and separated from the gate electrode; Including, 8. The semiconductor device according to claim 7, wherein the opening has a shape such that a surface of the gate electrode that faces the first surface with the barrier layer therebetween extends toward the drain electrode while being spaced apart from the first surface.

9. forming a first layer containing a first element at a first concentration and having a first opening on a first surface side of a substrate; forming a second layer between the first surface of the substrate and the first layer, the second layer containing the first element at a second concentration different from the first concentration, the second layer having a second opening communicating with the first opening of the first layer and having a smaller opening width than the first opening; A method for manufacturing a semiconductor device, comprising:

10. A substrate; a first layer provided on a first surface side of the substrate, containing a first element at a first concentration and having a first opening; a second layer provided between the first surface of the substrate and the first layer, containing the first element at a second concentration different from the first concentration, and having a second opening communicating with the first opening of the first layer and having an opening width smaller than that of the first opening; An electronic device comprising a semiconductor device including:

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