Chip-like electronic component, method of manufacturing chip-like electronic component, and mounting method for chip-like electronic component

Abstract

To provide a chip-like electronic component of which the mountability onto a substrate is improved, a method of manufacturing a chip-like electronic component, and a mounting method for a chip-like electronic component.SOLUTION: A multilayer ceramic capacitor 1 includes a substantially rectangular parallelepiped base part 16 having: a first face 7a and a second face 7b; a third face 8a and a fourth face 8b; and a fifth face 9a and a sixth face 9b, a first thin part 12a protruding from the first face 7a of the base part 16, a second thin part 12b protruding from the second face 7b of the base part 16, a first external electrode 3 covering the first thin part 12a, and a second external electrode 4 covering the second thin part 12b. The first external electrode 3 comprises a first ground conductive layer 13a and a first plating layer 14a, and the second external electrode 4 comprises a second ground conductive layer 13b and a second plating layer 14b.SELECTED DRAWING: Figure 1C

Description

[Technical Field]

[0001] The present disclosure relates to a chip-type electronic component, a method for manufacturing a chip-type electronic component, and a method for mounting a chip-type electronic component. [Background technology]

[0002] A conventional chip-type electronic component is described, for example, in Patent Document 1. This conventional technology describes a technology in which, in an electronic component having external electrode terminals formed by successively forming a conductive paste layer and a metal layer on both ends or one end of an electronic component element, the thickness of the external electrode terminals on the surface opposite the mounting surface is made thinner than the thickness of the external electrode terminals on the mounting surface, thereby reducing air leakage from the gap between the suction nozzle and the insulating resin layer when the electronic component is mounted on a mounting board, thereby improving the component mounting rate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2-039414 Summary of the Invention [Problem to be solved by the invention]

[0004] As electronic components become smaller, it becomes necessary to take measures to prevent component pickup errors during component mounting. The incidence of pickup errors tends to increase as the size of the electronic components increases, requiring smaller pickup nozzles, or as the distance between the external electrode terminals decreases.

[0005] In the prior art of Patent Document 1, the thickness of the external electrode terminals is made thinner so that the external electrode terminals come into contact with the suction nozzle that picks up the chip-type electronic component, preventing air leakage in the gap between the external electrode terminals and the element surface of the electronic component, but this is not effective enough, and the mountability of the chip-type electronic component is reduced. Therefore, there has been a demand for chip-type electronic components with improved mountability, a method for manufacturing chip-type electronic components, and a method for mounting chip-type electronic components. [Means for solving the problem]

[0006] A chip-type electronic component according to the present disclosure includes a substantially rectangular parallelepiped base having first and second surfaces facing each other, third and fourth surfaces connected to the first and second surfaces and facing each other, and fifth and sixth surfaces connected to the first and second surfaces and the third and fourth surfaces and facing each other, a first thin-walled portion protruding from the first surface of the base, a second thin-walled portion protruding from the second surface of the base, a first external electrode covering the first thin-walled portion and formed between a first imaginary plane including the fifth surface and a second imaginary plane including the sixth surface, and a second external electrode covering the second thin-walled portion and formed between the first imaginary plane and the second imaginary plane, wherein the first thin-walled portion has a first surface facing the first imaginary plane and a second surface facing the second imaginary plane, has a third surface facing the first imaginary plane and a fourth surface facing the second imaginary plane, the first external electrode has a first underlying conductive layer laminated on the first surface, a second underlying conductive layer laminated on the second surface, and a first plating layer laminated between the first underlying conductive layer and the first imaginary plane, between the first underlying conductive layer and the second imaginary plane, and over the surface of the first thin-walled portion between the first surface and the second surface, and the second external electrode has a third underlying conductive layer laminated on the third surface, a fourth underlying conductive layer laminated on the fourth surface, and a second plating layer laminated between the third underlying conductive layer and the first imaginary plane, between the fourth underlying conductive layer and the second imaginary plane, and over the surface of the second thin-walled portion between the third surface and the fourth surface.

[0007] The method for manufacturing chip-type electronic components according to the present disclosure includes the steps of stacking a plurality of ceramic green sheets to obtain a base laminate having a first thin-walled portion for forming a first external electrode, a second thin-walled portion for forming a second external electrode, and a base conductive layer disposed on the first thin-walled portion and the second thin-walled portion; cutting the base laminate to obtain a plurality of individual element body precursors; firing the plurality of element body precursors; and forming a plating layer located on the surface of the base conductive layer on the first thin-walled portion and the second thin-walled portion of the plurality of element body precursors after firing to obtain the first external electrode and the second external electrode.

[0008] The mounting method for chip-type electronic components according to the present disclosure includes the steps of preparing the above-mentioned chip-type electronic component, a substrate for mounting the chip-type electronic component, and a suction nozzle for suctioning the chip-type electronic component; suctioning the fifth main surface, the first plating layer surface, and the second plating layer surface of the chip-type electronic component with the suction nozzle and transporting them onto a mounting surface of the substrate; and mounting the chip-type electronic component transported to the mounting surface of the substrate on the mounting surface.

[0009] A chip-type electronic component according to the present disclosure includes a first surface and a second surface that are perpendicularly adjacent to each other, a third surface and a fourth surface that are positioned symmetrically with respect to the first surface and the second surface with respect to a first imaginary plane that is parallel to the first surface, a fifth surface and a sixth surface that are positioned symmetrically with respect to the first surface and the second surface with respect to a second imaginary plane that is parallel to the second surface and the fourth surface, a seventh surface and an eighth surface that are positioned symmetrically with respect to the third surface and the fourth surface with respect to the two imaginary planes and that are also positioned symmetrically with respect to the fifth surface and the sixth surface with respect to the first imaginary plane, and a front surface. a base portion having a ninth surface and a tenth surface that are perpendicular to the first surface to the eighth surface and face each other; a first thin portion that protrudes from the first surface and the second surface of the base portion; a second thin portion that protrudes from the third surface and the fourth surface of the base portion; a third thin portion that protrudes from the fifth surface and the sixth surface of the base portion; a fourth thin portion that protrudes from the seventh surface and the eighth surface of the base portion; a first external electrode that covers the first thin portion; a second external electrode that covers the second thin portion; and a fourth external electrode covering the fourth thin portion, wherein each of the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode is formed across a third imaginary plane including the ninth surface and a fourth imaginary plane including the tenth surface, and each of the first thin portion, the second thin portion, the third thin portion, and the fourth thin portion has a first surface facing the third imaginary plane and a second surface facing the fourth imaginary plane, and Each of the fourth external electrodes has an underlying conductive layer laminated on each of the first surface and the second surface, and a plating layer laminated between the underlying conductive layer and the third imaginary plane, between the underlying conductive layer and the fourth imaginary plane, and over the surface of the first thin-walled portion between the first surface and the second surface, the second thin-walled portion between the first surface and the second surface, the surface of the third thin-walled portion between the first surface and the second surface, and the surface of the fourth thin-walled portion between the first surface and the second surface.

[0010] Another method for manufacturing chip-type electronic components according to the present disclosure includes the steps of: stacking a plurality of ceramic green sheets to obtain a base laminate having a first thin-walled portion for forming a first external electrode, a second thin-walled portion for forming a second external electrode, a third thin-walled portion for forming a third external electrode, and a fourth thin-walled portion for forming a fourth external electrode, as well as an underlying conductive layer disposed on the first thin-walled portion, the second thin-walled portion, the third thin-walled portion, and the fourth thin-walled portion; cutting the base laminate to obtain a plurality of individual element body precursors; firing the plurality of element body precursors; and forming a plating layer located on the surface of the underlying conductive layer on the first thin-walled portion, the second thin-walled portion, the third thin-walled portion, and the fourth thin-walled portion of the plurality of element body precursors after firing, to obtain the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode.

[0011] Another method for mounting chip-type electronic components according to the present disclosure includes the steps of preparing the chip-type electronic component, a substrate for mounting the chip-type electronic component, and a suction nozzle for suctioning the chip-type electronic component; suctioning the ninth surface, the first plating layer surface, and the second plating layer surface of the chip-type electronic component with the suction nozzle and transporting them onto a mounting surface of the substrate; and mounting the chip-type electronic component transported to the mounting surface of the substrate on the mounting surface. [Effects of the Invention]

[0012] The chip-type electronic component, the method for manufacturing a chip-type electronic component, and the method for mounting a chip-type electronic component according to the present disclosure can improve mountability. [Brief explanation of the drawings]

[0013] [Figure 1A] 1 is a cross-sectional view showing a configuration of a multilayer ceramic capacitor as an embodiment of a chip-type electronic component according to the present disclosure. [Figure 1B] 1 is a cross-sectional view showing a state in which a multilayer ceramic capacitor according to the present disclosure is sucked by a cylindrical suction nozzle. [Figure 1C] 1 is a perspective view showing a configuration of a multilayer ceramic capacitor according to the present disclosure. [Figure 2A] FIG. 3 is a view showing a first ceramic green sheet on which a first internal electrode layer is formed. [Figure 2B] FIG. 10 is a view showing a second green sheet on which a second internal electrode layer is formed. [Figure 2C] FIG. 10 is a view showing a third green sheet on which a first conductive underlayer and a third conductive underlayer are formed. [Figure 2D] 10 is a diagram showing a ceramic pattern disposed between a first conductive underlying layer and a third conductive underlying layer. FIG. [Figure 3A] FIG. 1 shows a ceramic paste printed directly onto a laminate. [Figure 3B] 3 is a diagram showing a pattern of a first conductive base layer, a pattern of a third conductive base layer, and a ceramic paste pattern. FIG. [Figure 3C] FIG. 10 is a diagram showing the pattern of a first internal electrode layer printed on a green sheet. [Figure 3D] FIG. 4 is a diagram showing the pattern of a first internal electrode layer formed on a green sheet. [Figure 3E] FIG. 4 is a diagram showing patterns of a first fired dummy member and a second fired dummy member formed on a support sheet. [Figure 4] FIG. 2 is a perspective view showing a base laminate. [Figure 5A] FIG. 2 is a perspective view showing a state in which the base laminate has been cut. [Figure 5B] FIG. 2 is a perspective view showing an element precursor before firing. [Figure 6] 1 is a flowchart illustrating a manufacturing procedure of a multilayer ceramic capacitor. [Figure 7A] FIG. 2 is a perspective view showing an element precursor. [Figure 7B] FIG. 7B is a cross-sectional view taken along the line VIIB-VIIB in FIG. 7A. [Figure 7C] FIG. 3 is a cross-sectional view showing a laminate after firing. [Figure 7D] 1 is a cross-sectional view showing a multilayer ceramic capacitor in which a first plating layer and a second plating layer are formed on a laminate. [Figure 8A]FIG. 10 is a perspective view showing a four-terminal multilayer ceramic capacitor according to another embodiment of the present disclosure. [Figure 8B] FIG. 8B is a plan view of the multilayer ceramic capacitor shown in FIG. 8A. [Figure 8C] FIG. 8C is an enlarged cross-sectional view taken along the cross-sectional line VIIIC-VIIIC in FIG. 8B. [Figure 9] 1 is a perspective view showing a base laminate in which green sheets on which internal electrode patterns are formed are laminated on a support sheet. FIG. [Figure 10A] FIG. 2 is a perspective view showing a state in which the base laminate has been cut. [Figure 10B] FIG. 2 is a perspective view showing an element precursor before firing. [Figure 10C] 10C is a cross-sectional view taken along the cutting line XC-XC in FIG. 10B. [Figure 11] 8C is a flowchart illustrating a manufacturing procedure of the multilayer ceramic capacitor according to the embodiment shown in FIG. 8B. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of a chip-type electronic component, a manufacturing method for a chip-type electronic component, and a mounting method for a chip-type electronic component according to the present disclosure will be described with reference to the drawings. The drawings referred to below are schematic, and the dimensional ratios and the like shown in the drawings are not necessarily accurate. Below, a multilayer ceramic capacitor, which is an example of a chip-type electronic component, will be described. However, the chip-type electronic component according to the present disclosure is not limited to a multilayer ceramic capacitor and may be a multilayer piezoelectric element, a multilayer thermistor element, a multilayer chip coil, a ceramic multilayer substrate, or the like. In this specification, for convenience, a Cartesian coordinate system X, Y, and Z is defined in some of the drawings. The X-axis direction is also referred to as the first direction or the length direction. The Y-axis direction is also referred to as the second direction or the width direction. The Z-axis direction is also referred to as the third direction, the height direction, or the stacking direction.

[0015] FIG. 1A is a cross-sectional view showing the configuration of a multilayer ceramic capacitor 1 according to an embodiment of a chip-type electronic component according to the present disclosure, and FIG. 1B is a cross-sectional view showing the multilayer ceramic capacitor 1 according to the present disclosure being sucked by a cylindrical suction nozzle N. FIG. 1C is a perspective view showing the configuration of the multilayer ceramic capacitor 1 according to the present disclosure. The multilayer ceramic capacitor 1 of this embodiment includes a laminate 2, a first external electrode 3, and a second external electrode 4. The diameter D of the suction surface N1 of the suction nozzle N is, for example, 0.5 mm or more and 2 mm or less. The suction surface N1 of the suction nozzle N can simultaneously suck a first main surface 209a of the multilayer ceramic capacitor 1. The first main surface 209a is composed of a fifth surface 9a, a first plating layer surface 15a, and a third plating layer surface 15c, which will be described later.

[0016] The laminate 2 is formed by alternately stacking a plurality of dielectric layers 5 and a plurality of internal electrode layers 6, and is generally rectangular. The laminate 2 includes a base 16, a first thin portion 12a, and a second thin portion 12b. The base 16 has a first surface 7a and a second surface 7b facing each other in the first direction X, a third surface 8a and a fourth surface 8b facing each other in the second direction, and a fifth surface 9a and a sixth surface 9b facing each other in the third direction Z.

[0017] The first thin-walled portion 12a has a first surface 11a located closer to the second imaginary plane 10b than the first imaginary plane 10a and a second surface 11b located closer to the first imaginary plane 10a than the second imaginary plane 10b, and protrudes from the first surface 7a. The second thin-walled portion 12b has a third surface 11c located closer to the second imaginary plane 10b than the first imaginary plane 10a, and a fourth surface 11d located closer to the first imaginary plane 10a than the second imaginary plane 10b, and protrudes from the second surface 7b.

[0018] The first external electrode 3 covers the first thin portion 12a, is connected to the ends of the multiple internal electrode layers 6 exposed from the first end face 17a, and is formed from the first end face 17a to the first surface 7a, a first imaginary plane 10a including the fifth surface 9a, and a second imaginary plane 10b including the sixth surface 9b. The second external electrode 4 covers the second thin portion 12b, is connected to the ends of the multiple internal electrode layers 6 exposed from the second end face 17b, and is formed from the second end face 17b to the second surface 7b, the first imaginary plane 10a, and the second imaginary plane 10b.

[0019] The first external electrode 3 has a first underlying conductive layer 13a laminated on the first surface 11a and second surface 11b of the first thin-walled portion 12a, and a first plating layer 14a formed (laminated) to cover the first underlying conductive layer 13a between the first underlying conductive layer 13a and the first imaginary plane 10a, between the first underlying conductive layer 13a and the second imaginary plane 10b, and over the surface of the first thin-walled portion 12a between the first surface 11a and the second surface 11b. The second external electrode 4 includes a second conductive underlayer 13b laminated on the third surface 11c and the fourth surface 11d of the second thin portion 12b, and a second plating layer 14b formed (laminated) to cover the second conductive underlayer 13b between the second conductive underlayer 13b and the first imaginary plane 10a, between the second conductive underlayer 13b and the second imaginary plane 10b, and over the surface of the second thin portion 12b between the third surface 11c and the fourth surface 11d. The first plating layer 14a may be provided on a portion of the surface of the first thin portion 12a between the first surface 11a and the second surface 11b (e.g., only on the side of the first end face 17a). The second plating layer 14b may be provided on a portion of the surface of the second thin portion 12b between the third surface 11c and the fourth surface 11d (e.g., only on the side of the second end face 17b).

[0020] The first plating layer 14a has a first plating layer surface 15a that is substantially flush with the fifth surface 9a and a second plating layer surface 15b that is substantially flush with the sixth surface 9b. The second plating layer 15b has a third plating layer surface 15c that is substantially flush with the fifth surface 9a and a fourth plating layer surface 15d that is substantially flush with the sixth surface 9b.

[0021] The dielectric layer 5 is made of an insulating material. The dielectric layer 5 may be made of a ceramic material whose main component is, for example, barium titanate (BaTiO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), or barium zirconate (BaZrO3). Hereinafter, unless otherwise specified, the dielectric layer 5 is assumed to be made of a ceramic material whose main component is BaTiO3. In this specification, the term "main component" refers to the component with the highest content in the material or member of interest. The content may be expressed, for example, in mol% or mass%.

[0022] The dielectric layer 5 may contain metal elements such as magnesium (Mg), manganese (Mn), vanadium (V), etc., and rare earth elements such as yttrium (Y), dysprosium (Dy), holmium (Ho), terbium (Tb), ytterbium (Yb), etc. In this case, it is possible to improve the high-temperature accelerated life and temperature characteristics of capacitance of the multilayer ceramic capacitor 1.

[0023] The thinner the dielectric layer 5, the greater the capacitance of the multilayer ceramic capacitor 1. The thickness of the dielectric layer 5 may be, for example, not less than about 0.4 μm and not more than about 10 μm.

[0024] The internal electrode layers 6 are made of a metal material, and may be made of a metal such as nickel (Ni), copper (Cu), silver (Ag), tin (Sn), platinum (Pt), palladium (Pd), or gold (Au), or an alloy containing these metals.

[0025] The internal electrode layer 6 is exposed at a first end face 17a or a second end face 17b depending on the polarity. The end of the internal electrode layer 6 exposed at the first end face 17a is covered with one of the pair of external electrodes 3, 4 (first external electrode 3) and connected to the first external electrode 3. The end of the internal electrode layer 6 exposed at the second end face 17b is covered with the other of the pair of external electrodes 3, 4 (second external electrode 4) and connected to the second external electrode 4.

[0026] As long as the characteristics of the multilayer ceramic capacitor can be ensured, the thinner the internal electrode layers 6, the more internal defects caused by internal stress during firing of the laminate 2 or during voltage application can be suppressed, improving the reliability of the multilayer ceramic capacitor 1. The thickness of the internal electrode layers 6 may be, for example, about 0.4 to 1.5 μm or less.

[0027] The first external electrode 3 and the second external electrode 4 may be made of a metal material whose main component is a metal such as Ni, Cu, Sn, Pt, Pd, Ag, or Au, or an alloy of these metals. The first external electrode 3 and the second external electrode 4 may be formed using a thick film formation technique such as a dipping method, a screen printing method, or a gravure printing method.

[0028] 2A is a diagram showing a first ceramic green sheet 30a on which a first internal electrode layer 6a is formed, FIG. 2B is a diagram showing a second green sheet 30b on which a second internal electrode layer 6b is formed, FIG. 2C is a diagram showing a third green sheet 30c on which a first conductive underlayer 13a and a third conductive underlayer 13c are formed, and FIG. 2D is a diagram showing a fourth ceramic green sheet 30d on which a ceramic pattern 5c disposed between the first conductive underlayer 13a and the second conductive underlayer 13b is formed. Note that the term "ceramic green sheet" may be abbreviated to "green sheet." The green sheets 30a to 30d may have an average thickness of, for example, about 0.5 μm to 10 μm.

[0029] First, in step S0, a raw material powder containing a dielectric material such as BaTiO3, CaTiO3, or SrTiO3, or a mixture thereof, as a main component, is prepared as the material for the dielectric layer 5. The raw material powder may contain magnesium carbonate (Mg2CO3) powder, dysprosium oxide (Dy2O3) powder, manganese carbonate (MnCO3) powder, glass powder, or the like. The glass powder may be, for example, a SiO2-BaO-CaO-based glass powder. An organic vehicle is mixed with the prepared raw material powder to prepare a ceramic slurry. The organic vehicle used to prepare the ceramic slurry may be, for example, a butyral-based resin dissolved in a solvent mixture of ethyl alcohol and toluene. The prepared ceramic slurry is formed into a green sheet material for the ceramic green sheet that will become the dielectric layer 5 by a sheet forming method such as a doctor blade method or a die coater method. The green sheet material may have an average thickness of, for example, about 0.5 μm to 10 μm.

[0030] Next, a conductive paste is prepared by kneading a powder containing Ni as the main component with an organic vehicle as the material for the internal electrode layer 6. The organic vehicle used to prepare the conductive paste may be, for example, a solution of a resin such as ethyl cellulose in a solvent mixture of a dihydroterpineol-based solvent and butyl cellosolve. The dielectric material for the dielectric layer 5, a dispersant, etc. may be added to the powder containing Ni as the main component.

[0031] Next, using a conductive paste, electrode patterns for the first internal electrode layer 6a, the second internal electrode layer 6b, the first conductive base layer 13a, and the second conductive base layer 13b, which will become the internal electrode layers 6, are printed on the main surfaces of the green sheet material, respectively, to produce green sheets 30a to 30c shown in Figures 3A to 3C. The electrode patterns can be printed using a printing method such as screen printing or gravure printing. Furthermore, using a dielectric paste made of the same material as the material for the dielectric layer 5, a third ceramic green sheet 30d on which a ceramic pattern 5a shown in Figure 3D is formed is produced.

[0032] Figure 3A is a diagram showing a ceramic paste 31a printed directly on the laminate 2, Figure 3B is a diagram showing a first base conductive layer 13a, a second base conductive layer 13b, and a ceramic pattern 31a on the laminate 2, Figure 3C is a diagram showing a ceramic green sheet 30e in which a first internal electrode layer 6a is formed on a green sheet material, Figure 3D is a diagram showing a ceramic green sheet 30f in which a second internal electrode layer 6b is formed on a green sheet material, and Figure 3E is a diagram showing a first fired dummy member 33a, a second fired dummy member 33b, and a ceramic pattern 31b printed directly on a support sheet 36.

[0033] The first fired dummy member 33a and the second fired dummy member 33b are made of a zirconia paste containing zirconia powder as a main material. Because the zirconia powder in the zirconia paste does not undergo a firing reaction with the dielectric ceramic during firing, residual zirconia powder can be easily removed from the element precursor 36a by chamfering after firing, for example, by a barreling process, and a recess can be formed between the first conductive underlayer 13a and the second conductive underlayer 13b.

[0034] FIG. 4 is a perspective view showing the mother laminate 35, FIG. 5A is a perspective view showing the state where the mother laminate 35 is cut, FIG. 5B is a perspective view showing the green body precursor 36a before firing, and FIG. 6 is a flowchart for explaining the manufacturing procedure of the multilayer ceramic capacitor 1. The manufacturing method of the multilayer ceramic capacitor 1 according to the present embodiment includes a step S0 in which the manufacturing operation is started, a step S1 in which a plurality of ceramic green sheets 30a to 30f are laminated to produce a mother laminate 35 having a first thin portion 12a for forming the first external electrode 3, a second thin portion 12b for forming the second external electrode 4, and a first underlying conductive layer 13a and a second underlying conductive layer 13b disposed on the first thin portion 12a and the second thin portion 12b, a step S2 in which the mother laminate 35 is cut to produce a plurality of green body precursors 36a that are separated into individual pieces, a step S3 in which the plurality of green body precursors 36a are fired, and a step S4 in which a first plating layer 14a and a second plating layer 14b are respectively formed on the first thin portion 12a and the second thin portion 12b of the plurality of fired green body precursors 36a on the first surface 11a and the second surface 11b of the first underlying conductive layer 13a and the third surface 11c and the fourth surface 11d of the second underlying conductive layer 13b to form the first external electrode 3 and the second external electrode 4, and a step S5 in which the manufacturing operation ends.

[0035] The thickness T1 of the first underlying conductive layer 13a and the second underlying conductive layer 13b, which are regions for forming the first external electrode 3 and the second external electrode 4, is smaller than the thickness T2 between the first virtual plane 10a and the second virtual plane 10b, which are regions where the first external electrode 3 and the second external electrode 4 are not formed (T1 < T2). As shown in FIG. 4, a conductive paste 37 is printed in the regions for forming the first external electrode 3 and the second external electrode 4, and a dielectric paste 38 is printed in the regions where the first external electrode 3 and the second external electrode 4 are not formed to produce the mother laminate 35. The mother laminate 35 is obtained by laminating and pressing the ceramic green sheets 30a to 30f shown in FIGS. 3A to 3D. The pressing may be, for example, isostatic pressing.

[0036] Even when the base laminate 35 is press-processed, the base laminate 35 includes the first fired dummy members 33a and the second fired dummy members 33b, so that the surfaces of the base laminate 35 where the first fired dummy members 33a and the second fired dummy members 33b are located do not warp or bend. The first fired dummy members 33a and the second fired dummy members 33b do not undergo a sintering reaction with the dielectric ceramic during firing, and the heated materials of the first fired dummy members 33a and the second fired dummy members 33b can be removed from the element part in a chamfering process (barreling process) after firing. Because the first fired dummy members 33a and the second fired dummy members 33b are sand-like after firing, they can be easily removed from the first and second conductive base layers 13a and 13b by barrel polishing.

[0037] When the first firing dummy member 33a and the second firing dummy member 33b are made of resin paste, the dried resin paste disappears during firing, thereby forming flat first surfaces 11a, second surfaces 11b, third surfaces 11c, and fourth surfaces 11d in the regions of the element precursor 36a where the first external electrode 3 and the second external electrode 4 are to be formed. If, for example, an epoxy resin is used as the resin paste, the epoxy resin can disappear during firing because its heat resistance temperature is 150°C to 200°C. Instead of epoxy resin, a low-temperature decomposable resin, such as an acrylic resin, may be used. The heat resistance temperature of acrylic resin is 85°C to 100°C, so it can be thermally decomposed at a lower temperature during firing and disappear reliably, thereby forming flat first surfaces 11a, second surfaces 11b, third surfaces 11c, and fourth surfaces 11d of the element precursor 36a without any deflection or warpage. This results in the first plating layer surface 15a, second plating layer surface 15b, third plating layer surface 15c, and fourth plating layer surface 15d, which become the surfaces of the first external electrode 3 and the second external electrode 4, and these can be reliably adsorbed by the suction nozzle N.

[0038] Figure 7A is a perspective view showing the element precursor 36a, Figure 7B is a cross-sectional view taken along the section line VIIB-VIIB in Figure 7A, Figure 7C is a cross-sectional view showing the laminate 2 after firing, and Figure 7D is a cross-sectional view showing the multilayer ceramic capacitor 1 in which a first plating layer 14a and a second plating layer 14b are formed on the laminate 2.

[0039] Process S1 of preparing the base laminate 35 includes the steps of printing a first fired dummy member 33a in an area on the support sheet 36 where the first external electrode 3 is to be formed, printing a first conductive paste on the first fired dummy member 33a, printing a second fired dummy member 33b in an area on the support sheet 36 where the second external electrode 4 is to be formed, printing a second conductive paste on the second fired dummy member 33b, printing a dielectric paste 38 in an area where the first external electrode 3 and the second external electrode 4 are not to be formed, and laminating green sheets 30a to 31f on which the first internal electrode layer 6a and the second internal electrode layer 6b are laid onto the base laminate 35 on which the dielectric paste 38 has been printed.

[0040] Fig. 8A is a perspective view showing a four-terminal multilayer ceramic capacitor 1a according to another embodiment of the present disclosure, Fig. 8B is a plan view of the multilayer ceramic capacitor 1a1 shown in Fig. 8A, and Fig. 8C is an enlarged cross-sectional view taken along the line VIIIC-VIIIC in Fig. 8B. Note that parts corresponding to those in the above-described embodiment are designated by the same reference numerals.

[0041] The multilayer ceramic capacitor 1a1 of this embodiment includes a base 50, a first thin portion 105, a second thin portion 106, a third thin portion 107, a fourth thin portion 108, a first external electrode 101 covering the first thin portion 105, a second external electrode 102 covering the second thin portion 106, a third external electrode 103 covering the third thin portion 107, and a fourth external electrode 104 covering the fourth thin portion 108.

[0042] The base 50 has a first surface 47a1 and a second surface 47a2 that are vertically adjacent to each other, a third surface 47b1 and a fourth surface 47b2 that are positioned symmetrically to the first surface 47a1 and the second surface 47a2 with respect to a first imaginary plane 41 that is parallel to the first surface 47a1, a fifth surface 47c1 and a sixth surface 47c2 that are positioned symmetrically to the first surface 47a1 and the second surface 47a2 with respect to a second imaginary plane 42 that is parallel to the second surface 47a2 and the fourth surface 47b2, a seventh surface 47d1 and an eighth surface 47d2 that are positioned symmetrically to the third surface 47b1 and the fourth surface 47b2 with respect to the second imaginary plane 42 and that are also positioned symmetrically to the fifth surface 47c1 and the sixth surface 47c2 with respect to the first imaginary plane 41, and a ninth surface 49a and a tenth surface 49b that are perpendicularly connected to the first surface 47a1 to the eighth surface 47d2 and face each other.

[0043] The first thin portion 105 protrudes from the first surface 47a1 and the second surface 47a2 of the base 50. The second thin portion 106 protrudes from the third surface 47b1 and the fourth surface 47b2 of the base 50. The third thin portion 107 protrudes from the fifth surface 47c1 and the sixth surface 47c2 of the base 50. The fourth thin portion 108 protrudes from the seventh surface 47d1 and the eighth surface 47d2 of the base 50.

[0044] Each of the first external electrode 101, the second external electrode 102, the third external electrode 103, and the fourth external electrode 104 is formed across a third imaginary plane 43 including the ninth surface 49a and a fourth imaginary plane 44 including the tenth surface 49b. Each of the first thin-walled portion 105, the second thin-walled portion 106, the third thin-walled portion 107, and the fourth thin-walled portion 108 has a first surface 109 facing the third imaginary plane 43 and a second surface 110 facing the fourth imaginary plane 44. Each of the first external electrode 101, the second external electrode 102, the third external electrode 103, and the fourth external electrode 104 has an underlying conductive layer 113 laminated on each of the first surface 109 and the second surface 110, and a plating layer 114 laminated between the underlying conductive layer 113 and the third imaginary plane 43, between the underlying conductive layer 113 and the fourth imaginary plane 44, and over the surface of the first thin-walled portion 105 between the first surface 109 and the second surface 110, the second thin-walled portion 106 between the first surface 109 and the second surface 110, the surface of the third thin-walled portion 107 between the first surface 109 and the second surface 110, and the surface of the fourth thin-walled portion 108 between the first surface 109 and the second surface 110. The plating layer 114 may be provided only on a part of the surface of each of the first thin portion 105 to the fourth thin portion 108 between the first surface 109 and the second surface 110.

[0045] Each of the first external electrode 101, the second external electrode 102, the third external electrode 103, and the fourth external electrode 104 has a base conductive layer 113 and a plating layer 114. Therefore, compared to the conventional multilayer ceramic capacitor 1a shown in Fig. 8A, the first to fourth external electrodes 101 to 104 of the multilayer ceramic capacitor 1a1 of this embodiment are substantially flush with the ninth surface 49a and the tenth surface 49b of the base 50, so that the area including the ninth surface 49a or the tenth surface 49b can be reliably sucked by the suction nozzle N even with a suction force lower than that of the conventional multilayer ceramic capacitor 1a.

[0046] The four external electrodes 101 to 104 of the four-terminal multilayer ceramic capacitor 1a1 of this embodiment are selectively connected to the internal electrode layers 6a, 6b that are stacked at positions where a required capacitance can be obtained. Therefore, the positions where the first thin portion 105 to the fourth thin portion 108 are formed correspond to the four corners on the diagonal when the multilayer ceramic capacitor 1a1 is viewed from above.

[0047] Fig. 9 is a perspective view showing a base laminate 135 in which a plurality of green sheets having internal electrode patterns are laminated on a support sheet 134, Fig. 10A is a perspective view showing an element precursor 136 in a state in which the base laminate 135 is cut, Fig. 10B is a perspective view showing the element precursor 136 before firing, and Fig. 10C is a cross-sectional view taken along the cutting line XC-XC in Fig. 10B. Fig. 11 is a flowchart for explaining the manufacturing procedure of the multilayer ceramic capacitor 1a1 of the embodiment shown in Fig. 8B.

[0048] The manufacturing method of the multilayer ceramic capacitor 1a1 of this embodiment starts with manufacturing operations in step S10, and includes the following steps: step S11 of stacking a plurality of ceramic green sheets on a support sheet 134 to obtain a base laminate 135 having first thin portions 105 to fourth thin portions 108 and an underlying conductive layer 113 arranged on the first thin portions 105 to fourth thin portions 108; step S12 of cutting the base laminate 135 to obtain a plurality of individual element body precursors 136; step S13 of firing the plurality of element body precursors 136; and step S14 of forming a plating layer 114 located on the surface of the underlying conductive layer 113 on the first thin portion 105, the second thin portion 106, the third thin portion 107, and the fourth thin portion 108 of the fired plurality of element body precursors 136, thereby forming a first external electrode 101, a second external electrode 102, a third external electrode 103, and a fourth external electrode 104.

[0049] The above-mentioned step S11 for obtaining the base laminate 135 includes the steps of printing first fired dummy members 137a in areas on the support sheet 134 where the first external electrodes 101 will be formed, printing a first conductive paste on the first fired dummy members 137a, printing second fired dummy members 137b in areas on the support sheet 134 where the second external electrodes 102 will be formed, printing a second conductive paste on the second fired dummy members 137b, and printing third fired dummy members 137c in areas on the support sheet 134 where the third external electrodes 103 will be formed. the step of printing a third conductive paste on the second fired dummy member 137c; the step of printing a fourth fired dummy member 137d in an area on the support sheet 134 where the fourth external electrode 104 is to be formed; the step of printing a fourth conductive paste on the fourth fired dummy member 137d; the step of printing a dielectric paste in an area where the first external electrode 101, the second external electrode 102, the third external electrode 103, and the fourth external electrode 104 are not to be formed; and the step of stacking ceramic green sheets on the base laminate 135 on which the dielectric paste has been printed.

[0050] Step S11 for obtaining the base laminate 135 includes the steps of printing first fired dummy members 137a in regions on the support sheet 134 where the first external electrodes 101 are to be formed, printing a first conductive paste on the first fired dummy members 137a, printing second fired dummy members 137b in regions on the support sheet 134 where the second external electrodes 102 are to be formed, printing a second conductive paste on the second fired dummy members 137b, and printing a second conductive paste on the second fired dummy members 137b in regions on the support sheet 134 where the third external electrodes 103 are to be formed. The method includes the steps of printing a third fired dummy member 137c, printing a third conductive paste on the third fired dummy member 137c, printing a fourth fired dummy member 137d in an area on the support sheet 134 where the fourth external electrode 104 is to be formed, printing a fourth conductive paste on the fourth fired dummy member 137d, and printing a dielectric paste in an area where the first external electrode 101, the second external electrode 102, the third external electrode 103, and the fourth external electrode 104 are not to be formed.

[0051] The mounting method for chip-type electronic components of this embodiment includes the steps of preparing the aforementioned chip-type electronic component, a multilayer ceramic capacitor 1a1, a substrate for mounting the multilayer ceramic capacitor 1a1, and a suction nozzle N for suctioning the multilayer ceramic capacitor 1a1; suctioning the ninth surface 49a, the first plating layer surface 15a, and the second plating layer surface 15b of the multilayer ceramic capacitor 1a1 with the suction nozzle N and transporting the multilayer ceramic capacitor 1a1 onto the mounting surface of the substrate; and mounting the multilayer ceramic capacitor 1a1 transported onto the mounting surface of the substrate by, for example, wire bonding or reflow heating.

[0052] In the above-described embodiments shown in FIGS. 1 to 8D, zirconia is printed on the first firing dummy member 137a and the second firing dummy member 137b. However, a resin paste may be used. The resin may be, for example, an epoxy resin or an acrylic resin. The heat resistance temperature of epoxy resin is 150°C to 200°C, so it can be removed during firing. The heat resistance temperature of acrylic resin is 85°C to 100°C, so it can be removed in a short time during firing.

[0053] According to this embodiment, the first external electrode 3 and the second external electrode 4 or the first external electrodes 101 to the fourth external electrodes 104 are formed by the underlying conductive layers 13a, 13b and the plating layers 14a, 14b so as to cover the thin portions 12a, 12b of the laminate 2, thereby providing a chip-type electronic component with improved mountability to a substrate.

[0054] The present disclosure can be implemented with the following configurations (1) to (14).

[0055] (1) A base portion having a first surface and a second surface facing each other, a third surface and a fourth surface connected to the first surface and the second surface and facing each other, and a fifth surface and a sixth surface connected to the first surface and the second surface and the third surface and the fourth surface and facing each other; a first thin portion protruding from the first surface of the base; a second thin portion protruding from the second surface of the base; a first external electrode covering the first thin portion and formed across a first imaginary plane including the fifth surface and a second imaginary plane including the sixth surface; a second external electrode covering the second thin portion and formed between the first imaginary plane and the second imaginary plane, the first thin-walled portion has a first surface facing the first imaginary plane and a second surface facing the second imaginary plane, the second thin-walled portion has a third surface facing the first imaginary plane and a fourth surface facing the second imaginary plane, the first external electrode has a first underlying conductive layer laminated on the first surface, a second underlying conductive layer laminated on the second surface, and a first plating layer laminated between the first underlying conductive layer and the first imaginary plane, between the second underlying conductive layer and the second imaginary plane, and over the surface of the first thin-walled portion between the first surface and the second surface; a second external electrode including a third conductive underlayer laminated on the third surface, a fourth conductive underlayer laminated on the fourth surface, and a second plating layer laminated between the third conductive underlayer and the first imaginary plane, between the fourth conductive underlayer and the second imaginary plane, and over the surface of the second thin-walled portion between the third surface and the fourth surface.

[0056] (2) The chip-type electronic component according to the above configuration (1), wherein the first plating layer has a first plating layer surface that is substantially coplanar with the first imaginary plane and a second plating layer surface that is substantially coplanar with the second imaginary plane, and the second plating layer has a third plating layer surface that is substantially coplanar with the first imaginary plane and a fourth plating layer surface that is substantially coplanar with the second imaginary plane.

[0057] (3) stacking a plurality of ceramic green sheets to obtain a base laminate having a first thin-walled portion for forming a first external electrode, a second thin-walled portion for forming a second external electrode, and a base conductive layer disposed on the first thin-walled portion and the second thin-walled portion; cutting the base laminate to obtain a plurality of individual element precursors; firing the plurality of element precursors; and forming a base conductive layer and a plating layer located on the surface of the base conductive layer on the first thin-walled portions and second thin-walled portions of the plurality of element body precursors after firing, thereby obtaining the first external electrodes and the second external electrodes.

[0058] (4) The step of obtaining the base laminate includes: a step of printing a first firing dummy member in an area on a support sheet where the first external electrode is to be formed; printing a first conductive paste on the first firing dummy member; printing a second firing dummy member in an area on the support sheet where the second external electrode is to be formed; printing a second conductive paste on the second firing dummy member; printing a dielectric paste on an area where the first external electrode and the second external electrode are not formed; and laminating the ceramic green sheet on the base laminate on which the dielectric paste has been printed.

[0059] (5) The method for producing chip-type electronic components according to the above configuration (4), wherein the first sintered dummy member and the second sintered dummy member are pastes containing zirconia powder as a main material.

[0060] (6) The method for producing chip-type electronic components according to the above configuration (4), wherein the first firing dummy member and the second firing dummy member are made of resin paste.

[0061] (7) preparing the chip-type electronic component according to the above configuration (2), a substrate for mounting the chip-type electronic component, and a suction nozzle for suctioning the chip-type electronic component; a step of suctioning the fifth surface, the first plating layer surface, and the second plating layer surface of the chip-type electronic component with the suction nozzle and transporting the chip-type electronic component onto a mounting surface of the substrate; and mounting the chip electronic component carried onto the mounting surface of the substrate on the mounting surface.

[0062] (8) A base having a first surface and a second surface that are perpendicularly adjacent to each other, a third surface and a fourth surface that are symmetrically positioned with respect to the first surface and the second surface with respect to a first imaginary plane that is parallel to the first surface, a fifth surface and a sixth surface that are symmetrically positioned with respect to the first surface and the second surface with respect to a second imaginary plane that is parallel to the second surface and the fourth surface, a seventh surface and an eighth surface that are symmetrically positioned with respect to the third surface and the fourth surface with respect to the second imaginary plane and that are symmetrically positioned with respect to the fifth surface and the sixth surface with respect to the first imaginary plane, and a ninth surface and a tenth surface that are perpendicularly connected to the first surface to the eighth surface and face each other; a first thin portion protruding from the first surface and the second surface of the base; a second thin portion protruding from the third surface and the fourth surface of the base; a third thin portion protruding from the fifth surface and the sixth surface of the base; a fourth thin portion protruding from the seventh surface and the eighth surface of the base; a first external electrode covering the first thin portion; a second external electrode covering the second thin portion; a third external electrode covering the third thin portion; a fourth external electrode covering the fourth thin portion, each of the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode is formed across a third imaginary plane including the ninth surface and a fourth imaginary plane including the tenth surface; each of the first thin-walled portion, the second thin-walled portion, the third thin-walled portion, and the fourth thin-walled portion has a first surface facing the third imaginary plane and a second surface facing the fourth imaginary plane; a plating layer laminated between the underlying conductive layer and the third imaginary plane, between the underlying conductive layer and the fourth imaginary plane, and over the surface of the first thin-walled portion between the first surface and the second surface, the second thin-walled portion between the first surface and the second surface, the surface of the third thin-walled portion between the first surface and the second surface, and the surface of the fourth thin-walled portion between the first surface and the second surface.

[0063] (9) A chip-type electronic component according to the above configuration (8), wherein the plating layer has a first plating layer surface that is substantially flush with the third imaginary plane and a second plating layer surface that is substantially flush with the fourth imaginary plane.

[0064] (10) A step of stacking a plurality of ceramic green sheets to obtain a base laminate having a first thin-walled portion for forming a first external electrode, a second thin-walled portion for forming a second external electrode, a third thin-walled portion for forming a third external electrode, and a fourth thin-walled portion for forming a fourth external electrode, as well as an underlying conductive layer disposed on the first thin-walled portion, the second thin-walled portion, the third thin-walled portion, and the fourth thin-walled portion; cutting the base laminate to obtain a plurality of individual element precursors; firing the plurality of element precursors; forming a plating layer located on the surface of the underlying conductive layer on the first thin-walled portion, the second thin-walled portion, the third thin-walled portion, and the fourth thin-walled portion of the plurality of element precursors after firing, thereby forming the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode.

[0065] (11) The step of obtaining the base laminate includes: a step of printing a first firing dummy member in an area on a support sheet where the first external electrode is to be formed; printing a first conductive paste on the first firing dummy member; printing a second firing dummy member in an area on the support sheet where the second external electrode is to be formed; printing a second conductive paste on the second firing dummy member; a step of printing a third fired dummy member in an area on the support sheet where the third external electrode is to be formed; printing a third conductive paste on the third firing dummy member; printing a fourth firing dummy member in an area on the support sheet where the fourth external electrode is to be formed; printing a fourth conductive paste on the fourth firing dummy member; a step of printing a dielectric paste on areas where the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode are not to be formed, to obtain a base laminate; and laminating the ceramic green sheet on the base laminate on which the dielectric paste has been printed.

[0066] (12) The chip-type electronic component according to the above configuration (10), wherein the first sintered dummy member, the second sintered dummy member, the third sintered dummy member, and the fourth sintered dummy member are pastes primarily made of zirconia powder.

[0067] (13) The method for producing a chip-type electronic component according to the above configuration (11), wherein the first firing dummy member, the second firing dummy member, the third firing dummy member, and the fourth firing dummy member are made of resin paste.

[0068] (14) A step of preparing the chip-type electronic component according to the above configuration (9), a substrate for mounting the chip-type electronic component, and a suction nozzle for suctioning the chip-type electronic component; a step of suctioning the ninth surface, the first plating layer surface, and the second plating layer surface of the chip-type electronic component with the suction nozzle and transporting the chip-type electronic component onto a mounting surface of the substrate; and mounting the chip electronic component carried onto the mounting surface of the substrate on the mounting surface.

[0069] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above-described embodiments, and various modifications and improvements are possible within the scope of the gist of the present disclosure. It goes without saying that all or part of the components constituting each of the above-described embodiments can be combined as appropriate within the scope of not contradicting each other. [Explanation of symbols]

[0070] 1,1a1 multilayer ceramic capacitor 2. Laminate 3 1st external electrode 4 2nd external electrode 5 Dielectric Layer 6 Internal electrode layer 6a 1st internal electrode layer 6b Second internal electrode layer 7a 1st page 7b 2nd side 8a 3rd page 8b Side 4 9a Page 5 9b Page 6 10a First virtual plane 10b Second virtual plane 11a 1st surface 11b 2nd surface 11c 3rd surface 11d 4th surface 12a 1st thin section 12b 2nd thin section 13a First conductive base layer 13b Second base conductive layer 14a First plating layer 14b Second plating layer 15a First plating layer surface 15b Second plating layer surface 15c Third plating layer surface 15d Fourth plating layer surface 16 base 17a First end surface 17b 2nd end face 30a~30f ceramic green sheet 31a~31e Ceramic Pattern 33a First firing dummy member 33b Second firing dummy member 34 Ceramic Paste Pattern 35 Mother laminate 36 Support Sheet 36a element precursor 37 Conductive Paste 38 Dielectric Paste 41 First virtual plane 42 Second virtual plane 43 Third virtual plane 44 Fourth virtual plane 47a1 Page 1 47a2 2nd side 47b1 3rd page 47b2 Side 4 47c1 5th page 47c2 Page 6 47d1 7th floor 47d2 Side 8 49a Page 9 49b Page 10 50 base 101 1st external electrode 102 2nd external electrode 103 Third external electrode 104 4th external electrode 105 1st thin section 106 2nd thin section 107 Third thin section 108 4th thin section 109 1st surface 110 Second surface 113 Undercoat conductive layer 114 plating layer 134 Support Sheet 135 Mother laminate 136 Prime Body Precursor 137a First firing dummy member 137b Second firing dummy member 137c Third firing dummy member 137d Fourth firing dummy member 209a 1st principal surface N suction nozzle N1 Adsorption surface

Claims

1. a substantially rectangular parallelepiped base portion having a first surface and a second surface that face each other, a third surface and a fourth surface that are connected to the first surface and the second surface and face each other, and a fifth surface and a sixth surface that are connected to the first surface, the second surface, and the third surface and the fourth surface and face each other; a first thin portion protruding from the first surface of the base; a second thin portion protruding from the second surface of the base; a first external electrode covering the first thin portion and formed across a first imaginary plane including the fifth surface and a second imaginary plane including the sixth surface; a second external electrode covering the second thin portion and formed across the first imaginary plane and the second imaginary plane, the first thin-walled portion has a first surface facing the first imaginary plane and a second surface facing the second imaginary plane, the second thin-walled portion has a third surface facing the first imaginary plane and a fourth surface facing the second imaginary plane, the first external electrode has a first underlying conductive layer laminated on the first surface, a second underlying conductive layer laminated on the second surface, and a first plating layer laminated between the first underlying conductive layer and the first imaginary plane, between the second underlying conductive layer and the second imaginary plane, and over a surface of the first thin-walled portion between the first surface and the second surface; a second external electrode including a third conductive underlayer laminated on the third surface, a fourth conductive underlayer laminated on the fourth surface, and a second plating layer laminated between the third conductive underlayer and the first imaginary plane, between the fourth conductive underlayer and the second imaginary plane, and over the surface of the second thin-walled portion between the third surface and the fourth surface.

2. the first plating layer has a first plating layer surface that is substantially flush with the first imaginary plane and a second plating layer surface that is substantially flush with the second imaginary plane, 2. The chip-type electronic component according to claim 1, wherein the second plating layer has a third plating layer surface that is substantially coplanar with the first imaginary plane and a fourth plating layer surface that is substantially coplanar with the second imaginary plane.

3. a step of stacking a plurality of ceramic green sheets to obtain a base laminate having a first thin-walled portion for forming a first external electrode, a second thin-walled portion for forming a second external electrode, and a base conductive layer disposed on the first thin-walled portion and the second thin-walled portion; cutting the base laminate to obtain a plurality of individual element precursors; firing the plurality of element precursors; and forming a plating layer located on the surface of the underlying conductive layer on the first thin-walled portions and second thin-walled portions of the plurality of element body precursors after firing, thereby obtaining the first external electrodes and the second external electrodes.

4. The step of obtaining the base laminate includes: a step of printing a first firing dummy member in an area on a support sheet where the first external electrode is to be formed; printing a first conductive paste on the first firing dummy member; printing a second firing dummy member in an area on the support sheet where the second external electrode is to be formed; printing a second conductive paste on the second firing dummy member; printing a dielectric paste on an area where the first external electrode and the second external electrode are not formed; 4. The method for producing chip-type electronic components according to claim 3, further comprising the step of laminating the ceramic green sheets onto a base laminate on which the dielectric paste has been printed.

5. 5. The method for manufacturing chip-type electronic components according to claim 4, wherein the first sintered dummy member and the second sintered dummy member are made of a paste containing zirconia powder as a main material.

6. 5. The method for manufacturing chip-type electronic components according to claim 4, wherein the first sintered dummy member and the second sintered dummy member are made of resin paste.

7. a step of preparing the chip electronic component according to claim 2, a substrate for mounting the chip electronic component, and a suction nozzle for suctioning the chip electronic component; a step of suctioning the fifth surface, the first plating layer surface, and the second plating layer surface of the chip-type electronic component with the suction nozzle and transporting the chip-type electronic component onto a mounting surface of the substrate; and mounting the chip electronic component carried onto the mounting surface of the substrate on the mounting surface.

8. a base portion having a first surface and a second surface that are perpendicularly adjacent to each other, a third surface and a fourth surface that are symmetrically positioned with respect to the first surface and the second surface with respect to a first imaginary plane that is parallel to the first surface, a fifth surface and a sixth surface that are symmetrically positioned with respect to the first surface and the second surface with respect to a second imaginary plane that is parallel to the second surface and the fourth surface, a seventh surface and an eighth surface that are symmetrically positioned with respect to the third surface and the fourth surface with respect to the second imaginary plane and that are symmetrically positioned with respect to the fifth surface and the sixth surface with respect to the first imaginary plane, and a ninth surface and a tenth surface that are perpendicularly connected to the first surface to the eighth surface and face each other; a first thin portion protruding from the first surface and the second surface of the base; a second thin portion protruding from the third surface and the fourth surface of the base; a third thin portion protruding from the fifth surface and the sixth surface of the base; a fourth thin portion protruding from the seventh surface and the eighth surface of the base; a first external electrode covering the first thin portion; a second external electrode covering the second thin portion; a third external electrode covering the third thin portion; a fourth external electrode covering the fourth thin portion, each of the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode is formed across a third imaginary plane including the ninth surface and a fourth imaginary plane including the tenth surface; each of the first thin-walled portion, the second thin-walled portion, the third thin-walled portion, and the fourth thin-walled portion has a first surface facing the third imaginary plane and a second surface facing the fourth imaginary plane; a plating layer laminated between the base conductive layer and the third imaginary plane, between the base conductive layer and the fourth imaginary plane, and over a surface of the first thin-walled portion between the first surface and the second surface, a surface of the second thin-walled portion between the first surface and the second surface, a surface of the third thin-walled portion between the first surface and the second surface, and a surface of the fourth thin-walled portion between the first surface and the second surface.

9. 9. The chip-type electronic component according to claim 8, wherein the plating layer has a first plating layer surface that is substantially flush with the third imaginary plane and a second plating layer surface that is substantially flush with the fourth imaginary plane.

10. a step of stacking a plurality of ceramic green sheets to obtain a base laminate having a first thin-walled portion for forming a first external electrode, a second thin-walled portion for forming a second external electrode, a third thin-walled portion for forming a third external electrode, and a fourth thin-walled portion for forming a fourth external electrode, as well as an underlying conductive layer disposed on the first thin-walled portion, the second thin-walled portion, the third thin-walled portion, and the fourth thin-walled portion; cutting the base laminate to obtain a plurality of individual element precursors; firing the plurality of element precursors; forming a plating layer located on the surface of the underlying conductive layer on the first thin-walled portion, the second thin-walled portion, the third thin-walled portion, and the fourth thin-walled portion of each of the plurality of element precursors after firing, thereby forming the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode.

11. The step of obtaining the base laminate includes: a step of printing a first firing dummy member in an area on a support sheet where the first external electrode is to be formed; printing a first conductive paste on the first firing dummy member; printing a second firing dummy member in an area on the support sheet where the second external electrode is to be formed; printing a second conductive paste on the second firing dummy member; printing a third firing dummy member in an area on the support sheet where the third external electrode is to be formed; printing a third conductive paste on the third firing dummy member; printing a fourth firing dummy member in an area on the support sheet where the fourth external electrode is to be formed; printing a fourth conductive paste on the fourth firing dummy member; 11. The method for manufacturing a chip-type electronic component according to claim 10, further comprising the step of printing a dielectric paste in areas where the first external electrodes, the second external electrodes, the third external electrodes, and the fourth external electrodes are not formed.

12. 12. The method for manufacturing chip-type electronic components according to claim 11, wherein the first sintered dummy member, the second sintered dummy member, the third sintered dummy member, and the fourth sintered dummy member are made of paste containing zirconia powder as a main material.

13. 12. The method for manufacturing a chip-type electronic component according to claim 11, wherein the first firing dummy member, the second firing dummy member, the third firing dummy member, and the fourth firing dummy member are made of resin paste.

14. a step of preparing the chip electronic component according to claim 9, a substrate for mounting the chip electronic component, and a suction nozzle for suctioning the chip electronic component; a step of suctioning the ninth surface, the first plating layer surface, and the second plating layer surface of the chip-type electronic component with the suction nozzle and transporting the chip-type electronic component onto a mounting surface of the substrate; and mounting the chip electronic component carried onto the mounting surface of the substrate on the mounting surface.

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