Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device suitable for reducing resistance, and a method for manufacturing the same.SOLUTION: A semiconductor device A10 includes: a semiconductor element 10; electrodes 21 located on a z1 side in a thickness direction z of the semiconductor element 10; redistribution lines 40 located on the z1 side in the thickness direction z with respect to the electrodes 21 and electrically connected to the electrodes 21; terminals 50 located on the z1 side in the thickness direction z with respect to the redistribution lines 40 and electrically connected to the redistribution lines 40; and conductive bonding layers 60 located on the z1 side in the thickness direction z with respect to the terminals 50 and electrically connected to the terminals 50. The terminal 50 includes a first terminal and a second terminal 502. The conductive bonding layer 60 includes a first conductive bonding layer electrically connected to the first terminal, and a second conductive bonding layer 602 electrically connected to the second terminal 502. When viewed in the thickness direction z, an area of the second terminal 502 is larger than that of the first terminal, and the area of the second conductive bonding layer 602 is larger than that of the first conductive bonding layer.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses an example of a semiconductor device. The semiconductor device includes a substrate having an element formation surface, pad terminals provided on the element formation surface, a passivation film covering a portion of the pad terminal and the element formation surface, Cu rewiring extending from the pad terminal, an organic coating covering the Cu rewiring, and a resin film covering the organic coating. When a large current flows through a semiconductor device having the above configuration, the resistance can be reduced by increasing the area of ​​the Cu rewiring in a planar view. However, as semiconductor devices become larger in current, even lower resistance may be required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-165335

[0004] [overview] The present disclosure has been made in light of the above circumstances, and a main object of the present disclosure is to provide a semiconductor device suitable for achieving low resistance.

[0005] A semiconductor device provided by a first aspect of the present disclosure comprises a semiconductor element, an electrode located on one side of the semiconductor element in a thickness direction, a rewiring located on one side of the electrode in the thickness direction and conductive to the electrode, a terminal located on one side of the rewiring in the thickness direction and conductive to the rewiring, and a conductive bonding layer located on one side of the terminal in the thickness direction and conductive to the terminal, wherein the terminal includes a first terminal and a second terminal, the conductive bonding layer includes a first conductive bonding layer conductive to the first terminal and a second conductive bonding layer conductive to the second terminal, and the area of ​​the second terminal is larger than the area of ​​the first terminal when viewed in the thickness direction, and the area of ​​the second conductive bonding layer is larger than the area of ​​the first conductive bonding layer when viewed in the thickness direction.

[0006] A second aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor element having an electrode disposed on one side in a thickness direction; forming a first insulating film on one side in the thickness direction of the semiconductor element, the first insulating film having a first opening exposing the electrode; forming a rewiring on the electrode and a portion of the first insulating film so that a portion of the rewiring is accommodated in the first opening of the first insulating film; forming a second insulating film on one side in the thickness direction of the rewiring, the second insulating film having a second opening and a third opening exposing a portion of the rewiring; forming a terminal on a portion of the rewiring and a portion of the second insulating film so that a portion of the rewiring is accommodated in the second opening and the third opening of the second insulating film; and forming a conductive bonding layer on the terminal, wherein the area of ​​the third opening is larger than the area of ​​the second opening when viewed in the thickness direction, and the step of forming the conductive bonding layer is performed using screen printing.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view of FIG. 1 in which the terminals and the conductive bonding layers are omitted. [Figure 3] FIG. 3 is a plan view of FIG. 2 in which the second insulating film is omitted. [Figure 4] FIG. 4 is a partially enlarged cross-sectional view taken along line IV-IV in FIG. [Figure 5] FIG. 5 is a partially enlarged cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is a cross-sectional view showing a step of an example of a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. [Figure 7] FIG. 7 is a cross-sectional view showing a step subsequent to FIG. [Figure 8] FIG. 8 is a cross-sectional view showing a step subsequent to FIG. [Figure 9] FIG. 9 is a cross-sectional view showing a step subsequent to FIG. [Figure 10] FIG. 10 is a cross-sectional view showing a step subsequent to FIG. [Figure 11] FIG. 11 is a cross-sectional view showing a step subsequent to FIG. [Figure 12] FIG. 12 is a cross-sectional view showing a step subsequent to FIG. [Figure 13] FIG. 13 is a cross-sectional view showing a step subsequent to FIG. [Figure 14] FIG. 14 is a cross-sectional view showing a step subsequent to FIG. [Figure 15] FIG. 15 is a cross-sectional view showing a step subsequent to FIG. [Figure 16] FIG. 16 is a cross-sectional view showing a step subsequent to FIG. [Figure 17] FIG. 17 is a cross-sectional view showing a step subsequent to FIG. [Figure 18] FIG. 18 is a cross-sectional view showing a step subsequent to FIG. [Figure 19] FIG. 19 is a cross-sectional view showing a step subsequent to FIG. [Figure 20] FIG. 20 is a cross-sectional view showing a step subsequent to FIG. [Figure 21]FIG. 21 is a cross-sectional view showing a step subsequent to FIG. [Figure 22] FIG. 22 is a cross-sectional view showing a step subsequent to FIG. [Figure 23] FIG. 23 is a cross-sectional view showing a step subsequent to FIG. [Figure 24] FIG. 24 is a cross-sectional view showing a step subsequent to FIG. [Figure 25] FIG. 25 is a cross-sectional view showing a step subsequent to FIG. [Figure 26] FIG. 26 is a cross-sectional view showing a step subsequent to FIG. [Figure 27] FIG. 27 is a plan view showing a semiconductor device according to the second embodiment of the present disclosure. [Figure 28] FIG. 28 is a plan view of FIG. 27 in which the terminals and the conductive bonding layers are omitted. [Figure 29] FIG. 29 is a cross-sectional view similar to FIG. 4, showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 30] FIG. 30 is a cross-sectional view similar to FIG. 5, showing a semiconductor device according to a third embodiment of the present disclosure.

[0009] [Detailed explanation] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0010] In the following, identical or similar components are denoted by the same reference numerals, and redundant explanations will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0011] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an object) B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an object) B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an object) B" includes "a certain object A is in contact with a certain object B and is located on (an object) B" and "a certain object A is located on (an object) B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "object A overlaps object B when viewed in a certain direction" includes "object A overlaps the entire object B" and "object A overlaps a part of object B." Furthermore, the phrase "object A (its material) contains material C" includes "object A (its material) is made of material C" and "object A (its material) is mainly composed of material C." Furthermore, in this disclosure, the phrase "a surface A faces direction B (on one side or the other side of direction B)" is not limited to the case where surface A is at an angle of 90° to direction B, but also includes the case where surface A is tilted with respect to direction B.

[0012] First Embodiment 1 to 5, a semiconductor device A10 according to a first embodiment of the present disclosure will be described. The semiconductor device A10 is an LSI (Large Scale Integration) known as a Wafer Level-Chip Size Package (WL-CSP). The semiconductor device A10 includes a semiconductor element 10, multiple electrodes 21, a passivation film 22, a first insulating film 31, a second insulating film 32, multiple rewirings 40, multiple terminals 50, and multiple conductive bonding layers 60.

[0013] For ease of explanation, the following will refer to the thickness direction z, the first direction x, and the second direction y, which are perpendicular to each other. The thickness direction z corresponds to the thickness direction of the semiconductor device A10. Furthermore, "plan view" refers to the view in the thickness direction z. The first direction x is perpendicular to the thickness direction z. The second direction y is perpendicular to the thickness direction z and the first direction x. One side of the thickness direction z is referred to as the z1 side of the thickness direction z, and the other side of the thickness direction z is referred to as the z2 side of the thickness direction z. Furthermore, the z1 side of the thickness direction z is sometimes referred to as the upper side, and the z2 side of the thickness direction z is sometimes referred to as the lower side. However, such terms as "upper," "lower," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component, etc. in the thickness direction z, and do not necessarily define the relationship with the direction of gravity.

[0014] FIG. 1 is a plan view of the semiconductor device A10. FIG. 2 is a plan view of the semiconductor device A10, omitting multiple terminals 50 and multiple conductive bonding layers 60. FIG. 3 is a plan view of the semiconductor device A10, omitting the second insulating film 32 compared to FIG. 2. FIG. 4 is a partially enlarged cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a partially enlarged cross-sectional view taken along line VV in FIG. 1.

[0015] As shown in FIGS. 4 and 5 , the semiconductor device 10 includes a semiconductor substrate 11 and a semiconductor layer 12 located on the z1 side of the semiconductor substrate 11 in a thickness direction z. The semiconductor device 10 has a main surface 10A facing the z1 side of the thickness direction z. The semiconductor layer 12 includes the main surface 10A. The semiconductor substrate 11 is obtained from, for example, a silicon wafer. Various semiconductor circuits, such as transistors and diodes, are configured on and near the main surface 10A of the semiconductor layer 12. The semiconductor layer 12 includes, for example, a first circuit 121 and a second circuit 122. The second circuit 122 is a switching circuit, such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). The first circuit 121 is a control circuit for driving the second circuit 122. The second circuit 122 is driven and controlled by the first circuit 121. The semiconductor device 10 is an LSI including the first circuit 121 and the second circuit 122 described above, for example.

[0016] 4 and 5, the multiple electrodes 21 are located on the z1 side in the thickness direction z of the semiconductor element 10. The multiple electrodes 21 are in contact with the main surface 10A of the semiconductor element 10 (the surface facing the z1 side in the thickness direction z). The multiple electrodes 21 are each electrically connected to various semiconductor circuits configured in the semiconductor layer 12. The multiple electrodes 21 include, for example, aluminum (Al).

[0017] As shown in FIGS. 4 and 5, the passivation film 22 covers the main surface 10A of the semiconductor element 10 and a portion of each of the multiple electrodes 21. The passivation film 22 is a thin film containing silicon dioxide (SiO2) or silicon nitride (Si3N4), or a laminate of these thin films. The passivation film 22 has multiple openings 221. The multiple openings 221 are individually arranged on the multiple electrodes 21. Each of the multiple electrodes 21 is exposed from the passivation film 22 through the corresponding opening 221.

[0018] As shown in FIGS. 4 and 5 , the first insulating film 31 is located between the semiconductor element 10 and the second insulating film 32 in the thickness direction z. The first insulating film 31 covers a portion of each of the multiple electrodes 21 and the passivation film 22. The first insulating film 31 is an insulator containing an organic compound. The organic compound includes, but is not limited to, polyimide. The first insulating film 31 includes a portion located between the passivation film 22 and the multiple rewirings 40. As shown in FIGS. 4 and 5 , the first insulating film 31 has a first opening 311 penetrating the first insulating film 31 in the thickness direction z. As viewed in the thickness direction z, the first opening 311 overlaps one of the multiple openings 221 in the passivation film 22. In the semiconductor device A10, the first opening 311 exposes one of the multiple electrodes 21. In the illustrated example, the first opening 311 is inclined with respect to the thickness direction z. The cross-sectional area of ​​the first opening 311 in a direction perpendicular to the thickness direction z decreases from the z1 side in the thickness direction z toward the z2 side in the thickness direction z.

[0019] 4 and 5, the rewirings 40 are located on the z1 side in the thickness direction z with respect to the electrodes 21. The rewirings 40 are located between the electrodes 21 and the terminals 50 in the thickness direction z. Each of the rewirings 40 is electrically connected to one of the electrodes 21.

[0020] Each of the multiple rewirings 40 includes a first base layer 40a and a first conductive layer 40b. The first base layer 40a includes a barrier layer in contact with any of the multiple electrodes 21 and the first insulating film 31, and a seed layer stacked on the barrier layer. The barrier layer includes titanium (Ti). The seed layer includes copper (Cu). The first conductive layer 40b is stacked on the seed layer of the first base layer 40a. The first conductive layer 40b includes copper. The dimension of the first conductive layer 40b in the thickness direction z is larger than the dimension of the first base layer 40a in the thickness direction z.

[0021] As shown in FIGS. 4 and 5 , each of the multiple rewirings 40 has a main portion 41 and a contact portion 42. The contact portion 42 is electrically connected to one of the multiple electrodes 21. The contact portion 42 is in contact with the first insulating film 31 and is housed in the first opening 311 of the first insulating film 31. When viewed in the thickness direction z, the entire contact portion 42 overlaps one of the multiple openings 221 of the passivation film 22. The main portion 41 is located on the opposite side of the multiple electrodes 21 in the thickness direction z, with the contact portion 42 sandwiched therebetween. The contact portion 42 is connected to the main portion 41. The main portion 41 is sandwiched between the first insulating film 31 and the second insulating film 32.

[0022] As shown in FIGS. 3 to 5, the main portion 41 (rewiring 40) includes a first wiring portion 411 and a second wiring portion 412. The first wiring portion 411 is a wiring portion that is electrically connected between the contact portion 42 and the terminal 50. The first wiring portion 411 includes a portion that overlaps one terminal 50 as viewed in the thickness direction z. The second wiring portion 412 is connected to the first wiring portion 411. The second wiring portion 412 is a wiring portion that overlaps multiple terminals 50 as viewed in the thickness direction z. In FIG. 3, the second wiring portion 412 is hatched. In the illustrated example, the second wiring portion 412 is provided over a wide range as viewed in the thickness direction z. In the semiconductor device A10, one of the multiple rewirings 40 includes the first wiring portion 411 and the second wiring portion 412. The remaining multiple rewirings 40 include only the first wiring portion 411 and do not include the second wiring portion 412.

[0023] 1, 3, and 4, the first wiring portion 411 (the rewiring 40 including only the first wiring portion 411) is electrically connected to the first circuit 121 of the semiconductor element 10 via the electrode 21. As shown in FIGS. 1, 3, and 5, the second wiring portion 412 is electrically connected to the second circuit 122 of the semiconductor element 10 via the first wiring portion 411 and the electrode 21.

[0024] As shown in FIGS. 4 and 5 , the second insulating film 32 is located on the z1 side in the thickness direction z with respect to the first insulating film 31. The second insulating film 32 covers the first insulating film 31 and the multiple rewirings 40. The second insulating film 32 is an insulator containing an organic compound. The second insulating film 32 contains, for example, polyimide. In the semiconductor device A10, the composition of the second insulating film 32 is the same as the composition of the first insulating film 31. The second insulating film 32 may contain polyamide, polybenzoxazole, phenolic resin, or the like instead of polyimide.

[0025] The second insulating film 32 is in contact with the multiple terminals 50. As shown in FIG. 4, a dimension t2 of the second insulating film 32 in the thickness direction z is larger than a dimension t1 of the first insulating film 31 in the thickness direction z. As shown in FIGS. 2, 4, and 5, the second insulating film 32 has multiple second openings 321 and multiple third openings 322, each penetrating the second insulating film 32 in the thickness direction z. The second opening 321 exposes the main portion 41 (first wiring portion 411) of one of the multiple rewirings 40 (the rewiring 40 including only the first wiring portion 411). The second opening 321 accommodates a portion of one of the multiple terminals 50. The second opening 321 exposes the main portion 41 (second wiring portion 412) of one of the multiple rewirings 40 (the rewiring 40 including the first wiring portion 411 and the second wiring portion 412). As shown in FIGS. 2, 4, and 5, the area of ​​the third opening 322 is larger than the area of ​​the second opening 321 when viewed in the thickness direction z. In the illustrated example, the second opening 321 and the third opening 322 are inclined with respect to the thickness direction z. The cross-sectional area of ​​each of the second opening 321 and the third opening 322 in a direction perpendicular to the thickness direction z decreases from the z1 side in the thickness direction z toward the z2 side in the thickness direction z.

[0026] 4 and 5, each of the multiple terminals 50 is located on the opposite side of the semiconductor element 10 in the thickness direction z with respect to the multiple electrodes 21 and the multiple rewirings 40. Each of the multiple terminals 50 is electrically connected to one of the main portions 41 (first wiring portion 411 or second wiring portion 412) of the multiple rewirings 40. As a result, each of the multiple terminals 50 is electrically connected to one of the multiple electrodes 21. Each of the multiple terminals 50 is located on the z1 side in the thickness direction z with respect to the rewirings 40 connected to it.

[0027] Each of the multiple terminals 50 includes a second base layer 50a and a second conductive layer 50b. The second base layer 50a includes a barrier layer in contact with any of the rewirings 40 (main portions 41) and the second insulating film 32, and a seed layer stacked on the barrier layer. The barrier layer contains titanium. The seed layer contains copper. The second conductive layer 50b is stacked on the seed layer of the second base layer 50a. The second conductive layer 50b contains copper. The dimension of the second conductive layer 50b in the thickness direction z is larger than the dimension of the second base layer 50a in the thickness direction z.

[0028] The multiple terminals 50 include multiple first terminals 501 and multiple second terminals 502. As shown in FIG. 4, the first terminal 501 is connected to the first wiring portion 411. The first terminal 501 is electrically connected to the first circuit 121 of the semiconductor element 10 via the first wiring portion 411 and the electrode 21. As shown in FIG. 5, the second terminal 502 is connected to the second wiring portion 412. The second terminal 502 is electrically connected to the second circuit 122 of the semiconductor element 10 via the second wiring portion 412, the first wiring portion 411, and the electrode 21. In this embodiment, as shown in FIGS. 1 and 5, multiple second terminals 502 (eight second terminals 502 in the example shown in FIG. 1) are connected to the second wiring portion 412.

[0029] 1 and 5, the first terminals 501 are appropriately arranged in the first direction x and the second direction y when viewed in the thickness direction z. Each of the first terminals 501 has a substantially circular shape when viewed in the thickness direction z.

[0030] 1 , each of the multiple second terminals 502 extends in a first direction x or a second direction y when viewed in the thickness direction z. When viewed in the thickness direction z, the area of ​​the second terminal 502 is larger than the area of ​​the first terminal 501. A length L2 in the first direction x of the second terminal 502 extending in the first direction x is at least twice the length L1 in the first direction x of the first terminal 501. Furthermore, a length L4 in the second direction y of the second terminal 502 extending in the second direction y is at least twice the length L3 in the second direction y of the first terminal 501. In the illustrated example, the length L2 in the first direction x of the second terminal 502 extending in the first direction x is approximately 3.9 times the length L1 in the first direction x of the first terminal 501. Furthermore, the length L4 in the second direction y of the second terminal 502 extending in the second direction y is about 2.4 to about 3.9 times the length L3 in the second direction y of the first terminal 501. Note that the ratio of the length L2 in the first direction x of the second terminal 502 to the length L1 in the first direction x of the first terminal 501 and the ratio of the length L4 in the second direction y of the second terminal 502 to the length L3 in the second direction y of the first terminal 501 are not limited to the above.

[0031] 4, the first terminal 501 includes a first portion 51 and a second portion 52. The first portion 51 is housed in the second opening 321 of the second insulating film 32. The second portion 52 is connected to the first portion 51 and protrudes from the second opening 321. When viewed in the thickness direction z, the second portion 52 protrudes outward beyond the second opening 321.

[0032] 5, the second terminal 502 includes a third portion 53 and a fourth portion 54. The third portion 53 is housed in the third opening 322 of the second insulating film 32. The fourth portion 54 is connected to the third portion 53 and protrudes from the third opening 322. When viewed in the thickness direction z, the fourth portion 54 protrudes outward beyond the third opening 322.

[0033] 1, 3, and 4, the first terminal 501 is electrically connected to the first circuit 121 of the semiconductor element 10 via the first wiring portion 411 (the rewiring 40 including only the first wiring portion 411) and the electrode 21. As shown in FIGS. 1, 3, and 5, the second terminal 502 is electrically connected to the second circuit 122 of the semiconductor element 10 via the second wiring portion 412, the first wiring portion 411, and the electrode 21.

[0034] As shown in Figures 4 and 5, the multiple conductive bonding layers 60 are located on the z1 side of the multiple terminals 50 in the thickness direction z. The multiple conductive bonding layers 60 are individually connected to the multiple terminals 50. The multiple conductive bonding layers 60 include metal. The multiple conductive bonding layers 60 are, for example, solder. The multiple conductive bonding layers 60 are made of a material including tin (Sn). The melting points of the multiple conductive bonding layers 60 are lower than the melting points of the multiple terminals 50. The upper surface of the conductive bonding layer 60 (the surface facing the z1 side in the thickness direction z) is curved. Note that the shape of the conductive bonding layer 60 is not limited to the example shown in the figures.

[0035] The plurality of conductive bonding layers 60 include a plurality of first conductive bonding layers 601 and a plurality of second conductive bonding layers 602. The plurality of first conductive bonding layers 601 are individually electrically connected to the plurality of first terminals 501. The plurality of second conductive bonding layers 602 are individually electrically connected to the plurality of second terminals 502. Each of the plurality of first conductive bonding layers 601 entirely overlaps the corresponding first terminal 501. Each of the plurality of second conductive bonding layers 602 entirely overlaps the corresponding second terminal 502. As shown in FIGS. 1 and 4, each of the plurality of first conductive bonding layers 601 has a substantially circular shape when viewed in the thickness direction z and is substantially the same shape and size as the first terminal 501. As shown in FIGS. 1 and 5, each of the plurality of second conductive bonding layers 602 has substantially the same shape and size as the corresponding second terminal 502 when viewed in the thickness direction z.

[0036] 1 , each of the multiple second conductive bonding layers 602 extends in the first direction x or the second direction y when viewed in the thickness direction z. The area of ​​the second conductive bonding layer 602 is larger than the area of ​​the first conductive bonding layer 601 when viewed in the thickness direction z. The length L2 of the second conductive bonding layer 602 in the first direction x is at least twice the length L1 of the first conductive bonding layer 601 in the first direction x. The length L4 of the second conductive bonding layer 602 in the second direction y is at least twice the length L3 of the first conductive bonding layer 601 in the second direction y. In the illustrated example, the length L2 of the second conductive bonding layer 602 in the first direction x is approximately 3.9 times the length L1 of the first conductive bonding layer 601 in the first direction x. Furthermore, the length L4 in the second direction y of the second conductive bonding layer 602 extending in the second direction y is about 2.4 to about 3.9 times the length L3 in the second direction y of the first conductive bonding layer 601. Note that the ratio of the length L2 in the first direction x of the first conductive bonding layer 601 to the length L1 in the first direction x of the first conductive bonding layer 601 and the ratio of the length L4 in the second direction y of the second conductive bonding layer 602 to the length L3 in the second direction y of the first conductive bonding layer 601 are not limited to the above.

[0037] Next, an example of a method for manufacturing the semiconductor device A10 will be described below with reference to Figures 6 to 26. Figures 6 to 26 are partially enlarged cross-sectional views showing one step of the method for manufacturing the semiconductor device A10. Figures 6 to 9, 11 to 13, 15, 17, 19, 21, 23, and 25 correspond to the cross section shown in Figure 5. Figures 10, 14, 16, 18, 20, 22, 24, and 26 correspond to the cross section shown in Figure 4.

[0038] First, as shown in FIG. 6 , a semiconductor element 10 is prepared. Here, the semiconductor element 10 corresponds to one element of a silicon wafer. A plurality of electrodes 21 and a passivation film 22 are arranged on the z1 side of the semiconductor element 10 in the thickness direction z. Next, as shown in FIG. 7 , a first insulating film 31 is formed on the z1 side of the semiconductor element 10 in the thickness direction z. The first insulating film 31 is formed by applying photosensitive polyimide to the passivation film 22, for example, by spin coating, and then curing the applied polyimide through lithographic patterning. A plurality of first openings 311 are formed in the first insulating film 31 by lithographic patterning. The plurality of first openings 311 expose portions of each of the plurality of electrodes 21. The method for forming the first insulating film 31 can be appropriately changed depending on the material of the first insulating film 31 used. In the illustrated example, the first openings 311 are inclined with respect to the thickness direction z, but this is not limiting. Depending on the method for forming the first opening 311, the first opening 311 may have a shape that follows the thickness direction z and is not inclined with respect to the thickness direction z.

[0039] Next, as shown in FIG. 8, a first underlayer 40a is formed. The first underlayer 40a can be formed by, for example, but not limited to, a spin coating method. For example, a sputtering method can also be used. Through this process, the entire first insulating film 31, as well as parts of the passivation film 22 and the electrodes 21 exposed by each of the first openings 311 in the first insulating film 31, are covered with the first underlayer 40a. In other words, the entire upper surface (the surface facing the z1 side in the thickness direction z) of the semiconductor device A10 in the process of fabrication shown in FIG. 7 is covered with the first underlayer 40a. In forming the first underlayer 40a, a barrier layer containing, for example, titanium may be formed first, and then a seed layer containing copper may be formed.

[0040] Next, as shown in FIGS. 9 to 11, the first conductive layer 40b is formed. To form the first conductive layer 40b, first, as shown in FIGS. 9 and 10, a first resist 81 is applied to the first base layer 40a, and then the first resist 81 is lithographically patterned. This results in a plurality of openings 811 penetrating the first resist 81 in the thickness direction z. Next, as shown in FIG. 11, the first conductive layer 40b is deposited by electrolytic plating using the first base layer 40a as a conductive path. The first conductive layer 40b contains, for example, copper. As a result of the above, a plurality of first conductive layers 40b are formed, each individually accommodated in a plurality of openings 811.

[0041] 12, after removing the first resist 81, the region of the first base layer 40a exposed from the first conductive layer 40b is removed. The first base layer 40a is removed by wet etching using a mixed solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2), for example. As shown in FIG. 12, the first conductive layer 40b is partially contained in the first opening 311 and is formed on a portion of the first insulating film 31 and on the electrode 21. This completes the formation of the multiple rewirings 40.

[0042] Next, as shown in FIGS. 13 and 14 , the second insulating film 32 is formed. The second insulating film 32 is formed by applying a material containing photosensitive polyimide to the plurality of rewirings 40 and the first insulating film 31 exposed from the plurality of rewirings 40, followed by lithographic patterning and curing. By lithographic patterning, a plurality of second openings 321 and a plurality of third openings 322 are formed in the second insulating film 32. Here, the area of ​​the third opening 322 is larger than the area of ​​the second opening 321 when viewed in the thickness direction z. As shown in FIG. 14 , a portion of the rewirings 40 (a portion of the first wiring portion 411) is exposed from the second opening 321. Furthermore, as shown in FIG. 13 , a portion of the rewirings 40 (a portion of the second wiring portion 412) is exposed from the third opening 322. The method for forming the second insulating film 32 can be appropriately changed depending on the material of the second insulating film 32 used. In the illustrated example, the second opening 321 and the third opening 322 are inclined with respect to the thickness direction z, but this is not limiting. Depending on the method for forming the second opening 321 and the third opening 322, the second opening 321 and the third opening 322 may have a shape that follows the thickness direction z and not be inclined with respect to the thickness direction z.

[0043] Next, as shown in FIGS. 15 and 16 , a second underlayer 50a is formed. The second underlayer 50a can be formed by, for example, but not limited to, a sputtering method. This process covers the entire second insulating film 32 and portions of the rewirings 40 (portions of the first wiring portion 411 and the second wiring portion 412) exposed through the second openings 321 and the third openings 322 of the second insulating film 32. That is, the entire upper surface (the surface facing the z1 side in the thickness direction z) of the semiconductor device A10 in the process of fabrication shown in FIGS. 13 and 14 is covered with the second underlayer 50a. In forming the second underlayer 50a, a barrier layer containing, for example, titanium may be formed first, followed by a seed layer containing copper.

[0044] Next, as shown in FIGS. 17 to 20, the second conductive layer 50b is formed. To form the second conductive layer 50b, first, as shown in FIGS. 17 and 18, a second resist 82 is applied to the second base layer 50a, and then the second resist 82 is lithographically patterned. This results in a plurality of openings 821 penetrating the second resist 82 in the thickness direction z. Next, the second conductive layer 50b is deposited by electrolytic plating using the second base layer 50a as a conductive path. The second conductive layer 50b contains, for example, copper. As a result of the above, a plurality of second conductive layers 50b are formed, each individually accommodated in a plurality of openings 821.

[0045] 19 and 20, after removing the second resist 82, the regions of the second base layer 50a exposed from the plurality of second conductive layers 50b are removed. The second base layer 50a is removed by wet etching using, for example, a mixed solution of sulfuric acid and hydrogen peroxide. This forms the plurality of terminals 50 (the plurality of first terminals 501 and the plurality of second terminals 502).

[0046] Next, a plurality of conductive bonding layers 60 are formed. To form the plurality of conductive bonding layers 60, first, as shown in FIGS. 21 and 22 , a screen 91 is placed on the z1 side of the plurality of terminals 50 in the thickness direction z. The screen 91 is a metal plate (metal mask) in which a plurality of slits 911 and a plurality of slits 912, which are openings penetrating in the thickness direction z, are formed. The slits 911 have a shape and size corresponding to the first terminals 501 when viewed in the thickness direction z. The slits 912 have a shape and size corresponding to the second terminals 502 when viewed in the thickness direction z.

[0047] Next, as shown in FIGS. 23 and 24, a solder-containing material (conductive bonding layer 60) is printed on the multiple terminals 50 using a screen printing technique. As a result, the first conductive bonding layer 601 is positioned only at the position that passes through the slit 911 on the first terminal 501. The second conductive bonding layer 602 is positioned only at the position that passes through the slit 912 on the second terminal 502. Thereafter, the screen 91 is removed. The first conductive bonding layer 601 and the second conductive bonding layer 602 positioned as described above have their tips on the z1 side in the thickness direction z at the same position in the thickness direction z. Note that "screen printing" includes both the use of a metal mask and the use of a mesh screen.

[0048] Next, the conductive bonding layer 60 (first conductive bonding layer 601 and second conductive bonding layer 602) made of a material containing solder is melted by reflow. Finally, the melted material is hardened. As a result, as shown in FIGS. 25 and 26, a plurality of conductive bonding layers 60 (a plurality of first conductive bonding layers 601 and a plurality of second conductive bonding layers 602) are formed, which are individually arranged on a plurality of terminals 50 (a plurality of first terminals 501 and a plurality of second terminals 502).

[0049] Finally, the semiconductor element 10, which is one element of the silicon wafer, is divided into individual pieces by blade dicing or the like. Through the above steps, the semiconductor device A10 is manufactured. Note that the above-described manufacturing method for the semiconductor device A10 is an example, and is not limited to this.

[0050] When the semiconductor device A10 is in use, the semiconductor device A10 is surface-mounted on, for example, a circuit board (not shown). Each of the multiple terminals 50 of the semiconductor device A10 is conductively bonded to a conductive portion of the circuit board via one of multiple conductive bonding layers 60. This allows the multiple electrodes 21 of the semiconductor device A10 to be electrically connected to the conductive portion of the circuit board.

[0051] Next, the effects of the semiconductor device A10 will be described.

[0052] The semiconductor device A10 includes a semiconductor element 10, an electrode 21, rewiring 40, a terminal 50, and a conductive bonding layer 60. The electrode 21 is located on the z1 side of the semiconductor element 10 in the thickness direction z. The rewiring 40 is located on the z1 side of the electrode 21 in the thickness direction z and is electrically connected to the electrode 21. The terminal 50 is located on the z1 side of the rewiring 40 in the thickness direction z and is electrically connected to the rewiring 40. The terminal 50 and the conductive bonding layer 60 form a conductive path between the semiconductor element 10 and a circuit board or the like on which the semiconductor device A10 is mounted. The terminal 50 includes a first terminal 501 and a second terminal 502, and the conductive bonding layer 60 includes a first conductive bonding layer 601 and a second conductive bonding layer 602. The area of ​​the second terminal 502 is larger than the area of ​​the first terminal 501 in the thickness direction z. Furthermore, the area of ​​the second conductive bonding layer 602 is larger than the area of ​​the first conductive bonding layer 601 when viewed in the thickness direction z. With this configuration, in the terminal 50 that forms a conductive path between the semiconductor element 10 and the outside (such as a circuit board), the second terminal 502 can have a lower resistance than the first terminal 501. Furthermore, the second conductive bonding layer 602 that forms the conductive path can have a lower resistance than the first conductive bonding layer 601. Therefore, even when a large current flows in the semiconductor device A10, it is possible to improve the low resistance of the semiconductor device A10.

[0053] The second terminal 502 and the second conductive bonding layer 602 extend in a first direction x that is perpendicular to the thickness direction z. The length L2 of the second terminal 502 in the first direction x is at least twice the length L1 of the first terminal 501 in the first direction x. Furthermore, the length L2 of the second conductive bonding layer 602 in the first direction x is at least twice the length L1 of the first conductive bonding layer 601 in the first direction x. With this configuration, it is possible to appropriately reduce the resistance of the second terminal 502 and the second conductive bonding layer 602 compared to the first terminal 501 and the first conductive bonding layer 601.

[0054] The semiconductor device 10 has a first circuit 121 and a second circuit 122. The first terminal 501 is electrically connected to the first circuit 121, and the second terminal 502 is electrically connected to the second circuit 122. The second circuit 122 is driven and controlled by the first circuit 121. The second circuit 122 is, for example, a switching circuit, and a large current can flow through the second terminal 502 and the second conductive bonding layer 602 that are electrically connected to the second circuit 122. With this configuration, it is possible to efficiently reduce the resistance of the second terminal 502 and the second conductive bonding layer 602, through which a large current can flow.

[0055] In the manufacture of the semiconductor device A10, the step of forming the conductive bonding layer 60 is performed using screen printing. With this configuration, the height positions (positions of the tips on the z1 side in the thickness direction z) of the first conductive bonding layer 601 and the second conductive bonding layer 602, which have different areas in the thickness direction z, can be aligned. This improves mounting reliability when the semiconductor device A10 is mounted on a circuit board or the like via the multiple conductive bonding layers 60 (the multiple first conductive bonding layers 601 and the multiple second conductive bonding layers 602).

[0056] 27 to 30 show other embodiments of the semiconductor device of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals as in the above-described embodiment, and redundant explanations will be omitted. Furthermore, the configurations of the various parts in each embodiment can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0057] Second Embodiment 27 and 28 show a semiconductor device A20 according to a second embodiment of the present disclosure. Fig. 27 is a plan view of the semiconductor device A20. Fig. 28 is a plan view of the semiconductor device A20, in which the terminals 50 and the conductive bonding layers 60 are omitted.

[0058] The semiconductor device A20 includes a plurality of second terminals 502 and a plurality of second conductive bonding layers 602 that have larger areas in the thickness direction z than the semiconductor device A10 of the above embodiment. The second terminals 502 and the second conductive bonding layers 602 located near the center of the semiconductor device A10 in the first direction x and the second direction y in the thickness direction z have rectangular shapes extending in the first direction x and the second direction y. The length L2 of the second terminals 502 and the second conductive bonding layers 602 in the first direction x is at least twice the length L1 of the first terminals 501 and the first conductive bonding layer 601 in the first direction x, and the length L4 of the second terminals 502 and the second conductive bonding layer 602 in the second direction y is at least twice the length L3 of the first terminals 501 and the first conductive bonding layer 601 in the second direction y. In the illustrated example, the length L2 in the first direction x of the second terminal 502 and the second conductive bonding layer 602 located near the center in the first direction x and the second direction y is approximately 2.4 to 3.9 times the length L1 in the first direction x of the first terminal 501 and the first conductive bonding layer 601, and the length L4 in the second direction y of the second terminal 502 and the second conductive bonding layer 602 is approximately 2.4 to 3.9 times the length L3 in the second direction y of the first terminal 501 and the first conductive bonding layer 601.

[0059] In the semiconductor device A20, the area of ​​the second terminal 502 is larger than the area of ​​the first terminal 501 when viewed in the thickness direction z. Furthermore, the area of ​​the second conductive bonding layer 602 is larger than the area of ​​the first conductive bonding layer 601 when viewed in the thickness direction z. With this configuration, in the terminal 50 that forms a conductive path between the semiconductor element 10 and the outside (such as a circuit board), the second terminal 502 can have a lower resistance than the first terminal 501. Furthermore, the second conductive bonding layer 602 that forms the conductive path can have a lower resistance than the first conductive bonding layer 601. Therefore, even when a large current flows in the semiconductor device A20, it is possible to improve the low resistance of the semiconductor device A20.

[0060] Furthermore, the semiconductor device A20 includes a plurality of first terminals 501 and a plurality of second conductive bonding layers 602 each having a larger area in the thickness direction z. In the semiconductor device A20, some of the plurality of second terminals 502 and the plurality of second conductive bonding layers 602 have a length L2 in the first direction x that is at least twice the length L1 of the first terminals 501 and the first conductive bonding layers 601 in the first direction x, and a length L4 in the second direction y that is at least twice the length L3 of the first terminals 501 and the first conductive bonding layers 601 in the second direction y. This configuration allows the resistance of the second terminals 502 and the second conductive bonding layers 602 to be more efficiently reduced. Furthermore, the semiconductor device A20, by incorporating a configuration common to the semiconductor device A10, achieves the same effects as the semiconductor device A10.

[0061] Third Embodiment Figures 29 and 30 show a semiconductor device A30 according to a third embodiment of the present disclosure. Figures 29 and 30 are partially enlarged cross-sectional views of the semiconductor device A30. Figure 29 corresponds to the cross section shown in Figure 4, and Figure 30 corresponds to the cross section shown in Figure 5.

[0062] The semiconductor device A30 differs from the semiconductor device A10 of the above embodiment in that a third insulating film 33 is further provided.

[0063] The third insulating film 33 is located on the opposite side of the semiconductor element 10 from the plurality of electrodes 21 in the thickness direction z. The third insulating film 33 covers the z2 side of the semiconductor element 10 in the thickness direction z. The third insulating film 33 is made of, for example, an insulating resin sheet.

[0064] In the semiconductor device A30, the area of ​​the second terminal 502 is larger than the area of ​​the first terminal 501 when viewed in the thickness direction z. Furthermore, the area of ​​the second conductive bonding layer 602 is larger than the area of ​​the first conductive bonding layer 601 when viewed in the thickness direction z. With this configuration, in the terminal 50 that forms a conductive path between the semiconductor element 10 and the outside (such as a circuit board), the second terminal 502 can have a lower resistance than the first terminal 501. Furthermore, the second conductive bonding layer 602 that forms the conductive path can have a lower resistance than the first conductive bonding layer 601. Therefore, even when a large current flows in the semiconductor device A30, it is possible to improve the low resistance of the semiconductor device A30.

[0065] The semiconductor device A30 further includes a third insulating film 33. The third insulating film 33 covers the z2 side of the semiconductor element 10 in the thickness direction z. This allows the semiconductor element 10 (semiconductor device A30) to be appropriately protected. In addition, the semiconductor device A30 has a configuration in common with the semiconductor device A10, and thereby achieves the same effects as the semiconductor device A10.

[0066] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways. In the above-described embodiment, the semiconductor devices A10 to A30 are configured as WL-CSPs, but the present disclosure is not limited to this. The semiconductor device according to the present disclosure may be, for example, a resin package type semiconductor device sealed with mold resin.

[0067] The present disclosure includes configurations relating to the following notes. [Appendix 1] A semiconductor element (10), an electrode (21) located on one side (z1 side) in the thickness direction (z) of the semiconductor element (10); a rewiring (40) located on one side (z1 side) of the electrode (21) in the thickness direction (z) and electrically connected to the electrode (21); a terminal (50) located on one side (z1 side) of the rewiring (40) in the thickness direction (z) and electrically connected to the rewiring (40); a conductive bonding layer (60) located on one side (z1 side) of the terminal (50) in the thickness direction (z) and electrically connected to the terminal (50), The terminal (50) includes a first terminal (501) and a second terminal (502), the conductive bonding layer (60) includes a first conductive bonding layer (601) electrically connected to the first terminal (501) and a second conductive bonding layer (602) electrically connected to the second terminal (502); When viewed in the thickness direction (z), the area of ​​the second terminal (502) is larger than the area of ​​the first terminal (501), A semiconductor device (A10), wherein the area of ​​the second conductive bonding layer (602) is larger than the area of ​​the first conductive bonding layer (601) when viewed in the thickness direction (z). [Appendix 2] The semiconductor device (A10) according to Appendix 1, wherein the second conductive bonding layer (602) overlaps the entire first terminal (501) when viewed in the thickness direction (z). [Appendix 3] the second terminal (502) and the second conductive bonding layer (602) extend in a first direction (x) perpendicular to the thickness direction (z); The length of the second terminal (502) in the first direction (x) is at least twice the length of the first terminal (501) in the first direction (x), A semiconductor device (A10) described in Appendix 1 or 2, wherein the length of the second conductive bonding layer (602) in the first direction (x) is at least twice the length of the first conductive bonding layer (601) in the first direction (x). [Appendix 4] The length of the second terminal (502) in a first direction (x) perpendicular to the thickness direction (z) is at least twice the length of the first terminal in the first direction, the length of the second terminal (502) in a second direction (y) perpendicular to the thickness direction and the first direction (x) is at least twice the length of the second terminal (502) in the second direction (y); The length of the second conductive bonding layer (602) in the first direction (x) is at least twice the length of the first conductive bonding layer (601) in the first direction (x), A semiconductor device (A20) described in Appendix 1 or 2, wherein the length of the second conductive bonding layer (602) in the second direction (y) is at least twice the length of the first conductive bonding layer (601) in the second direction (y). [Appendix 5] The semiconductor device (A10) according to any one of appendices 1 to 4, wherein the conductive bonding layer (60) is made of a material containing tin. [Appendix 6] The semiconductor device further includes a first insulating film (31) located between the semiconductor element (10) and the rewiring (40) in the thickness direction (z), The first insulating film (31) has a first opening (311) that penetrates in the thickness direction (z) and exposes the electrode (21), The semiconductor device (A10) according to any one of appendixes 1 to 5, wherein a portion of the rewiring (40) is housed in the first opening (311). [Appendix 7] a second insulating film (32) located on one side (z1 side) of the first insulating film (31) in the thickness direction (z) and covering the rewiring (40); The second insulating film (32) is provided with a second opening (321) and a third opening (322) that penetrate the second insulating film (32) in the thickness direction (z) and expose the rewiring (40), A portion of the first terminal (501) is accommodated in the second opening (321), The semiconductor device (A10) according to Appendix 6, wherein a portion of the second terminal (502) is housed in the third opening (322). [Appendix 8] The semiconductor device (A10) according to appendix 7, wherein the area of ​​the third opening (322) is larger than the area of ​​the second opening (321) as viewed in the thickness direction (z). [Appendix 9] The semiconductor device (A10) according to appendix 7 or 8, wherein the dimension of the second insulating film (32) in the thickness direction (z) is larger than the dimension of the first insulating film (31) in the thickness direction (z). [Appendix 10] The first terminal (501) includes a first portion (51) accommodated in the second opening (321) and a second portion (52) protruding from the second opening (321), The semiconductor device (A10) according to any one of appendices 7 to 9, wherein the second portion (52) protrudes outward beyond the second opening (321) when viewed in the thickness direction (z). [Appendix 11] the second terminal (502) includes a third portion (53) accommodated in the third opening (322) and a fourth portion (54) protruding from the third opening (322); The semiconductor device (A10) according to any one of appendices 7 to 10, wherein the fourth portion (54) protrudes outward beyond the third opening (322) when viewed in the thickness direction (z). [Appendix 12] A semiconductor device (A10) according to any one of Appendices 7 to 11, wherein the rewiring (40) includes a first base layer (40a) in contact with the electrode (21) and the first insulating film (31), and a first conductive layer (40b) stacked on the first base layer (40a). [Appendix 13] The semiconductor device (A10) described in Appendix 12, wherein the terminal (50) includes a second base layer (50a) in contact with the rewiring (40) and the second insulating film (32), and a second conductive layer (50b) stacked on the second base layer (50a). [Appendix 14] The semiconductor device (A30) according to any one of appendices 1 to 13, further comprising a third insulating film (33) covering the other side (z2 side) of the semiconductor element (10) in the thickness direction (z). [Appendix 15] A step of preparing a semiconductor element (10) having an electrode (21) disposed on one side (z1 side) in the thickness direction (z); forming a first insulating film (31) having a first opening (311) exposing the electrode (21) on one side (z1 side) in the thickness direction (z) of the semiconductor element (10); forming a rewiring (40) on the electrode (21) and a part of the first insulating film (31) so that a part of the rewiring is accommodated in the first opening (311) of the first insulating film (31); forming a second insulating film (32) having a second opening (321) and a third opening (322) exposing a part of the rewiring (40) on one side (z1 side) of the rewiring (40) in the thickness direction (z); forming a terminal (50) on a part of the rewiring (40) and a part of the second insulating film (32) so that a part of the terminal is accommodated in the second opening (321) and the third opening (322) of the second insulating film (32); and forming a conductive bonding layer (60) on the terminal (50), When viewed in the thickness direction (z), the area of ​​the third opening (322) is larger than the area of ​​the second opening (321); A method for manufacturing a semiconductor device (A10), wherein the step of forming the conductive bonding layer (60) is performed by screen printing. [Appendix 16] The semiconductor element (10) has a first circuit (121) and a second circuit (122) that is driven and controlled by the first circuit (121), A semiconductor device (A10) according to any one of Appendices 1 to 14, wherein the first terminal (501) is electrically connected to the first circuit (121), and the second terminal (502) is electrically connected to the second circuit (122). [Explanation of symbols]

[0068] A10, A20, A30: Semiconductor device 10: Semiconductor element 10A: Main surface 11: Semiconductor substrate 12: Semiconductor layer 121: 1st circuit 122: 2nd circuit 21: Electrode 22: Passivation film 221 :Aperture 31: First insulating film 311: First opening 32: Second insulating film 321: Second opening 322: Third opening 33: Third insulating film 40: Rewiring 40a: 1st base layer 40b: First conductive layer 41: Main section 411: 1st wiring section 412: 2nd wiring section 42: Contact part 50: Terminal 50a: Second base layer 50b: Second conductive layer 501: 1st terminal 502: 2nd terminal 51: Part 1 52: Part 2 53: Part 3 54: Part 4 60: Conductive bonding layer 601: First conductive bonding layer 602: Second conductive bonding layer 81: First Resist 82: Second Resist 811,821:Aperture 91: Screen 911,912:Slit L1, L2, L3, L4: Length t1, t2: dimensions x :1st direction y: second direction z: thickness direction

Claims

1. A semiconductor element; an electrode located on one side in a thickness direction of the semiconductor element; a rewiring located on one side of the electrode in the thickness direction and electrically connected to the electrode; a terminal located on one side of the rewiring in the thickness direction and electrically connected to the rewiring; a conductive bonding layer located on one side of the terminal in the thickness direction and electrically connected to the terminal, the terminals include a first terminal and a second terminal; the conductive bonding layer includes a first conductive bonding layer electrically connected to the first terminal and a second conductive bonding layer electrically connected to the second terminal; When viewed in the thickness direction, the area of ​​the second terminal is larger than the area of ​​the first terminal, A semiconductor device, wherein the area of ​​the second conductive bonding layer is larger than the area of ​​the first conductive bonding layer when viewed in the thickness direction.

2. The semiconductor device according to claim 1 , wherein the second conductive bonding layer overlaps the entire second terminal when viewed in the thickness direction.

3. the second terminal and the second conductive bonding layer extend in a first direction perpendicular to the thickness direction, the length of the second terminal in the first direction is at least twice the length of the first terminal in the first direction; 2 . The semiconductor device according to claim 1 , wherein the length of the second conductive bonding layer in the first direction is at least twice the length of the first conductive bonding layer in the first direction.

4. a length of the second terminal in a first direction perpendicular to the thickness direction is at least twice the length of the first terminal in the first direction; a length of the second terminal in a second direction perpendicular to the thickness direction and the first direction is at least twice the length of the first terminal in the second direction; the length of the second conductive bonding layer in the first direction is at least twice the length of the first conductive bonding layer in the first direction; The semiconductor device according to claim 1 , wherein the length of the second conductive bonding layer in the second direction is at least twice the length of the first conductive bonding layer in the second direction.

5. The semiconductor device according to claim 1 , wherein the conductive bonding layer is made of a material containing tin.

6. a first insulating film located between the semiconductor element and the rewiring in the thickness direction; the first insulating film has a first opening penetrating the first insulating film in the thickness direction and exposing the electrode; 6. The semiconductor device according to claim 1, wherein a portion of said rewiring is accommodated in said first opening.

7. a second insulating film located on one side of the first insulating film in the thickness direction and covering the rewiring; the second insulating film is provided with a second opening and a third opening that penetrate the second insulating film in the thickness direction and expose the rewiring; a portion of the first terminal is accommodated in the second opening; The semiconductor device according to claim 6 , wherein a portion of said second terminal is accommodated in said third opening.

8. The semiconductor device according to claim 7 , wherein an area of ​​said third opening is larger than an area of ​​said second opening when viewed in said thickness direction.

9. 8. The semiconductor device according to claim 7, wherein the dimension of said second insulating film in said thickness direction is larger than the dimension of said first insulating film in said thickness direction.

10. the first terminal includes a first portion accommodated in the second opening and a second portion protruding from the second opening, The semiconductor device according to claim 7 , wherein the second portion protrudes outward beyond the second opening when viewed in the thickness direction.

11. the second terminal includes a third portion accommodated in the third opening and a fourth portion protruding from the third opening, The semiconductor device according to claim 7 , wherein the fourth portion protrudes outward beyond the third opening when viewed in the thickness direction.

12. 8. The semiconductor device according to claim 7, wherein said rewiring includes a first base layer in contact with said electrode and said first insulating film, and a first conductive layer stacked on said first base layer.

13. 13 . The semiconductor device according to claim 12 , wherein the terminal includes a second base layer in contact with the rewiring and the second insulating film, and a second conductive layer stacked on the second base layer.

14. 6. The semiconductor device according to claim 1, further comprising a third insulating film covering the other side of said semiconductor element in said thickness direction.

15. preparing a semiconductor element having an electrode disposed on one side in a thickness direction; forming a first insulating film having a first opening exposing the electrode on one side of the semiconductor element in the thickness direction; forming a rewiring on the electrode and a part of the first insulating film so that a part of the rewiring is accommodated in the first opening of the first insulating film; forming a second insulating film having a second opening and a third opening exposing a part of the rewiring on one side of the rewiring in the thickness direction; forming a terminal on a part of the rewiring and a part of the second insulating film so that a part of the terminal is accommodated in the second opening and the third opening of the second insulating film; forming a conductive bonding layer on the terminal; When viewed in the thickness direction, the area of ​​the third opening is larger than the area of ​​the second opening, The method for manufacturing a semiconductor device, wherein the step of forming the conductive adhesive layer is performed by screen printing.

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