Anti-hacking mechanism for flash memory device

Abstract

To provide a mechanism for preventing hacking of a flash memory device.SOLUTION: A flash memory system includes an array including a plurality of flash memory cells organized into rows and columns, and a logic fault detection (LFD) circuit including a command logic circuit, a replica command logic circuit, and a comparator for comparing an output of the command logic circuit and an output of the replica command logic circuit. The comparator generates a first output value and enables access to the array if an output of the command logic circuit and an output of the replica command logic circuit are identical, and the comparator generates a second output value and disables access to the array if the output of the command logic circuit and the output of the replica command logic circuit are not identical.SELECTED DRAWING: Figure 18

Description

[Technical Field]

[0001] This application claims the benefit of U.S. Patent Application No. 15 / 784,025, filed October 13, 2017. A number of mechanisms have been disclosed to enhance security and prevent hacking of flash memory devices. [Background technology]

[0002] Nonvolatile memory cells are well known in the art. FIG. 1 shows a prior art nonvolatile split-gate memory cell 10 including five terminals. The memory cell 10 comprises a semiconductor substrate 12 of a first conductivity type, such as P-type. The substrate 12 has a surface on which a first region 14 (also known as a source line SL) of a second conductivity type, such as N-type, is formed. A second region 16 (also known as a drain line) of N-type is also formed on the surface of the substrate 12. Between the first region 14 and the second region 16 is a channel region 18. A bit line BL20 is connected to the second region 16. A word line WL22 is positioned above and insulated from a first portion of the channel region 18. A word line 22 has little or no overlap with the second region 16. A floating gate FG24 is above another portion of the channel region 18. The floating gate 24 is insulated therefrom and adjacent to the word line 22. The floating gate 24 is also adjacent to the first region 14. The floating gate 24 may overlap the first region 14 and provide coupling from the first region 14 to the floating gate 24. A coupling gate CG (also known as a control gate) 26 is above the floating gate 24 and insulated therefrom. An erase gate EG 28 is above the first region 14 and adjacent to and insulated from the floating gate 24 and the coupling gate 26. An upper corner of the floating gate 24 may face toward an inside corner of a T-shaped erase gate 28 to improve erase efficiency. The erase gate 28 is also insulated from the first region 14. The memory cell 10 is more particularly described in U.S. Pat. No. 7,868,375, the disclosure of which is incorporated herein by reference in its entirety.

[0003] One exemplary operation for erasing and programming a prior art nonvolatile memory cell 10 is as follows: The memory cell 10 is erased by the Fowler-Nordheim tunneling mechanism by applying a high voltage to the erase gate 28 and leaving the other terminals equal to 0 volts. Electrons tunnel from the floating gate 24 to the erase gate 28, causing the floating gate 24 to become positively charged, turning on the cell 10 in the read state. The resulting erased state of the cell is known as the "1" state.

[0004] The memory cell 10 is programmed by a source-side hot electron programming mechanism by applying a high voltage to the coupling gate 26, a high voltage to the source line 14, a medium voltage to the erase gate 28, and a programming current to the bit line 20. A portion of the electrons flowing across the gap between the word line 22 and the floating gate 24 gain enough energy to inject into the floating gate 24, causing it to become negatively charged and turning off the cell 10 in the read state. The resulting programmed state of the cell is known as the "0" state.

[0005] The memory cell 10 is read in a current sensing mode as follows: a bias voltage is applied to the bit line 20, a bias voltage is applied to the word line 22, a bias voltage is applied to the coupling gate 26, a bias or zero voltage is applied to the erase gate 28, and the source line 14 is grounded. In the erased state, there is a cell current flowing from the bit line 20 to the source line 14; in the programmed state, there is little or no cell current flowing from the bit line 20 to the source line 14. Alternatively, the memory cell 10 can be read in a reverse current sensing mode, in which the bit line 20 is grounded and a bias voltage is applied to the source line 24. In this mode, current flows in the reverse direction from the source line 14 to the bit line 20.

[0006] Alternatively, memory cell 10 can be read in a voltage sensing mode as follows: a bias current (to ground) is applied to bit line 20, a bias voltage is applied to word line 22, a bias voltage is applied to coupling gate 26, a bias voltage is applied to erase gate 28, and a bias voltage is applied to source line 14. In the erased state, there is a cell output voltage (significantly above 0V) on bit line 20, and in the programmed state, there is a small or near-zero output voltage on bit line 20. Alternatively, memory cell 10 can be read in a reverse voltage sensing mode, in which bit line 20 is biased to a bias voltage and a bias current (to ground) is applied to source line 14. In this mode, the output voltage of memory cell 10 is on source line 14 instead of bit line 20.

[0007] In the prior art, various combinations of positive or zero voltages were applied to the word line 22, the coupling gate 26, and the floating gate 24 to perform read, program, and erase operations.

[0008] In response to a read, erase, or program command, logic circuitry 451 (FIG. 4) causes various voltages to be applied to various portions of both selected and unselected memory cells 10 in a timely and least disruptive manner.

[0009] The voltages and currents applied to the selected and unselected memory cells 10 are as follows: As used below, the following abbreviations are used: source line or first region 14 (SL), bit line 20 (BL), word line 22 (WL), and coupling gate 26 (CG). Table 1: Operation of Flash Memory Cell 10 Using Positive Voltages for Read, Erase, and Program [Table 1]

[0010] In applicant's most recent application, U.S. Patent Application No. 14 / 602,262, filed January 21, 2015 (incorporated by reference), applicant disclosed an invention in which negative voltages could be applied to word lines 22 and / or coupling gates 26 during read, program, and / or erase operations. In this embodiment, voltages and currents were applied to selected and unselected memory cells 10 as follows: Table 2: Flash memory cells using negative voltages for reading and / or programming 10 Movements [Table 2]

[0011] In another embodiment of U.S. patent application Ser. No. 14 / 602,262, a negative voltage can be applied to the word line 22 when the memory cell 10 is unselected during read, erase, and program operations, and a negative voltage can be applied to the coupling gate 26 during an erase operation, such that the following voltages are applied: Table 3: Operation of Flash Memory Cell 10 Using Negative Voltages for Erase [Table 3]

[0012] The CGINH signal listed above is an inhibit signal and is applied to the coupling gate 26 of unselected cells that share an erase gate 28 with the selected cell.

[0013] 2 shows one embodiment of another prior art flash memory cell 210. Similar to prior art flash memory cell 10, flash memory cell 210 includes a substrate 12, a first region (source line) 14, a second region 16, a channel region 18, a bit line 20, a word line 22, a floating gate 24, and an erase gate 28. Unlike prior art flash memory cell 10, flash memory cell 210 does not include a coupling gate or a control gate, but only four terminals: bit line 20, word line 22, erase gate 28, and source line 14. This significantly reduces the complexity of the circuits, such as decoder circuits, required to operate an array of flash memory cells.

[0014] The erase operation (erase through the erase gate) and read operation are similar to those in Figure 1, except that there is no control gate bias. The programming operation is also performed without a control gate bias, so the program voltage on the source line is higher to compensate for the lack of control gate bias.

[0015] Table 4 shows typical voltage ranges that can be applied to the four terminals to perform read, erase, and program operations. Table 4: Operation of Flash Memory Cell 210 [Table 4]

[0016] 3 illustrates one embodiment of another prior art flash memory cell 310. Similar to prior art flash memory cell 10, flash memory cell 310 includes substrate 12, first region (source line) 14, second region 16, channel region 18, bit line 20, and floating gate 24. Unlike prior art flash memory cell 10, flash memory cell 310 does not include a coupling gate, control gate, or erase gate. Additionally, word line 322 replaces word line 22 and, as illustrated, has a different physical shape than word line 22.

[0017] One exemplary operation for erasing and programming a prior art nonvolatile memory cell 310 is as follows: The cell 310 is erased through the Fowler-Nordheim tunneling mechanism by applying a high voltage to the word line 322 and 0 volts to the bit line and source line. Electrons tunnel from the floating gate 24 to the word line 322, causing the floating gate 24 to become positively charged and turning on the cell 310 in the read state. The resulting erased state of the cell is known as the "1" state. The cell 310 is programmed through a source-side hot electron programming mechanism by applying a high voltage to the source line 14, a small voltage to the word line 322, and a programming current to the bit line 320. A portion of the electrons flowing across the gap between the word line 322 and the floating gate 24 gain enough energy to inject into the floating gate 24, causing it to become negatively charged and turning off the cell 310 in the read state. The resulting programmed state of the cell is known as the "0" state.

[0018] Exemplary voltages that can be used for read, program, erase, and standby operations in memory cell 310 are shown in Table 5 below. Table 5: Operation of Flash Memory Cell 310 [Table 5]

[0019] Security and anti-tamper measures are becoming increasingly important as cyber attackers and hackers become more sophisticated. For example, when a mobile phone is stolen, it is common for the thief or phone seller to attempt to obtain data from the phone. This can be done by hacking the password to the phone or by hacking the underlying hardware within the phone.

[0020] The prior art includes numerous software-based security measures that can be implemented at the system level (e.g., for a phone). However, these measures do not prevent disassembling the phone and extracting data directly from non-volatile storage devices such as flash memory devices. To date, the security measures available for flash memory devices have been extremely limited.

[0021] What is needed are improved security measures specifically for flash memory devices. Summary of the Invention

[0022] Several embodiments are disclosed for enhancing security and preventing hacking of flash memory devices. The embodiments prevent hacking of flash memory chips to obtain data stored within the chips. The embodiments include the use of fault detection circuitry, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.

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[0041] [Brief explanation of the drawings]

[0042] [Figure 1] 1 is a cross-sectional view of a prior art non-volatile memory cell to which the present invention is applicable; [Figure 2] 1 is a cross-sectional view of another prior art nonvolatile memory cell to which the present invention is applicable; [Figure 3] 1 is a cross-sectional view of another prior art nonvolatile memory cell to which the present invention is applicable; [Figure 4] FIG. 4 is a layout diagram of a die comprising non-volatile memory cells of the type shown in FIGS. 1-3 and including embodiments described herein for increasing the security of data stored within the die. [Figure 5] 1 shows a flash memory array with a protected area. [Figure 6] 1 illustrates a method for password-protected access to a flash memory device. [Figure 7] 1 illustrates a flash memory system. [Figure 8] 1 illustrates another flash memory system. [Figure 9] 1 illustrates a compensation array in a flash memory system. [Figure 10] 1 shows a memory array with a separate component for adding noise to a read operation. [Figure 11] 1 illustrates a differential memory array in a flash memory system. [Figure 12] 1 illustrates a sense amplifier circuit in a flash memory system. [Figure 13] 1 illustrates another sense amplifier circuit in a flash memory system. [Figure 14] A compensation memory array and a dummy array are shown. [Figure 15A] 1 illustrates a manufacturing technique for a die containing a flash memory system. [Figure 15B] 1 illustrates a manufacturing technique for a die containing a flash memory system. [Figure 15C] 1 illustrates a manufacturing technique for a die containing a flash memory system. [Figure 16] 1 illustrates a die layout technique for a flash memory system. [Figure 17A] 1 illustrates an address fault detection system for a flash memory system. [Figure 17B] 1 illustrates an address fault detection system for a flash memory system. [Figure 17C] 1 illustrates an address fault detection system for a flash memory system. [Figure 18] 1 shows a logic fault detection circuit for a flash memory system. [Figure 19] 1 illustrates a chip failure detection circuit for a flash memory system. [Figure 20] 1 illustrates another chip failure detection circuit for a flash memory system. DETAILED DESCRIPTION OF THE INVENTION

[0043] FIG. 4 illustrates one embodiment of a flash memory system that includes the security enhancements described herein. Die 400 includes memory arrays 401, 402, 403, and 404 for storing data, each memory array optionally utilizing memory cells 4 as in FIG. 1, memory cells 24 as in FIG. 2, memory cells 34 as in FIG. 3, or other known types of memory cells; row decoder circuits 405, 406, 407, and 408 used to access and read or write rows in memory arrays 401, 402, 403, and 404, respectively; column decoder circuits 409, 410, 411, and 412 used to access and read or write columns in memory arrays 401, 402, 403, and 404, respectively; sense circuit 413 used to read data from memory arrays 401 and 403; sense circuit 414 used to read data from memory arrays 402 and 404; and analog, chip fault detection (CFD), and physically unclonable (physically unclonable) functions. Die 400 includes a PUF (Programmable Operated Function) circuit 450, logic and logic fault detection (LFD) circuit 451 for providing various control functions such as redundancy and built-in self-test, a high-voltage circuit 452 used to provide positive and negative voltage supplies to the system, a charge pump circuit 453 for providing increased voltages for erase and program operations of memory arrays 401, 402, 403, and 404, an interface circuit (ITFC) 454 for providing interface pins for connecting to other macros on the chip, and high-voltage decoder circuits 418, 419, 420, and 421 used during read, erase, and program operations as needed. Die 400 further includes address fault detection blocks 422, 423, 424, and 425, and array fault detection sense circuits 426, 427, 428, and 429.

[0044] A first embodiment is shown in FIG. 5, where specific sectors and information sectors are subject to security measures to make them protected sectors and protected information sectors, respectively. Array 500 is an example of one of memory arrays 401, 402, 403, and 404 for storing data. Array 500 comprises rows and columns of memory cells, such as memory cell 4 of FIG. 1, memory cell 24 of FIG. 2, memory cell 34 of FIG. 3, or other known types of memory cells. Array 500 is divided into multiple sectors. A sector typically consists of two rows of memory cells within the array. Unprotected sectors 501 and 502 are normal sectors with no additional security measures. Protected sectors 503 and 504 are written to and read from using a scrambling algorithm described below.

[0045] In one embodiment, sector 507 is never erased or programmed and serves as a random number generator source, as described in U.S. Provisional Application No. 62 / 479,193, filed March 20, 2017, entitled “System And Method For Generating Random Numbers Based On Non-volatile Memory Cell Array Entropy” (the “Random Number Application”), which is incorporated herein by reference and is filed by the same assignee as the present application. As shown in the Random Number Application, by using differential sensing to read memory cells in pairs (requiring four memory cells for each bit of information), it has been discovered that in subthreshold operation (meaning the select gate is off, so that any detected read current is leakage current only), the leakage current provides a good measure of the cell's randomness. The value of each bit of information is derived from the leakage currents of the four memory cells and combined onto two bit lines, and the two combined currents are subtracted from each other to produce a positive or negative result reflecting the single bit value. The combination of these single-bit values ​​of all dedicated cells, providing a random number (reflecting the cell-to-cell randomness of memory cell fabrication), is unique to the memory cell array and can be reliably and repeatedly read from the memory cell array. Alternatively, the random number can be generated by a PUF (Physically Unclonable Function) based on the intrinsic characteristics of flash memory cells, such as coupling ratio variations, dimensional characteristics (e.g., width, length, thickness), and electrical mismatches (such as threshold voltage variations). For example, programming or erasing all cells in the array with a fixed voltage results in several random cell current levels for different cells. Differential latch sensing can be used with two different cells to establish a random output that essentially compares one cell to another. The two cells are strategically positioned to maximize entropy. Any mismatch between the two cells results in a random, unique number.To improve the repeatability of random number generation over process, temperature, and voltage variations, multiple cells can be used to represent one supercell. For example, 16 cells can represent one input to a differential amplifier, so a total of 32 cells are required to generate one random bit.

[0046] Here, control logic 451 uses the random number application invention or other techniques to determine a random number from cells within sector 507 and utilizes that random number for programming and reading from protected sectors 503 and 504. For example, random number R can be applied as an offset to an address. If a write operation to protected sectors 503 and 504 is targeted to address A, the write operation will actually be directed to R. * It may actually occur at a location in the row corresponding to address A with an offset in the row equal to k (k is a constant for generating integer values), where the offset is R within that row but to the right of the cell corresponding to address A. * A write simply occurs at the cell that is at position k (where it wraps around to the cell in that row in the first column and after the cell in that row in the last column). In this way, random number R influences the location of write operations to fixed sectors 503 and 504. For read operations from sectors 503 and 504, the same random number R is used to implement an offset to address A, which is the target of the read request. Thus, a hacker wishing to read data from address A will not be able to read data from address A because the hacker will not know random number R.

[0047] In another embodiment, data can be read from protected sectors 503 and 504, and optionally random data can be read in parallel from another sector, so that if the sense amplifier is hacked, it is unclear which data was stored in protected sectors 503 and 504 and which data was "dummy" random data read from elsewhere.

[0048] Metadata or system information is typically also stored in array 500. Here, unprotected information sector 505 is a normal information sector with no additional security measures, and protected information sector 506 is subject to the same mechanisms as protected sectors 503 and 504, the only difference being that protected information sector 506 contains metadata or system information and does not contain user data.

[0049] 6 illustrates a password-protected access method 600 whereby an external device is granted access to the die 400 for reading or writing only if it provides a password previously stored in the protected information sector 506. First, the die 400 receives a password authentication request 601 including a received password 602 (step 610). Next, an authentication controller 603 compares the received password 602 with a stored password 604 (step 620). Here, the authentication controller 603 may be part of the logic circuit 451, and the stored password 604 may have been previously stored in the protected information sector 506 or elsewhere on the die 400 during manufacture of the die 400, during initial configuration of the die 400, or may be the user's password during initial use of the die 400. If the received password 602 is the same as the stored password 604, the die 400 grants the access requested by the external device (step 630). If the received password 602 is not the same as the stored password 604, the die 400 does not allow the access requested by the external device (step 640). Optionally, access to the protected information sector 506 can be disabled after the stored password 604 is initially stored, for example by setting an OTP bit. Optionally, the stored password 604 can be encrypted and decrypted by the authentication controller 603 using a unique key generated by a PUF (Physically Unclonable Function), based on a random number generator or a variation of a non-volatile memory such as those described above.

[0050] 7 shows flash memory system 700 (which may be implemented on die 400). Flash memory system 700 includes arrays 701 and 702 (corresponding to arrays 401 and 403 of FIG. 4), row decoders 703 and 704 (corresponding to row decoders 405 and 406), column decoders 705 and 706 (corresponding to column decoders 406 and 408), and sense circuit 710 (corresponding to sense circuit 410). Flash memory system 700 also includes a reference array 709 and a sense circuit current reference 708.

[0051] Each column of flash memory cells in array 701 is coupled to a bit line, such that there is one bit line for every column in array 701. Similarly, each column of flash memory cells in array 702 is coupled to a bit line, such that there is one bit line for every column in array 702. Column decoders 705 and 706 connect selected bit lines to sense circuit 710 during a read operation for a selected address. Sense circuit 710 includes multiple sense amplifier circuits 707a, 707b, ..., 707n, where n is the number of bit lines that can be simultaneously read and is referred to as the IO width of flash memory system 700 (typically, n is 32 or 64). These sense amplifier circuits are collectively referred to as sense amplifier circuits 707.

[0052] In this embodiment, reference array 709 is an array of dummy flash memory cells that are identical in structure to the flash memory cells of arrays 701 and 702, but are not actually used to store user data. Reference array 709 functions to generate read reference biases for sensing both arrays 701 and 702. In an alternative embodiment, reference array 709 comprises standard reference transistors without flash memory cells. These standard reference transistors are sized and / or biased differently to provide different trip points (i.e., current or voltage levels that distinguish between "0" and "1") for sensing circuit 710. In another alternative embodiment, reference array 709 comprises standard reference resistors without flash memory cells. These standard reference resistors are sized differently to provide different trip points for sensing circuit 710.

[0053] A sense circuit current reference 708 is coupled to one or more of the dummy flash memory cells and generates a current that is mirrored in each of the sense amplifier circuits 707 using current mirroring techniques. The mirrored reference current is the reference current that is compared against a selected memory cell from array 701 or 702 to generate an output indicative of the value of the data stored in the selected memory cell.

[0054] 8 shows another flash memory system 800, which may be implemented on a die 800. Like flash memory system 700, flash memory system 800 includes arrays 701 and 702, row decoders 703 and 704, and column decoders 705 and 706. Flash memory system 800 further includes reference arrays 801 and 802 and sensing circuit 803.

[0055] Each column of flash memory cells in array 701 is coupled to a bit line, such that there is one bit line for every column in array 701. Similarly, each column of flash memory cells in array 702 is coupled to a bit line, such that there is one bit line for every column in array 702. Column decoders 705 and 706 connect selected bit lines to sense circuit 803 during a read operation for a selected address. Sense circuit 803 includes multiple sense amplifier circuits 804a, 804b, ..., 804n, where n is the number of bit lines that can be simultaneously read and is referred to as the IO width of flash memory system 800 (typically, n is 32 or 64). These sense amplifier circuits are collectively referred to as sense amplifier circuits 804.

[0056] In this embodiment, both reference arrays 801 and 802 are arrays of dummy flash memory cells that are identical in structure to the flash memory cells of arrays 701 and 702, but are not actually used to store user data. When a selected memory cell is in array 701, each sense amplifier circuit 804 is connected to a memory cell in reference array 802, which functions as a reference memory cell. When a selected memory cell is in array 702, each sense amplifier circuit 804 is connected to a memory cell in reference array 801, which acts as a reference memory cell. Thus, unlike flash memory system 700, flash memory system 800 does not require the use of sense circuit current reference 708 or a current mirror. In another alternative embodiment, reference arrays 801 and 802 include standard reference transistors without flash memory cells. These standard reference transistors are sized and / or biased differently to provide different trip points for sense circuit 803. In another alternative embodiment, reference arrays 801 and 802 include standard reference resistors without flash memory cells. These standard reference resistors are sized differently to provide different trip points for the sensing circuit 803 .

[0057] 9 illustrates a system power balancing system and method for providing security against a situation in which a hacker is monitoring power consumption signatures, such as by utilizing a side-channel attack using simple power analysis (SPA) or differential power analysis (DPA) of the die 400 or specific components within the die 400 in an attempt to determine the data stored within the array. Specifically, in prior art flash memory systems, a hacker can identify the data being read by the sensing circuitry based on the power consumption of each read cycle. For example, a different amount of power is consumed to read a "1" from a flash memory cell compared to reading a "0" from the flash memory cell. Therefore, by monitoring the power consumption of the sensing circuitry, the value of the cell being read can be inferred, and therefore the data being read from the array.

[0058] In the system of FIG. 9 , when data D is written to address A in array 401 or 403, its complement, data D, is written to address A in array 402 or 404. Then, when data is read from address A in array 401 or 403, data is also simultaneously read from address A in array 402 or 404. Because the data stored in the two arrays at the same address are always complements of each other, both a “1” and a “0” are read for each read operation, and the combined power consumption of sense circuits 413 and 414 is the same for all read operations. Therefore, a hacker cannot determine the data being read from either array by simply monitoring the power consumed by sense circuits 413 and 414. The above power balancing technique can be applied at the system level where multiple instances of flash memory macros are used. In this case, data D is stored in one instance and data D is stored in another instance, and both data D and data D are simultaneously activated for a read operation.

[0059] FIG. 10 illustrates a memory array and noise component 1000, where data is written to array 401 or 403 as in the prior art. However, during a read operation, sense circuit 413 reads data from array 401 or 403, and sense circuit 414 simultaneously reads random data from an address in array 402 or 404. Thus, the combined power consumption of sense circuits 413 and 414 includes a component due to the data read from array 401 or 403 and a component due to “0”s or “1”s read from the random data in array 402 or 404. As a result, particularly in situations where “1”s and “0”s or “0”s and “1”s are read by sense circuits 413 and 414, not all of the data read from array 401 or 403 can be identified based on the power consumption of sense circuits 413 and 414 due to the random data read from array 402 or 404. In an embodiment including multiple instances of flash memory macros, only one flash memory macro is required to store the random data. The macro with random data is activated in parallel when reading data from any other flash memory macro.

[0060] FIG. 11 illustrates a differential memory array 1100, where the arrays are arrays 401 and 403 of FIG. 4. It should be understood that the arrays may also be arrays 402 and 404 and their associated circuitry, or any other pair of arrays. In the system of FIG. 11, when data D is written to address A in array 401, its complement, data D, is written to address A in array 403. Then, when data is read from address A in arrays 401 or 403, data is also simultaneously read from address A in array 403. Because the data stored in the two arrays at the same address are always complements of each other, both a "1" and a "0" are read for each read operation, and the power consumption of the sense circuit 413 is the same for all read operations. Therefore, a hacker cannot determine the data read from either array by simply monitoring the power consumed by the sense circuit 413.

[0061] 12 shows an exemplary circuit of the sense circuit 413. The sense amplifier circuit 1200 includes a memory data read block 1201, a memory reference read block 1202, and a differential amplifier block 1203.

[0062] The memory data read block 1201 comprises a sense load PMOS transistor 1204, a switch 1205 that applies a bias voltage VBLRD_BIAS to a sense node 1222, and an enable sense NMOS transistor 1206 coupled to a selected memory cell 1207. The sense load PMOS transistor 1204 provides a read reference current that is compared with the cell current from the memory cell 1207. The sense node 1222 is high (towards VDDIO 1219) when the read reference current from the sense load PMOS transistor 1204 is greater than the memory cell current and is low (towards ground) when the memory cell current is greater than the read reference current. The reference current from the sense load PMOS transistor 1204 can optionally be provided using a current mirror configuration that sinks current from a reference memory cell. Alternatively, the reference current from the sense load PMOS transistor 1204 can be provided using a current mirror configuration that mirrors a current from an appropriately sized or biased reference resistor or transistor.

[0063] The memory reference read block 1202 includes a sense load PMOS transistor 1208, a switch 1209 that applies a bias voltage VBLRD_BIAS to a reference node 1220, and an enable sense NMOS transistor 1201 coupled to a compensation memory cell 1211. The compensation memory cell 1211 functions as a holding capacitor that holds the reference voltage VBLRD_BIAS on the sense node 1220. Alternatively, an explicit capacitor such as a metal oxide metal cap (MOMCAP) can be used as the holding capacitor. Alternatively, parasitic capacitance, such as from the junction capacitance or gate capacitance of node 1220, can be used as the holding capacitor. The reference block 1202 functions as a dummy block for the reference node 1220. The reference sense load PMOS transistor 1208 may be in an off state or may be used to provide compensation leakage current, such as leakage at node 1220 from junction and / or transistor leakage of unselected bit lines. The bias voltage level of VBLRD_BIAS serves as a reference voltage at reference node 1220 to which the sense voltage at sense node 1222 is compared.

[0064] Differential amplifier block 1203 comprises input cross-coupled PMOS transistors 1213 and 1215 and input cross-coupled NMOS transistors 1214 and 1216 which together form a comparator, PMOS enabling transistor 1212 (which also acts as a transient bias tail current for cross-coupled PMOS transistors 1213 and 1215), and NMOS enabling transistor 1217 (which also acts as a transient bias tail current for cross-coupled NMOS transistors 1214 and 1216). In comparison, NMOS transistor 1217 first triggers the comparison from NMOS transistors 1214 and 1216 to generate a voltage delta between nodes 1220 and 1222, and then PMOS transistor 1212 is enabled to initiate the comparison from PMOS transistors 1213 and 1220 which restores full power to both nodes 1220 and 1222. Alternatively, both NMOS transistor 1217 and PMOS transistor 1212 can be enabled simultaneously to trigger the comparison.

[0065] In operation, the differential amplifier block 1203 compares the sense node 1222 created by the memory data read block 1201 with the reference node 1220 created by the memory reference read block 1202 to generate the output 1220. Initially, the voltages at nodes 1222 and 1220 are initialized at the same reference voltage level VBLRD_BIAS (by switches 1205 and 1209). The voltage at sense node 1222 then develops (high or low depending on the selected memory cell current 1207, which is less or greater than the read reference current conducting PMOS transistor 1204). A comparison is then triggered to compare the voltage at sense node 1222 with the voltage at reference node 1220 (by transistors 1217 and 1212). The final voltages at sense node 1222 and reference node 1220 are at full supply levels after the comparison is completed.

[0066] If the read reference current conducting transistor 1204 exceeds the memory cell current drawn from memory cell 1207 (indicating a "0" stored in the selected memory cell), output 1220 will be low. If the read reference current in transistor 1204 is less than the memory cell current drawn from memory 1207 (indicating a "1" stored in the selected memory cell), output 1220 will be high.

[0067] Memory data read block 1201 and memory reference read block 1202 draw power from power bus 1219 (also labeled VDDIO, i.e., IO power supply), which is typically about 3.0 volts. Differential amplifier block 1203 draws power from power bus 1218 (VDDSA, typically also labeled core logic power supply), which is typically about 1.05 volts or less for scaled technology nodes, such as 28 nm and below. To obtain high memory cell currents for high performance requirements, the read bit line voltage needs to be as high as possible, which means the voltage at node 1222 needs to be high, such as 1V to 1.4V. This means that transistor 1204 needs to operate from a much higher voltage supply than the core logic supply, which is typically ≦1.05V. Therefore, circuit blocks 1201 and 1202 need to operate from a much higher IO supply than the core logic supply. This means that circuit blocks 1201 and 1202 include 3V IO transistors, which require a relatively large area.

[0068] In another operation method of the sensing circuit 1200, the sensing circuit 1200 operates as a differential sensing circuit with two compensation cells as follows. The sense load PMOS transistor 1204 of the memory data read block 1201 may be in an off state or may be used to provide a compensation leakage current, such as leakage at node 1222 from junction and / or transistor leakage of the selected bit line. The switch 1205 is used to precharge the sense node 1222 to the bias voltage VBLRD_BIAS. Meanwhile, the switch 1209 is used to precharge the reference node 1220 to the bias voltage VBLRD_BIAS. The compensation memory cell 1211 is coupled to another memory cell having data that compensates for the data of the selected cell 1207. After the precharge period, for example, when the selected cell 1207 data is "1" and the compensation cell 1211 data is "0," the sense node 1222 and the reference node 1220 both discharge toward ground, and the sense node 1222 is discharged faster. At a particular time during the ramp down, the comparator circuit 1203 is enabled to compare the sense node 1222 with the reference node 1220. In the above case where the data in the selected cell 1207 is "1" and the data in the compensation cell 1211 is "0", the sense node 1222 goes to ground and the reference node 1220 goes to VDDSA. In this case, the entire circuit 1200 needs to operate only from the VDDSA supply (core logic supply). This method is the preferred method for application to the differential memory array 1100.

[0069]

[0070] 13 shows a power balancing circuit for sense circuit 413. Sense amplifier circuit 1300 includes a memory data read block 1301, a memory reference read block 1302, and a differential amplifier block 1303. Sensing circuit 1300 is a balanced (constant) power differential latch sensing circuit that provides balanced power in response to any data pattern.

[0071] The memory data read block 1301 comprises a sense load PMOS transistor 1304, a switch 1305 that applies a bias voltage VBLRD_BIAS to a sense node 1322, and an enable sense NMOS transistor 1306 coupled to a selected memory cell 1307. The sense load PMOS transistor 1304 provides a read reference current that is compared to the cell current from the memory cell 1307. The sense node 1322 is high (towards VDDIO 1319) when the read reference current from the sense load PMOS transistor 1304 is greater than the memory cell current and is low (towards ground) when the memory cell current is greater than the read reference current. The reference current from the sense load PMOS transistor 1304 can optionally be provided using a current mirror configuration that sinks current from a reference memory cell. Alternatively, the reference current from the sense load PMOS transistor 1304 can be provided using a current mirror configuration that mirrors a current from an appropriately sized or biased reference resistor or transistor.

[0072] The memory reference read block 1302 includes a sense load PMOS transistor 1308, a switch 1309 that applies a bias voltage VBLRD_BIAS to a reference node 1320, and an enable sense NMOS transistor 1301 coupled to a compensation memory cell 1311. The compensation memory cell 1311 functions as a holding capacitor that holds the reference voltage VBLRD_BIAS on the sense node 1320. Alternatively, an explicit capacitor such as a MOMCAP (metal oxide metal cap) can be used as the holding capacitor. Alternatively, parasitic capacitance, such as from the junction capacitance or gate capacitance of node 1320, can be used as the holding capacitor. The reference block 1302 functions as a dummy block for the reference node 1320. The reference sense load PMOS transistor 1308 may be in an off state or may be used to provide a bias current, including a reference current and a compensation leakage current, such as for leakage at node 1320 from junction and / or transistor leakage of unselected bit lines. The bias voltage level of VBLRD_BIAS serves as a reference voltage at reference node 1320 that is compared to the sense voltage at sense node 1322 .

[0073] Differential amplifier block 1303 comprises input cross-coupled PMOS transistors 1313 and 1315 and input cross-coupled NMOS transistors 1314 and 1316, which together form a comparator, PMOS enable transistor 1312 (which also acts as a transient bias tail current for cross-coupled PMOS transistors 1313 and 1315), and NMOS enable transistor 1317 (which also acts as a transient bias tail current for cross-coupled NMOS transistors 1314 and 1316). In comparison, NMOS transistor 1317 first triggers the comparison from NMOS transistors 1314 and 1316 to generate a voltage delta between nodes 1320 and 1322, and then PMOS transistor 1313 is enabled to initiate the comparison from PMOS transistors 1313 and 1320, which restores full power to both nodes 1320 and 1322. Alternatively, both NMOS transistor 1317 and PMOS transistor 1312 can be enabled simultaneously to trigger the comparison.

[0074] Differential amplifier block 1303 further comprises PMOS transistor 1318 and NMOS transistors 1319 and 1320, which together form a balance power circuit capable of providing balanced power for sense circuit 1300 in response to any data pattern. Transistor 1319 is sized so that the voltage level of sense node 1322 is lower than the voltage level of reference node 1320 when selected cell 1307 is in an erased state (the memory cell is conducting a large current).

[0075] In operation, differential amplifier block 1303 compares sense node 1322, created by memory data read block 1301, with reference node 1320, created by memory reference read block 1302, to generate output 1320. Initially, the voltages at nodes 1322 and 1320 are initialized at the same reference voltage level VBLRD_BIAS (by switches 1305 and 1309). The voltage at sense node 1322 then develops to be greater or less than reference node 1320 (depending on the selected memory cell current 1307 relative to the read reference current conducting in PMOS transistor 1304). A comparison is then triggered to compare the voltage at sense node 1322 with the voltage at reference node 1320 (by transistors 1317 and 1313). The final voltages at sense node 1322 and reference node 1320 are at full supply levels after the comparison is completed.

[0076] If the read reference current conducting transistor 1304 exceeds the memory cell current drawn from memory cell 1307 (indicating a "0" stored in the selected memory cell), output 1320 will be low. If the read reference current in transistor 1304 is less than the memory cell current drawn from memory cell 1307 (indicating a "1" stored in the selected memory cell), output 1320 will be high.

[0077] Memory data read block 1301 and memory reference read block 1302 draw power from power bus 1319 (also labeled VDDIO, i.e., IO power supply), which is typically about 3.0 volts. Differential amplifier block 1303 draws power from power bus 1318 (VDDSA, typically also labeled core logic power supply), which is typically about 1.05 volts or less for scaled technology nodes, such as 28 nm and below. To obtain high memory cell currents for high performance requirements, the read bit line voltage needs to be as high as possible, which means the voltage at node 1322 needs to be high, such as 1V to 1.4V. This means that transistor 1304 needs to operate from a much higher voltage supply than the core logic supply, which is typically ≦1.05V. Therefore, circuit blocks 1301 and 1302 need to operate from a much higher IO supply than the core logic supply. This means that circuit blocks 1301 and 1302 include 3V IO transistors, which require a relatively large area.

[0078] 14 illustrates a system and method for providing security against the situation of monitoring the power consumption of die 400 or specific components within die 400 during programming operations. Specifically, prior art flash memory systems can identify whether a cell has been programmed (i.e., a "0" has been written to the cell) by monitoring the power consumption of each programming cycle, which indicates whether a "0" has been programmed (where unprogrammed means the cell remains at "1").

[0079] 14, when data D is written to address A in array 401, its complement, data D, is simultaneously written to dummy array 1401. If data D is "0", address A in array 401 is programmed to "1" and data D is "1", meaning no programming occurs in dummy array 401. If data D is "1", address A in array 401 is not programmed and data D is "1" and is programmed into the cell in dummy array 1401. Therefore, for any programming operation, the power consumption is the same, and therefore a hacker cannot determine whether the data at address A in array 401 is "0" or "1" based on the programming operation.

[0080] 15A shows a wafer 1501. In the prior art, the wafer 1501 is manufactured and contains multiple different instances of the die 400.

[0081] FIG. 15B shows nine exemplary instances of die 400 within wafer 1501. In the prior art, it is common to include wafer test interconnects (not shown) within each die. After wafer 1501 is fabricated, the wafer test interconnects (not shown) are used to test each die 400. Then, once it is known which die 400 passed the test procedure and which die 400 failed, wafer 1501 is sliced ​​into individual die 400. Exemplary slice lines, known as scribe lines 1503, are shown in FIG. 15B. Hackers have been known to take prior art devices, remove the packaging, and use the wafer test interconnects to access the contents of the die 400.

[0082] 15C illustrates an improved method of slicing a wafer 1501 with protected test interconnects. A wafer test interconnect matrix 1502 is shown extending into the scribe area. Specifically, horizontal scribe lines are now created directly adjacent the bottom edges of the die 400, thus removing each die 400 from its bonded wafer test interconnect matrix 1502 such that the remaining portions of the wafer test interconnect matrix 1502 do not adhere to the die 400 when the die are packaged and sent to the field. Thus, a hacker cannot use the wafer test interconnect matrix 1502 to access the contents of the die 400 because the wafer test interconnect matrix 1502 is no longer present.

[0083] FIG. 16 illustrates die 1600, one embodiment of die 400. In the prior art, hackers often removed packaging from the chip and electrically probed the semiconductor die to determine the die's contents. Die 1600 includes a design to counter such behavior. Die 1600 includes a top-enabled logic fault detection (LFD) interconnect matrix 1601, a metal shield 1602, and other layers 1603 (including the remaining active chip layers and metal layers). Top-enabled LFD interconnect matrix 1601 and metal shield 1602 are essential components of the fixed circuitry of die 1600. If a hacker electrically probes die 1600, the LFD interconnect matrix and / or metal shield 1602 may be damaged, and the damaged metal may create shorts and / or open circuits, destroying the circuitry coupled to the damaged area, resulting in intrusion fault detection, allowing the on-chip controller to take preventative or security measures, such as disabling chip access or chip operation. This makes it much more difficult to determine the contents of the die 1600 by performing electrical probing of the die 1600 .

[0084] FIG. 17A illustrates one embodiment of an address fault detection system. Memory system 1700 includes row decoder 405, array 401, and column decoder 411, as in the previous embodiments. Memory system 1700 further includes address fault detection array 1701, address fault detection array 1702, address fault detection array 1704, address fault detection circuit 1703, and address fault detection circuit 1705. Column decoder 411 is a set of multiplexers, often comprising hierarchical multiplexers. Referring to FIG. 17B, a portion of an exemplary column decoder 411 is shown. Each column in array 401 is coupled to a bit line. Here, four bit lines are shown, labeled BL0-BL3. The first level of multiplexers selects a pair of adjacent bit lines to be activated. Two such multiplexers, namely, T0 and T1, are shown. The second level of multiplexers selects a bit line from among the pair of adjacent bit lines. Here, each bit line has its own multiplexer, labeled V0-V3, so if BL0 is intended to be selected, W0 and V0 are activated.

[0085] Referring again to FIG. 17A, it can be seen that column decoder 411 is susceptible to faults, just like row decoder 405. In this example, address Y is input to column decoder 411, and address X is input to row decoder 405. Address Y includes a bit that indicates which multiplexer is activated (which in turn asserts a bit line). Each bit line is coupled to a row in address fault detection array 1701. When the bit line is asserted, row in address fault detection array 1701 is asserted, row in address fault detection array 1702 is asserted, and a value is output. That value can be compared to the column portion of address Y. If the values ​​are different, a fault has occurred and the wrong bit line has been asserted. Address fault detection array 1704 is used to detect when an unwanted row address is asserted. When a row (such as word line WL0) is asserted in a malicious manner, row in address fault detection array 1704 is asserted and a value is output. That value can be compared to address X by address fault detection circuit 1705. If the values ​​are different, a fault has occurred and the wrong word line has been asserted.

[0086] An exemplary encoding scheme for use in the embodiment of FIG. 17A is shown in FIG. 17C. Here, two hierarchies of multiplexers are used. The first hierarchies include multiplexers controlled by values ​​T[0] through T[3], and the second hierarchies include multiplexers controlled by values ​​V[0] through V[7]. It should be understood that additional hierarchies are possible. Here, each multiplexer in the first hierarchies is associated with a 3-bit value (e.g., V[0]=000), and each multiplexer in the second hierarchies is associated with a 2-bit value (e.g., T[0]=00). Address fault detection arrays 1701 and 1702 contain encoded values ​​for each multiplexer value. Each "0" in the column component of an address is encoded as "01," and each "1" in an address is encoded as "10."

[0087] Referring again to Figure 17A, the encoding scheme of Figure 17C can be used. Address fault detection circuit 1703 outputs a "0" if a "11" or "00" pattern is detected in the bit pairs of the encoded values ​​stored in address fault detection array 1701. Thus, memory system 1700 can detect faults in the column component of the address. This scheme applies equally to row address fault detection.

[0088] 18 illustrates a logic fault detection circuit 1800. The logic fault detection circuit includes erase / program / read / test (E / P / R / T) command logic 1801, duplicate erase / program / read / test command logic 1802, and logic fault detector (digital comparator) 1803. The erase / program / read / test command logic 1801 receives signals from input pins containing commands for the memory device, such as CEb, Web, CLK, Din, and address signals, and generates erase / program / read / test chip enable signals. The duplicate erase / program / read / test command logic 1802 generates the erase / program / read / test chip enable signals based in part on stored configuration data (e.g., E / P / R / T signal sequencing) and can therefore be considered “ideal” enable signals to be used during erase, program, read, and test operations. The valid signals from the erase / program / read / test command logic 1801 and the duplicate erase / program / read / test command logic 1802 are provided to a logic fault detector (digital comparator) 1803 for comparison. If the signals are the same, the output of the logic fault detector circuit 1803 indicates no fault. If the signals are different, the output of the logic fault detector circuit 1803 indicates a fault. A fault may occur, for example, if a hacker forces a read command using an input pin in an attempt to read data stored in the array. A hacker may not know the exact sequence and timing of the input signals used, and the resulting valid signal from the erase / program / read / test command logic 1801 may be slightly different from the ideal valid signal from the duplicate erase / program / read / test command logic 1802, resulting in an LFD fault indication. This scheme can be used to detect unwanted addressing logic by monitoring the addressing decode circuitry.

[0089] Another embodiment of logic fault detection circuit 1800 relates to duplicate erase / program / read / test command logic 1802 to receive the same signals from the same input pins as erase / program / read / test command logic 1801. This embodiment provides security against a scenario where a hacker bypasses the pins and simply provides an enable signal directly, in which case logic fault detector 1803 receives an enable signal at one input (e.g., from the output of erase / program / read / test command logic 1801) but does not receive an enable signal from the other input (e.g., from duplicate erase / program / read / test command logic 1802) because the hacker would not know that an enable signal needs to be provided to two locations so as not to trigger a fault by logic fault detection circuit 1803.

[0090] FIG. 19 shows a chip analog and / or mixed-signal fault detection circuit 1900. Any tampering with the circuits used by the flash memory chip, such as by physical intrusion such as micro-probing, is detected. The chip fault detection circuit includes a power supply fault detector 1901, a high-voltage erase / program / read fault detector 1902, a clock (CLK) fault detector 1903, a temperature fault detector 1904, and a flash circuit fault detector 1905. The power supply fault detector 1901 outputs a "1" when it detects a power supply outside a pre-specified range. The high-voltage erase / program / read fault detector 1902 outputs a "1" when it detects a high-voltage signal outside a pre-specified range. The clock fault detector 1903 outputs a "1" when it detects a clock signal outside a pre-specified frequency range. The temperature fault detector 1904 outputs a "1" when it detects an operating temperature outside a pre-specified range. The flash circuit fault detector 1905 outputs a "1" when any of the other modules outputs a "1" (i.e., a fault is detected by any of the modules). In one embodiment, the flash circuit failure detector 1905 is a NOR gate.

[0091] FIG. 20 shows a chip fault detection circuit 2000. The chip fault detection circuit 2000 includes a circuit 2001 and a replica circuit 2002. The circuit 2001 provides an output Vr1, and the circuit 2002 provides an output Vr2. Vr1 and Vr2 are provided to a DeltaV detector 2003, which outputs a "1" if the voltage difference between Vr1 and Vr2 exceeds a certain threshold (e.g., 100-200 mV), and outputs a "0" otherwise. Examples of the circuit 2001 include an on-chip reference bandgap circuit, a linear voltage regulator (LDO) circuit, an HV regulator, etc. The chip fault detection circuit 2000 protects against a situation in which a hacker attempts to manipulate the behavior of the chip by probing it and injecting specific signals into the circuit.

[0092] In all of the above embodiments, various countermeasures can be invoked if a fault is detected or if some other event occurs that indicates a potential security breach. For example, the "chip valid" signal can be deasserted, rendering the entire chip, including die 400, inoperable. Or certain operations, such as read operations, can be prevented by deasserting a signal, such as the read valid signal. Many other countermeasures are possible.

[0093] References to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely to refer to one or more features that may be encompassed by one or more of the claims. The materials, processes, and numerical examples described above are merely illustrative and should not be considered to limit the scope of the claims. It should be noted that, as used herein, the terms "over" and "on" both encompass "directly on" (without an intermediate material, element, or gap disposed therebetween) and "indirectly on" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" encompasses "directly adjacent" (without an intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween). For example, forming an element "over a substrate" can encompass both forming the element directly on the substrate without any intermediate material / element or indirectly forming the element on the substrate through one or more intermediate materials / elements.

Claims

1. an array including a first plurality of flash memory cells and a second plurality of flash memory cells; a decode circuit for receiving an address, wherein if the address corresponds to the first plurality of flash memory cells, the decode circuit activates a row and column corresponding to the address for a read or program operation, and if the address corresponds to the second plurality of flash memory cells, the decode circuit performs a scramble function on the address to generate a scrambled address and activates the row and column corresponding to the scrambled address for a read or program operation.

2. 10. The flash memory system of claim 1, wherein the scrambling function utilizes a random number generated from leakage currents in a plurality of cells in the array.

3. 10. The flash memory system of claim 1, wherein the scrambling function utilizes a random number generated from a current resulting from a fixed program or erase voltage of a plurality of cells in the array.

4. 2. The flash memory system of claim 1, wherein the first plurality of flash memory cells and the second plurality of flash memory cells are split-gate flash memory cells.

5. an array including a plurality of flash memory cells organized in rows and columns; a stored password in a protected row of flash memory cells in the array; and and an authentication circuit for permitting access to the array for read or program operations if a received password is identical to the stored password, and for disallowing access to the array for read or program operations if the received password is not identical to the stored password.

6. 6. The flash memory system of claim 5, wherein the row containing the stored password is disabled for erase and program operations.

7. 6. The flash memory system of claim 5, wherein the plurality of flash memory cells are split-gate flash memory cells.

8. a first array of flash memory cells; a second array of flash memory cells; a write circuit for receiving an address that writes data to the address in the first array and writes the complement of the data to the address in the second array; a read circuit for receiving an address that reads the data from the address in the first array and simultaneously reads the complement of the data from the address in the second array.

9. a first sense amplifier coupled to the first array for performing a read operation on the first array; 9. The flash memory system of claim 8, further comprising: a second sense amplifier coupled to said second array for performing read operations on said second array.

10. 9. The flash memory system of claim 8, comprising sense amplifiers coupled to the first array and the second array for performing read operations on the first array and the second array.

11. 9. The flash memory system of claim 8, wherein the first array of flash memory cells and the second array of flash memory cells comprise split-gate flash memory cells.

12. a first array of flash memory cells; a second array of flash memory cells; a read circuit for receiving an address that reads the data from the address in the first array and simultaneously reads data from a random location in the second array.

13. 13. The flash memory system of claim 12, wherein the first array of flash memory cells and the second array of flash memory cells comprise split-gate flash memory cells.

14. fabricating a wafer including a plurality of semiconductor dies and circuitry coupled to and external to the dies; and cutting the wafer to separate the die from the circuitry and the remainder of the wafer.

15. a first layer including a metal layer; a second layer including a metal shield and adjacent to the first layer; a third layer including an interconnect matrix adjacent to the second layer; The flash memory semiconductor die, wherein the first layer, the second layer, and the third layer form a circuit that is inoperable if the interconnect matrix is ​​damaged.

16. The die of claim 15 , wherein the circuitry is inoperable if the metal shield is damaged.

17. an array including a plurality of flash memory cells organized in rows and columns; a logic fault detection circuit including a command logic circuit, a duplicate command logic circuit, and a comparator for comparing an output of the command logic circuit with an output of the duplicate command logic circuit; the comparator generates a first output value that enables access to the array when the output of the command logic circuit and the output of the replicated command logic circuit are identical; The comparator generates a second output value and disables access to the array if the output of the command logic circuit and the output of the duplicate command logic circuit are not identical.

18. 20. The system of claim 17, wherein the output of the replicated command logic indicates an erase, program, read, or test command.

19. 20. The system of claim 17, wherein the command logic and the replicated command logic receive input signals from pins of the flash memory system.

20. 20. The system of claim 17, further comprising address decode logic.

21. 20. The flash memory system of claim 17, wherein the plurality of flash memory cells are split-gate flash memory cells.

22. an array including a plurality of flash memory cells organized in rows and columns; a fault detection circuit for generating an output, wherein access to the array is enabled when the output is a first value and access to the array is disabled when the output is a second value.

23. 23. The flash memory system of claim 22, wherein the fault detection circuitry includes circuitry for determining whether a power supply value is within a range of pre-specified levels.

24. 23. The flash memory system of claim 22, wherein the fault detection circuitry includes circuitry for determining whether a high voltage erase, program, or read signal exceeds a pre-specified level.

25. 23. The flash memory system of claim 22, wherein the fault detection circuitry includes circuitry for determining whether a frequency of a received clock signal exceeds a predesignated frequency.

26. 23. The flash memory system of claim 22, wherein the fault detection circuitry includes circuitry for determining whether a measured temperature exceeds a predesignated temperature.

27. 23. The flash memory system of claim 22, further comprising an address fault detection circuit.

28. 23. The flash memory system of claim 22, wherein the plurality of flash memory cells are split-gate flash memory cells.

29. an array including a plurality of flash memory cells organized in rows and columns; a first circuit for generating a first voltage; a second circuit for generating a second voltage; a fault detection circuit for generating an output, the output being a first value when a difference between the first voltage and the second voltage exceeds a pre-specified value, and the output being a second value when a difference between the first voltage and the second voltage does not exceed a pre-specified value; When the output is the first value, access to the array is disabled, and when the output is the second value, access to the array is enabled.

30. 30. The flash memory system of claim 29, wherein the first circuit is a high voltage regulator circuit and the second circuit is a replica circuit.

31. 30. The flash memory system of claim 29, wherein the plurality of flash memory cells are split-gate flash memory cells.

32. an array including a plurality of flash memory cells organized in rows and columns; and an analog mixed-signal fault detection circuit; a logic fault detection circuit; and an address fault detection circuit.

33. 33. The flash memory system of claim 32, wherein the plurality of flash memory cells are split-gate flash memory cells.

34. an array including a plurality of flash memory cells organized in rows and columns; a power balance latch sense amplifier circuit for receiving an address, the power balance latch sense amplifier circuit reading the data from the address in the array.

35. 35. The flash memory system of claim 34, wherein the plurality of flash memory cells are split-gate flash memory cells.

36. a first array of flash memory cells; a second array of flash memory cells; a write circuit for receiving an address that writes data to the address in the first array and simultaneously writes a complement of the data to the address in the second array.

37. 37. The system of claim 36, further comprising: a read circuit for receiving an address that reads the data from the address in the first array and simultaneously reads the complement of the data from the address in the second array.

38. 37. The flash memory system of claim 36, wherein the first array of flash memory cells and the second array of flash memory cells comprise split-gate flash memory cells.

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