Nor flash memory and manufacturing method thereof

Abstract

To provide a NOR flash memory which suppresses leakage current of non-selected cells and is compatible with a NAND flash memory.SOLUTION: A NOR flash memory 100 of the present invention includes: an active region 120 formed within a silicon substrate 110 so as to extend along a bit line direction; a trench 130 adjacent to the active region 120; a charge storage layer 140 formed on the active region 120 for each memory cell; a sidewall insulator 162 formed within the trench 130 and formed on a sidewall of the active region 120; a first control gate 150 formed on the charge storage layer 140 for each memory cell; and a second control gate 170 formed on the first control gate 150 so as to extend along a word line direction. The second control gate 170 is electrically connected to the first control gate 150 and contacts the sidewall insulator 162 within the trench 130.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a two-dimensional (2D) NOR flash memory. [Background technology]

[0002] NOR flash memory employs a floating gate (FG) with excellent charge retention characteristics in its cell structure. The floating gate is made of, for example, polysilicon. For example, Patent Document 1 discloses a NOR flash memory that reduces the power supply voltage without degrading the operating speed by making the overlap region between the floating gate and the drain layer narrower than the overlap region between the floating gate and the source layer. [Prior art documents] [Patent documents]

[0003] [Non-Patent Document 1] Japanese Patent Application Laid-Open No. 2006-339207 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional FG-type NOR flash memory, as miniaturization progresses, the leakage current between the bit line and source line in unselected cells increases during read and write operations, preventing normal operation. This makes it impossible to achieve a gate length of 45 nm or less, which makes it impossible to reduce the cell area.

[0005] There is also a demand for chips that include both high-speed access NOR flash memory and large-capacity NAND flash memory, but in this case, compatibility between the cell array structures and manufacturing processes of both is required.

[0006] The present invention aims to solve the above-mentioned conventional problems, and to provide a NOR flash memory that suppresses the leakage current of unselected cells and is compatible with NAND flash memories, and a method for manufacturing the same. [Means for solving the problem]

[0007] The NOR flash memory according to the present invention includes an active region formed in a semiconductor substrate so as to extend in a bit line direction, a trench adjacent to the active region, a charge storage layer formed on the active region for each memory cell and including a nitride layer sandwiched between insulating layers, a sidewall insulator formed in the trench and on a sidewall of the active region, a first conductive layer formed on the charge storage layer for each memory cell, and a second conductive layer formed on the first conductive layer so as to extend in a word line direction, the second conductive layer being electrically connected to the first conductive layer and contacting the sidewall insulator within the trench.

[0008] In one embodiment, a memory cell is composed of a memory cell transistor formed on the surface side of the active region and a sidewall transistor formed on the side of the active region. In one embodiment, a source / drain region adjacent to the channel region of the memory cell transistor is formed on the surface of the active region, and a source / drain region adjacent to the channel of the sidewall transistor is formed on the side of the active region. In one embodiment, the trench is aligned with the sidewalls of the first conductive layer and the charge storage layer. In one embodiment, the charge storage layer has an ONO structure of oxide / nitride / oxide, a structure including a stack of multiple types of insulating films other than oxide between a silicon substrate and the nitride layer, or a structure including a stack of multiple types of insulating films other than oxide between the nitride and the first conductive layer. In one embodiment, the memory cell transistor and the sidewall transistor are connected in parallel, and multiple memory cells are connected in series between a bit line side select transistor and a source line side select transistor. In one embodiment, the bit line side select transistor is electrically connected to a bit line, and the source line side select transistor is electrically connected to a source line. In one embodiment, the trench is formed in a self-aligned manner when etching the first conductive layer, the charge storage layer, and the semiconductor substrate.

[0009] A method for manufacturing a NOR flash memory according to the present invention includes the steps of: forming a stack of a charge storage layer and a first conductive layer, the charge storage layer including a nitride layer sandwiched between insulating layers, on a semiconductor substrate; simultaneously etching the first conductive layer, the charge storage layer, and the semiconductor substrate to pattern the first conductive layer and the charge storage layer in the bit line direction and form trenches in the semiconductor substrate to define active regions; forming a sidewall insulator covering sidewalls of the charge storage layer, the first conductive layer, and the active region; forming a second conductive layer extending in the word line direction so as to cover the sidewall insulator and the first conductive layer; and forming impurity regions for source / drain on the surface and side surfaces of the active region that are not covered by the second conductive layer.

[0010] In one embodiment, the manufacturing method further includes forming the second conductive layer on the entire surface of the semiconductor substrate including the first conductive layer, simultaneously etching the second conductive layer, the first conductive layer, and the charge storage layer to pattern the second conductive layer, the first conductive layer, and the charge storage layer in the word line direction. In one embodiment, the manufacturing method further includes filling the trench with an insulator, where the surface of the filled insulator is lower than the surface of the active region, and the bottom of the sidewall insulator is connected to the insulator. In one embodiment, the manufacturing method further includes forming a mask pattern covering the cell array region, removing the charge storage layer and the first conductive layer in the peripheral region, and forming a gate insulating film and a gate material in the peripheral region, the gate insulating film and the gate material being separated from the charge storage layer and the first conductive layer. In one embodiment, the step of forming the gate insulating film and the gate material includes forming the gate insulating film and the gate material on the entire surface of the semiconductor substrate and planarizing the gate insulating film and the gate material until the first conductive layer in the cell array region is exposed. [Effects of the Invention]

[0011] According to the present invention, a charge storage layer including a nitride layer is formed for each memory cell, which suppresses leakage current between the bit line and the source line in unselected cells compared to FG-type memory cells, reduces capacitive coupling between adjacent memory cells, and narrows the threshold distribution of memory cells. Furthermore, by aligning the trench adjacent to the active region with the sidewalls of the charge storage layer and the first conductive layer, it is possible to reduce capacitive coupling between adjacent memory cells while achieving high integration of the cell array. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a plan view of a cell array portion of a two-dimensional NOR flash memory according to an embodiment of the present invention; [Figure 2] 2A is a cross-sectional view taken along line AA in FIG. 1, and FIG. 2B is a cross-sectional view taken along line BB in FIG. [Figure 3]3A is an equivalent circuit of the cell array shown in FIG. 1, FIG. 3B is an equivalent circuit of one memory cell, and FIG. 3C is a cross-sectional view of one memory cell. [Figure 4] 3A to 3C are diagrams illustrating a manufacturing process of a cell array portion of the NOR flash memory according to the present embodiment. [Figure 5] 3A to 3C are diagrams illustrating a manufacturing process of a cell array portion of the NOR flash memory according to the present embodiment. [Figure 6] 3A to 3C are diagrams illustrating a manufacturing process of a cell array portion of the NOR flash memory according to the present embodiment. [Figure 7] Figure 7(A) is a plan view of the substrate when the first control gate, charge storage layer and substrate are etched through mask pattern M1, Figure 7(B) is a plan view of the substrate after mask pattern M1 has been removed, and Figure 7(C) is a plan view of the substrate after mask pattern M2 has been formed. [Figure 8] 1A to 1C are diagrams illustrating manufacturing processes for a cell array region and a peripheral region of a NOR flash memory according to an embodiment of the present invention. [Figure 8A] 10A to 10C are diagrams illustrating another manufacturing process for the cell array region and the peripheral region of the NOR flash memory of the present embodiment. [Figure 9] 1A to 1C are diagrams illustrating manufacturing processes for a cell array region and a peripheral region of a NOR flash memory according to an embodiment of the present invention. [Figure 10] 1A to 1C are diagrams illustrating manufacturing processes for a cell array region and a peripheral region of a NOR flash memory according to an embodiment of the present invention. [Figure 11] FIG. 11(A) is a diagram showing the threshold distribution of memory cells, and FIG. 11(B) is a table showing the bias voltages of the various parts during a read operation. [Figure 12] FIG. 12(A) is a diagram showing a part of the cell array during a program operation, and FIG. 12(B) is a table showing bias voltages of each part during the program operation. [Figure 13] 10 is a table showing bias voltages at various parts during an erase operation. DETAILED DESCRIPTION OF THE INVENTION

[0013] The two-dimensional NOR flash memory according to the present invention uses silicon nitride (SiN) as a charge storage layer, for example, a SONOS type (Si / oxide / nitride / oxide) charge storage layer to narrow the threshold voltage distribution (Vth) of memory cells. The NOR flash memory according to the present invention is used as a storage medium in various semiconductor devices (e.g., microcontrollers, microprocessors, logic devices, etc. that incorporate such flash memories). [Example]

[0014] Next, an embodiment of the present invention will be described with reference to the drawings. It should be noted that the scale of the drawings is exaggerated to facilitate understanding of the invention and does not necessarily represent the scale of an actual product.

[0015] 1 is a plan view of a cell array portion of a two-dimensional NOR flash memory according to an embodiment of the present invention. In the NOR flash memory 100 of this embodiment, for example, a P-type semiconductor substrate 110 is formed with a plurality of active regions 120 extending in the bit line direction, and each active region 120 is isolated by a trench 130.

[0016] A plurality of memory cells are formed between bit line-side select transistors connected to an SGD gate line and source line-side select transistors connected to an SGS gate line. A bit line BL is electrically connected to the drain regions of the bit line-side select transistors via contacts CT1, and a common source line SL is electrically connected to the sources of the source line-side select transistors via contacts CT2. As an example, four word lines WL0-WL3 are arranged between the bit line-side select transistors and the source line-side select transistors, and each of the word lines WL0-WL3 is electrically connected to the gates of corresponding memory cells in the row direction. This cell array structure has a significant portion in common with the cell array structure of a NAND flash memory, and is therefore compatible.

[0017] FIG. 2A shows a cross section of the area where memory cells are formed, taken along line AA. As shown in the figure, an active region 120 formed in a semiconductor substrate 110 provides a channel region for the memory cell. A patterned charge storage layer 140 is formed on the active region 120 for each memory cell. The charge storage layer 140 can be formed, for example, with an ONO structure, such as oxide / nitride / oxide, and can store charge at the nitride interface. Alternatively, the charge storage layer 140 can be formed by stacking multiple types of insulating films between the silicon substrate and the nitride layer, rather than a single oxide layer, or by stacking multiple types of insulating films between the nitride and the gate, rather than a single oxide layer. A first control gate (CG1) 150 is formed above the charge storage layer 140 and patterned for each memory cell. The first control gate 150 can be formed, for example, with impurity-doped conductive polysilicon, or by stacking multiple low-resistance materials, such as TaN, and another metal layer.

[0018] A trench insulator 160 is formed to fill the trench 130. An outermost surface S of the trench insulator 160 is located lower than an outermost surface of the active region 120. A sidewall insulator 162 is formed to cover the sidewalls of the first control gate 150 and the charge storage layer 140. The bottom of the sidewall insulator 162 is connected to the trench insulator 160.

[0019] The outermost surface of the first control gate 150 is exposed by the sidewall insulator 162, and a second control gate 170 extending in the word line direction is formed on the first control gate 150. The second control gate 170 is electrically connected to the first control gate 150 directly below it, and the second control gate 170, together with the first control gate 150, constitutes each of the word lines WL0 to WL3. The second control gate 170 desirably has low resistance and is made of a metal material such as Al or Cu. The first control gate 150 may be made of the same material as the second control gate 170, or may be made of a different material.

[0020] Although not shown here, in the bit line side select transistor and the source line side select transistor, the second control gate 170, together with the first control gate 150, respectively constitutes the SGD gate line and the SGS gate line, and the second control gate 170 is electrically connected to the first control gate 150 of the bit line side select transistor and the source line side select transistor, respectively.

[0021] 2(B) shows a cross section along line BB of an area where no memory cells are formed. An N-type diffusion region 180 for the memory cell is formed on the surface of active region 120 adjacent to the channel region of the memory cell, i.e., on the surface of active region 120 exposed by the word line. Furthermore, an N-type diffusion region 180A is formed to a certain depth on the opposing side of active region 120, and this diffusion region 180A is connected to diffusion region 180 on the surface.

[0022] Unlike the memory cell region, the charge storage layer 140 and the first control gate 150 are not formed on the active region 120, but a trench insulator 160 fills the trench 130, and a sidewall insulator 162 protrudes from the active region 120. Also, the second control gate 170 is not formed, and instead an interlayer insulating film 190 is formed to cover the trench insulator 160, the sidewall insulator 162 and the active region 120.

[0023] 3A is an equivalent circuit of the cell array portion of FIG. 1, FIG. 3B is an equivalent circuit of one memory cell, and FIG. 3C is a cross-sectional view of one memory cell. As shown in the figure, two or more memory cells MC (four memory cells are shown in the example) are connected between the bit line side select transistor BL_SEL and the source line side select transistor SL_TR. One memory cell MC includes a memory cell transistor CELL_TR and a sidewall transistor SW_TR connected in parallel, and these four memory cells MC are connected in series.

[0024] The memory cell transistor CELL_TR includes a channel region on the top surface of the active region 120, a charge storage layer 140 and a first control gate 150 on the active region 120, and an N-type diffusion region 180 serving as a source / drain. On the other hand, the sidewall transistor CELL_TR includes a channel region on the side of the active region 120, a sidewall insulator 162 serving as a gate insulating film, and an N-type diffusion region 180A serving as a source / drain. The threshold value of the sidewall transistor CELL_TR is adjusted by the film thickness of the sidewall insulator 162, the boron concentration in the channel region, etc.

[0025] As described above, in the NOR flash memory 100 of this embodiment, the charge storage layer 140 has an ONO structure of oxide / nitride / oxide, and the ONO structure provides a SONOS structure formed between the silicon substrate (or silicon well) 110 and the first control gate 150 made of polysilicon. During a program operation, the charge storage layer 140 stores charges that have tunneled from the channel region through the oxide layer by FN tunneling at the interface with the nitride layer, and during an erase operation, the charges stored in the charge storage layer are released to the channel region by tunneling through the oxide layer by FN tunneling.

[0026] In this embodiment, the thickness of the nitride layer (SiN layer) of the charge storage layer 140 is sufficiently smaller than the thickness of the floating gate of the FG structure, and the nitride layer is an insulating film, so that the capacitive coupling between adjacent memory cells can be reduced compared to the FG structure, and as a result, it is possible to narrow the threshold distribution of the memory cells. Furthermore, since the cell array structure of the NOR flash memory 100 of this embodiment has a configuration in which multiple memory cells are connected in series between the bit line side select transistor and the source line side select transistor, when a NAND flash memory is formed on the same chip, the manufacturing process can be simplified by using a compatible process.

[0027] Next, a manufacturing process for the cell array portion of the NOR flash memory of this embodiment will be described with reference to Figures 4 to 7. As shown in Figure 4(A), a charge storage layer 210 having a three-layer structure, for example, an oxide film such as SiO2, a SiN film such as Si3N4, and an oxide film such as SiO2, is formed on the surface of a P-type silicon substrate or P-type well 200 (hereinafter referred to as "substrate" for convenience) by CVD or the like. Furthermore, a first control gate 220 made of, for example, polysilicon is formed on the charge storage layer 210.

[0028] Next, as shown in Fig. 4(B), a mask material 230 such as a resist is formed. Next, the mask material 230 is patterned by a photolithography process into mask patterns M1 that are spaced apart at regular intervals and extend in the bit line direction, as shown in Fig. 4(C).

[0029] Next, as shown in Fig. 5(D), the exposed first control gate 220, charge storage layer 210, and substrate 200 are simultaneously anisotropically etched using a mask pattern M1 to form a stack of the charge storage layer 210 and first control gate 220 patterned in the bit line direction on the substrate 200. Simultaneously with this patterning, trenches 240 that define active regions 202 are formed in the substrate 200. Fig. 7(A) is a plan view of the substrate when the first control gate 220, charge storage layer 210, and substrate 200 have been etched using the mask pattern M1, and Fig. 5(D) corresponds to the cross section taken along line BB in Fig. 7(A).

[0030] When etching the stack of the charge storage layer 210 and the first control gate 220, the trench 240 is formed so as to be self-aligned with the stack of the charge storage layer 210 and the first control gate 220. Therefore, the trench 240 is formed with high precision without causing any positional error between the stack of the charge storage layer 210 and the first control gate 220. In addition, the charge storage layer 210 is protected from etching because it is covered by the first control gate 220.

[0031] 5(E), an insulating film 250 is formed on the entire surface of the substrate 200 including the trench 240, and then the insulating film 250 is etched so that a trench insulator 250A remains in the trench 240. At this time, the mask pattern M1 protects the first control gate 220 from etching.

[0032] Next, as shown in FIG. 5(F), the mask pattern M1 is removed. The outermost surface of the trench insulator 250A in the trench 240 is located lower than the outermost surface of the active region 202. Thus, the active region 202 extending in the bit line direction is isolated by the trench insulator 250A, and a stack of the charge storage layer 210 and the first control gate 220 is formed on the active region 202. FIG. 7(B) is a plan view of the substrate after removing the mask pattern M1, and FIG. 5(F) corresponds to the cross section taken along line CC in FIG. 7(B).

[0033] Next, as shown in Fig. 6(G), an insulating film 260 is formed on the entire surface of the substrate, and the insulating film 260 is anisotropically etched to form a sidewall insulating film 260A that covers the sidewalls of the charge storage layer 210 and the first control 210, as shown in Fig. 6(H). The sidewall insulating film 260A is connected to the trench insulator 250A at the bottom.

[0034] Next, as shown in FIG. 6(I), a conductive material 270 is formed over the entire surface of the substrate, and a mask pattern M2 extending in the word line direction is formed thereon. FIG. 7(C) is a plan view of the substrate after the mask pattern M2 has been formed, and FIG. 6(I) corresponds to the cross section taken along line DD in FIG. 7(C). The conductive material 270 is etched through the mask pattern M2 to pattern a second control gate extending in the word line direction. At this time, in areas where memory cells will not be formed, the conductive material 270, first control gate 220, and charge storage layer 210 exposed by the mask pattern M2 are simultaneously etched, exposing the active region 202, as shown in FIG. 6(J).

[0035] Next, phosphorus or arsenic ions are implanted into the exposed active region 202 to form N-type diffusion regions 180, 180A on the surface and side surfaces of the active region 202, as shown in Fig. 2(B). Next, an insulating film is formed over the entire surface of the substrate including the second control gate, and the insulating film is planarized by CMP or the like until the surface of the second control gate is exposed.

[0036] Next, the manufacturing process for the cell array region and the peripheral region of the NOR flash memory of this embodiment will be described with reference to Figures 8 to 10. As shown in Figure 8(A), a charge storage layer 310 and a first control gate (CG1) 320 are formed on the entire surface of a P-type silicon substrate 300, and then a mask pattern M3 is formed to cover the cell array region. Next, as shown in Figure 8(B), the mask pattern M3 is used as an etching mask to remove the charge storage layer 310 and the first control gate 320 on the peripheral region by etching.

[0037] After removing the mask pattern M3, as shown in FIG. 8(C), a gate insulating film 330 is formed on the entire surface of the substrate 300, including the peripheral region. The gate insulating film 330 is, for example, a silicon oxide film. Sense amplifiers, decoders, and other circuits are formed in the peripheral region, and these circuits include transistors driven at high voltages and transistors driven at low voltages. Therefore, the gate insulating film 330 is formed with multiple thicknesses, including thick and thin films suitable for high and low voltages. After the gate insulating film 330 is formed, a gate material 340 for the transistors in the peripheral region is formed on the entire surface of the substrate 300. The gate material 340 is, for example, polysilicon.

[0038] Next, the gate insulating film 330 and the gate material 340 are etched back or planarized to expose the first control gate 320 in the cell array region and the gate material 340 in the peripheral region, as shown in Fig. 8(D). Through these steps, the charge storage layer 310 and the first control gate 320 in the cell array region can be formed separately from the gate insulating film 330 and the gate material 340 in the peripheral region.

[0039] In the above process, the gate insulating film 330 and gate material 340 are formed after removing the mask pattern M3. However, this is just an example, and the mask pattern M3 may be left. As shown in FIG. 8A(E), the gate insulating film 330A and gate material 340A are formed over the entire surface of the substrate, including the mask pattern M3. In this case, the height of the mask pattern M3 in the cell array region is set to be approximately the same as the height of the gate material 340A when the gate insulating film 330A in the peripheral region is a thick insulating film with a high breakdown voltage. Furthermore, the gate insulating film 330A around the boundary between the cell array region and the peripheral region is a thick insulating film with a high breakdown voltage.

[0040] 8A(F), a planarization process is performed to expose the mask pattern M3 in the cell array region and the gate material 340A in the peripheral region, and then the mask pattern M3 is removed. Through these processes, the charge storage layer 310 and the first control gate 320 in the cell array region can be formed separately from the gate insulating film 330A and the gate material 340A in the peripheral region.

[0041] After the first control gate 320 in the cell array region and the gate material 340 in the peripheral region are formed separately, a mask pattern M4 is formed as shown in FIG. 9E, and the gate materials, gate insulating film, and silicon in the cell array region and the peripheral region are simultaneously etched to form trenches 350 and 352 in the substrate 300. The trench 350 formed in the cell array region may have a different size and / or depth than the trench 352 formed in the peripheral region.

[0042] After removing the mask pattern M4, an insulating material 360 is formed to fill the trenches 350 and 352, as shown in FIG. 9(F). The insulating material 360 is, for example, a silicon oxide film. Next, as shown in FIG. 9(G), the insulating material 360 is etched to form trench insulators 360A in the trenches 350 and 352. In the peripheral region, the trench insulator 360A filling the trench 352 is etched to the same height as the gate material 340, but is not etched any deeper.

[0043] Next, as previously described with reference to FIGS. 6(G) and 6(H), a sidewall insulating film (not shown here) is formed to cover the sidewalls of the active region 202, the charge storage layer 210, and the first control gate 220.

[0044] 10(H), a conductive material 370, which is a precursor of the second control gate, is formed on the entire surface of the substrate 300, including the first control gate 320 and the gate material 340. The conductive material 370 is not particularly limited, but may be a metal material such as Al or Cu. The conductive material 370 is electrically connected to the first control gate 320 and the gate material 340. Alternatively, a metal silicide may be formed between the conductive material 370 and the first control gate 320 and the gate material 340.

[0045] Next, as shown in FIG. 10(I), the conductive material 370 in the region where the charge storage layer 310 and the first control gate 320 are to be formed in the cell array is patterned to extend in the word line direction, forming a second control gate 370A. The second control gate 370A is electrically connected to a corresponding plurality of first control gates 320 in the row direction, providing a word line (see FIG. 6(I) for details). Furthermore, by patterning the conductive material 370, the underlying first control gates 320 and charge storage layer 310 are simultaneously etched, exposing the active region (see FIG. 6(J) for details). Meanwhile, in the peripheral region, the conductive material 370 is patterned to form a wiring layer 370B electrically connected to the gate material 340 and the like.

[0046] After patterning the second control gate 370A, ion implantation is performed to form N-type impurity regions for source / drain in the exposed active region 202. Then, bit lines BL and source lines SL are formed in the cell array region, similar to a conventional NAND flash memory.

[0047] The 2D-NOR flash memory of this embodiment has a charge storage layer formed by stacking multiple insulating layers, including SiN, between silicon and a control gate. The control gate is composed of two layers: a first control gate formed on the charge storage layer and a second control gate formed on the first control gate. The charge storage layer and the first control gate are successively deposited on silicon (Si). The first control gate, the charge storage layer, and the silicon are simultaneously etched to form a trench isolation region self-aligned to the first control gate and the charge storage layer. A second control gate is then formed on the first control gate, and the first control gate and the second control gate are electrically connected to each other to form a word line. The end of the word line in the cell array region is connected to a row decoder, which applies a bias to the word line WL for read, write (program), and erase operations.

[0048] Next, the operation of the NOR flash memory of this embodiment will be described. In the NOR flash memory of this embodiment, as shown in the equivalent circuit of the cell array in Figure 3, one memory cell is composed of two transistors: a memory cell transistor CELL_TR and a sidewall transistor SW_TR. The cell transistor CELL_TR includes a charge storage layer 140 formed on the surface of the active region and gated by a first control gate 150 and a second control gate 170. The sidewall transistor SW_TR includes a sidewall insulator formed on the side of the active region and gated by the second control gate 170 filled in the trench.

[0049] The charge storage layer of the memory cell transistor CELL_TR stores charge when programmed, and therefore the threshold voltage (Vt) of the memory cell transistor changes according to the charge in the charge storage layer. The bit line side select transistor BL_SEL and the source line side select transistor SL_SEL also consist of two transistors (i.e., the memory cell transistor CELL_TR and the sidewall transistor SW_TR). However, these transistors are not applied to program or erase operations. Therefore, there is no charge or a fixed charge in the charge storage layer, and the threshold voltage (Vt) is maintained at a constant value. Therefore, the threshold Vt of the source line side select transistor SL_SEL is determined by the lower threshold Vt of these two transistors. The threshold Vt of the bit line side select transistor BL_SEL is also determined by the lower threshold Vt.

[0050] In the cell array, memory cells connected to one word line can be called one page, and memory cells in multiple pages sandwiched between SGS and SGD can be called one block, which is similar to the cell array of NAND flash memory.

[0051] Next, the read operation of the NOR flash memory of this embodiment will be described. Figure 11(A) shows the threshold Vt distribution of the memory cell transistor CELL_TR when the NOR flash memory stores one bit per memory cell. WL1 is the voltage applied to the word line WL of the selected memory cell during read. The threshold Vt distribution of the sidewall transistor SW_TR is WL1 must be higher than

[0052] The threshold voltage Vt of the "1" cell is V WL1 The threshold voltage Vt of the memory cell transistor CELL_TR is set lower than V WL1 If the threshold voltage Vt of a "0" cell is V, the selected memory cell transistor CELL_TR is turned on, but the sidewall transistor SW_TR is turned off. WL1The threshold voltage Vt of the memory cell transistor CELL_TR is set higher than V WL1 If the voltage is higher than 0 V, the selected memory cell transistor CELL_TR is in the off state and the sidewall transistor SW_TR is in the off state.

[0053] The bias voltages for each part during a read operation are shown in the table in Figure 11(B). Cells of one page in the selected block are read simultaneously. To correctly read the selected cells, a voltage V is applied to the unselected word lines. WL2 is applied, where V WL2 is set higher than the threshold Vt of the sidewall transistor SW_TR. Therefore, all of the sidewall transistors SW_TR connected to unselected word lines are turned on, that is, all unselected memory cells are turned on regardless of the threshold Vt of their memory transistors CELL_TR, and the sidewall transistor SW_CELL of the selected memory cell is turned off, so that data in the selected memory cell transistor CELL_TR is read correctly. During a read operation, a voltage higher than the threshold Vt of the source line side select transistor SL_TR and the bit line side select transistor BL_SEL is applied to the SGS gate and SGD gate, turning on these select transistors.

[0054] For example, in Figure 3, when data is read from a memory cell MC connected to word line WL1, the sidewall transistor SW_TR connected to word line WL1 is in the off state, and the sidewall transistors SW_TR connected to unselected word lines WL0, WL2, and WL3 are all in the on state, and a current flows from the bit line BL to the source line SL according to the data "0" or "1" held in the memory cell transistor CELL_TR connected to word line WL1, and this current is sensed by the sense amplifier.

[0055] During read, the unselected cell array (unselected block) is V WL、 V SGS and V SGDare grounded. That is, the word lines WL and the SGS and SGD gates of the unselected cell arrays are grounded during read. To prevent read errors from the unselected cell arrays, the threshold voltage Vt of the source line side select transistors and bit line side select transistors must be higher than 0V. As a result, the unselected cell arrays can be completely turned off. Therefore, when a positive bias is applied to the bit line BL and the source line and P-well are grounded, if the cell being read in the selected block is a "1" cell, current flows from the bit line BL to the source line SL, but in the unselected blocks, no current flows from the bit line BL to the source line SL.

[0056] In the NOR flash memory of this embodiment, the cell array structure is similar to the NAND structure in that memory cells are connected between source line side select transistors and bit line side select transistors, and therefore the source line side select transistors and bit line side select transistors have relatively long gate lengths, making it possible to minimize leakage current between the bit lines and source lines of unselected blocks. This allows the gate length of the memory cells themselves to be shortened, reducing the effective cell size and the memory cell area.

[0057] The bias voltages during programming are shown in the table in Figure 12(B). In the programming operation, it is possible to program cells in one page at a time. Figure 12(A) shows two NOR cell arrays surrounded by dashed lines, and shows an example in which cell M1 connected to word line WL1 is programmed with "0" and cell M2 is programmed with "1" (i.e., "0" programming inhibit).

[0058] 0V is applied to the bit line BL of the left cell array, and some positive voltage (1.2 to 3V) is applied to the bit line BL of the right cell array. A high voltage (V program =8 to 16V) is applied to other word lines WL in the same cell array, and V program Almost half the voltage (V passA positive bias (1-2V) is applied to the SGD gate, which must be higher than the threshold voltage Vt of the bit line side select transistor BL_SEL. 0V is applied to the SGS gate, a positive bias (1-2V) is applied to the source line SL, and the P-well is grounded.

[0059] Applying 0V to the left bit line BL and applying a positive bias to the SGD gate turns on the bit line side select transistor BL_SEL and grounds the source side of the source line side select transistor SL_SEL. pass By applying V to the unselected cells, the unselected cells are also turned on, and 0V is transferred to the channel region of the selected cell (the left-hand cell M1 connected to WL1). The channel is grounded and a high voltage (V program ) allows electrons to tunnel into the charge storage layer, thus increasing the threshold voltage Vt of cell M1 and programming cell M1 to the "0" state.

[0060] Meanwhile, a slight positive bias is applied to the right bit line BL, so that the bit line side select transistor BL_SEL is turned off. By applying 0V to the SGS gate, the source line side select transistor SL_SEL is turned off. Therefore, the channel of the right NOR cell array is isolated from the bit line BL and the source line SL. Then, V is applied to the unselected word line WL and the selected word line WL1. pass and V program By applying a voltage of 0 V to the NOR cell array on the right, the channel region of the NOR cell array on the right can be boosted. This reduces the voltage difference between the silicon surface and the word line WL, preventing electron tunneling from the silicon surface to the charge storage layer, and preventing the threshold voltage Vt of cell M2 from shifting. Therefore, the selected cell M2 is programmed to "1." This programming sequence is essentially the same as programming conventional NAND flash memory.

[0061] Also, during program operation, the V WL、 VSGS and V SGD The non-selected blocks are grounded, and the source line side select transistors and bit line side select transistors, which have relatively long gate lengths, can be used to completely turn off the non-selected blocks. This allows the gate length of the memory cells themselves to be shortened, thereby reducing the effective cell size.

[0062] Next, the erase operation will be described. The bias voltages during the erase operation are shown in the table of FIG. 13. In the NOR flash memory of this embodiment, it is possible to erase one block at a time. All the word lines WL of the selected block are grounded, and V is applied to the P-well. erase By applying a voltage (8 to 16V), electrons in the charge storage layer move to the silicon surface, or holes on the silicon surface tunnel into the charge storage layer. This shifts the cell's threshold voltage Vt downward, and the cell enters the "1" state. The bit line BL, source line SL, SGS gate line, SGD gate line, and word line WL of the unselected block are in a floating state. The word line WL is in a floating state, and V WL V p-well Since the threshold voltage Vt of the cells in the unselected blocks is automatically boosted to a value close to .gt., the threshold voltage Vt of the cells in the unselected blocks does not shift.

[0063] The thickness of the sidewall insulating film (Tox: effective oxide thickness) which is the gate insulating film of the sidewall transistor is V program or V erase To avoid breakdown of the sidewall insulating film, the electric field applied between the second control gate and the sidewall of the silicon (active region) must be 5MV / cm or less (V program / Tox≦5MV / cm, and V erase / Tox≦5MV / cm).

[0064] As described above, the NOR flash memory according to this embodiment stores charges in a charge storage layer formed by stacking insulating layers containing nitride. Each memory cell includes a sidewall transistor including a sidewall insulator formed on the trench sidewall and a second control gate in the trench, and a memory cell transistor including a charge storage layer, a first control gate, and a second control gate formed on the silicon surface side. A source and a drain are formed in the space between the two cells, and ion implantation of the source and drain is performed on the surface and sidewall of the silicon (active region).

[0065] In this embodiment, an example of a charge storage layer having a three-layer structure of oxide / nitride / oxide is shown, but the present invention is not limited to this, and a charge storage layer having four or more layers including nitride may also be used. Also, the memory cell may be an SLC type that stores one bit (binary data) or a type that stores multiple bits.

[0066] Although the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the specific embodiment, and various modifications and variations are possible within the scope of the gist of the invention described in the claims. [Explanation of symbols]

[0067] 100: NOR flash memory 110: Semiconductor substrate 120:Active region 130: Trench 140: Charge storage layer 150: First Control Gate (CG1) 160: Trench insulator 162: Sidewall insulator 170: Second Control Gate 180, 182: N-type impurity region CELL_TR: memory cell transistor SW_TR: Sidewall transistor

Claims

1. A NOR type flash memory, an active region formed in a semiconductor substrate so as to extend in a bit line direction; a trench adjacent to the active region; a charge storage layer formed on the active region for each memory cell, the charge storage layer including a nitride layer sandwiched between insulating layers; a sidewall insulator formed in the trench and on a sidewall of the active region; a first conductive layer formed on the charge storage layer for each memory cell; a second conductive layer formed on the first conductive layer so as to extend in a word line direction; The second conductive layer is electrically connected to the first conductive layer and contacts the sidewall insulator within the trench.

2. 2. The NOR type flash memory according to claim 1, wherein the memory cell is composed of a memory cell transistor formed on the surface side of said active region and a sidewall transistor formed on the side surface of said active region.

3. 3. The NOR type flash memory according to claim 2, wherein source / drain regions adjacent to the channel region of the memory cell transistor are formed on the surface of the active region, and source / drain regions adjacent to the channel of the sidewall transistor are formed on the side of the active region.

4. 2. The NOR flash memory of claim 1, wherein the trench is aligned with sidewalls of the first conductive layer and the charge storage layer.

5. 2. The NOR type flash memory according to claim 1, wherein the charge storage layer comprises an ONO structure of oxide / nitride / oxide, or a structure including a stack of multiple types of insulating films other than oxide between a silicon substrate and the nitride layer, or a structure including a stack of multiple types of insulating films other than oxide between the nitride and the first conductive layer.

6. the memory cell transistor and the sidewall transistor are connected in parallel; 3. The NOR type flash memory according to claim 2, wherein a plurality of memory cells are connected in series between the bit line side select transistor and the source line side select transistor.

7. 7. The NOR flash memory according to claim 6, wherein said bit line side select transistor is electrically connected to a bit line, and said source line side select transistor is electrically connected to a source line.

8. 6. The NOR type flash memory according to claim 5, wherein said trench is formed in a self-aligned manner when said first conductive layer, said charge storage layer and said semiconductor substrate are etched.

9. A method for manufacturing a NOR type flash memory, comprising: forming a stack of a charge storage layer and a first conductive layer on a semiconductor substrate, the charge storage layer including a nitride layer sandwiched between insulating layers; simultaneously etching the first conductive layer, the charge storage layer, and the semiconductor substrate to pattern the first conductive layer and the charge storage layer in a bit line direction and to form trenches in the semiconductor substrate that define active regions; forming a sidewall insulator covering sidewalls of the charge storage layer, the first conductive layer, and the active region; forming a second conductive layer extending in a word line direction so as to cover the sidewall insulator and the first conductive layer; forming impurity regions for source / drain on the surface and side surfaces of the active region that are not covered by the second conductive layer; A manufacturing method comprising the steps of:

10. The manufacturing method further comprises: forming the second conductive layer on the entire surface of the semiconductor substrate including the first conductive layer; 10. The manufacturing method according to claim 9, further comprising the step of simultaneously etching the second conductive layer, the first conductive layer, and the charge storage layer to pattern the second conductive layer, the first conductive layer, and the charge storage layer in a word line direction.

11. The manufacturing method according to claim 9 , further comprising the step of filling the trench with an insulator, the surface of the filled insulator being lower than the surface of the active region, and the bottom of the sidewall insulator being connected to the insulator.

12. The manufacturing method further comprises: forming a mask pattern covering a cell array region, and removing the charge storage layer and the first conductive layer on a peripheral region; forming a gate insulating film and a gate material on a peripheral region, the gate insulating film and the gate material being separated from the charge storage layer and the first conductive layer; The method of claim 10, comprising:

13. The step of forming the gate insulating film and the gate material includes:

13. The manufacturing method according to claim 12, further comprising forming the gate insulating film and the gate material on the entire surface of a semiconductor substrate, and planarizing the gate insulating film and the gate material until the first conductive layer on the cell array region is exposed.

14. 11. The manufacturing method according to claim 10, wherein the charge storage layer comprises an ONO structure of oxide / nitride / oxide, or a structure including a stack of multiple types of insulating films other than oxide between a silicon substrate and the nitride layer, or a structure including a stack of multiple types of insulating films other than oxide between the nitride and the first conductive layer.

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