Imaging element and imaging device

Abstract

To simplify a circuit of an imaging device.SOLUTION: An imaging device includes: a first substrate having a plurality of pixel blocks including one or more pixels; a control circuit part including a first control block including a first exposure control part for controlling exposure time for pixels included in a first pixel block within the plurality of pixel blocks and a second control block including a second exposure control part for controlling exposure time for pixels included in a second pixel block within the plurality of pixel blocks; and a second substrate arranged external of the control circuit part, having a peripheral circuit part for controlling signal read of pixels respectively included at least in the first pixel block and the second pixel block within the plurality of pixel blocks.SELECTED DRAWING: Figure 1E

Description

[Technical Field]

[0001] The present invention relates to an imaging element and an imaging device. [Background technology]

[0002] It is known that in an imaging device having a plurality of pixels, the exposure time for each pixel is changed (for example, Patent Document 1). Patent Document 1 Special Publication No. 2015-532797

[0003] In conventional imaging devices, simplification of the circuitry is desired. Summary of the Invention

[0004] In a first aspect of the present invention, there is provided an imaging element comprising: a first substrate having a plurality of pixel blocks each including one or more pixels; a control circuit section including a first control block including a first exposure control section for controlling the exposure time of pixels included in a first pixel block among the plurality of pixel blocks; and a second control block including a second exposure control section for controlling the exposure time of pixels included in a second pixel block among the plurality of pixel blocks; and a second substrate having a peripheral circuit section arranged outside the control circuit section and controlling signal readout of pixels included in at least the first pixel block and the second pixel block among the plurality of pixel blocks.

[0005] In a second aspect of the present invention, there is provided an imaging device including the imaging element of the first aspect.

[0006] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0007] [Figure 1A] 1 is a diagram showing an overview of an image sensor 400 according to an embodiment of the present invention. [Figure 1B] An example of a specific configuration of the pixel section 110 will be shown. [Figure 1C] 1 shows an example of a circuit configuration of a pixel 112. [Figure 1D] An example of a more specific configuration of the control circuit section 210 will be shown. [Figure 1E] 10 is a diagram for explaining an example of a wiring method for the imaging element 400. FIG. [Figure 2A] 1 shows an example of a timing chart illustrating the imaging operation of the imaging element 400. [Figure 2B] 1 shows an example of a timing chart illustrating the imaging operation of the imaging element 400. [Figure 3] 10 shows a timing chart illustrating an imaging operation of an imaging element according to a comparative example. [Figure 4A] An example of a subject captured by the image sensor 400 is shown. [Figure 4B] 1 shows a timing chart illustrating the imaging operation of the imaging element 400. [Figure 5] FIG. 4 is a diagram showing an overview of an image sensor 400. [Figure 6] An example of a specific configuration of the pixel section 110 will be shown. [Figure 7] An example of a more specific configuration of the control circuit section 210 will be shown. [Figure 8] 1 shows an example of a circuit configuration of a pixel 112. [Figure 9] 10 is a diagram for explaining an example of a wiring method for the imaging element 400. FIG. [Figure 10] 10 is a diagram for explaining an example of a wiring method for the imaging element 400. FIG. [Figure 11] 10 is a diagram for explaining an example of a wiring method for the imaging element 400. FIG. [Figure 12] 1 shows an example of a timing chart illustrating an imaging operation in a pixel block 120 of the imaging element 400. [Figure 13] An example of exposure timing for each pixel block 120 is shown below. [Figure 14] FIG. 8 is a diagram showing an overview of an image sensor 800 according to another embodiment. [Figure 15] An example of a specific configuration of the pixel portion 610 is shown. [Figure 16] An example of a more specific configuration of the control circuit section 710 will be shown. [Figure 17] An example of exposure timing for each pixel block 620 is shown. [Figure 18] Another example of the pixel 114 of the image sensor 400, 800 is shown. [Figure 19] 10 shows an example of a timing chart illustrating an imaging operation in a pixel block 120 using the pixel 114. [Figure 20] An example of exposure timing for each pixel block 120 using the pixel 114 is shown. [Figure 21] FIG. 1 is a block diagram showing an example of the configuration of an imaging device 500 according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0009] In this specification, the X-axis and Y-axis are perpendicular to each other, and the Z-axis is perpendicular to the XY plane. The XYZ-axes form a right-handed system. The direction parallel to the Z-axis may be referred to as the stacking direction of the image sensor 400. In this specification, the terms "up" and "down" are not limited to the up and down directions in the direction of gravity. These terms merely refer to relative directions in the Z-axis direction. Note that in this specification, the arrangement in the X-axis direction will be described as a "row" and the arrangement in the Y-axis direction as a "column," but the matrix direction is not limited to this.

[0010] 1A is a diagram showing an overview of an image sensor 400 according to this embodiment. The image sensor 400 captures an image of a subject. The image sensor 400 generates image data of the captured subject. The image sensor 400 includes a first substrate 100 and a second substrate 200. As shown in FIG. 1A, the first substrate 100 is stacked on the second substrate 200.

[0011] The first substrate 100 has a pixel section 110. The pixel section 110 outputs a pixel signal based on incident light.

[0012] The second substrate 200 has a control circuit section 210 and a peripheral circuit section 230 .

[0013] The control circuit unit 210 receives pixel signals output from the first substrate 100. The control circuit unit 210 processes the input pixel signals. In this example, the control circuit unit 210 is disposed on the second substrate 200 at a position facing the pixel unit 110. The control circuit unit 210 may output a control signal to the pixel unit 110 to control driving of the pixel unit 110.

[0014] The peripheral circuit unit 230 controls the driving of the control circuit unit 210. In one example, the peripheral circuit unit 230 controls signal readout of pixels included in the pixel unit 110. The peripheral circuit unit 230 is arranged around the control circuit unit 210 on the second substrate 200. The peripheral circuit unit 230 may also be electrically connected to the first substrate 100 and control the driving of the pixel unit 110. In this example, the peripheral circuit unit 230 is arranged along two sides of the second substrate 200, but the arrangement of the peripheral circuit unit 230 is not limited to this example.

[0015] In addition to the first substrate 100 and the second substrate 200, the imaging element 400 may have a memory chip stacked on the second substrate 200. For example, the memory chip performs image processing according to the signal output by the second substrate 200. The imaging element 400 may have a back-illuminated or front-illuminated structure.

[0016] 1B shows an example of a specific configuration of the pixel section 110. In this example, an enlarged view of the pixel section 110 and a pixel block 120 provided in the pixel section 110 is shown.

[0017] The pixel unit 110 has a plurality of pixel groups 115 arranged side by side in the row and column directions. In this example, the pixel unit 110 has M×N pixel groups 115 (M and N are natural numbers). In this example, M is equal to N, but M and N may be different.

[0018] The pixel group 115 has at least one pixel 112. In this example, the pixel group 115 has m×n pixels 112 (m and n are natural numbers). For example, the pixel group 115 has 16×16 pixels 112. The number of pixels 112 corresponding to the pixel group 115 is not limited to this. In this example, the case where m is equal to n is illustrated, but m may be different from n. The pixel group 115 has multiple pixels 112 connected to a common control line in the row direction. For example, each pixel 112 in the pixel group 115 is connected to a common control line so that they are set to the same exposure time. In one example, n pixels 112 arranged in the row direction are connected by a common control line.

[0019] On the other hand, different exposure times may be set for the different pixel groups 115. That is, the pixels 112 of one pixel group 115 may have the same exposure time, but may be set to different exposure times for the other pixel groups 115. For example, if the pixels 112 of one pixel group 115 are connected in the row direction by a common control line, the pixels 112 of the other pixel groups 115 may be connected in common by a different control line.

[0020] The pixel block 120 has one or more pixel groups 115. In this example, the pixel block 120 has two pixel groups 115 arranged side by side in the column direction. The pixel block 120 is arranged to correspond to a control block 220, which will be described later. That is, two pixel groups 115 are arranged for one control block 220. When the pixel block 120 has multiple pixel groups 115, each pixel group 115 may be set to a different exposure time. When the pixel block 120 has one pixel group 115, one pixel group 115 is arranged for the control block 220. The pixel block 120 has 2m×n pixels 112. For example, the pixel block 120 has 32×16 pixels 112. The number of pixels 112 corresponding to the pixel block 120 is not limited to this.

[0021] The pixels 112 have a photoelectric conversion function that converts light into electric charges. The pixels 112 accumulate the electric charges generated by photoelectric conversion. 2m pixels 112 are arranged in the column direction and connected to a common signal line 122. The 2m pixels 112 are arranged in n columns in the row direction in the pixel block 120.

[0022] 1C shows an example of the circuit configuration of a pixel 112. The pixel 112 includes a photoelectric conversion unit 104, a transfer unit 123, a discharge unit 124, a reset unit 126, and a pixel output unit 127. The pixel output unit 127 includes an amplifier unit 128 and a selection unit 129. In this example, the transfer unit 123, the discharge unit 124, the reset unit 126, the amplifier unit 128, and the selection unit 129 are described as N-channel FETs, but the type of transistor is not limited to this.

[0023] The photoelectric conversion unit 104 has a photoelectric conversion function of converting light into electric charges. The photoelectric conversion unit 104 accumulates the electric charges generated by photoelectric conversion. The photoelectric conversion unit 104 is, for example, a photodiode.

[0024] The transfer unit 123 transfers the charges accumulated in the photoelectric conversion unit 104 to the accumulation unit 125. The transfer unit 123 is an example of a transfer gate that transfers the charges of the photoelectric conversion unit 104. A gate terminal of the transfer unit 123 is connected to a local control line for inputting a first transfer control signal φTX1. The local control line will be described later.

[0025] The discharge unit 124 discharges the charges accumulated in the photoelectric conversion unit 104 to a power supply wiring to which a power supply voltage VDD is supplied. A gate terminal of the discharge unit 124 is connected to a local control line for inputting a second transfer control signal φTX2. Note that, although the discharge unit 124 has been described in this example as discharging the charges of the photoelectric conversion unit 104 to a power supply wiring to which a power supply voltage VDD is supplied, the discharge unit 124 may also discharge the charges to a power supply wiring to which a power supply voltage different from the power supply voltage VDD is supplied.

[0026] The charge from the photoelectric conversion unit 104 is transferred to the accumulation unit 125 by the transfer unit 123. The accumulation unit 125 is an example of a floating diffusion (FD).

[0027] The reset unit 126 discharges the charge in the storage unit 125 to a power supply line to which a predetermined power supply voltage VDD is supplied. A gate terminal of the reset unit 126 is connected to a global control line 163 for inputting a reset control signal φRST. The global control line 163 will be described later.

[0028] The pixel output unit 127 outputs a signal based on the potential of the storage unit 125 to the signal line 122. The pixel output unit 127 has an amplifier unit 128 and a selection unit 129. The amplifier unit 128 has a gate terminal connected to the storage unit 125, a drain terminal connected to a power supply line to which a power supply voltage VDD is supplied, and a source terminal connected to the drain terminal of the selection unit 129.

[0029] The selection unit 129 controls the electrical connection between the pixel 112 and the signal line 122. When the selection unit 129 electrically connects the pixel 112 and the signal line 122, a pixel signal is output from the pixel 112 to the signal line 122. A gate terminal of the selection unit 129 is connected to a global control line 163 for inputting a selection control signal φSEL. A source terminal of the selection unit 129 is connected to the load current source 121.

[0030] The load current source 121 supplies a current to the signal line 122. The load current source 121 may be provided on the first substrate 100 or on the second substrate 200.

[0031] 1D shows an example of a more specific configuration of the control circuit section 210. In this example, an enlarged view of the control circuit section 210 and a control block 220 provided in the control circuit section 210 is shown.

[0032] The control circuit unit 210 has control blocks 220 arranged in the row and column directions. In this example, the control circuit unit 210 has (M / 2)×N control blocks 220. In this example, the control circuit unit 210 has one control block 220 for two pixel groups 115 arranged side by side in the column direction.

[0033] The control blocks 220 are disposed at positions corresponding to the pixel blocks 120. The control blocks 220 control the driving of the corresponding pixel blocks 120. For example, the control blocks 220 control the exposure time of the pixel blocks 120. The control blocks 220 may control the exposure time for each pixel group 115. The control blocks 220 also have processing circuits such as AD converters, and process signals output by the pixel blocks 120. In one example, the control blocks 220 convert analog pixel signals output from the corresponding pixel blocks 120 into digital signals. The control blocks 220 in this example include an exposure control unit 10, a pixel driving unit 20, a joining unit 30, a signal processing unit 40, and a signal output unit 50.

[0034] The exposure control unit 10 controls exposure of the plurality of pixels 112. The exposure control unit 10 generates a signal for controlling the exposure time of the pixels 112. In one example, the exposure control unit 10 adjusts at least one of the start timing and end timing of exposure to control the exposure time for each pixel group 115. The exposure control unit 10 in this example is provided extending in the row direction.

[0035] The pixel driving unit 20 is bonded to the first substrate 100 and drives a plurality of pixels 112. The pixel driving unit 20 selects and drives an arbitrary pixel 112 from the plurality of pixels 112. In this example, the pixel driving unit 20 is provided extending in the column direction. As a result, the pixel driving unit 20 is disposed at a position corresponding to 2m pixels 112 disposed in the column direction. The exposure control unit 10 and the pixel driving unit 20 are disposed in an L-shape, with the pixel driving unit 20 extending in the column direction and the exposure control unit 10 extending in the row direction.

[0036] The bonding unit 30 bonds the first substrate 100 and the second substrate 200. The bonding unit 30 inputs pixel signals input from the first substrate 100 to the signal processing unit 40. The bonding units 30 are provided corresponding to n pixels 112 arranged in the row direction, and input pixel signals to the signal processing unit 40 for each column.

[0037] The signal processing unit 40 converts analog signals output by the pixel unit 110 into digital signals. In this example, the signal processing unit 40 converts analog pixel signals into digital signals. The signal processing unit 40 sequentially converts analog signals from 2m pixels 112 arranged in the column direction into digital signals. The signal processing unit 40 converts analog signals from pixels 112 arranged in n columns in the row direction in parallel into digital signals.

[0038] The signal output unit 50 receives a digital signal from the signal processing unit 40. In one example, the signal output unit 50 temporarily stores the digital signal. The signal output unit 50 may have a latch circuit for storing the digital signal. The signal output unit 50 is provided between the signal processing unit 40 and the exposure control unit 10 in the column direction, and outputs a digital signal. In this example, the signal output unit 50 outputs the digital signal to the outside of the control circuit unit 210. The signal output unit 50 extends in the row direction and is provided adjacent to the signal processing unit 40 and the exposure control unit 10.

[0039] The image sensor 400 of this example has a function of reading out pixel signals in parallel using a control block 220 provided for each pixel block 120. The image sensor 400 can set the exposure time for each pixel group 115 according to the intensity of incident light, thereby expanding the dynamic range.

[0040] 1E is a diagram illustrating an example of a wiring method for the image sensor 400. In this example, the global driving section 234 is provided in the peripheral circuit section 230 disposed on both ends of the control circuit section 210.

[0041] The local control line 161 is connected to the pixel block 120a. In this example, the local control line 161 is connected to the gate terminals of the transfer unit 123 and the discharge unit 124 provided in the pixel block 120a. The local control line 161 supplies the first transfer control signal φTX1 and the second transfer control signal φTX2 output from the control block 220a to the pixel block 120a. The local control line 161 is an example of a first control line connected to a first pixel in the pixel block 120a. The local control line 161 may be provided corresponding to the pixel group 115 in the pixel block 120a. For example, in the pixel group 115, a common local control line 161 is connected to n pixels 112 arranged in the row direction.

[0042] The local control line 162 is connected to the pixel block 120b. In this example, the local control line 162 is connected to the gate terminals of the transfer unit 123 and the discharge unit 124 provided in the pixel block 120b. The local control line 162 supplies the first transfer control signal φTX1 and the second transfer control signal φTX2 output from the control block 220b to the pixel block 120b. The local control line 162 is an example of a second control line connected to a second pixel in the pixel block 120b. The local control line 162 may be provided corresponding to the pixel group 115 in the pixel block 120b. For example, in the pixel group 115, a common local control line 162 is connected to n pixels 112 arranged in the row direction.

[0043] The global driver 234 outputs a reset control signal φRST, a selection control signal φSEL, and a transfer selection control signal φTXSEL. The global driver 234 is connected to global control lines 163 that output signals to each pixel block 120. The global driver 234 supplies the reset control signal φRST and the selection control signal φSEL to the plurality of pixel blocks 120 via the global control lines 163. The global driver 234 supplies the transfer selection control signal φTXSEL to the plurality of control blocks 220 via the global control lines 163.

[0044] The transfer selection control signal φTXSEL is supplied from the global driver 234 to the control block 220 to control the exposure time for each pixel group 115. The control block 220, to which the transfer selection control signal φTXSEL is supplied, outputs the transfer selection control signal φTXSEL to the corresponding pixel block 120. The pixel block 120 determines whether to input the transfer selection control signal φTXSEL to the pixel 112 as the first transfer control signal φTX1 or the second transfer control signal φTX2. As a result, input of the first transfer control signal φTX1 or the second transfer control signal φTX2 to the pixel 112 is skipped.

[0045] For example, when the first transfer control signal φTX1 determines the end time of exposure, the control block 220 extends the exposure time by skipping the first transfer control signal φTX1. Also, when the first transfer control signal φTX1 determines the start time of exposure, the control block 220 can shorten the exposure time by skipping the first transfer control signal φTX1. In this way, the exposure time of the pixel group 115 can be adjusted by the transfer selection control signal φTXSEL. The same applies when the second transfer control signal φTX2 determines the start or end time of exposure.

[0046] The global control line 163 is provided in common to multiple pixel blocks 120. In this example, the global control line 163 is wired so as to cross the first substrate 100 in the row direction. The global control line 163 may also be wired so as to cross the first substrate 100 in the column direction. The global control line 163 is an example of a third control line that is provided in common to the pixels connected to the local control line 161 and the pixels connected to the local control line 162.

[0047] For example, the global control line 163 is connected to the gate terminals of the reset unit 126 and the selection unit 129 of the pixel block 120, and supplies a reset control signal φRST and a selection control signal φSEL. The global control line 163 is also connected to each of the multiple control blocks 220, and supplies a transfer selection control signal φTXSEL to the exposure control unit 10.

[0048] In this example, the global driving unit 234 outputs the transfer selection control signal φTXSEL from the second substrate 200 to the first substrate 100, but the transfer selection control signal φTXSEL may be output to the control block 220 without being supplied to the first substrate 100. In this case, the global control line 163 is provided on the second substrate 200.

[0049] The plurality of bumps 152 are provided on the bonding surfaces where the first substrate 100 and the second substrate 200 are bonded to each other. The bumps 152 of the first substrate 100 are aligned with the bumps 152 of the second substrate 200. The plurality of opposing bumps 152 are bonded and electrically connected by applying pressure to the first substrate 100 and the second substrate 200 or the like.

[0050] The image sensor 400 of this example controls the exposure time for each pixel group 115 by changing the timing of at least one of the transfer unit 123 and the discharge unit 124 using local control lines. By combining local control lines and global control lines, the image sensor 400 can control the exposure time with fewer control lines.

[0051] 2A shows an example of a timing chart illustrating the imaging operation of the image sensor 400. In this example, the driving of the image sensor 400 is controlled by a first transfer control signal φTX1, a second transfer control signal φTX2, a reset control signal φRST, and a selection control signal φSEL.

[0052] The second transfer control signal φTX2 controls the timing to start exposure. The exposure start timing corresponds to the falling edge of the second transfer control signal φTX2 (for example, time T1). That is, before the exposure start time T1, the second transfer control signal φTX2 turns on the discharge unit 124 to discharge the charge accumulated in the photoelectric conversion unit 104, and exposure starts at the falling edge of the second transfer control signal φTX2. In this example, the second transfer control signal φTX2 is locally controlled, so the exposure time can be adjusted for each pixel group 115.

[0053] The first transfer control signal φTX1 controls the timing to end exposure. At time T3, the first transfer control signal φTX1 turns on the transfer unit 123, thereby transferring the charges accumulated in the photoelectric conversion unit 104 to the accumulation unit 125. The timing to end exposure corresponds to the falling edge of the first transfer control signal φTX1 (for example, time T4). In this example, the first transfer control signal φTX1 is a globally controlled signal, so the timing to end exposure is the same for each pixel group 115.

[0054] The reset control signal φRST controls the timing of discharging the charge accumulated in the storage unit 125. At time T2, the reset control signal φRST turns on the reset unit 126, thereby discharging the charge in the storage unit 125. In this example, by discharging the charge in the storage unit 125 before the timing of the end of exposure, it is possible to suppress the influence of the charge remaining in the storage unit 125 when the charge is transferred from the photoelectric conversion unit 104.

[0055] The selection control signal φSEL is a signal for selecting an arbitrary pixel 112. The selection control signal φSEL controls the on / off of the selection unit 129. At time T2, the selection control signal φSEL is set to high. At time T3, the pixel 112 for which the selection control signal φSEL is set to high outputs a pixel signal to the signal line 122 in response to the first transfer control signal φTX1 being turned on. On the other hand, the pixel 112 for which the selection control signal φSEL is not set to high does not output a pixel signal.

[0056] The image sensor 400 of this example locally controls the second transfer control signal φTX2, thereby changing the exposure start timing for each pixel group 115 and controlling the exposure time for each pixel group 115. The image sensor 400 may also locally control the first transfer control signal φTX1 to control the exposure end timing for each pixel group 115. The image sensor 400 may also locally control both the first transfer control signal φTX1 and the second transfer control signal φTX2 to control both the exposure start timing and end timing for each pixel group 115.

[0057] 2B shows an example of a timing chart illustrating the imaging operation of the image sensor 400. In this example, the driving of the image sensor 400 is controlled by a first transfer control signal φTX1, a reset control signal φRST, and a selection control signal φSEL. The image sensor 400 of this example differs from the case of FIG. 2A in that the timing of the start of exposure is controlled by the first transfer control signal φTX1. In this example, the differences from FIG. 2A will be particularly described.

[0058] The first transfer control signal φTX1 controls the timing of the start and end of exposure. In frame (n), exposure starts at time T5 and ends at time T7.

[0059] At exposure start time T5, the first transfer control signal φTX1 falls, thereby starting exposure. That is, before exposure start time T5, the first transfer control signal φTX1 turns on the transfer unit 123 while the reset control signal φRST is on, thereby discharging the charge accumulated in the photoelectric conversion unit 104, and exposure starts at the falling edge of the first transfer control signal φTX1. In this example, the first transfer control signal φTX1 is a locally controlled signal, so the timing at which exposure starts for each pixel group 115 can be changed. However, the timing at which exposure starts for each pixel group 115 may also be synchronized.

[0060] Furthermore, at exposure end time T7, the first transfer control signal φTX1 falls, thereby ending the exposure. That is, before exposure end time T7, the first transfer control signal φTX1 turns on the transfer unit 123 while the reset control signal φRST is off, thereby transferring the charge accumulated in the photoelectric conversion unit 104 to the storage unit 125, and exposure ends at the falling edge of the first transfer control signal φTX1. In this example, the first transfer control signal φTX1 is a locally controlled signal, so the timing at which exposure ends can be changed for each pixel group 115. However, the timing at which exposure ends can also be synchronized for each pixel group 115.

[0061] The selection control signal φSEL is a signal for selecting an arbitrary pixel 112. At time T6, the pixel 112 for which the selection control signal φSEL is set high outputs a pixel signal to the signal line 122.

[0062] The reset control signal φRST controls the timing of discharging the charge accumulated in the accumulation unit 125. The reset control signal φRST may be a globally controlled signal. Since the reset control signal φRST is always on except at the timing of readout, no charge is accumulated in the accumulation unit 125. On the other hand, by turning off the reset control signal φRST and turning on the first transfer control signal φTX1 at the timing of readout, charge is transferred from the photoelectric conversion unit 104 to the accumulation unit 125. In this example, the reset control signal φRST has the same switching timing during readout, so it can be made common to the pulse of the selection control signal φSEL.

[0063] The image sensor 400 of this example locally controls the first transfer control signal φTX1, thereby changing the timing of when exposure starts or ends for each pixel group 115, and thereby controlling the exposure time for each pixel group 115. Furthermore, the image sensor 400 uses a common pulse for the reset control signal φRST and the selection control signal φSEL, which allows for further simplification of the control circuit.

[0064] 3 is a timing chart showing the imaging operation of an image sensor according to a comparative example. In this example, the driving of the image sensor is controlled by a first transfer control signal φTX1, a reset control signal φRST, and a selection control signal φSEL.

[0065] In the comparative example, the start of exposure is controlled by the first transfer control signal φTX1 and the reset control signal φRST. The exposure start timing is the timing (time t1) of the falling edges of the first transfer control signal φTX1 and the reset control signal φRST. The exposure end timing is the timing (time t2) of the falling edge of the first transfer control signal φTX1. In the comparative example, the exposure start timing and end timing are controlled globally, and the exposure time is not controlled for each pixel group 115.

[0066] 4A shows an example of a subject captured by the image sensor 400. The image sensor 400 of this example controls the exposure time for each pixel group 115 in a situation where the afternoon sun is shining outside a tunnel.

[0067] Areas 1 to 5 are five areas divided according to brightness. Areas 1 to 5 are numbered in order of brightness. Area 1 is the brightest area where the setting sun is directly visible. Area 2 is the area corresponding to the tunnel exit and is darker than Area 1. Area 3 is the area where the setting sun is reflected inside the tunnel and is darker than Area 2. Area 4 is the area inside the tunnel where the setting sun shines in from the exit and is darker than Area 3. Area 5 is the darkest area inside the tunnel where the setting sun does not shine in from the exit.

[0068] The image sensor 400 controls the exposure time for each pixel group 115 according to the brightness of each region. The image sensor 400 controls the exposure time so that the brighter the pixel group 115 in the region, the shorter the exposure time. The exposure time for region 1 is set to the shortest, and the exposure time for region 5 is set to the longest. For example, the exposure times for regions 1 to 5 are 1 / 19200 s, 1 / 1920 s, 1 / 960 s, 1 / 240 s, and 1 / 120 s.

[0069] 4B shows a timing chart illustrating the imaging operation of the image sensor 400. The image sensor 400 of this example controls the exposure time for each of the pixel groups 115 in regions 1 to 5. In this example, the period from time T11 to time T19 corresponds to the video frame rate.

[0070] In region 1, the control block 220 controls driving so that the exposure time of the pixel group 115 is a predetermined exposure time ET1. In this example, the control block 220 controls the start of exposure using the second transfer control signal φTX2 and the end of exposure using the first transfer control signal φTX1. In region 1, exposure ends at each of times T12 to T19.

[0071] In region 2, the control block 220 controls driving so that the exposure time in the pixel group 115 is exposure time ET2, which is longer than ET1. The control block 220 makes the exposure start time for region 2 earlier than region 1 and the exposure end time coincident with region 1. Therefore, in region 2, exposure ends at each of times T12 to T19. The exposure time ET2 for region 2 is shorter than the period of the sensor rate.

[0072] In region 3, the control block 220 controls driving so that the exposure time in the pixel group 115 is exposure time ET3, which is longer than ET2. The control block 220 makes the exposure start time for region 3 earlier than region 2 and the exposure end time coincide with region 2. Therefore, in region 3, exposure ends at each of times T12 to T19. The exposure time ET3 for region 3 is set to be the same as the period of the sensor rate.

[0073] In region 4, the control block 220 controls driving so that the exposure time in the pixel group 115 is exposure time ET4, which is longer than ET3. The control block 220 sets the exposure start time for region 4 to the same time as region 3, but skips the end time of the exposure using the transfer selection control signal φTXSEL. In this example, the control block 220 skips three times using the transfer selection control signal φTXSEL, thereby achieving an exposure time four times longer than that of region 3. In region 4, the transfer selection control signal φTXSEL is supplied at each of times T12 to T14.

[0074] In region 5, the control block 220 controls driving so that the exposure time of the pixel group 115 is an exposure time ET5 that is longer than ET4. The control block 220 sets the same exposure start time for region 5 as for region 4, but increases the number of times to skip the exposure end time using the transfer selection control signal φTXSEL. In this example, the control block 220 skips seven times using the transfer selection control signal φTXSEL, thereby achieving an exposure time that is twice that of region 4. The exposure time ET5 for region 5 is set to be the same as the period of the video frame rate. In region 5, the transfer selection control signal φTXSEL is supplied at each of times T12 to T18.

[0075] The image sensor 400 of this example achieves short-time exposure by shortening the interval between the first transfer control signal φTX1 and the second transfer control signal φTX2. The image sensor 400 also achieves long-time exposure by skipping control of the first transfer control signal φTX1 using the transfer selection control signal φTXSEL. This allows for an expanded dynamic range.

[0076] Fig. 5 is a diagram showing an overview of an image sensor 400. The image sensor 400 captures an image of a subject. The image sensor 400 generates image data of the captured subject. The image sensor 400 includes a first substrate 100 and a second substrate 200. As shown in Fig. 5, the first substrate 100 is stacked on the second substrate 200.

[0077] The first substrate 100 has a pixel section 110 and a connection region 150. Light is incident on the pixel section 110. The pixel section 110 outputs a pixel signal based on the incident light. The first substrate 100 is sometimes referred to as a pixel chip. The connection region 150 is arranged around the pixel section 110. In the example of FIG. 5, a pair of connection regions 150 are arranged along two opposing sides of the first substrate 100, in front and behind the pixel section 110.

[0078] The second substrate 200 has a control circuit section 210, a peripheral circuit section 230, and a signal processing section 250. The second substrate 200 may be referred to as a processing circuit chip.

[0079] The control circuit section 210 outputs a control signal to the pixel section 110 for controlling the driving of the pixel section 110. The control circuit section 210 of this example is disposed on the second substrate 200 at a position facing the pixel section 110.

[0080] The peripheral circuit unit 230 controls the driving of the control circuit unit 210. The peripheral circuit unit 230 is arranged around the control circuit unit 210 on the second substrate 200. The peripheral circuit unit 230 may also be electrically connected to the first substrate 100 and control the driving of the pixel unit 110. In this example, the peripheral circuit unit 230 is arranged along two opposing sides of the second substrate 200, but the arrangement of the peripheral circuit unit 230 is not limited to this example.

[0081] The pixel signals output from the first substrate 100 are input to the signal processing unit 250. The signal processing unit 250 performs signal processing on the pixel signals. For example, the signal processing unit 250 performs processing to convert analog signals into digital signals. Specifically, the signal processing unit 250 performs processing to convert the input pixel signals into digital signals. The signal processing unit 250 may perform other signal processing. Examples of other signal processing include noise removal processing such as analog or digital CDS (Correlated Double Sampling). The signal processing unit 250 is arranged on the periphery, i.e., outside, of the control circuit unit 210. In the example of FIG. 5, a pair of signal processing units 250 are arranged in front of and behind the control circuit unit 210 along two opposing sides of the second substrate 200.

[0082] In addition to the first substrate 100 and the second substrate 200, the imaging element 400 may have a third substrate stacked on the second substrate 200. A memory for storing image data may be arranged on the third substrate. Furthermore, the third substrate may perform image processing according to the signal output by the second substrate 200. The structure of the imaging element 400 may be a back-illuminated type or a front-illuminated type.

[0083] 6 shows an example of a specific configuration of the pixel section 110. In this example, an enlarged view of the pixel section 110 and a pixel block 120 provided in the pixel section 110 is shown.

[0084] The pixel section 110 has a plurality of pixel blocks 120 arranged side by side in the row and column directions. In this example, the pixel section 110 has M×N (M and N are natural numbers) pixel blocks 120. In this example, the case where M is equal to N is illustrated, but M and N may be different.

[0085] Each pixel block 120 has at least one pixel 112. In this example, the pixel block 120 has m×n pixels 112 (m and n are natural numbers). For example, the pixel block 120 has 16×16 pixels 112. The number of pixels 112 corresponding to the pixel block 120 is not limited to this. In this example, the case where m is equal to n is illustrated, but m may be different from n. The pixel block 120 has multiple pixels 112 connected to a common control line in the row direction. For example, each pixel 112 in the pixel block 120 is connected to a common control line so that the pixels 112 are set to the same exposure time. In one example, n pixels 112 arranged in the row direction are connected by a common control line.

[0086] On the other hand, different exposure times may be set for each of the multiple pixel blocks 120. That is, the pixels 112 of each pixel block 120 may have the same exposure time, but may be set to different exposure times for the other pixel blocks 120. For example, when the pixels 112 of a pixel block 120 are connected in the row direction by a common control line, the pixels 112 of the other pixel blocks 120 may be connected in common by a different control line.

[0087] The pixel blocks 120 are arranged corresponding to the control blocks 220 described later. In this embodiment, one pixel block 120 is arranged for one control block 220.

[0088] The pixels 112 have a photoelectric conversion function that converts light into electric charges. The pixels 112 accumulate the electric charges generated by the photoelectric conversion. m pixels 112 are arranged side by side in the column direction and connected to a common signal line 122. The m pixels 112 are arranged side by side in n columns in the row direction in the pixel block 120.

[0089] In other words, the pixel block 120 is a group of pixels 112 connected by a common control line. The pixel block 120 can also be said to be the smallest unit of a circuit for multiple pixels 112 for which the same exposure time is set.

[0090] 7 shows an example of a more specific configuration of the control circuit section 210. In this example, an enlarged view of the control circuit section 210 and a control block 220 provided in the control circuit section 210 is shown.

[0091] The control circuit section 210 has control blocks 220 arranged side by side in the row and column directions. The control circuit section 210 of this example has M×N control blocks 220.

[0092] The control blocks 220 are disposed at positions corresponding to the pixel blocks 120. For example, the control blocks 220 and the pixel blocks 120 are disposed at positions where they overlap when viewed from the stacking direction of the first substrate 100 and the second substrate 200. In this case, the areas of the control blocks 220 and the pixel blocks 120 may be substantially the same, including the margin between adjacent blocks.

[0093] The control block 220 controls the driving of the corresponding pixel block 120. For example, the control block 220 controls the exposure time of the corresponding pixel block 120. The control block 220 of this example includes an exposure control unit 10 and a pixel driving unit 20.

[0094] The exposure control unit 10 controls exposure of the multiple pixels 112. The exposure control unit 10 generates a signal for controlling the exposure time of the pixels 112. In one example, the exposure control unit 10 controls the exposure time for each pixel block 120 by adjusting at least one of the start timing and end timing of the exposure.

[0095] The pixel driving unit 20 is electrically connected to the plurality of pixels 112 and drives the plurality of pixels 112. The pixel driving unit 20 selects and drives an arbitrary pixel 112 from the plurality of pixels 112. The pixel driving unit 20 is disposed at a position corresponding to the m pixels 112 arranged in the column direction. The image sensor 400 can set the exposure time for each pixel block 120 according to the intensity of incident light, thereby expanding the dynamic range.

[0096] Instead of providing one control block 220 for one pixel block 120, one control block may be provided for N pixel blocks 120 (N is a natural number greater than or equal to 2). The N pixel blocks 120 corresponding to one pixel block are sometimes referred to as a pixel block group. For example, two pixel blocks 120 arranged side by side in the column direction may be treated as one pixel block group, and one control block 220 may be provided for each pixel block group. In this case, the control block 220 may control the exposure time for each pixel block 120.

[0097] In other words, the control block 220 is electrically connected to at least one pixel block 120 and can be said to be the smallest unit of a circuit that controls exposure of the pixels 112 in the at least one pixel block 120 .

[0098] 8 shows an example of the circuit configuration of the pixel 112. The pixel 112 includes a photoelectric conversion unit 104, a transfer unit 123, a discharge unit 124, a reset unit 126, and a pixel output unit 127. The pixel output unit 127 includes an amplifier unit 128 and a selection unit 129. In this example, the transfer unit 123, the discharge unit 124, the reset unit 126, the amplifier unit 128, and the selection unit 129 are described as N-channel FETs, but the type of transistor is not limited to this.

[0099] The photoelectric conversion unit 104 has a photoelectric conversion function of converting light into electric charges. The photoelectric conversion unit 104 accumulates the electric charges generated by photoelectric conversion. The photoelectric conversion unit 104 is, for example, a photodiode.

[0100] The transfer unit 123 transfers the charges accumulated in the photoelectric conversion unit 104 to the storage unit 125. The transfer unit 123 is an example of a transfer gate that transfers the charges of the photoelectric conversion unit 104. In other words, the transfer unit 123 serves as the gate, the photoelectric conversion unit 104 serves as the source, and the storage unit 125 serves as the drain, forming a so-called transfer transistor. The gate terminal of the transfer unit 123 is connected to a local transfer control line for each pixel block 120 for inputting a control signal φTX1.

[0101] The discharge unit 124 discharges the charges accumulated in the photoelectric conversion unit 104 to a power supply wiring to which a power supply voltage VDD is supplied. A gate terminal of the discharge unit 124 is connected to a local discharge control line for each pixel block 120 for inputting a discharge control signal φTX2. Note that, in this example, the discharge unit 124 has been described as discharging the charges of the photoelectric conversion unit 104 to a power supply wiring to which a power supply voltage VDD is supplied, but the discharge unit 124 may also be discharged to a power supply wiring to which a power supply voltage different from the power supply voltage VDD is supplied.

[0102] The charge from the photoelectric conversion unit 104 is transferred to the accumulation unit 125 by the transfer unit 123. The accumulation unit 125 is an example of a floating diffusion (FD).

[0103] The reset unit 126 discharges the charge in the storage unit 125 to a power supply line to which a predetermined power supply voltage VDD is supplied. A gate terminal of the reset unit 126 is connected to a global reset control line across multiple pixel blocks 120 for inputting a reset control signal φRST.

[0104] The pixel output unit 127 outputs a signal based on the potential of the storage unit 125 to the signal line 122. The pixel output unit 127 has an amplifier unit 128 and a selection unit 129. The amplifier unit 128 has a gate terminal connected to the storage unit 125, a drain terminal connected to a power supply line to which a power supply voltage VDD is supplied, and a source terminal connected to the drain terminal of the selection unit 129.

[0105] The selection unit 129 controls the electrical connection between the pixel 112 and the signal line 122. When the selection unit 129 electrically connects the pixel 112 and the signal line 122, a pixel signal is output from the pixel 112 to the signal line 122. A gate terminal of the selection unit 129 is connected to a global selection control line that spans multiple pixel blocks 120 and inputs a selection control signal φSEL. A source terminal of the selection unit 129 is connected to the load current source 121.

[0106] The load current source 121 supplies a current to the signal line 122. The load current source 121 may be provided on the first substrate 100 or on the second substrate 200.

[0107] Hereinafter, any one of the charges accumulated in the photoelectric conversion unit 104, the charges transferred to the accumulation unit 125, and the signal based on the potential of the accumulation unit 125, or all of these may be collectively referred to as a pixel signal.

[0108] In other words, the pixel 112 includes at least one photoelectric conversion unit 104, and a pixel output unit 127 as a readout unit that reads out an image signal from the at least one photoelectric conversion unit 104 to a signal line 122. The pixel 112 can also be said to be the smallest unit of a circuit that outputs pixel signals that constitute an image to the signal line 122.

[0109] 9, 10, and 11 are diagrams for explaining an example of a wiring method for the imaging element 400. Note that in Fig. 10 and Fig. 11, connection regions are omitted to simplify the drawings.

[0110] 9, the first substrate 100 has connection regions 132 and 150 provided around the pixel unit 610 and electrically connected to the pixel unit 610. The second substrate 200 has connection regions 232 and 255 provided around the control circuit unit 210 and electrically connected to the control circuit unit 210.

[0111] The pair of connection regions 132 are connected to a pair of connection regions 232 located opposite each other. The mutually connected connection regions 132, 232 input a control signal from a global driving unit 234 to the pixel unit 610 using a global control line.

[0112] The pair of connection regions 150 are connected to a pair of connection regions 254, 255 located opposite each other. The mutually connected connection regions 150, 254, 255 input pixel signals from the pixel unit 110 to the corresponding ADC units 252, 253 using a common signal line.

[0113] 10 , the global driver 234 outputs a reset control signal φRST, a selection control signal φSEL, and a transfer selection control signal φTXSEL. The global driver 234 is connected to a reset control line 143 and a selection control line 145 that output signals to each pixel block 120. The global driver 234 supplies the reset control signal φRST to the multiple pixel blocks 120 via the reset control line 143 and the selection control signal φSEL via the selection control line 145. The global driver 234 supplies the transfer selection control signal φTXSEL to the multiple control blocks 220 via the transfer selection control line 147.

[0114] The transfer selection control signal φTXSEL is supplied from the global driver 234 to the control block 220 to control the exposure time for each pixel block 120. The control block 220, to which the transfer selection control signal φTXSEL is supplied, outputs the transfer selection control signal φTXSEL to the corresponding pixel block 120. The pixel block 120 determines whether to input the transfer selection control signal φTXSEL to the pixel 112 as the transfer control signal φTX1 or the discharge control signal φTX2. As a result, input of the transfer control signal φTX1 or the discharge control signal φTX2 to the pixel 112 is skipped.

[0115] For example, when the transfer control signal φTX1 determines the end time of exposure, the control block 220 extends the exposure time by skipping the transfer control signal φTX1. When the transfer control signal φTX1 determines the start time of exposure, the control block 220 shortens the exposure time by skipping the transfer control signal φTX1. In this way, the exposure time of the pixel block 120 can be adjusted by the transfer selection control signal φTXSEL. The same applies when the discharge control signal φTX2 determines the start or end time of exposure.

[0116] The reset control line 143, the selection control line 145, and the transfer selection control line 147 are wired globally, i.e., are provided in common to multiple pixel blocks 120. In this example, the reset control line 143, the selection control line 145, and the transfer selection control line 147 are wired so as to cross the pixel unit 110 in the row direction. The reset control line 143, the selection control line 145, and the transfer selection control line 147 may also be wired so as to cross the pixel unit 110 in the column direction.

[0117] For example, the reset control line 143 is connected to the gate terminal of the reset unit 126 of the pixel block 120 and supplies a reset control signal φRST. The selection control line 145 is connected to the gate terminal of the selection unit 129 of the pixel block 120 and supplies a selection control signal φSEL. In addition, the transfer selection control line 147 is connected to each of the multiple control blocks 220 and supplies a transfer selection control signal φTXSEL to the exposure control unit 10.

[0118] In this example, the global driving unit 234 outputs the transfer selection control signal φTXSEL from the second substrate 200 to the first substrate 100, but the transfer selection control signal φTXSEL may be output to the control block 220 without being supplied to the first substrate 100. In this case, the transfer selection control line 147 is provided on the second substrate 200.

[0119] On the other hand, the transfer control line 141a and the discharge control line 142a are connected to the pixel block 120a. In this example, the transfer control line 141a is connected to the gate terminal of the discharge transfer unit 123 provided in the pixel block 120a. The transfer control line 141a supplies the transfer control signal φTX1 output from the control block 220a to the pixel block 120a. In this example, the discharge control line 142a is connected to the gate terminal of the discharge unit 124 provided in the pixel block 120a. The discharge control line 142a supplies the discharge control signal φTX2 output from the control block 220a to the pixel block 120a.

[0120] The transfer control line 141b and the discharge control line 142b are connected to the pixel block 120b. In this example, the transfer control line 141b is connected to the gate terminal of the discharge transfer unit 123 provided in the pixel block 120b. The transfer control line 141b supplies the transfer control signal φTX1 output from the control block 220b to the pixel block 120b. In this example, the discharge control line 142b is connected to the gate terminal of the discharge unit 124 provided in the pixel block 120b. The discharge control line 142b supplies the discharge control signal φTX2 output from the control block 220b to the pixel block 120b.

[0121] A plurality of bumps 152 are provided on the bonding surfaces where the first substrate 100 and the second substrate 200 are bonded to each other. The bumps 152 of the first substrate 100 are aligned with the bumps 152 of the second substrate 200. The opposing bumps 152 are bonded and electrically connected by applying pressure to the first substrate 100 and the second substrate 200, for example. In this case, the bumps 152 of the global control lines may be located under the corresponding pixel blocks 120 or in the connection regions 132, 232. On the other hand, the bumps 152 of the local control lines are located under the corresponding pixel blocks 120 (and also on the control blocks 220).

[0122] The image sensor 400 of this example controls the exposure time for each pixel block 120 by changing the timing of at least one of the transfer unit 123 and the discharge unit 124 using local control lines. By combining local control lines and global control lines, the image sensor 400 can control the exposure time with fewer control lines.

[0123] 11, a common signal line 122 extending in the column direction is arranged for each column within pixel block 120c. Furthermore, this signal line 122 is also common to multiple pixel blocks 120c and 120d arranged in the column direction. Therefore, in this example, one signal line 122 is connected to m×M pixels 112 arranged in a single column, and pixel signals from these pixels 112 are output.

[0124] An ADC (analog-digital converter) 256 is connected to each of the signal lines 122 on the side of the second substrate 200 via a bump 152. A plurality of ADCs 256 corresponding to the plurality of signal lines 122 constitute an ADC unit 252.

[0125] 11, the ADCs 256 corresponding to the pixel blocks 120c and 120d in the odd-numbered columns are provided in the ADC unit 252, and the ADCs 256 corresponding to the pixel blocks 120e and 120f in the even-numbered columns are provided in the ADC unit 253. However, the arrangement of the pixel blocks 120c etc. and the corresponding ADC units 252 etc. is not limited to this.

[0126] With the above configuration, each ADC 256 converts pixel signals output sequentially from the m×M pixels 112 in one connected column into digital signals and outputs the digital signals. In this case, the ADC units 252, 253 as a whole convert pixel signals from the pixels 112 arranged in n×N columns in the row direction into digital signals in parallel. From this perspective, this digital conversion can also be considered a type of so-called column ADC. Note that, although a single-slope ADC is an example of an ADC, other digital conversion methods may also be used. Furthermore, the connection positions of each pixel 112 and the signal line 122 are not limited to the form shown in FIG. 11 and may, for example, be within each pixel block 120c, etc.

[0127] 12 shows an example of a timing chart illustrating the imaging operation in the pixel block 120 of the image sensor 400. In this example, the driving of the pixel block 120 is controlled by a transfer control signal φTX1, a discharge control signal φTX2, a reset control signal φRST, and a selection control signal φSEL.

[0128] The discharge control signal φTX2 controls the timing to start exposure. The exposure start timing corresponds to the falling edge of the discharge control signal φTX2 (for example, time T1). That is, before the exposure start time T1, the discharge control signal φTX2 turns on the discharge unit 124 to discharge the charge accumulated in the photoelectric conversion unit 104, and exposure starts at the falling edge of the discharge control signal φTX2. In this example, the discharge control signal φTX2 is controlled locally, so the exposure time can be adjusted for each pixel block 120.

[0129] The transfer control signal φTX1 controls the timing to end exposure. At time T3, the transfer control signal φTX1 turns on the transfer unit 123, thereby transferring the charges accumulated in the photoelectric conversion unit 104 to the accumulation unit 125. The timing to end exposure corresponds to the falling edge of the transfer control signal φTX1 (for example, time T4).

[0130] The reset control signal φRST controls the timing of discharging the charge accumulated in the storage unit 125. At time T2, the reset control signal φRST turns on the reset unit 126, thereby discharging the charge in the storage unit 125. In this example, by discharging the charge in the storage unit 125 before the timing of the end of exposure, it is possible to suppress the influence of the charge remaining in the storage unit 125 when the charge is transferred from the photoelectric conversion unit 104.

[0131] The selection control signal φSEL is a signal for selecting an arbitrary pixel 112. The selection control signal φSEL controls the on / off of the selection unit 129. At time T2, the selection control signal φSEL is set to high. At time T3, the pixel 112 for which the selection control signal φSEL is set to high outputs a pixel signal to the signal line 122 in response to the transfer control signal φTX1 being turned on. On the other hand, the pixel 112 for which the selection control signal φSEL is not set to high does not output a pixel signal.

[0132] The image sensor 400 of this example locally controls the discharge control signal φTX2, thereby changing the exposure start timing for each pixel block 120 and controlling the exposure time for each pixel block 120. The image sensor 400 may also locally control the transfer control signal φTX1 to control the exposure end timing for each pixel block 120. The image sensor 400 may also locally control both the transfer control signal φTX1 and the discharge control signal φTX2 to control both the exposure start timing and end timing for each pixel block 120.

[0133] The pixel signal of each pixel 112 corresponds to the amount of charge accumulated in the photoelectric conversion unit 104. Therefore, controlling the timing of exposure of the pixel 112 can be said to be controlling the timing of charge accumulation in the photoelectric conversion unit 104. More specifically, controlling the timing of exposure of the pixel 112 can be said to be controlling the timing and length of the charge accumulation time from discharge to transfer of the charge.

[0134] 13 shows an example of exposure timing for each pixel block 120. In this example, the exposure time is controlled for each of three pixel blocks 120 arranged in a row. Here, the image sensor 400 changes the amount of exposure by shifting the pixel reset time for each pixel block 120.

[0135] Meanwhile, the timing of reading out pixel signals is in order starting from the top pixel block 120. That is, pixel signals are read out from the pixels 112 in "pixel block 1," then from the pixels 112 in "pixel block 2," and then from the pixels 112 in "pixel block 3."

[0136] Furthermore, within each pixel block 120, pixel signals are sequentially read out from the pixels 112 in the upper rows as described in Fig. 12. Therefore, when viewed from the entire pixel unit 110, pixel signals are read out sequentially from the upper row of the m x M pixels 112 in the same column that are connected to a common signal line 122. In other words, the global drive unit 234 sets the selection control signal φSEL to high for each row, from the first row to the m x Mth row, across the multiple pixel blocks 120 lined up in a single column.

[0137] 11, for multiple pixel blocks 120 arranged in one row, a common selection control line 145 is connected to the n×N pixels arranged in the same row. Therefore, pixel signals are read out in parallel from the n×N pixels 112 connected to the row for which the selection control signal φSEL is set high. This makes it possible to output pixel signals for one frame.

[0138] 11, these pixel signals are converted into digital signals by the ADC units 252, 252. The digitally converted pixel signals are output to the subsequent image processing stage, and form an image for one frame.

[0139] As described above, pixel signals are read out sequentially from the top row of the same column among multiple pixel blocks 120. From this viewpoint, the readout method of this embodiment can be said to be a so-called rolling shutter method for the entire pixel unit 110. However, it should be noted that even in this case, different exposure times can be set for each pixel block 120.

[0140] As described above, according to this embodiment, among a plurality of pixel blocks 120 arranged in a row, pixel signals are read from the pixels 112 of the upper pixel block 120, and then pixel signals are read from the pixels 112 of the pixel block 120 below that. Therefore, distortion of the image due to the read order when capturing an image of a moving subject is smoothed out, and the sense of incongruity felt by the viewer in the image can be reduced. More specifically, when a moving subject is captured in parallel from a plurality of pixel blocks 120 arranged in a row, a plurality of sawtooth-shaped steps corresponding to the positions between the pixel blocks 120 appear in the vertical direction of the image (i.e., corresponding to the pixel column direction), causing the viewer to feel uncomfortable. In contrast, according to this embodiment, the plurality of steps do not appear in the image.

[0141] Furthermore, in this embodiment, an ADC unit is not provided within the control block 220, and the signal processing unit 250 is arranged outside the control circuit unit 210. This allows the area of ​​the control block 220 to be reduced, and the size of the pixel blocks 120 arranged at positions corresponding to the control block 220 to be reduced, i.e., exposure control by the control block 220 can be performed in units of a small number of pixels. This allows for precise exposure time control within an image, making it possible to make the boundaries of the pixel blocks 120 less noticeable on the image. Furthermore, since digital conversion is not performed directly below the pixels 112, the impact of noise on the pixels 112 due to heat generation can be suppressed.

[0142] The signal processing unit 250 does not have to be provided in multiple separate areas, and may be provided in one area for the entire pixel unit 110.

[0143] 14 is a diagram showing an overview of an image sensor 800 according to another embodiment. In the image sensor 800, the same components as those in the image sensor 400 are given the same reference numerals and descriptions thereof will be omitted.

[0144] The imaging element 800 includes a first substrate 600 and a second substrate 700. As shown in FIG.

[0145] Similar to the image sensor 400, the first substrate 600 has a pixel section 610, and the second substrate 700 has a control circuit section 210 and a peripheral circuit section 230. However, the connection region 150 of the first substrate 100 is not provided around the pixel section 610 of the first substrate 600. Furthermore, the signal processing section 250 of the second substrate 200 is not provided around the control circuit section 710 of the second substrate 700.

[0146] The control circuit unit 710 receives pixel signals output from the first substrate 100. The control circuit unit 710 processes the input pixel signals. In this example, the control circuit unit 710 is disposed on the second substrate 200 at a position facing the pixel unit 610. The control circuit unit 710 further outputs control signals to the pixel unit 610 for controlling the driving of the pixel unit 610.

[0147] 15 shows an example of a specific configuration of the pixel unit 610. The pixel unit 610 has M×N pixel blocks 620, and each pixel block 620 has m×n pixels 112, and the configuration of the pixels 112 is similar to that of the pixel unit 110.

[0148] Similar to the pixel block 120, the pixels 112 arranged in a row within the pixel block 620 are connected to a common signal line 122. However, the signal line 122 is not shared between multiple pixel blocks 620, and the pixel blocks 620 are independent of each other.

[0149] 16 shows an example of a more specific configuration of the control circuit unit 710. Similar to the control circuit unit 210, the control circuit unit 710 has M×N control blocks 720, each of which is arranged at a position corresponding to a pixel block 620.

[0150] The control block 720 includes an exposure control unit 10 and a pixel driving unit 20 similar to those of the control block 220. The control block 720 further includes a junction unit 730, a signal processing unit 740, and a signal output unit 750.

[0151] The bonding unit 730 bonds the first substrate 600 and the second substrate 700 together. The bonding unit 730 inputs pixel signals input from the first substrate 600 to the signal processing unit 740. The bonding units 730 are provided corresponding to n pixels 112 arranged in the row direction, and input pixel signals to the signal processing unit 740 for each column.

[0152] The signal processing unit 740 converts analog signals output by the pixel unit 610 into digital signals. In this example, the signal processing unit 740 converts analog pixel signals into digital signals. The signal processing unit 740 sequentially converts analog signals from m pixels 112 arranged in the column direction into digital signals. The signal processing unit 740 has ADCs in a number corresponding to the number of columns of the corresponding pixel block 120, and uses these ADCs to convert analog signals in parallel from the pixels 112 arranged in n columns in the row direction.

[0153] The signal output unit 750 receives a digital signal from the signal processing unit 740. In one example, the signal output unit 750 temporarily stores the digital signal. The signal output unit 750 may have a latch circuit for storing the digital signal. The signal output unit 750 is provided between the signal processing unit 740 and the exposure control unit 10 in the column direction, and outputs the digital signal. The signal output unit 750 in this example outputs the digital signal to the outside of the control circuit unit 710.

[0154] The control block 720 of this example has therein a signal processing unit 740 and a signal output unit 750. That is, the circuit that converts pixel signals into digital signals is arranged inside the control circuit unit 710, and is not arranged outside.

[0155] The image sensor 800 of this example is capable of setting the exposure time for each pixel block 620 according to the intensity of incident light, and is therefore capable of expanding the dynamic range, similar to the image sensor 400. The image sensor 800 can also read out pixel signals in parallel for each pixel block 620 using a control block 720 provided for each pixel block 620. However, in this embodiment, the readout timing is controlled as described below.

[0156] 17 shows an example of exposure timing for each pixel block 620. In this example, the exposure time is controlled for each of three pixel blocks 620 arranged in a row. Here, the image sensor 800, like the image sensor 400, changes the amount of exposure by shifting the pixel reset time for each pixel block 620.

[0157] Meanwhile, the timing of pixel signal readout is in order starting from the top pixel block 620. That is, pixel signals are read out from the pixels 112 in "pixel block 1," then from the pixels 112 in "pixel block 2," and then from the pixels 112 in "pixel block 3."

[0158] Furthermore, within the pixel block 620, pixel signals are sequentially read out from the pixels 112 in the upper row, as in the image sensor 400. Therefore, when looking at the entire pixel unit 110, pixel signals are sequentially read out from the upper row of the m×M pixels 112 in the same column connected to the common signal line 122.

[0159] In the image sensor 800, a signal line 122 and a signal processing unit 740 are provided corresponding to each of the plurality of pixel blocks 620. More specifically, a signal line 122 and an ADC of the signal processing unit 740 are provided corresponding to each column of the plurality of pixel blocks 620. Therefore, pixel signals can be simultaneously read out from a plurality of pixel blocks 620 aligned in the column direction. However, in this embodiment, the global driving unit 234 sets the selection control signal φSEL to high row by row, spanning the plurality of pixel blocks 120 aligned in a single column from the first row to the m×Mth row.

[0160] As a result, as shown in Figure 17, of the multiple pixel blocks 120 arranged in a row as in Figure 13, pixel signals are read out from the pixels 112 of the upper pixel block 120, and then pixel signals are read out from the pixels 112 of the pixel block 120 below it.

[0161] As described above, from the viewpoint that pixel signals are ultimately read out sequentially from the top row of the same column among the multiple pixel blocks 620, similar to the image sensor 400, the readout method of this embodiment can also be said to be a so-called rolling shutter method for the entire pixel unit 610. However, even in this case, it is possible to set different exposure times for each pixel block 620, similar to the image sensor 400. As a result, similar to the image sensor 400, image distortion caused by the readout order when capturing an image of a moving subject is smoothed out in the image sensor 800, thereby reducing the sense of incongruity of the image perceived by the viewer.

[0162] 18 shows another example of pixel 114 of image sensors 400 and 800. In pixel 114, the same components as those in pixel 112 are denoted by the same reference numerals, and descriptions thereof will be omitted. Pixel 114 does not have the discharge section 124 that was provided in pixel 112. Pixel 114 is sometimes called a four-transistor type.

[0163] 19 shows an example of a timing chart illustrating an imaging operation in a pixel block 120 using pixels 114. In this example, the drive of the image sensor 400 is controlled by a transfer control signal φTX1, a reset control signal φRST, and a selection control signal φSEL. The image sensor 400 of this example differs from the case of FIG. 12 in that the timing of the start of exposure is controlled by a transfer control signal φTX1. In this example, the differences from FIG. 12 will be particularly described.

[0164] The transfer control signal φTX1 controls the timing of the start and end of exposure. In frame (n), exposure starts at time T5 and ends at time T7.

[0165] At exposure start time T5, the transfer control signal φTX1 falls, thereby starting exposure. That is, before exposure start time T5, the transfer control signal φTX1 turns on the transfer unit 123 while the reset control signal φRST is on, thereby discharging the charge accumulated in the photoelectric conversion unit 104, and exposure starts at the falling edge of the transfer control signal φTX1. In this example, the transfer control signal φTX1 is a locally controlled signal, so the timing at which exposure starts in each pixel block 120 can also be changed.

[0166] Furthermore, at exposure end time T7, the transfer control signal φTX1 falls, thereby ending the exposure. That is, before exposure end time T7, the transfer control signal φTX1 turns on the transfer unit 123 while the reset control signal φRST is off, thereby transferring the charge accumulated in the photoelectric conversion unit 104 to the accumulation unit 125, and exposure ends at the falling edge of the transfer control signal φTX1. In this example, the transfer control signal φTX1 is a locally controlled signal, so the timing at which exposure ends can also be changed for each pixel block 120.

[0167] The selection control signal φSEL is a signal for selecting an arbitrary pixel 114. At time T6, the pixel 114 for which the selection control signal φSEL is set high outputs a pixel signal to the signal line 122.

[0168] The reset control signal φRST controls the timing of discharging the charge accumulated in the storage section 125. The reset control signal φRST may be a globally controlled signal. Since the reset control signal φRST is always on except at the timing of readout, no charge is accumulated in the storage section 125. On the other hand, by turning off the reset control signal φRST and turning on the transfer control signal φTX1 at the timing of readout, charge is transferred from the photoelectric conversion section 104 to the storage section 125. In this example, the reset control signal φRST has the same switching timing during readout, so it can be made common to the pulse of the selection control signal φSEL.

[0169] Fig. 20 shows an example of exposure timing for each pixel block 120 using the pixels 114. As explained in Fig. 19, the pixels 114 undergo a reset operation during the operation period of reading out pixel signals. Therefore, Fig. 20 and its explanation will explain the readout timing, and will omit an explanation of the reset timing.

[0170] 20, the timing of reading out pixel signals is in the order from the top pixel block 120, as in Fig. 13. That is, pixel signals are read out from the pixels 114 in "pixel block 1," then from the pixels 114 in "pixel block 2," and then from the pixels 114 in "pixel block 3."

[0171] Furthermore, pixel signals are sequentially read out from the pixels 114 in the upper row within the pixel block 120. Therefore, when looking at the entire pixel unit 110, pixel signals are sequentially read out from the upper row of the m×M pixels 114 in the same column connected to the common signal line 122.

[0172] As described above, the pixel signals are ultimately read out in order from the top row of the same column among the multiple pixel blocks 120, just as when pixel 112 is used. From this viewpoint, the readout method of this embodiment can also be said to be a so-called rolling shutter method for the entire pixel unit 110.

[0173] 20, furthermore, in a particular frame, a particular pixel block 120 is not read out (this can also be referred to as skipping, skipping, or thinning out). This allows the exposure time to be changed for each pixel block 120.

[0174] For example, in the example of Figure 20, in "frame k," "pixel block 1" and "pixel block 3" are read out, but "pixel block 2" is not read out. In the next "frame k+1," "pixel block 1," "pixel block 2," and "pixel block 3" are all read out. Therefore, in "frame k+1," the exposure time of "pixel block 2" is longer than the exposure time of "pixel block 1" and "pixel block 3." Here, if the temporal frame rate of readout is constant, skipping readout n times for a specific pixel block 120 can increase the exposure time by (n+1) times.

[0175] The configuration of not reading out a specific pixel block 120 in a specific frame can also be applied to image sensors 400 and 800 that use pixels 112. In this case, if the exposure start timing based on the discharge control signal φTX2 is set immediately after the readout timing, the same operation as in FIG. 20 is possible. On the other hand, by controlling the exposure start timing based on the discharge control signal φTX2 independently of the readout timing, it is possible to perform a readout operation that combines the readout shown in FIG. 13 and the readout shown in FIG. 20. That is, while controlling the exposure start timing for each pixel block 120 as in FIG. 13, it is possible to select whether or not to read out a specific frame for each pixel block 120 as in FIG. 20. This allows the exposure time to be set more dynamically and precisely for each pixel block 120, and reduces the sense of incongruity felt by the viewer when capturing an image of a moving subject.

[0176] In any of the above embodiments, the storage unit 125 and pixel output unit 127 may be shared with other pixels. Also, the pixel 112 may be configured with a plurality of photoelectric conversion units 104 and transfer units 123.

[0177] 21 is a block diagram showing an example of the configuration of an imaging device 500 according to an embodiment. The imaging device 500 includes an imaging element 400, a system control unit 501, a drive unit 502, a photometry unit 503, a work memory 504, a recording unit 505, a display unit 506, a drive unit 514, and a photographing lens 520. While an example including the imaging element 400 will be described, an imaging element 800 may be included instead.

[0178] The photographing lens 520 guides the subject light beam incident along the optical axis OA to the image sensor 400. The photographing lens 520 is composed of a group of multiple optical lenses, and focuses the subject light beam from the scene near its focal plane. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the image capturing device 500. Note that in FIG. 21, the photographing lens 520 is represented by a single virtual lens placed near the pupil.

[0179] The driver 514 drives the photographing lens 520. In one example, the driver 514 changes the focus position by moving the optical lens group of the photographing lens 520. The driver 514 may also drive an iris diaphragm in the photographing lens 520 to control the amount of subject light entering the image sensor 400.

[0180] The drive unit 502 has a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 400 in accordance with instructions from the system control unit 501. Furthermore, the operation unit 508 receives instructions from the photographer using a release button or the like.

[0181] The image sensor 400 passes pixel signals to an image processing unit 511 in the system control unit 501. The image processing unit 511 generates image data by performing various image processes using the work memory 504 as a workspace. For example, when generating image data in JPEG file format, a color video signal is generated from a signal obtained using the Bayer array, and then compression processing is performed. The generated image data is recorded in a recording unit 505 and converted into a display signal, which is then displayed on a display unit 506 for a preset time.

[0182] The photometry unit 503 detects the luminance distribution of a scene prior to a series of shooting sequences for generating image data. The photometry unit 503 includes, for example, an AE sensor with approximately one million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance of each region of the scene.

[0183] The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution. The image sensor 400 may also serve as the photometry unit 503. The calculation unit 512 also executes various calculations for operating the imaging device 500. Part or all of the drive unit 502 may be mounted on the image sensor 400. Part of the system control unit 501 may be mounted on the image sensor 400.

[0184] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0185] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the process must be performed in this order. The invention described in this specification can also be implemented in the following forms. [Item 1] A plurality of pixels; a first control line connected to a first pixel among the plurality of pixels and outputting a control signal for controlling the first pixel; a second control line connected to a second pixel among the plurality of pixels and outputting a control signal for controlling the second pixel; a third control line connected to the first pixel and the second pixel, through which a control signal for controlling the first pixel and the second pixel is output; An imaging element comprising: [Item 2] Each of the plurality of pixels is a photoelectric conversion unit that converts light into electricity to generate electric charges; a transfer unit that transfers charges from the photoelectric conversion unit; a storage unit that stores the charges transferred by the transfer unit; a reset unit that discharges the charge of the storage unit; a pixel output unit that converts the charge of the storage unit into a pixel signal and outputs the pixel signal; having Item 1. The imaging element according to item 1. [Item 3] the first control line is connected to the transfer unit of the first pixel; the second control line is connected to the transfer unit of the second pixel, the third control line is connected to the reset unit of the first pixel and the second pixel; Item 2. The imaging element according to item 2. [Item 4] the pixel output unit includes a selection unit that selects whether to output the pixel signal; the third control line is connected to the selection unit of the first pixel and the second pixel; Item 2. The imaging device according to item 2 or 3. [Item 5] a plurality of pixel blocks each including one or more of the plurality of pixels; the first control line is connected to a first pixel block among the plurality of pixel blocks; the second control line is connected to a second pixel block among the plurality of pixel blocks; Item 5. The imaging device according to any one of items 2 to 4. [Item 6] a pixel chip having the plurality of pixels; a signal processing chip stacked on the pixel chip and processing pixel signals from the plurality of pixels; Equipped with the signal processing chip has a plurality of control blocks provided corresponding to the plurality of pixel blocks, respectively, for controlling exposure for each of the one or more pixels; Item 5. The imaging device according to item 5. [Item 7] The signal processing chip comprises: a main circuit unit having the plurality of control blocks; a peripheral circuit section provided around the main circuit section in the signal processing chip; Equipped with the peripheral circuit unit has a global driver connected to the third control line; Item 7. The imaging device according to item 6. [Item 8] the global driver supplies a selection control signal for selecting the transfer unit to the plurality of control blocks via the third control line. Item 7. The imaging device according to item 7. [Item 9] The transfer unit a first transfer unit that transfers the charges of the photoelectric conversion unit to the accumulation unit; a second transfer unit that transfers and discharges the charges of the photoelectric conversion unit; Including, the plurality of control blocks control an exposure time for each of the one or more pixels by changing a timing of at least one of the first transfer unit and the second transfer unit. Item 9. The imaging device according to any one of items 6 to 8. [Item 10] 10. An imaging device comprising the imaging element according to any one of items 1 to 9. [Item 11] a first control block that controls exposure of a first pixel included in the first pixel block; a second control block that controls exposure of second pixels included in the second pixel block; a conversion unit that converts a first signal output from the first pixel and a second signal output from the second pixel into a digital signal; Equipped with the first pixel block and the second pixel block are aligned in a column direction, The conversion unit is an image sensor that reads out the second signal after reading out the first signal. [Item 12] the first pixel block has a plurality of the first pixels arranged in row and column directions, Item 12. The imaging element according to item 11, wherein each of the plurality of conversion units is connected to the first pixels arranged in a column direction in the first pixel block. [Item 13] the second pixel block has a plurality of the second pixels arranged in row and column directions, Item 13. The imaging element according to item 12, wherein each of the other plurality of conversion units is connected to the second pixels arranged in the column direction in the second pixel block. [Item 14] the second pixel block has a plurality of the second pixels arranged in row and column directions, Item 13. The imaging element according to item 12, wherein each of the plurality of conversion units is connected to the first pixels arranged in a column direction in the first pixel block and the second pixels arranged in a column direction in the second pixel block. [Item 15] a first substrate on which the first pixel block and the second pixel block are provided; a second substrate on which the first control block, the second control block, and the conversion unit are provided; are stacked, the first control block is disposed in an area corresponding to the first pixel block, and the second control block is disposed in an area corresponding to the second pixel block; 15. The imaging device according to any one of items 11 to 14, wherein the conversion unit is arranged in an area corresponding to the outside of an area corresponding to the first pixel block and the second pixel block. [Item 16] An imaging device having the imaging element according to any one of items 11 to 15. [Explanation of symbols]

[0186] 10 exposure control unit, 20 pixel driving unit, 30 junction unit, 40 signal processing unit, 50 signal output unit, 100, 600 first substrate, 104 photoelectric conversion unit, 110, 610 pixel unit, 112, 114 pixel, 115 pixel group, 120, 620 pixel block, 121 load current source, 122 signal line, 123 transfer unit, 124 Discharge section, 125, storage section, 126, reset section, 127, pixel output section, 128, amplifier section, 129, selection section, 132, connection area, 141, transfer control line, 142, discharge control line, 143, reset control line, 145, selection control line, 147, transfer selection control line, 150, connection area, 152, bump, 161, local control line , 162... Local control line, 163... Global control line, 200, 700... Second board, 210, 710... Control circuit section, 220, 720... Control block, 230... Peripheral circuit section, 232... Connection area, 234... Global driving section, 250, 740... Signal processing section, 252, 253... ADC section, 254, 255... Connection area, 256... AD C, 400, 800... imaging element, 500... imaging device, 501... system control unit, 502... driving unit, 503... photometry unit, 504... work memory, 505... recording unit, 506... display unit, 508... operation unit, 511... image processing unit, 512... calculation unit, 514... driving unit, 520... photographing lens, 730... joint unit, 750... signal output unit

Claims

[Claim 1] a first pixel block including a first photoelectric conversion unit that converts light into electric charges, a first transfer unit that transfers the electric charges converted by the first photoelectric conversion unit, a first accumulation unit to which the electric charges converted by the first photoelectric conversion unit are transferred by the first transfer unit, a first amplification unit electrically connected to the first accumulation unit, and a first selection unit electrically connected to the first amplification unit; a second pixel block including: a second photoelectric conversion unit that converts light into electric charges and that is arranged alongside the first photoelectric conversion unit in the row direction; a second transfer unit that transfers the electric charges converted by the second photoelectric conversion unit; a second accumulation unit to which the electric charges converted by the second photoelectric conversion unit are transferred by the second transfer unit; a second amplification unit electrically connected to the second accumulation unit; and a second selection unit electrically connected to the second amplification unit; a first substrate having A substrate to be laminated together with the first substrate, a control circuit unit including a first control block that outputs a first transfer control signal for controlling the first transfer unit, and a second control block that outputs a second transfer control signal for controlling the second transfer unit; a driver that outputs a selection control signal for controlling the first selector and the second selector; a second substrate having Equipped with the first transfer unit is electrically connected to a first transfer control line to which the first transfer control signal is output; the second transfer unit is electrically connected to a second transfer control line to which the second transfer control signal is output; the first selection unit and the second selection unit are electrically connected to a selection control line to which the selection control signal is output; Image sensor.

Images