Wafer and semiconductor device

Abstract

To provide a wafer and a semiconductor device that can stabilize characteristics.SOLUTION: According to an embodiment, a wafer includes a substrate including silicon carbide. The substrate includes a first surface and a second surface. The substrate includes a first region between the second surface and the first surface in a first direction from the second surface to the first surface, a second region between the second surface and the first region in the first direction, and a third region between the first region and the first surface in the first direction. The substrate includes nitrogen. The first region includes a first element including at least one selected from the group consisting of phosphorus and arsenic. A first concentration of the first element in the first region is higher than a second concentration of the first element in the second region and higher than a third concentration of the first element in the third region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The present invention relates to a wafer and a semiconductor device. [Background technology]

[0002] For example, there is a semiconductor device including silicon carbide, and stable characteristics are desired in the semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-146748 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present invention provide a wafer and a semiconductor device that can stabilize characteristics. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a wafer includes a substrate including silicon carbide. The substrate includes a first surface and a second surface. The substrate includes a first region between the second surface and the first surface in a first direction from the second surface to the first surface, a second region between the second surface and the first region in the first direction, and a third region between the first region and the first surface in the first direction. The substrate includes nitrogen. The first region includes a first element including at least one selected from the group consisting of phosphorus and arsenic. A first concentration of the first element in the first region is higher than a second concentration of the first element in the second region and higher than a third concentration of the first element in the third region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. [Figure 2] FIG. 2 is a graph illustrating the wafer according to the first embodiment. [Figure 3] 3(a) to 3(d) are schematic plan views illustrating the characteristics of the wafer. [Figure 4] FIG. 4 is a schematic cross-sectional view illustrating the wafer according to the first embodiment. [Figure 5] FIG. 5 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0008] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. As shown in FIG. 1 , a wafer 110 according to the embodiment includes a substrate 18. The substrate 18 includes silicon carbide (SiC). The substrate 18 is, for example, a silicon carbide bulk substrate. The substrate 18 is, for example, a silicon carbide bulk single crystal substrate. In one example, the silicon carbide included in the substrate 18 is 4H—SiC. The substrate 18 may include 3C—SiC. The conductivity type of the substrate 18 is arbitrary.

[0009] The substrate 18 includes a first surface F1 and a second surface F2. The first surface F1 may be, for example, the upper surface. The second surface F2 may be, for example, the lower surface. A first direction D1 from the second surface F2 to the first surface F1 is defined as the Z-axis direction. A direction perpendicular to the Z-axis direction is defined as the X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction. The first surface F1 and the second surface F2 are, for example, aligned along the XY plane. The substrate 18 is aligned along the XY plane.

[0010] The substrate 18 includes a first region 18a, a second region 18b, and a third region 18c. The first region 18a is located between the second face F2 and the first face F1 in the first direction D1. The second region 18b is located between the second face F2 and the first region 18a in the first direction D1. The third region 18c is located between the first region 18a and the first face F1 in the first direction D1.

[0011] In the embodiment, the substrate 18 may further include a fourth region 18d. The fourth region 18d includes the first surface F1. The third region 18c is located between the first region 18a and the fourth region 18d in the first direction D1.

[0012] In the embodiment, the substrate 18 includes a first condition or a second condition. In the first condition, the substrate 18 includes nitrogen. In the first condition, the substrate 18 is n-type. In the first condition, the first region 18a includes a first element including at least one selected from the group consisting of phosphorus and arsenic.

[0013] Under the first condition, the concentration of the first element (first concentration) in the first region 18a is higher than the concentration of the first element (second concentration) in the second region 18b and higher than the concentration of the first element (third concentration) in the third region 18c. The first region 18a is a region where the concentration of the first element is maximum in the first direction D1.

[0014] In the second condition, the substrate 18 includes aluminum. In the second condition, the substrate 18 is p-type. In the second condition, the first region 18a includes a second element including at least one selected from the group consisting of gallium and indium.

[0015] Under the second condition, the concentration of the second element (first concentration) in the first region 18a is higher than the concentration of the second element (second concentration) in the second region 18b and higher than the concentration of the second element (third concentration) in the third region 18c. The first region 18a is a region where the concentration of the second element is maximum in the first direction D1.

[0016] By providing such first region 18a, for example, it is possible to suppress the expansion of stacking faults, thereby providing a wafer with stable characteristics.

[0017] FIG. 2 is a graph illustrating the wafer according to the first embodiment. 2, the horizontal axis represents the position pZ in the Z-axis direction. The vertical axis represents the concentration C1 of the first element or the second element. Below, a case will be described in which the substrate 18 satisfies the first condition and the first region 18a contains the first element.

[0018] 2, a first concentration of a first element (at least one selected from the group consisting of phosphorus and arsenic) in the first region 18a is higher than a second concentration of the first element in the second region 18b, which is higher than a third concentration of the first element in the third region 18c.

[0019] For example, the substrate 18 includes a first position p1, a second position p2, and a third position p3. The first position p1 is included in the first region 18a. The second position p2 is between the second surface F2 and the first position p1 in the first direction D1. The third position p3 is between the first position p1 and the first surface F1 in the first direction D1.

[0020] In the first direction D1, the concentration of the first element in the substrate 18 is a first peak value v1 at a first position p1. The concentration v2 of the first element at a second position p2 is 1 / 10 of the first peak value v1. The concentration v3 of the first element at a third position p3 is 1 / 10 of the first peak value v1. In this example, the distance w1 along the first direction D1 between the second position p2 and the third position p3 is 0.2 μm or more and 0.4 μm or less. In one example, the first peak value v1 (the peak value of the concentration of the first element) is 1×10 16 cm -3 More than 1×10 18 cm -3 When the substrate 18 satisfies the first condition, the nitrogen concentration in the substrate 18 is 5×10 18 cm -3 More than 1×10 19 cm -3 The following is fine.

[0021] In this way, by providing the first region 18a where the concentration of the first element is locally high, it is believed that, for example, the first element terminates dangling bonds of Si. This suppresses the migration of defects. In the case where the substrate 18 contains nitrogen, a first element with an atomic weight larger than that of nitrogen is locally introduced. It is believed that the first element with a large atomic weight effectively suppresses the migration of defects.

[0022] The concentration of the first element in the first region 18a (first concentration) may be 50 times or more the concentration of the first element in the third region 18c (third concentration).

[0023] In FIG. 2, the substrate 18 may satisfy the second condition, and the first region 18a may contain a second element (at least one selected from the group consisting of gallium and indium). In this case, the vertical axis of FIG. 2 represents the concentration C1 of the second element. In this case, in the first direction D1, the concentration of the second element in the substrate 18 has a first peak value v1 at a first position p1. The concentration v2 of the second element at a second position p2 is 1 / 10 of the first peak value v1. The concentration v3 of the second element at a third position p3 is 1 / 10 of the first peak value v1. In this example, the distance w1 along the first direction D1 between the second position p2 and the third position p3 is 0.2 μm or more and 0.4 μm or less. In one example, the first peak value v1 (peak value of the concentration of the second element) is 1×10 16 cm -3 More than 1×10 18 cm -3 When the substrate 18 satisfies the second condition, the aluminum concentration in the substrate 18 is 1×10 18 cm -3 5x10 or more 18 cm -3 The following is fine.

[0024] In this way, by providing the first region 18a where the concentration of the second element is locally high, it is believed that, for example, the second element terminates dangling bonds of Si. This suppresses the migration of defects. In the case where the substrate 18 contains aluminum, a second element with an atomic weight larger than that of aluminum is locally introduced. It is believed that the second element with a larger atomic weight effectively suppresses the migration of defects.

[0025] The concentration of the second element in the first region 18a (first concentration) may be 50 times or more the concentration of the second element in the third region 18c (third concentration).

[0026] For example, a first element or a second element is implanted near the surface of the substrate 18. A high-temperature treatment causes the first element or the second element to migrate from interstitial sites to lattice sites. The high-temperature treatment may be a heat treatment performed when epitaxially growing a silicon carbide layer on the substrate 18. The first element or the second element that has migrated from interstitial sites to lattice sites terminates dangling bonds of Si. For example, the movement (migration) of partial dislocations in Si is inhibited. This, for example, suppresses replication of stacking faults during epitaxial growth. For example, single Shockley stacking faults (1SSFs) are effectively suppressed. For example, double Shockley stacking faults (2SSFs) are effectively suppressed. For example, intrinsic Frank stacking faults (IFSFs) are effectively suppressed.

[0027] In the embodiment, for example, when the first region 18a contains the first element, the first region 18a may contain bonds between the first element and silicon. In this case, the first region 18a contains at least one of bonds between phosphorus and silicon and bonds between arsenic and silicon. These bonds, for example, suppress the propagation of defects.

[0028] For example, when the first region 18a contains the second element, the first region 18a contains a bond between the second element and silicon. In this case, the first region 18a contains at least one of a bond between gallium and silicon and a bond between indium and silicon. These bonds, for example, suppress the propagation of defects.

[0029] 1, the first distance dz1 between the first region 18a and the first surface F1 may be shorter than the second distance dz2 between the second surface F2 and the first region 18a. For example, the first element or the second element can be efficiently implanted from the first surface F1. The first region 18a, in which the concentration of the first element or the second element is locally high, can be stably obtained.

[0030] 1 and 2, the substrate 18 may further include a fourth region 18d. The fourth region 18d includes the first surface F1. The third region 18c is located between the first region 18a and the fourth region 18d in the first direction D1.

[0031] When the substrate 18 satisfies the first condition, the concentration of the first element in the fourth region 18d (fourth concentration) may be higher than the concentration of the first element in the third region 18c (third concentration).

[0032] When the substrate 18 satisfies the second condition, the concentration of the second element in the fourth region 18d (fourth concentration) may be higher than the concentration of the second element in the third region 18c (third concentration).

[0033] For example, when the first element or the second element is implanted into the first region 18a by ion implantation or the like, the first element or the second element may segregate to the surface (first face F1). For example, excess first element or second element present between lattices may diffuse toward the surface and segregate. This may result in the formation of a fourth region 18d having a high concentration of the first element or the second element. For example, the first element or the second element segregated to the surface of the substrate 18 may act as a surface step smoothing (surfactant) during epitaxial growth. This suppresses the occurrence of basal plane dislocations at the start of epitaxial growth.

[0034] The maximum value of the concentration of the first element (fourth concentration) in the fourth region 18d may be higher than the concentration of the first element (first concentration) in the first region 18a. The fourth concentration may be equal to or lower than the first concentration.

[0035] The maximum value of the concentration (fourth concentration) of the second element in the fourth region 18d may be higher than the concentration (first concentration) of the second element in the first region 18a. The fourth concentration may be equal to or lower than the first concentration.

[0036] The first element or the second element may contribute to the termination of dangling bonds of Si and may not substantially affect the conductivity.

[0037] As shown in FIG. 1 , the wafer 110 may further include a silicon carbide member 10M. The silicon carbide member 10M is, for example, epitaxially grown on a substrate 18. The silicon carbide member 10M may include a first silicon carbide region 10 containing a third element. The third element includes at least one element selected from the group consisting of nitrogen, phosphorus, and arsenic. The first surface F1 is located between the second surface F2 and the first silicon carbide region 10. The concentration of the third element in the first silicon carbide region 10 is, for example, 1×10 14 cm -3 More than 1×10 16 cm -3 When the substrate 18 satisfies the first condition, the concentration of nitrogen in the substrate 18 may be higher than the concentration of the third element in the first silicon carbide region 10.

[0038] The silicon carbide member 10M may further include a second silicon carbide region 20 containing a fourth element. The first silicon carbide region 10 is located between the substrate 18 and the second silicon carbide region 20 in the first direction D1. The fourth element includes at least one selected from the group consisting of boron, aluminum, and gallium. The concentration of the fourth element in the second silicon carbide region 20 is, for example, 5×10 17 cm -3 More than 1×10 20 cm -3 The following is fine.

[0039] For example, substrate 18 includes basal plane dislocations (BPDs). Basal plane dislocations in substrate 18 cause basal plane dislocations in first silicon carbide region 10. During operation of the semiconductor device, stacking faults propagate from the basal plane dislocations in first silicon carbide region 10. The stacking faults are, for example, single Shockley stacking faults.

[0040] For example, when holes are injected into an n-type silicon carbide semiconductor device, stacking faults originating from BPDs expand, which can easily degrade forward characteristics. Furthermore, when partial dislocations in stacking faults reach the p-type semiconductor region, leakage current increases in reverse characteristics, which can lead to breakdown voltage failure.

[0041] In the embodiment, the first region 18a is provided in the substrate 18, thereby suppressing the expansion of stacking faults originating from BPDs. This suppresses the deterioration of characteristics caused by the expansion of stacking faults. According to the embodiment, a semiconductor device with stable characteristics can be provided.

[0042] 3(a) to 3(d) are schematic plan views illustrating the characteristics of the wafer. 3(a) and 3(b) correspond to a wafer 110 according to the embodiment. 3(c) and 3(d) correspond to a wafer 119 according to a reference example. In the wafer 119, the substrate 18 does not have a first region 18a containing the first element or the second element. These figures schematically illustrate photoluminescence images. By irradiating the wafer with ultraviolet light, it is possible to determine whether BPDs expand into stacking faults. 3(a) and 3(c) correspond to the state before ultraviolet light irradiation. 3(b) and 3(d) correspond to the state after ultraviolet light irradiation.

[0043] As shown in FIGS. 3(c) and 3(d), in the wafer 119 of the reference example, stacking faults SF starting from BPDs are expanded by irradiation with ultraviolet light.

[0044] In contrast, as shown in Figures 3(a) and 3(b), in the wafer 110 according to the embodiment, although the stacking faults SF expand when irradiated with ultraviolet light, the stacking faults SF do not expand beyond the first region 18a. In the embodiment, the stacking faults SF are prevented from reaching the silicon carbide member 10M. The leakage current path is suppressed. As a result, stable characteristics can be obtained.

[0045] In the embodiment, in the second region 18b below the first region 18a, stacking faults SF expand due to at least one of voltage application and UV irradiation, whereas in the third region 18c above the first region 18a, stacking faults SF do not substantially expand due to at least one of voltage application and UV irradiation.

[0046] 1, the first region 18a may extend along a first plane (XY plane) intersecting the first direction D1. For example, the first region 18a may be provided in the form of one continuous layer.

[0047] FIG. 4 is a schematic cross-sectional view illustrating the wafer according to the first embodiment. 4, in the wafer 111 according to the embodiment, the substrate 18 includes a plurality of first regions 18a. Except for this, the configuration of the wafer 111 may be the same as the configuration of the wafer 110.

[0048] In the wafer 111, the multiple first regions 18a are provided along a plane (e.g., an XY plane) that intersects with the first direction D1. The multiple first regions 18a may be, for example, island-shaped or stripe-shaped.

[0049] The angle between the (0001) plane of the substrate 18 and the first face F1 is defined as angle θ. The thickness of one of the multiple first regions 18a along the first direction D1 is defined as thickness d. The distance between the multiple first regions 18a along the intersecting direction that intersects with the first direction D1 is defined as distance w. The angle θ, thickness d, and distance w may satisfy the relationship w<(d / tan θ).

[0050] This prevents the BPDs in the second regions 18b from passing between the first regions 18a and extending upward. For example, the BPDs in the second regions 18b collide with one of the first regions 18a. The BPDs colliding with one of the first regions 18a prevents the expansion of stacking faults originating from the BPDs.

[0051] The angle θ may be, for example, between 1° and 10° The angle θ corresponds to the offset angle.

[0052] (Second embodiment) FIG. 5 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. 5, the semiconductor device 120 according to the embodiment includes the substrate 18 of the wafer (in this example, the wafer 110) according to the first embodiment. The semiconductor device 120 may also include the substrate 18 of the wafer 111.

[0053] For example, the semiconductor device 120 includes a wafer 110, a third silicon carbide region 30, a first electrode 51, a second electrode 52, a third electrode 53, and an insulating member 61. The wafer 110 includes a substrate 18 and a silicon carbide member 10M (the first silicon carbide region 10 and the second silicon carbide region 20).

[0054] The first silicon carbide region 10 contains at least one selected from the group consisting of nitrogen, phosphorus, and arsenic. The second silicon carbide region 20 contains at least one selected from the group consisting of boron, aluminum, and gallium. The third silicon carbide region 30 contains at least one selected from the group consisting of nitrogen, phosphorus, and arsenic.

[0055] The direction from the first electrode 51 to the second electrode 52 is along the first direction D1. The first silicon carbide region 10 includes a first partial region 10a and a second partial region 10b. The second silicon carbide region 20 includes a third partial region 20c and a fourth partial region 20d. The third partial region 20c is located between the first partial region 10a and the third silicon carbide region 30 in the first direction D1. The direction from the second partial region 10b to the third electrode 53 is along the first direction D1. The fourth partial region 20d is located between the second partial region 10b and the third silicon carbide region 30 in a second direction D2 that intersects with the first direction D1.

[0056] The first electrode 51 is electrically connected to the substrate 18. The second electrode 52 is electrically connected to the third silicon carbide region 30. The insulating member 61 is located between the second partial region 10b and the third electrode 53.

[0057] In this example, the second silicon carbide region 20 further includes a fifth partial region 20e. The third silicon carbide region 30 is located between the fourth partial region 20d and the fifth partial region 20e in the second direction D2. The second electrode 52 is electrically connected to the fifth partial region 20e.

[0058] For example, the current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential based on the potential of the second electrode 52. The third electrode 53 functions as a gate electrode. The semiconductor device 120 is, for example, a transistor.

[0059] In the semiconductor device 120, the substrate 18 may be n-type. In this case, the semiconductor device 120 is a MOS type FET. For example, the first silicon carbide region 10 corresponds to, for example, a drift layer. The second silicon carbide region 20 corresponds to, for example, a p-well. The third silicon carbide region 30 corresponds to, for example, an n-type + Corresponds to the source.

[0060] In the embodiment, the substrate 18 may be p-type, in which case the semiconductor device 120 is an IGBT (Insulated Gate Bipolar Transistor).

[0061] The wafer 110 (or wafer 111) according to the embodiment may be applied to a diode or the like.

[0062] The embodiments may include the following technical solutions. (Technical proposal 1) a substrate including silicon carbide; the substrate includes a first side and a second side; The substrate is a first region between the second surface and the first surface in a first direction from the second surface to the first surface; a second region between the second surface and the first region in the first direction; a third region between the first region and the first surface in the first direction; Including, the substrate comprises nitrogen; the first region includes a first element including at least one selected from the group consisting of phosphorus and arsenic; A wafer, wherein a first concentration of the first element in the first region is higher than a second concentration of the first element in the second region and higher than a third concentration of the first element in the third region.

[0063] (Technical proposal 2) the substrate includes a first position, a second position, and a third position; the first location is included in the first region, the second position is between the second surface and the first position in the first direction, the third position is between the first position and the first surface in the first direction, In the first direction, the concentration of the first element in the substrate has a first peak value at the first position; the concentration of the first element at the second position is 1 / 10 of the first peak value; the concentration of the first element at the third position is 1 / 10 of the first peak value; A wafer according to Technical Solution 1, wherein the distance along the first direction between the second position and the third position is 0.2 μm or more and 0.4 μm or less.

[0064] (Technical proposal 3) The first peak value of the first element in the substrate in the first direction is 1×10 16 cm -3 More than 1×10 18 cm -3 A wafer according to Technical Proposal 1, which is as follows:

[0065] (Technical proposal 4) 4. The wafer according to any one of Technical Schemes 1 to 3, wherein the first region includes a bond between silicon and the first element.

[0066] (Technical proposal 5) the substrate further includes a fourth region that includes the first surface; the third region is located between the first region and the fourth region in the first direction, 5. The wafer according to any one of Technical Schemes 1 to 4, wherein a fourth concentration of the first element in the fourth region is higher than the third concentration.

[0067] (Technical proposal 6) 6. The wafer according to any one of Technical Schemes 1 to 5, wherein the first concentration is 50 times or more the third concentration.

[0068] (Technical proposal 7) a substrate including silicon carbide; the substrate includes a first side and a second side; The substrate is a first region between the second surface and the first surface in a first direction from the second surface to the first surface; a second region between the second surface and the first region in the first direction; a third region between the first region and the first surface in the first direction; Including, the substrate comprises aluminum; the first region includes a second element including at least one selected from the group consisting of gallium and indium; a first concentration of the second element in the first region is higher than a second concentration of the second element in the second region and higher than a third concentration of the second element in the third region;

[0069] (Technical proposal 8) the substrate includes a first position, a second position, and a third position; the first location is included in the first region, the second position is between the second surface and the first position in the first direction, the third position is between the first position and the first surface in the first direction, In the first direction, the concentration of the second element in the substrate has a first peak value at the first position; the concentration of the second element at the second position is 1 / 10 of the first peak value; the concentration of the second element at the third position is 1 / 10 of the first peak value; A wafer according to Technical Solution 7, wherein the distance along the first direction between the second position and the third position is 0.2 μm or more and 0.4 μm or less.

[0070] (Technical proposal 9) The first peak value of the second element in the substrate in the first direction is 1×10 16 cm -3 More than 1×10 18 cm -3 A wafer according to Technical Proposal 7 below.

[0071] (Technical proposal 10) 10. The wafer according to any one of Technical Schemes 7 to 9, wherein the first region includes a bond between silicon and the second element.

[0072] (Technical proposal 11) the substrate further includes a fourth region that includes the first surface; the third region is located between the first region and the fourth region in the first direction, 11. The wafer according to any one of Technical Schemes 7 to 10, wherein a fourth concentration of the second element in the fourth region is higher than the third concentration.

[0073] (Technical proposal 12) 12. The wafer according to any one of Technical Schemes 7 to 11, wherein the first concentration is 50 times or more the third concentration.

[0074] (Technical proposal 13) In the second region, stacking faults are expanded by at least one of voltage application and ultraviolet irradiation, 13. The wafer according to any one of Technical Schemes 1 to 12, wherein in the third region, the stacking faults are not substantially expanded by at least one of the voltage application and the ultraviolet irradiation.

[0075] (Technical proposal 14) 14. The wafer according to any one of Technical Schemes 1 to 13, wherein the first region extends along a first plane that intersects with the first direction.

[0076] (Technical proposal 15) the substrate includes a plurality of the first regions; the plurality of first regions are provided along a plane intersecting the first direction, The angle θ between the (0001) plane of the substrate and the first plane, the thickness d of one of the plurality of first regions along the first direction, and the distance w between the plurality of first regions along an intersecting direction intersecting the first direction are expressed as follows: A wafer according to any one of Technical Schemes 1 to 14, which satisfies the relationship of w<(d / tan θ).

[0077] (Technical proposal 16) Further comprising a silicon carbide member; the silicon carbide member includes a first silicon carbide region containing a third element; the third element includes at least one selected from the group consisting of nitrogen, phosphorus, and arsenic, 16. The wafer according to any one of Technical Schemes 1 to 15, wherein the first surface is located between the second surface and the first silicon carbide region.

[0078] (Technical proposal 17) the silicon carbide member further includes a second silicon carbide region including a fourth element; the first silicon carbide region is between the substrate and the second silicon carbide region in the first direction; The wafer according to Technical Solution 16, wherein the fourth element includes at least one selected from the group consisting of boron, aluminum, and gallium.

[0079] (Technical proposal 18) A semiconductor device including the substrate of the wafer according to any one of Technical Schemes 1 to 17.

[0080] (Technical proposal 19) A wafer according to Technical Proposal 17; a third silicon carbide region; and A first electrode; A second electrode; A third electrode; an insulating member; Equipped with the third silicon carbide region contains at least one selected from the group consisting of nitrogen, phosphorus, and arsenic; a direction from the first electrode to the second electrode is along the first direction; the first silicon carbide region includes a first partial region and a second partial region; the second silicon carbide region includes a third partial region and a fourth partial region, the third partial region is located between the first partial region and the third silicon carbide region in the first direction; a direction from the second partial region to the third electrode is along the first direction; the fourth partial region is located between the second partial region and the third silicon carbide region in a second direction intersecting the first direction, the first electrode is electrically connected to the substrate; the second electrode is electrically connected to the third silicon carbide region; The insulating member is located between the second partial region and the third electrode.

[0081] (Technical proposal 20) the second silicon carbide region further includes a fifth partial region; the third silicon carbide region is located between the fourth partial region and the fifth partial region in the second direction; The semiconductor device described in Technical Proposal 19, wherein the second electrode is electrically connected to the fifth partial region.

[0082] According to the embodiment, it is possible to provide a wafer and a semiconductor device that can stabilize characteristics.

[0083] In this specification, "vertical" and "parallel" do not only mean strictly vertical and strictly parallel, but also include variations in the manufacturing process, and may mean substantially vertical and substantially parallel.

[0084] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of each element included in the wafer and semiconductor device, such as the substrate, silicon carbide member, silicon carbide region, electrode, and insulating member, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0085] Furthermore, any combination of two or more elements of each specific example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0086] In addition, all wafers and semiconductor devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the wafers and semiconductor devices described above as embodiments of the present invention also fall within the scope of the present invention, as long as they include the gist of the present invention.

[0087] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and it will be understood that these modifications and alterations also fall within the scope of the present invention.

[0088] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0089] 10, 20, 30: first, second, and third silicon carbide regions; 10M: silicon carbide member; 10a, 10b: first and second partial regions; 18: substrate; 18a-18d: first to fourth regions; 20c-20e: third to fifth partial regions; 51-53: first to third electrodes; 61: insulating member; 110, 111, 119: wafer; 120: semiconductor device; C1: concentration; D1, D2: first and second directions; F1, F2: first and second surfaces; SF: stacking fault; d: thickness; dz1, dz2: first and second distances; p1-p3: first to third positions; pZ: position; v1: first peak value; v2, v3: concentration; w, w1: distance; θ: angle

Claims

1. a substrate including silicon carbide; the substrate includes a first surface and a second surface; The substrate is a first region between the second surface and the first surface in a first direction from the second surface to the first surface; a second region between the second surface and the first region in the first direction; a third region between the first region and the first surface in the first direction; Including, the substrate comprises nitrogen; the first region includes a first element including at least one selected from the group consisting of phosphorus and arsenic; a first concentration of the first element in the first region is higher than a second concentration of the first element in the second region and higher than a third concentration of the first element in the third region;

2. the substrate includes a first position, a second position, and a third position; the first location is included in the first region; the second position is between the second surface and the first position in the first direction, the third position is between the first position and the first surface in the first direction; In the first direction, the concentration of the first element in the substrate has a first peak value at the first position; the concentration of the first element at the second position is 1 / 10 of the first peak value; the concentration of the first element at the third position is 1 / 10 of the first peak value; 2. The wafer according to claim 1, wherein the distance between the second position and the third position along the first direction is not less than 0.2 μm and not more than 0.4 μm.

3. The wafer according to claim 1 , wherein the first region includes bonds between silicon and the first element.

4. the substrate further includes a fourth region that includes the first surface; the third region is located between the first region and the fourth region in the first direction, 4. The wafer according to claim 1, wherein a fourth concentration of the first element in the fourth region is higher than the third concentration.

5. a substrate including silicon carbide; the substrate includes a first surface and a second surface; The substrate is a first region between the second surface and the first surface in a first direction from the second surface to the first surface; a second region between the second surface and the first region in the first direction; a third region between the first region and the first surface in the first direction; Including, the substrate comprises aluminum; the first region includes a second element including at least one selected from the group consisting of gallium and indium; a first concentration of the second element in the first region is higher than a second concentration of the second element in the second region and higher than a third concentration of the second element in the third region;

6. the substrate includes a first position, a second position, and a third position; the first location is included in the first region; the second position is between the second surface and the first position in the first direction, the third position is between the first position and the first surface in the first direction; In the first direction, the concentration of the second element in the substrate has a first peak value at the first position; the concentration of the second element at the second position is 1 / 10 of the first peak value; the concentration of the second element at the third position is 1 / 10 of the first peak value; 6. The wafer according to claim 5, wherein the distance between the second position and the third position along the first direction is not less than 0.2 μm and not more than 0.4 μm.

7. The wafer according to claim 5 , wherein the first region includes bonds between silicon and the second element.

8. the substrate further includes a fourth region that includes the first surface; the third region is located between the first region and the fourth region in the first direction, 8. The wafer according to claim 5, wherein a fourth concentration of the second element in the fourth region is higher than the third concentration.

9. In the second region, stacking faults are expanded by at least one of voltage application and ultraviolet irradiation, 2. The wafer according to claim 1, wherein in the third region, the stacking faults are not substantially expanded by at least one of the voltage application and the ultraviolet irradiation.

10. A semiconductor device comprising the substrate of the wafer of claim 1.

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