Detection circuit, signal transfer device, electronic apparatus, and vehicle

Abstract

To detect short circuit of a load without delay.SOLUTION: A detection circuit DET includes: a first comparator CMP1 for generating a first comparison signal S1 by comparing a node voltage Vx according to a drain-source voltage Vds (or a collector-emitter voltage Vce) of a power transistor M0 and a first reference voltage Vref1; a second comparator CMP2 for generating a second comparison signal S2 by comparing a gate voltage Vg of the power transistor M0 and a second reference voltage Vref2; and a logic circuit AND for outputting a detection signal S3 by receiving input of the first comparison signal S1 and the second comparison signal S2.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] The present disclosure relates to a detection circuit, a signal transmission device, an electronic device, and a vehicle. [Background technology]

[0002] Conventionally, signal transmission devices that transmit signals between a primary circuit system and a secondary circuit system while electrically insulating the primary circuit system from the secondary circuit system have been used in various applications (such as power supply devices or motor drive devices).

[0003] An example of the prior art related to the above is Patent Document 1 by the applicant of the present application. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2022 / 070944

[0005] [overview] A detection circuit for detecting a short circuit in a load can be mounted on, for example, the signal transmission device. However, there is room for improvement in the detection speed of the conventional detection device.

[0006] For example, a detection circuit according to the present disclosure includes a first comparator configured to compare a node voltage corresponding to a drain-source voltage or a collector-emitter voltage of a power transistor with a first reference voltage to generate a first comparison signal, a second comparator configured to compare a gate voltage of the power transistor with a second reference voltage to generate a second comparison signal, and a logic circuit configured to receive the first comparison signal and the second comparison signal and output a detection signal. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. [Figure 2] FIG. 2 is a diagram showing the basic structure of a transformer chip. [Figure 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8] FIG. 8 is an enlarged view (isolation structure) of region XIII shown in FIG. [Figure 9] FIG. 9 is a diagram schematically illustrating an example of the layout of a transformer chip. [Figure 10] FIG. 10 is a diagram showing a first embodiment (comparative example) of a detection circuit. [Figure 11] FIG. 11 is a diagram illustrating the load short-circuit detection operation in the first embodiment. [Figure 12] FIG. 12 is a diagram showing a second embodiment of the detection circuit. [Figure 13] FIG. 13 is a diagram illustrating the load short-circuit detection operation in the second embodiment. [Figure 14] FIG. 14 is a diagram showing a third embodiment of the detection circuit. [Figure 15] FIG. 15 is a diagram showing a fourth embodiment of the detection circuit. [Figure 16] FIG. 16 is a diagram showing the relationship between the slew rate of the gate-source voltage and the voltages at various parts in the second embodiment. [Figure 17] FIG. 17 is a diagram illustrating erroneous detection of a load short circuit in the second embodiment. [Figure 18] FIG. 18 is a diagram showing a first setting example of the blanking time. [Figure 19]FIG. 19 is a diagram showing a fifth embodiment of the detection circuit. [Figure 20] FIG. 20 is a diagram illustrating the load short-circuit detection operation in the fifth embodiment. [Figure 21] FIG. 21 is a diagram showing a second setting example of the blanking time. [Figure 22] FIG. 22 is a diagram showing a sixth embodiment of the detection circuit. [Figure 23] FIG. 23 is a diagram illustrating the load short-circuit detection operation in the sixth embodiment. [Figure 24] FIG. 24 is a diagram showing a third setting example of the blanking time. [Figure 25] FIG. 25 is a diagram showing a seventh embodiment of the detection circuit. [Figure 26] FIG. 26 is a diagram illustrating the load short-circuit detection operation in the seventh embodiment. [Figure 27] FIG. 27 is a diagram showing an eighth embodiment of the detection circuit. [Figure 28] FIG. 28 is a diagram illustrating the load short-circuit detection operation in the eighth embodiment. [Figure 29] FIG. 29 is a diagram showing the exterior of the vehicle.

[0008] [Detailed explanation] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0009] The controller chip 210 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC1 (for example, up to 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0010] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signals S11 or S21 in response to the logic level of the input pulse signal IN.

[0011] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0012] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0013] The driver chip 220 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC2 (for example, up to 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0014] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0015] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0016] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0017] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0018] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0019] More specifically, the transformer 231 outputs a reception pulse signal S12 from the secondary coil 231s in response to a transmission pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s in response to a transmission pulse signal S21 input to the primary coil 232p.

[0020] In this way, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0021] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0022] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0023] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs) / plug-in hybrid vehicles (PHVs), or xEVs such as fuel cell electric vehicles (FCEVs) / FCVs (fuel cell electric vehicles)).

[0024] <Trans chip (basic structure)> Next, the basic structure of transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of transformer chip 230. In transformer chip 230 shown in this figure, transformer 231 includes primary coil 231p and secondary coil 231s that face each other in the vertical direction. Transformer 232 includes primary coil 232p and secondary coil 232s that face each other in the vertical direction.

[0025] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0026] The primary coil 231p is laid spirally, starting from a first end connected to the internal terminal X21, so as to surround the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. Meanwhile, the primary coil 232p is laid spirally, starting from a first end connected to the internal terminal X23, so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0027] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged linearly and are used for wire bonding with the controller chip 210.

[0028] The secondary coil 231s is laid in a spiral shape, starting from a first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with a second end corresponding to the end point connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape, starting from a first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with a second end corresponding to the end point connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0029] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0030] <Transformer chip (2-channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0031] 3 to 7, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. Semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0032] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0033] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0034] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0035] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0036] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0037] The insulating side walls 53A to 53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A to 44D. Specifically, the insulating side walls 53A to 53D are formed flush with the chip side walls 44A to 44D. The insulating side walls 53A to 53D form ground surfaces that are flush with the chip side walls 44A to 44D.

[0038] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0039] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0040] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0041] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0042] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inside the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0043] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0044] 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0045] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0046] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0047] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0048] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0049] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the shapes shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0050] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0051] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a planar view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a planar view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0052] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0053] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0054] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0055] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0056] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0057] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0058] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0059] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0060] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.

[0061] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0062] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0063] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0064] The multiple high potential terminals 12 are each formed in an area close to the corresponding transformer 21A to 21D in a plan view. The high potential terminals 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0065] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0066] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0067] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0068] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0069] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0070] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0071] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0072] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0073] The plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The plurality of first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first low potential wirings 31, and will not be repeated here.

[0074] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0075] The through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0076] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0077] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0079] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0080] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0081] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0082] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0083] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0084] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0085] 6 and 7, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. In the following, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0086] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (multiple in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0087] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulation layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (the first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connection wiring 81 is formed at an interval from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z. Thereby, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the withstand voltage of the insulation layer 51 is enhanced.

[0088] The plurality of pad plug electrodes 82 are formed in the region between the high-potential terminal 12 (the first high-potential terminal 12A) and the high-potential connection wiring 81 within the uppermost insulation layer 56 and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively. The plurality of pad plug electrodes 82 each have a planar area less than the planar area of the high-potential connection wiring 81 in a plan view.

[0089] Referring to FIG. 7, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). It is preferable that the distance D1 exceeds the total thickness DT of the plurality of interlayer insulation layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. It is preferable that the distance D1 is 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. It is preferable that the distance D2 is 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the withstand voltage to be achieved.

[0090] Referring to FIGS. 6 and 7, the semiconductor device 5 includes dummy patterns 85 embedded in the insulation layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0091] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. In other words, the dummy pattern 85 does not function as a part of the transformers 21A to 21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses electric field concentration on the high-potential coil 23. In this embodiment, the dummy pattern 85 is routed at a line density per unit area equal to that of the high-potential coil 23. The line density of the dummy pattern 85 being equal to that of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within a range of ±20% of the line density of the high-potential coil 23.

[0092] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0093] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The shorter the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0094] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0095] Dummy patterns 85 include floating dummy patterns formed in an electrically floating state within insulating layer 51 so as to be positioned around transformers 21A to 21D.

[0096] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0097] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0098] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0099] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0100] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0101] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The second functional device 60 may include circuitry in which any two or more of the passive devices, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuitry may form part or all of an integrated circuit.

[0102] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0103] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0104] The device region 62 is a region including the first functional device 45 (plurality of transformers 21), the second functional device 60, plural low potential terminals 11, plural high potential terminals 12, first low potential wiring 31, second low potential wiring 32, first high potential wiring 33, second high potential wiring 34, and dummy patterns 85. The outer region 63 is a region outside the device region 62.

[0105] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0106] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in plan view.

[0107] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0108] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0109] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, a plurality) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0110] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0111] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) shape.

[0112] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0113] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined as the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0114] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0115] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0116] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a strip shape along the seal conductor 61 in plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 bites in toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0117] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0118] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0119] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0120] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0121] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high-potential coil 23 can be increased.

[0122] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0123] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0124] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the low potential terminals 11. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the high potential terminals 12.

[0125] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0126] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0127] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0128] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0129] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0130] The embodiments of the present disclosure can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0131] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0132] In the above embodiment, an example was described in which the second functional device 60 was formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0133] In the above embodiment, an example was described in which the dummy pattern 85 was formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0134] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes multiple transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0135] <Transformer arrangement> 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0136] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s that forms a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s that forms a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0137] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0138] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0139] That is, pads a5 and b5 are connected to one end of the primary coil forming first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0140] Pads a7 and b7 are connected to one end of the primary coil forming third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0141] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0142] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0143] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break occurs in each coil, but also to appropriately reject defective products in which an abnormal resistance value occurs in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0144] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0145] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0146] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0147] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner that couples them in the respective signal transmission directions, as shown in Fig. 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302 that transmit signals from the primary-side chip to the secondary-side chip are connected as a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 that transmit signals from the secondary-side chip to the primary-side chip are connected as a second pair by a second guard ring 306.

[0148] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0149] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0150] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0151] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. This configuration increases the area where the primary coil and secondary coil overlap, thereby improving the transmission efficiency of the transformer.

[0152] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0153] <Detection Circuit (First Embodiment)> 10 is a diagram showing a first embodiment of the detection circuit DET (corresponding to a comparative example to be compared with the second embodiment described later). The detection circuit DET is provided, for example, in the signal transmission device 200 described above (particularly the driver chip 220). The signal transmission device 200 may be, for example, a semiconductor integrated circuit device, a so-called insulated gate driver IC, mounted in an electronic device A together with a power transistor M0 and a load ZL externally attached to the signal transmission device 200. An example of the electronic device A is an in-vehicle traction inverter.

[0154] 1, the signal transmission device 200 transmits an input pulse signal IN of the primary circuit system 200p as an output pulse signal OUT of the secondary circuit system 200s while insulating the primary circuit system 200p from the secondary circuit system 200s. The output pulse signal OUT corresponds to a drive signal for the power transistor M0. As shown in this figure, a gate resistor Rg may be externally connected between the output pulse signal OUT and the gate of the power transistor M0.

[0155] The power transistor M0 to be driven by the signal transmission device 200 may be, for example, an N-channel MOS field effect transistor. Referring to this figure, the drain of the power transistor M0 is connected to a first terminal of a load ZL. A second terminal of the load ZL is connected to an application terminal of a first power system power supply voltage PVDD. The first power system power supply voltage PVDD may be, for example, 400 to 1200 V. The source of the power transistor M0 is connected to an application terminal of a second power system power supply voltage PVEE. The second power system power supply voltage PVEE may be, for example, 0 V. The second power system power supply voltage PVEE may be a negative voltage (<0 V).

[0156] A gate voltage Vg (and hence the output pulse signal OUT) is applied to the gate of the power transistor M0. The power transistor M0 is in the ON state when the gate-source voltage Vgs (=Vg-PVEE) is higher than the ON threshold voltage Vth(M0). On the other hand, the power transistor M0 is in the OFF state when the gate-source voltage Vgs is lower than the ON threshold voltage Vth(M0).

[0157] The detection circuit DET detects whether or not the two ends of the load ZL are short-circuited, in other words, whether or not the drain of the power transistor M0 is directly connected to the application terminal of the first power system power supply voltage PVDD without going through the load ZL. From another perspective, the detection circuit DET detects whether or not an abnormal state exists in which an excessive short-circuit current may flow through the power transistor M0 due to a short circuit in the load ZL.

[0158] Referring to the figure, the detection circuit DET includes a comparator CMP1, a current source CS, a resistor R1, a diode D1, a transistor M1, and a capacitor C1. The transistor M1 may be, for example, an N-channel transistor. At least some of these components may be built into the signal transmission device 200.

[0159] The comparator CMP1 generates a comparison signal S1 by comparing a node voltage Vx input to a non-inverting input terminal (+) with a reference voltage Vref1 input to an inverting input terminal (-). The comparison signal S1 goes high when the node voltage Vx is higher than the reference voltage Vref1. On the other hand, the comparison signal S1 goes low when the node voltage Vx is lower than the reference voltage Vref1. The reference voltage Vref1 may be, for example, 9 V. The comparator CMP1 may be built into the signal transmission device 200.

[0160] The current source CS is connected between the application terminal of the power supply voltage VCCx and the application terminal of the node voltage Vx, and supplies a bias current I1 toward the application terminal of the node voltage Vx. The current source CS may be built into the signal transmission device 200 or may be externally attached to the signal transmission device 200. The power supply voltage VCCx may be a power supply voltage VCC2 of, for example, 15 to 18 V, or may be a voltage higher than the node voltage Vx.

[0161] A first end of the resistor R1 is connected to the application end of the node voltage Vx. A second end of the resistor R1 is connected to the anode of the diode D1. A cathode of the diode D1 is connected to the drain of the power transistor M0. In this manner, the resistor R1 and the diode D1 may be connected in series between the application end of the node voltage Vx and the drain of the power transistor M0.

[0162] In this case, the node voltage Vx obtained when the load ZL is not short-circuited can rise to a voltage value (=Vd+V1+Vf) obtained by adding the drain voltage Vd of the power transistor M0 to the voltage V1 (=I1×R1) across the resistor R1 and the forward drop voltage Vf of the diode D1. Therefore, by adjusting the resistance value of the resistor R1, it is possible to adjust the threshold at which the node voltage Vx, and therefore the logic level of the comparison signal S1, switches. The resistor R1 also limits the forward current of the diode D1 that occurs when the drain-source voltage Vds swings negative. However, the resistor R1 may be omitted. The resistor R1 and the diode D1 may be external to the signal transmission device 200.

[0163] The drain of the transistor M1 is connected to the node to which the node voltage Vx is applied. The source of the transistor M1 is connected to the source of the power transistor M0, and therefore to the node to which the second power system power supply voltage PVEE is applied. The gate of the transistor M1 is connected to the node to which the gate signal G1 is applied. The transistor M1 is turned on when the gate signal G1 is at a high level. At this time, the voltage across the capacitor C1, i.e., the node voltage Vx, is discharged. On the other hand, the transistor M1 is turned off when the gate signal G1 is at a low level. At this time, the node voltage Vx is charged by the bias current I1. The transistor M1 may be built into the signal transmission device 200.

[0164] The gate signal G1 may fall from high to low as the output pulse signal OUT transitions to high. That is, the transistor M1 may be turned on / off in a complementary manner to the power transistor M0. In other words, the transistor M1 may be switched from an on state to an off state as the power transistor M0 turns on.

[0165] A first terminal of the capacitor C1 is connected to the node voltage Vx application terminal. A second terminal of the capacitor C1 is connected to the source of the power transistor M0, and further to the node voltage PVEE application terminal. The capacitor C1 is provided to set a blanking time Tbr, which will be described later. The capacitor C1 may be external to the signal transmission device 200.

[0166] The detection circuit DET of this embodiment employs the DESAT method of monitoring desaturation between the drain and source of the power transistor M0 as a method for detecting a short-circuit state of the load ZL. More specifically, the detection circuit DET detects whether the node voltage Vx corresponding to the drain-source voltage Vds (=Vd-PVEE) of the power transistor M0 is higher than the reference voltage Vref1 when the power transistor M0 is in the on state.

[0167] 11 is a diagram showing the load short-circuit detection operation in the first embodiment. From top to bottom, the diagram depicts the output pulse signal OUT, gate-source voltage Vgs, drain-source voltage Vds, gate signal G1, node voltage Vx, and comparison signal S1. The solid line indicates the behavior when the load ZL is not short-circuited. Meanwhile, the dashed line indicates the behavior when the load ZL is short-circuited.

[0168] At time t10, when the output pulse signal OUT rises from low level to high level, the gate-source voltage Vgs starts to rise.

[0169] If the load ZL is not short-circuited, the Miller effect causes the gate-source voltage Vgs to be maintained at the plateau voltage Vp while the drain-source voltage Vds decreases from high to low between times t11 and t12. This operating region is known as the plateau region. The plateau voltage Vp may be, for example, 10 V. Then, at time t12, the gate-source voltage Vgs begins to rise again, and the drain-source voltage Vds reaches a low level (≒0 V).

[0170] After the output pulse signal OUT rises from low to high, the gate signal G1 falls from high to low, for example, at time t11. As a result, the transistor M1 is turned off, and the node voltage Vx begins to rise with a time constant τ that corresponds to the capacitance value of the capacitor C1.

[0171] However, if the load ZL is not short-circuited, the drain-source voltage Vds drops to low level before the node voltage Vx exceeds the reference voltage Vref1 (at time t12 in this diagram). Therefore, the node voltage Vx drops to low level and remains below the reference voltage Vref1. As a result, the comparison signal S1 remains low. The low level of the comparison signal S1 can be understood as the logic level when no abnormality is detected.

[0172] On the other hand, if the load ZL is short-circuited, after time t10, the gate-source voltage Vgs rises almost steadily to a high level (≒ VCC2). Furthermore, the drain-source voltage Vds remains at a high level (≒ VCC2) without dropping. Therefore, the node voltage Vx continues to rise with the time constant τ mentioned above, exceeding the reference voltage Vref1 at time t13. As a result, the comparison signal S1 rises to a high level. The high level of the comparison signal S1 can be understood as the logic level when an abnormality (load short-circuit) is detected.

[0173] The signal transmission device 200 may have a function of forcibly turning off the power transistor M0 when the comparison signal S1 goes high, that is, a so-called load short-circuit protection function.

[0174] In the DESAT detection circuit DET, a blanking time Tbr (=t11 to t13) is set so as not to erroneously detect the node voltage Vx while the drain-source voltage Vds is decreasing from time t11 to t12, i.e., in the plateau region.

[0175] The blanking time Tbr can be set to any length by adjusting the capacitance value of the capacitor C1 and, in turn, the rising slope (time constant τ) of the node voltage Vx. Specifically, the blanking time Tbr needs to be set to a sufficient length (approximately 1 μs) that does not cause erroneous detection of the node voltage Vx, taking into account manufacturing variations in the power transistor M0, fluctuations in the load condition, and fluctuations in the junction temperature of the power transistor M0.

[0176] On the other hand, as the performance of the power transistor M0 has improved in recent years, the short-circuit resistance of the power transistor M0 has tended to decrease. Therefore, if the blanking time Tbr is long, there is a risk that the load short-circuit protection operation in response to the comparison signal S1 will not be completed in time.

[0177] In view of the above considerations, a second embodiment will be proposed below that does not require the blanking time Tbr and can detect a short circuit in the load ZL without delay.

[0178] <Detection Circuit (Second Embodiment)> 12 is a diagram showing a second embodiment of the detection circuit DET. The detection circuit DET of this embodiment is based on the first embodiment (FIG. 10) and further includes a comparator CMP2 and a logical product gate AND. Also, the capacitor C1 of the first embodiment is removed.

[0179] The comparator CMP2 generates a comparison signal S2 by comparing the gate voltage Vg of the power transistor M0, which is input to the non-inverting input terminal (+), with a reference voltage Vref2, which is input to the inverting input terminal (-). The comparison signal S2 goes high when the gate voltage Vg is higher than the reference voltage Vref2. On the other hand, the comparison signal S2 goes low when the gate voltage Vg is lower than the reference voltage Vref2. The reference voltage Vref2 may be, for example, 13 V. In other words, the reference voltage Vref2 may be set to a voltage value lower than the high level (≈VCC2) of the gate voltage Vg and higher than the plateau voltage Vp of the power transistor M0. The comparator CMP2 may be built into the signal transmission device 200.

[0180] The AND gate AND receives the comparison signals S1 and S2, performs a logical AND operation, and outputs a detection signal S3. The detection signal S3 goes low when at least one of the comparison signals S1 and S2 is low. On the other hand, the detection signal S3 goes high when both the comparison signals S1 and S2 are high.

[0181] The AND gate AND corresponds to a logic circuit that sets the detection signal S3 to a high level when the node voltage Vx is higher than the reference voltage Vref1 and the gate voltage Vg is higher than the reference voltage Vref2, i.e., when both the comparison signals S1 and S2 are at a high level. The high level of the detection signal S3 can be understood as the logic level when an abnormality is detected (when a load short circuit is detected). The AND gate AND may be built into the signal transmission device 200.

[0182] 13 is a diagram showing the load short-circuit detection operation in the second embodiment. From top to bottom, the diagram depicts the output pulse signal OUT, gate-source voltage Vgs, drain-source voltage Vds, gate signal G1, node voltage Vx, comparison signal S1, comparison signal S2, and detection signal S3. The solid line indicates the behavior when no short circuit occurs in the load ZL. Meanwhile, the dashed line indicates the behavior when a short circuit occurs in the load ZL.

[0183] At time t20, when the output pulse signal OUT rises from low level to high level, the gate-source voltage Vgs starts to rise.

[0184] If the load ZL is not short-circuited, from time t21 to t24, the gate-source voltage Vgs is maintained at the plateau voltage Vp due to the Miller effect, while the drain-source voltage Vds decreases from high to low. This operating region is known as the plateau region. The plateau voltage Vp may be, for example, 10 V. After that, at time t24, the gate-source voltage Vgs begins to rise again, and the drain-source voltage Vds reaches a low level (≈0 V). This behavior is not particularly different from the behavior in the first embodiment (times t11 to t12 in FIG. 11).

[0185] After the output pulse signal OUT rises from low to high, the gate signal G1 falls from high to low, for example, at time t21. As a result, the transistor M1 turns off. Unlike the first embodiment (FIG. 10), the detection circuit DET of this embodiment does not include the capacitor C1. Therefore, as the transistor M1 turns off, the node voltage Vx exceeds the reference voltage Vref1 without delay. As a result, the comparison signal S1 rises to high.

[0186] However, if the load ZL is not short-circuited, the gate-source voltage Vgs does not exceed the reference voltage Vref2 while the drain-source voltage Vds is decreasing from time t21 to t24, i.e., in the plateau region. Therefore, the comparison signal S2 is maintained at a low level, and the detection signal S3 also remains at a low level. The low level of the detection signal S3 can be understood as the logic level when no abnormality is detected.

[0187] Furthermore, as the drain-source voltage Vds decreases from time t21 to time t24, the node voltage Vx falls below the reference voltage Vref1 again before the end of the plateau region, at time t23 in this diagram, and therefore the comparison signal S1 falls to low level.

[0188] After the plateau region ends, at time t25, when the gate-source voltage Vgs exceeds the reference voltage Vref2, the comparison signal S2 rises to high level. However, at this point, the comparison signal S1 has already fallen to low level, so the detection signal S3 remains low.

[0189] On the other hand, if the load ZL is short-circuited, the gate-source voltage Vgs rises to a high level (≒VCC2) without any significant stagnation after time t20. Then, at time t22, when the gate-source voltage Vgs exceeds the reference voltage Vref2, the comparison signal S2 rises to a high level.

[0190] Furthermore, when transistor M1 is switched off at time t21, the node voltage Vx immediately exceeds the reference voltage Vref1. As a result, the comparison signal S1 rises to high level. Note that if the load ZL is short-circuited, the drain-source voltage Vds remains at high level (≒PVDD) without decreasing. Therefore, the node voltage Vx also remains above the reference voltage Vref1, and the comparison signal S1 remains at high level.

[0191] That is, when a short circuit occurs in the load ZL, the detection signal S3 rises to a high level at time t22. Then, since both the comparison signals S1 and S2 are maintained at a high level after time t22, the detection signal S3 also remains at a high level. As mentioned above, the high level of the detection signal S3 can be understood as the logic level when an abnormality is detected (when a load short circuit is detected).

[0192] The signal transmission device 200 may have a function of forcibly turning off the power transistor M0 when the detection signal S3 goes high, that is, a so-called load short-circuit protection function.

[0193] As described above, it is known that when the power transistor M0 is fully turned on, the gate-source voltage Vgs of the power transistor M0 becomes higher than the plateau voltage Vp. By utilizing this characteristic, the detection circuit DET of this embodiment is configured to detect the drain-source voltage Vds of the power transistor M0 only when the gate-source voltage Vgs of the power transistor M0 is higher than the plateau voltage Vp.

[0194] In this embodiment, the aforementioned blanking time Tbr is not required, and a short circuit of the load ZL can be detected without delay. Therefore, the time required for the load short-circuit protection operation to be activated, for example, the time from when the gate signal G1 falls to low level at time t21 to when the detection signal S3 rises to high level at time t22, is much shorter (for example, about 500 ns) than in the first embodiment (about 1 μs). As a result, safety in the event of a short circuit of the load ZL can be ensured even if the short-circuit withstand capability of the power transistor M0 is relatively small.

[0195] <Detection Circuit (Third Embodiment)> 14 is a diagram showing a third embodiment of the detection circuit DET. The detection circuit DET of this embodiment is based on the second embodiment (FIG. 12) described above, and further includes a resistor R.

[0196] The resistor R is connected between the application terminal of the power supply voltage VCCy and the application terminal of the node voltage Vx. The resistor R may be external to the signal transmission device 200. With such a configuration, a bias current I1' can be generated via the resistor R. The resistor R may be provided in parallel with the current source CS as shown in this figure. Alternatively, the current source CS may be omitted due to the insertion of the resistor R. The power supply voltage VCCy may be the power supply voltage VCC2 or a voltage higher than the node voltage Vx. The power supply voltage VCCy and the power supply voltage VCCx may be the same value or different values.

[0197] <Detection Circuit (Fourth Embodiment)> 15 is a diagram showing a fourth embodiment of the detection circuit DET. The detection circuit DET of this embodiment is based on the second embodiment (FIG. 12) and further includes resistors R11 to R13. Furthermore, the resistor R1 and current source CS of the previous embodiment have been removed.

[0198] A first terminal of the resistor R11 is connected to the application terminal of the power supply voltage VCCy. A second terminal of the resistor R11 and a first terminal of the resistor R12 are both connected to the anode of the diode D1. A second terminal of the resistor R12 and a first terminal of the resistor R13 are both connected to the application terminal of the node voltage Vx. A second terminal of the resistor R13 is connected to the source of the power transistor M0, and further to the application terminal of the second power system power supply voltage PVEE. Note that, as shown in this figure, the current source CS may be omitted due to the resistors R11 to R13 being externally connected. Alternatively, a current source CS may be provided, as in the second embodiment (FIG. 12) described above.

[0199] The resistors R12 and R13 connected in this manner function as a voltage divider circuit DIV that divides the drain voltage Vd (more precisely, Vd+Vf) to generate a node voltage Vx (=(Vd+Vf)×R13 / (R12+R13)). Note that the power supply voltage VCCy may be the power supply voltage VCC2, or may be a voltage higher than the drain voltage Vd (more precisely, Vd+Vf).

[0200] In the detection circuit DET of this embodiment, the drain voltage Vd when the comparison signal S1 switches to high level, that is, the DESAT detection voltage (=Vref1×(R12+R13) / R13−Vf) can be adjusted arbitrarily.

[0201] <Considerations regarding false detection of load short circuit> FIG. 16 is a diagram showing the relationship between the slew rate of the gate-source voltage Vgs and the voltages at various parts in the second embodiment. From top to bottom, the diagram shows the gate-source voltage Vgs, drain-source voltage Vds, and node voltage Vx of the power transistor M0. The gate-source voltage Vgs may also be understood as the gate voltage Vg. The drain-source voltage Vds may also be understood as the drain voltage Vd.

[0202] Also, the slew rate of the gate-source voltage Vgs is assumed to be faster on the left side of the page and slower on the right side. For example, the larger the gate current of the power transistor M0, or the smaller the gate capacitance of the power transistor M0, the faster the slew rate of the gate-source voltage Vgs. Conversely, the smaller the gate current of the power transistor M0, or the larger the gate capacitance of the power transistor M0, the slower the slew rate of the gate-source voltage Vgs.

[0203] As shown in this diagram, if the slew rate of the gate-source voltage Vgs is fast, there is a risk that the gate-source voltage Vgs will exceed the reference voltage Vref2 during the transition period of the drain-source voltage Vds. At this time, if the node voltage Vx is higher than the reference voltage Vref1, it may result in a false detection that the load ZL is short-circuited.

[0204] FIG. 17 is a diagram showing erroneous detection of a load short circuit in the second embodiment. As with FIG. 13, this diagram depicts, from top to bottom, the output pulse signal OUT, the gate-source voltage Vgs, the drain-source voltage Vds, the gate signal G1, the node voltage Vx, the comparison signal S1, the comparison signal S2, and the detection signal S3. The solid line indicates the behavior when the load ZL is not short-circuited. On the other hand, the dashed line indicates the behavior when the load ZL is short-circuited. This diagram also shows the behavior when the slew rate of the gate-source voltage Vgs is fast.

[0205] At time t30, when the output pulse signal OUT rises from low level to high level, the gate-source voltage Vgs starts to rise.

[0206] If the load ZL is not short-circuited, at time t31, the gate-source voltage Vgs is maintained at the plateau voltage Vp due to the Miller effect, and the drain-source voltage Vds begins to decrease from high level to low level.

[0207] The gate signal G1 falls from high to low at time t31, for example. As a result, the transistor M1 is turned off. At this time, the node voltage Vx exceeds the reference voltage Vref1 without delay. As a result, the comparison signal S1 rises to high. The behavior up to this point is basically the same as that of the second embodiment (FIG. 13).

[0208] However, if the slew rate of the gate-source voltage Vgs is fast, it is possible that the gate-source voltage Vgs will exceed the reference voltage Vref2 during the transition period of the drain-source voltage Vds. In this diagram, the gate-source voltage Vgs begins to rise again at time t32, and exceeds the reference voltage Vref2 at time t33. Therefore, the comparison signal S2 rises to a high level, and the comparison signal S1 is output as the detection signal S3.

[0209] At this point, the drain-source voltage Vds has not yet dropped to low level (≒0 V). Therefore, as shown in the diagram, a situation may arise in which the node voltage Vx exceeds the reference voltage Vref1 when the comparison signal S2 rises to high level, i.e., the comparison signal S1 is maintained at high level. In this situation, even if the load ZL is not short-circuited, the detection signal S3 switches to high level, i.e., the logic level for when an abnormality is detected (when a load short-circuit is detected).

[0210] Such erroneous detection of a load short circuit can also occur in the detection circuits DET of the third embodiment (FIG. 14) and the fourth embodiment (FIG. 15).

[0211] In view of the above considerations, a novel embodiment is proposed below that can suppress erroneous detection of a load short circuit even when the slew rate of the gate-source voltage Vgs is high by appropriately setting the blanking time Tbr.

[0212] <Blanking time (first setting example)> Figure 18 is a diagram showing a first setting example of the blanking time Tbr. As with the above-mentioned Figure 16, this diagram shows, from top to bottom, the gate-source voltage Vgs, drain-source voltage Vds, and node voltage Vx of the power transistor M0. The slew rate of the gate-source voltage Vgs is assumed to be faster on the left side of the page and slower on the right side.

[0213] As shown in the figure, in the first setting example, a blanking time Tbr of a predetermined length is set starting from the timing when the gate-source voltage Vgs starts to rise. The detection circuit DET may detect a load short circuit based on the comparison result between the node voltage Vx and the reference voltage Vref1 only when the blanking time Tbr has elapsed and the gate-source voltage Vgs is higher than the reference voltage Vref2. Note that the timing when the gate-source voltage Vgs starts to rise may be understood as the timing of issuing a command to raise the output pulse signal OUT, and therefore as the timing of issuing a command to turn on the power transistor M0.

[0214] For example, in the case where the slew rate of the gate-source voltage Vgs is fast, referring to this figure, if the gate-source voltage Vgs exceeds the reference voltage Vref2 before the blanking time Tbr has elapsed, a load short circuit may be detected according to the result of comparing the node voltage Vx with the reference voltage Vref1 once the blanking time Tbr has elapsed.

[0215] On the other hand, for example, if the slew rate of the gate-source voltage Vgs is slow, referring to this figure, if the gate-source voltage Vgs exceeds the reference voltage Vref2 after the blanking time Tbr has elapsed, a load short circuit may be detected based on the comparison result between the node voltage Vx and the reference voltage Vref1 at the time when the gate-source voltage Vgs exceeds the reference voltage Vref2.

[0216] This configuration makes it possible to suppress false detection of load short-circuits even when the slew rate of the gate-source voltage Vgs is high. Furthermore, in the first embodiment (FIG. 10), it is necessary to overestimate the blanking time Tbr. On the other hand, the first setting example in this figure, combined with gate voltage detection, eliminates the need to overestimate the blanking time Tbr. Therefore, it is possible to detect a short circuit in the load ZL without delay, at a level comparable to that of the second embodiment (FIG. 12).

[0217] <Detection Circuit (Fifth Embodiment)> 19 is a diagram showing a fifth embodiment of the detection circuit DET. The detection circuit DET of this embodiment is based on the second embodiment (FIG. 12) described above, and further includes a blanking time generation circuit TGNR. In addition, this diagram clearly shows the gate drive circuit GDRV as a circuit element integrated into the driver chip 220.

[0218] The detection circuit DET of this embodiment can be understood as a circuit configuration for realizing the first setting example (FIG. 18) of the blanking time Tbr described above.

[0219] The gate drive circuit GDRV receives the gate control signal Sx and generates the output pulse signal OUT. For example, the gate drive circuit GDRV may set the output pulse signal OUT to a high level when the gate control signal Sx is at a high level. Alternatively, for example, the gate drive circuit GDRV may set the output pulse signal OUT to a low level when the gate control signal Sx is at a low level. The gate drive circuit GDRV may be understood as the aforementioned driver 224. The gate control signal Sx may be understood as a logic signal output from the aforementioned pulse receiving circuit 223.

[0220] The blanking time generation circuit TGNR receives the gate control signal Sx and generates the timing signal LEB. For example, the blanking time generation circuit TGNR raises the timing signal LEB from low to high when the blanking time Tbr has elapsed since the gate control signal Sx rose to high. In other words, the timing signal LEB may be understood as a delayed signal of the gate control signal Sx.

[0221] The blanking time Tbr may be a variable value that is externally set, for example, by SPI (serial peripheral interface) communication or an external resistor.

[0222] The AND gate AND receives inputs of not only the comparison signals S1 and S2 but also the timing signal LEB, performs a logical AND operation, and outputs a detection signal S3. The detection signal S3 goes low when at least one of the comparison signals S1 and S2 and the timing signal LEB is low. On the other hand, the detection signal S3 goes high when all of the comparison signals S1 and S2 and the timing signal LEB are high.

[0223] The AND gate corresponds to a logic circuit that sets the detection signal S3 to a high level when the node voltage Vx is higher than the reference voltage Vref1, the gate voltage Vg is higher than the reference voltage Vref2, and the blanking time Tbr has elapsed, i.e., when the comparison signals S1 and S2 and the timing signal LEB are all at a high level. The high level of the detection signal S3 can be understood as the logic level at the time of abnormality detection (load short-circuit detection). The AND gate may be built into the signal transmission device 200.

[0224] FIG. 20 is a diagram showing the load short-circuit detection operation in the fifth embodiment. From top to bottom, the diagram depicts the gate control signal Sx, output pulse signal OUT, gate-source voltage Vgs, drain-source voltage Vds, gate signal G1, node voltage Vx, comparison signal S1, comparison signal S2, timing signal LEB, and detection signal S3. The solid line indicates the behavior when no short circuit occurs in the load ZL. Meanwhile, the dashed line indicates the behavior when a short circuit occurs in the load ZL. The diagram also shows the behavior when the slew rate of the gate-source voltage Vgs is fast.

[0225] At time t40, when the gate control signal Sx rises from low to high, the output pulse signal OUT rises from low to high. As a result, the gate-source voltage Vgs begins to rise. Also, when the gate control signal Sx rises to high, measurement of the blanking time Tbr begins.

[0226] If the load ZL is not short-circuited, at time t41, the gate-source voltage Vgs is maintained at the plateau voltage Vp due to the Miller effect, and the drain-source voltage Vds begins to decrease from high level to low level.

[0227] For example, at time t41, the gate signal G1 falls from high to low. As a result, the transistor M1 is turned off. At this time, the node voltage Vx exceeds the reference voltage Vref1 without delay. Therefore, the comparison signal S1 rises to high. The behavior up to this point is basically the same as that of the second embodiment (FIG. 13).

[0228] However, if the slew rate of the gate-source voltage Vgs is fast, it is possible that the gate-source voltage Vgs will exceed the reference voltage Vref2 during the transition period of the drain-source voltage Vds. In this diagram, the gate-source voltage Vgs begins to rise again at time t42, and exceeds the reference voltage Vref2 at time t43. Therefore, the comparison signal S2 rises to high level.

[0229] At this point, the drain-source voltage Vds has not yet fallen to low level (≈0 V), so as shown in the figure, a situation may arise in which the node voltage Vx exceeds the reference voltage Vref1 when the comparison signal S2 rises to high level, i.e., the comparison signal S1 is maintained at high level.

[0230] Therefore, if the blanking time Tbr is not introduced, the detection signal S3 will be switched to a high level, that is, to the logic level when an abnormality is detected (when a load short circuit is detected), even if no short circuit occurs in the load ZL.

[0231] On the other hand, in the detection circuit DET of this embodiment, the timing signal LEB is maintained at a low level until the blanking time Tbr has elapsed, and therefore, even if both the comparison signals S1 and S2 are at a high level, the detection signal S3 is maintained at a low level, i.e., the logic level when no abnormality is detected.

[0232] At time t44, as the drain-source voltage Vds decreases, the node voltage Vx again falls below the reference voltage Vref1, causing the comparison signal S1 to fall to low level.

[0233] After that, at time t45, when the blanking time Tbr expires, the timing signal LEB rises to high level. However, at this time, the comparison signal S1 has already fallen to low level, so the detection signal S3 remains low.

[0234] With this configuration, it is possible to suppress false detection of load short circuit even when the slew rate of the gate-source voltage Vgs is high.

[0235] <Blanking time (second setting example)> Figure 21 is a diagram showing a second setting example of the blanking time Tbr. In this diagram, similar to the previously mentioned Figures 16 and 18, from top to bottom, the gate-source voltage Vgs, drain-source voltage Vds, and node voltage Vx of the power transistor M0 are depicted. The slew rate of the gate-source voltage Vgs is assumed to be faster on the left side of the page and slower on the right side.

[0236] As shown in this figure, in the second setting example, a blanking time Tbr of a predetermined length is set starting from the timing at which the gate-source voltage Vgs exceeds the on-threshold voltage Vth(M0) of the power transistor M0, in other words, the turn-on timing of the power transistor M0.

[0237] With this configuration, as with the first setting example (Figure 18) mentioned above, it is possible to suppress false detection of load short-circuits even when the slew rate of the gate-source voltage Vgs is high. In addition, because there is no need to set the blanking time Tbr excessively, it is also possible to detect short-circuits in the load ZL without delay.

[0238] <Detection Circuit (Sixth Embodiment)> 22 is a diagram showing a sixth embodiment of the detection circuit DET. The detection circuit DET of this embodiment is based on the second embodiment (FIG. 12) and further includes a comparator CMP3 and a blanking time generation circuit TGNR.

[0239] The detection circuit DET of this embodiment can be understood as a circuit configuration for realizing the second setting example (FIG. 21) of the blanking time Tbr described above.

[0240] The comparator CMP3 generates a comparison signal Sy by comparing the gate voltage Vg input to its non-inverting input terminal (+) with a reference voltage Vref3 input to its inverting input terminal (-). The comparison signal Sy goes high when the gate voltage Vg is higher than the reference voltage Vref3. On the other hand, the comparison signal Sy goes low when the gate voltage Vg is lower than the reference voltage Vref3.

[0241] The reference voltage Vref3 can be understood as a threshold voltage for detecting whether the gate-source voltage Vgs of the power transistor M0 exceeds the on-threshold voltage Vth(M0). Therefore, the reference voltage Vref3 can be set to a voltage value lower than the reference voltage Vref2. For example, the reference voltage Vref3 may be set to a voltage value higher than the low level (≈GND2) of the gate voltage Vg and lower than the plateau voltage Vp of the power transistor M0. Furthermore, for example, the reference voltage Vref3 may be set to the threshold voltage (M0) or to the threshold voltage (M0) ±1V. In this manner, the reference voltage Vref3 can be set appropriately. The comparator CMP3 may be built into the signal transmission device 200.

[0242] The blanking time generation circuit TGNR receives the comparison signal Sy and generates the timing signal LEB. For example, the blanking time generation circuit TGNR raises the timing signal LEB from low to high when the blanking time Tbr has elapsed since the comparison signal Sy rose to high. In other words, the timing signal LEB may be understood as a delayed signal of the comparison signal Sy.

[0243] The AND gate AND receives inputs of not only the comparison signals S1 and S2 but also the timing signal LEB, performs a logical AND operation, and outputs a detection signal S3. The detection signal S3 goes low when at least one of the comparison signals S1 and S2 and the timing signal LEB is low. On the other hand, the detection signal S3 goes high when all of the comparison signals S1 and S2 and the timing signal LEB are high.

[0244] The AND gate AND corresponds to a logic circuit that sets the detection signal S3 to a high level when the node voltage Vx is higher than the reference voltage Vref1, the gate voltage Vg is higher than the reference voltage Vref2, and the blanking time Tbr has elapsed, i.e., when the comparison signals S1 and S2 and the timing signal LEB are all at a high level. The high level of the detection signal S3 can be understood as the logic level at the time of abnormality detection (load short-circuit detection). The AND gate AND may be built into the signal transmission device 200. As such, the configuration and operation of the AND gate AND are the same as those of the fifth embodiment (FIG. 19) described above.

[0245] FIG. 23 is a diagram showing the load short-circuit detection operation in the sixth embodiment. From top to bottom, the diagram depicts the output pulse signal OUT, gate-source voltage Vgs, drain-source voltage Vds, gate signal G1, node voltage Vx, comparison signal S1, comparison signal S2, comparison signal Sy, timing signal LEB, and detection signal S3. The solid line indicates the behavior when no short circuit occurs in the load ZL. Meanwhile, the dashed line indicates the behavior when a short circuit occurs in the load ZL. The diagram also shows the behavior when the slew rate of the gate-source voltage Vgs is fast.

[0246] At time t50, when the output pulse signal OUT rises from low level to high level, the gate-source voltage Vgs starts to rise.

[0247] At time t51, when the gate-source voltage Vgs exceeds the reference voltage Vref3, the comparison signal Sy rises to high level, and measurement of the blanking time Tbr starts.

[0248] If the load ZL is not short-circuited, at time t52, the gate-source voltage Vgs is maintained at the plateau voltage Vp due to the Miller effect, and the drain-source voltage Vds begins to decrease from high level to low level.

[0249] At time t52, for example, the gate signal G1 falls from high to low. As a result, the transistor M1 is turned off. At this time, the node voltage Vx exceeds the reference voltage Vref1 without delay. Therefore, the comparison signal S1 rises to high.

[0250] However, if the slew rate of the gate-source voltage Vgs is fast, it is possible that the gate-source voltage Vgs will exceed the reference voltage Vref2 during the transition period of the drain-source voltage Vds. In this diagram, the gate-source voltage Vgs begins to rise again at time t53, and at time t54 the gate-source voltage Vgs exceeds the reference voltage Vref2. Therefore, the comparison signal S2 rises to high level.

[0251] At this point, the drain-source voltage Vds has not yet fallen to low level (≈0 V), so as shown in the figure, a situation may arise in which the node voltage Vx exceeds the reference voltage Vref1 when the comparison signal S2 rises to high level, i.e., the comparison signal S1 is maintained at high level.

[0252] Therefore, if the blanking time Tbr is not introduced, the detection signal S3 will be switched to a high level, that is, to the logic level when an abnormality is detected (when a load short circuit is detected), even if no short circuit occurs in the load ZL.

[0253] On the other hand, in the detection circuit DET of this embodiment, the timing signal LEB is maintained at a low level until the blanking time Tbr has elapsed, and therefore, even if both the comparison signals S1 and S2 are at a high level, the detection signal S3 is maintained at a low level, i.e., the logic level when no abnormality is detected.

[0254] At time t55, as the drain-source voltage Vds decreases, the node voltage Vx again falls below the reference voltage Vref1, causing the comparison signal S1 to fall to low level.

[0255] After that, at time t56, when the blanking time Tbr expires, the timing signal LEB rises to a high level. However, at this time, the comparison signal S1 has already fallen to a low level, and therefore the detection signal S3 remains at a low level.

[0256] With this configuration, it is possible to suppress false detection of load short circuit even when the slew rate of the gate-source voltage Vgs is high.

[0257] <Blanking time (third example)> Figure 24 is a diagram showing a third setting example of the blanking time Tbr. In this diagram, similar to the previously mentioned Figures 16, 18, and 21, the gate-source voltage Vgs, drain-source voltage Vds, and node voltage Vx of the power transistor M0 are depicted from top to bottom. The slew rate of the gate-source voltage Vgs is assumed to be faster on the left side of the page and slower on the right side.

[0258] As shown in the figure, in the third setting example, as in the first setting example (FIG. 18) described above, a blanking time Tbr of a predetermined length is set starting from the timing when the gate-source voltage Vgs starts to rise, in other words, the timing when the power transistor M0 is instructed to turn on. However, unlike the first setting example described above, in the third setting example, before the blanking time Tbr has elapsed, the result of comparison between the node voltage Vx and the reference voltage Vref1 is not masked, but the node voltage Vx is forcibly pulled down.

[0259] For example, in the case where the slew rate of the gate-source voltage Vgs is fast, referring to this diagram, if the gate-source voltage Vgs exceeds the reference voltage Vref2 before the blanking time Tbr has elapsed, the node voltage Vx will be fixed at a low level lower than the reference voltage Vref1 until the blanking time Tbr has elapsed.

[0260] On the other hand, for example, if the slew rate of the gate-source voltage Vgs is slow, referring to this diagram, when the gate-source voltage Vgs exceeds the reference voltage Vref2 after the blanking time Tbr has elapsed, the node voltage Vx after the pull-down has been released is compared with the reference voltage Vref1 at the point when the gate-source voltage Vgs exceeds the reference voltage Vref2.

[0261] With this configuration, as with the first setting example (Fig. 18) and the second setting example (Fig. 21) described above, it is possible to suppress false detection of load short-circuits even when the slew rate of the gate-source voltage Vgs is high. In addition, because there is no need to set the blanking time Tbr excessively, it is also possible to detect a short circuit in the load ZL without delay.

[0262] <Detection Circuit (Seventh Embodiment)> 25 is a diagram showing a seventh embodiment of the detection circuit DET. The detection circuit DET of this embodiment is based on the fifth embodiment (FIG. 19) above, but the output terminal of the blanking time generation circuit TGNR is connected to the gate of the transistor M1 instead of the logical product gate AND.

[0263] The detection circuit DET of this embodiment can be understood as a circuit configuration for realizing the third setting example (FIG. 24) of the blanking time Tbr described above.

[0264] The blanking time generation circuit TGNR receives the gate control signal Sx and generates the gate signal G1. For example, the blanking time generation circuit TGNR drops the gate signal G1 from high to low when the blanking time Tbr has elapsed since the gate control signal Sx rose to high. In other words, the gate signal G1 may be understood as an inverted delayed signal of the gate control signal Sx.

[0265] FIG. 26 is a diagram showing the load short-circuit detection operation in the seventh embodiment. From top to bottom, the diagram depicts the gate control signal Sx, output pulse signal OUT, gate-source voltage Vgs, drain-source voltage Vds, gate signal G1, node voltage Vx, comparison signal S1, comparison signal S2, and detection signal S3. The solid line indicates the behavior when no short circuit occurs in the load ZL. Meanwhile, the dashed line indicates the behavior when a short circuit occurs in the load ZL. The diagram also shows the behavior when the slew rate of the gate-source voltage Vgs is fast.

[0266] At time t60, when the gate control signal Sx rises from low to high, the output pulse signal OUT rises from low to high. As a result, the gate-source voltage Vgs begins to rise. Also, when the gate control signal Sx rises to high, measurement of the blanking time Tbr begins.

[0267] If the load ZL is not short-circuited, at time t61, the gate-source voltage Vgs is maintained at the plateau voltage Vp due to the Miller effect, and the drain-source voltage Vds begins to decrease from high to low.

[0268] The gate signal G1 is maintained at a high level until the blanking time Tbr has elapsed. As a result, the transistor M1 is turned on, and the node voltage Vx is pulled down to a low level lower than the reference voltage Vref1. Therefore, the comparison signal S1 is maintained at a low level.

[0269] If the slew rate of the gate-source voltage Vgs is fast, it is possible that the gate-source voltage Vgs will exceed the reference voltage Vref2 during the transition period of the drain-source voltage Vds. In this diagram, the gate-source voltage Vgs begins to rise again at time t62, and exceeds the reference voltage Vref2 at time t63. Therefore, the comparison signal S2 rises to high level.

[0270] At this point, the drain-source voltage Vds has not yet dropped to low level (≈0 V). However, in the detection circuit DET of this embodiment, the comparison signal S1 is maintained at low level until the blanking time Tbr has elapsed. Therefore, the detection signal S3 is also maintained at low level, i.e., the logic level when no abnormality is detected.

[0271] After that, at time t64, as the blanking time Tbr expires, the gate signal G1 falls to low level. This turns off the transistor M1, and the pull-down of the node voltage Vx is released. At this point, the node voltage Vx falls below the reference voltage Vref1 due to the decrease in the drain-source voltage Vds. Therefore, the comparison signal S1 is maintained at low level, and the detection signal S3 remains low.

[0272] With this configuration, it is possible to suppress false detection of load short circuit even when the slew rate of the gate-source voltage Vgs is high.

[0273] <Detection Circuit (Eighth Embodiment)> 27 is a diagram showing an eighth embodiment of the detection circuit. The detection circuit DET of this embodiment is based on the sixth embodiment (FIG. 22) above, but the output terminal of the blanking time generation circuit TGNR is connected to the gate of the transistor M1 instead of the logical product gate AND.

[0274] The blanking time generation circuit TGNR receives the comparison signal Sy and generates the gate signal G1. For example, the blanking time generation circuit TGNR drops the gate signal G1 from high to low when the blanking time Tbr has elapsed since the comparison signal Sy rose to high. In other words, the gate signal G1 may be understood as an inverted delayed signal of the comparison signal Sy.

[0275] FIG. 28 is a diagram showing the load short-circuit detection operation in the eighth embodiment. From top to bottom, the diagram depicts the output pulse signal OUT, gate-source voltage Vgs, drain-source voltage Vds, comparison signal Sy, gate signal G1, node voltage Vx, comparison signal S1, comparison signal S2, and detection signal S3. The solid line indicates the behavior when no short circuit occurs in the load ZL. Meanwhile, the dashed line indicates the behavior when a short circuit occurs in the load ZL. The diagram also shows the behavior when the slew rate of the gate-source voltage Vgs is fast.

[0276] At time t70, when the output pulse signal OUT rises from low level to high level, the gate-source voltage Vgs starts to rise.

[0277] At time t71, when the gate-source voltage Vgs exceeds the reference voltage Vref3, the comparison signal Sy rises to high level, and measurement of the blanking time Tbr starts.

[0278] If the load ZL is not short-circuited, at time t72, the gate-source voltage Vgs is maintained at the plateau voltage Vp due to the Miller effect, and the drain-source voltage Vds begins to decrease from high level to low level.

[0279] The gate signal G1 is maintained at a high level until the blanking time Tbr has elapsed. As a result, the transistor M1 is turned on, and the node voltage Vx is pulled down to a low level lower than the reference voltage Vref1. Therefore, the comparison signal S1 is maintained at a low level.

[0280] If the slew rate of the gate-source voltage Vgs is fast, it is possible that the gate-source voltage Vgs will exceed the reference voltage Vref2 during the transition period of the drain-source voltage Vds. In this diagram, the gate-source voltage Vgs begins to rise again at time t73, and exceeds the reference voltage Vref2 at time t74. Therefore, the comparison signal S2 rises to high level.

[0281] At this point, the drain-source voltage Vds has not yet dropped to low level (≈0 V). However, in the detection circuit DET of this embodiment, the comparison signal S1 is maintained at low level until the blanking time Tbr has elapsed. Therefore, the detection signal S3 is also maintained at low level, i.e., the logic level when no abnormality is detected.

[0282] After that, at time t75, as the blanking time Tbr expires, the gate signal G1 falls to low level. This turns off the transistor M1, and the pull-down of the node voltage Vx is released. At this point, the node voltage Vx falls below the reference voltage Vref1 due to the decrease in the drain-source voltage Vds. Therefore, the comparison signal S1 is maintained at low level, and the detection signal S3 remains low.

[0283] With this configuration, it is possible to suppress false detection of load short circuit even when the slew rate of the gate-source voltage Vgs is high.

[0284] <Combination of embodiments> In the fifth to eighth embodiments (FIGS. 19, 22, 25, and 27) described above, the blanking time generation circuit TGNR is introduced based on the second embodiment (FIG. 12). However, the above configuration is merely an example, and the blanking time generation circuit TNGR may be introduced based on, for example, the third embodiment (FIG. 14) or the fourth embodiment (FIG. 15).

[0285] <Modification> The power transistor M0 in the above embodiment may be, for example, an IGBT. In that case, the drain and source of the power transistor M0 are interpreted as the collector and emitter of the power transistor M0, respectively. Furthermore, the drain-source voltage Vds and the gate-source voltage Vgs are interpreted as the collector-emitter voltage Vce and the gate-emitter voltage Vge, respectively.

[0286] <Application to vehicles> 29 is a diagram showing the exterior of a vehicle. Vehicle B of this configuration example is equipped with various electronic devices that operate with power supplied from a battery.

[0287] Vehicle B includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0288] The signal transmission device 200 described above can be incorporated into any of the electronic devices mounted on the vehicle B.

[0289] <Additional Notes> The detection circuit according to the present disclosure can detect a short circuit in a load without delay.

[0290] [Appendix 1] a first comparator (CMP1) configured to compare a node voltage (Vx) corresponding to a drain-source voltage (Vds) or a collector-emitter voltage (Vce) of the power transistor (M0) with a first reference voltage (Vref1) to generate a first comparison signal (S1); a second comparator (CMP2) configured to compare the gate voltage (Vg) of the power transistor (M0) with a second reference voltage (Vref2) to generate a second comparison signal (S2); a logic circuit (AND) configured to receive the first comparison signal (S1) and the second comparison signal (S2) and output a detection signal (S3); A detection circuit (DET) comprising:

[0291] [Appendix 2] 2. The detection circuit (DET) according to claim 1, wherein the second reference voltage (Vref2) is higher than a plateau voltage (Vp) of the power transistor (M0).

[0292] [Appendix 3] The detection circuit (DET) described in Appendix 2, wherein the logic circuit sets the detection signal (S3) to a logic level at the time of abnormality detection when the node voltage (Vx) is higher than the first reference voltage (Vref1) and the gate voltage (Vg) is higher than the second reference voltage (Vref2).

[0293] [Appendix 4] The detection circuit (DET) according to any one of appendices 1 to 3, further comprising a diode (D1) connected between an application terminal of the node voltage (Vx) and the drain or collector of the power transistor (M0).

[0294] [Appendix 5] The detection circuit (DET) according to any one of appendices 1 to 4, further comprising a resistor (R1) connected between an application terminal of the node voltage (Vx) and the drain or collector of the power transistor (M0).

[0295] [Appendix 6] The detection circuit (DET) according to any one of appendices 1 to 5, further comprising at least one of a current source (CS) and a resistor (R) configured to supply a bias current (I1, I1') toward the application terminal of the node voltage (Vx).

[0296] [Appendix 7] The detection circuit (DET) according to any one of appendices 1 to 6, further comprising a transistor (M1) connected between an application terminal of the node voltage (Vx) and a source or an emitter of the power transistor (M0), and configured to be turned on / off complementarily to the power transistor (M0).

[0297] [Appendix 8] The detection circuit (DET) according to any one of appendices 1 to 7, further comprising a voltage divider circuit (DIV) configured to divide a drain-source voltage (Vds) of the power transistor (M0) or a voltage corresponding thereto to generate the node voltage (Vx).

[0298] [Appendix 9] A signal transmission device (200) configured to transmit a drive signal (OUT) of the power transistor (M0) from a primary circuit system (200p) to a secondary circuit system (200s) while insulating the primary circuit system (200p) from a secondary circuit system (200s), and a detection circuit (DET) described in any one of Appendices 1 to 8 is provided in the secondary circuit system (200s).

[0299] [Appendix 10] A signal transmission device (200) according to Supplementary Note 9; the power transistor (M0) externally attached to the signal transmission device (200); An electronic device (A) comprising:

[0300] [Appendix 11] A vehicle (B) equipped with an electronic device (A) according to appendix 10.

[0301] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0302] 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42 First main surface 43 Second main surface 44A~44D Chip sidewall 45 First Functional Device 51 Insulating layer 52 Main insulating surface 53A~53D Insulated sidewall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 PCB plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High-potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 Second Pattern 95 Third Pattern 96 First Outer Line 97 Second Outer Line 98 First Intermediate Line 99 First connecting line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal Transmission Device 200p primary circuit system 200s Secondary circuit system 210 Controller Chip (1st Chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 buffer 220 Driver Chip (Second Chip) 221, 222 buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd transformer 303 Third Transformer 304 4th Transformer 305 1st Guard Ring 306 Second Guard Ring a1 to a8 pads (corresponding to the first current supply pads) b1~b8 pads (corresponding to the first voltage measurement pads) c1 to c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads A Electronic equipment AND logical product gate B vehicle C1 capacitor CMP1, CMP2, CMP3 comparators CS current source D1 Diode DET detection circuit DIV voltage divider circuit GDRV Gate drive circuit L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil M0 power transistor M1 transistor R, R1, R11, R12, R13 resistance Rg Gate resistance T21, T22, T23, T24, T25, T26 external terminals TGNR blanking time generation circuit X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias ZL load

Claims

1. a first comparator configured to compare a node voltage corresponding to a drain-source voltage or a collector-emitter voltage of the power transistor with a first reference voltage to generate a first comparison signal; a second comparator configured to compare the gate voltage of the power transistor with a second reference voltage to generate a second comparison signal; a logic circuit configured to receive the first comparison signal and the second comparison signal and output a detection signal; A detection circuit comprising:

2. 2. The detection circuit of claim 1, wherein the second reference voltage is higher than a plateau voltage of the power transistor.

3. 3. The detection circuit according to claim 2, wherein the logic circuit sets the detection signal to a logic level indicating an abnormality when the node voltage is higher than the first reference voltage and the gate voltage is higher than the second reference voltage.

4. 2. The detection circuit according to claim 1, further comprising a diode connected between an application terminal of the node voltage and the drain or collector of the power transistor.

5. 2. The detection circuit according to claim 1, further comprising a resistor connected between an application terminal of the node voltage and the drain or collector of the power transistor.

6. The detection circuit of claim 1 , further comprising at least one of a current source and a resistor configured to supply a bias current toward an application end of the node voltage.

7. 2. The detection circuit according to claim 1, further comprising a transistor connected between an application terminal of the node voltage and a source or an emitter of the power transistor, the transistor being configured to be turned on and off in a complementary manner to the power transistor.

8. 2. The detection circuit of claim 1, further comprising a voltage divider circuit configured to divide a drain-source voltage of the power transistor or a voltage corresponding thereto to generate the node voltage.

9. a blanking time generating circuit configured to generate a blanking time of a predetermined length; 2. The detection circuit according to claim 1, wherein the detection signal is maintained at a logic level when no abnormality is detected until the blanking time has elapsed.

10. 10. The detection circuit according to claim 9, wherein the blanking time is set with a timing of a turn-on instruction for the power transistor as a starting point.

11. 10. The detection circuit according to claim 9, wherein the blanking time is set with a timing at which the power transistor is turned on as a starting point.

12. a third comparator configured to compare the gate voltage of the power transistor with a third reference voltage lower than the second reference voltage to generate a third comparison signal; 12. The detection circuit according to claim 11, wherein the blanking time generation circuit receives an input of the third comparison signal and generates the blanking time.

13. 10. The detection circuit according to claim 9, wherein the logic circuit fixes the detection signal to a logic level when the abnormality is not detected, regardless of the logic levels of the first comparison signal and the second comparison signal, until the blanking time has elapsed.

14. 10. The detection circuit of claim 9, wherein the node voltage is fixed to a voltage value lower than the first reference voltage until the blanking time has elapsed.

15. A signal transmission device configured to transmit a drive signal for the power transistor from a primary circuit system to a secondary circuit system while insulating the primary circuit system from a secondary circuit system, wherein the detection circuit according to any one of claims 1 to 14 is provided in the secondary circuit system.

16. A signal transmission device according to claim 15; the power transistor externally attached to the signal transmission device; An electronic device comprising:

17. A vehicle comprising the electronic device according to claim 16.

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