Semiconductor device

Abstract

To provide a semiconductor device with improved reliability by suppressing short-circuiting between electrodes.SOLUTION: A semiconductor device according to the present disclosure includes a semiconductor substrate in which a transistor is formed. The semiconductor substrate has an active region in which the transistor is formed, and a termination region on the periphery of the active region. The termination region includes a first interlayer insulating film on the semiconductor substrate, a second interlayer insulating film thereon, a wiring electrode electrically connected to a gate electrode of the transistor, a termination electrode provided closer to an edge of the semiconductor substrate than the wiring electrode, and a field plate electrode provided between the wiring electrode and the termination electrode in a plan view. The wiring electrode, the field plate electrode, and the termination electrode are provided on the first interlayer insulating film. The field plate electrode is covered with the second interlayer insulating film. The wiring electrode, the field plate electrode covered with the second interlayer insulating film, and the termination electrode are covered with a protective film. The field plate electrode has a lower height than the wiring electrode and the termination electrode.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices having termination structures. [Background technology]

[0002] In conventional semiconductor device termination structures, the potential is stabilized by a two-layer field plate consisting of a lower field plate provided in the interlayer insulating film and an upper field plate provided on the interlayer insulating film, as disclosed in Figure 2 of Patent Document 1. However, the plate electrode of the upper field plate is thick, and the cross-sectional area subjected to horizontal stress is large.

[0003] That is, semiconductor devices are packaged by bonding wiring and other components to a semiconductor chip and then sealing it with resin. However, the sealing resin has the property of expanding and contracting due to heat. The expansion and contraction of the resin causes horizontal stress on the termination region of the semiconductor chip. When subjected to horizontal stress, electrodes provided on the interlayer insulating film, including the plate electrode, tend to slide horizontally. When an electrode slides and comes into contact with an electrode with a different potential from the plate electrode, such as a gate wiring, the plate electrode and the gate wiring are short-circuited, resulting in a problem of reduced reliability as a semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-245281 Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device that suppresses short circuits between electrodes and improves reliability. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure is a semiconductor device having a transistor formed on a semiconductor substrate, the semiconductor substrate having an active region in which the transistor is formed and a termination region surrounding the active region, the termination region comprising: a first interlayer insulating film provided on the semiconductor substrate; a second interlayer insulating film provided on the first interlayer insulating film; a wiring electrode electrically connected to a gate electrode of the transistor; a termination electrode provided closer to an edge portion of the semiconductor substrate than the wiring electrode; and a field plate electrode provided between the wiring electrode and the termination electrode in a planar view, the wiring electrode, the field plate electrode, and the termination electrode being provided on the first interlayer insulating film, the field plate electrode being covered with the second interlayer insulating film, the wiring electrode, the field plate electrode covered with the second interlayer insulating film, and the termination electrode being covered with a protective film, and the field plate electrode being shorter in height than the wiring electrode and the termination electrode. [Effects of the Invention]

[0007] According to the semiconductor device of the present disclosure, between the wiring electrode and the termination electrode there is only a field plate electrode that is shorter in height than the wiring electrode and the termination electrode. Therefore, even if the wiring electrode slides horizontally when the termination region is subjected to horizontal stress, there is no electrode that comes into contact with the wiring electrode, and therefore the reliability of the semiconductor device is not reduced. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a semiconductor device that is an RC-IGBT. [Figure 2] 2 is a cross-sectional view of a boundary portion between an IGBT region and a termination region of the semiconductor device of the first embodiment. [Figure 3] FIG. 10 is a cross-sectional view of a boundary between an IGBT region and a termination region of a semiconductor device according to a second embodiment. [Figure 4] FIG. 2 is a cross-sectional view showing the configuration of an IGBT region. [Figure 5]FIG. 11 is a cross-sectional view of a boundary between an IGBT region and a termination region of a semiconductor device according to a third embodiment. [Figure 6] FIG. 13 is a cross-sectional view of a boundary portion between an IGBT region and a termination region of a semiconductor device according to a first modification of the third embodiment. [Figure 7] FIG. 13 is a cross-sectional view of a boundary portion between an IGBT region and a termination region of a semiconductor device according to a second modification of the third embodiment. [Figure 8] FIG. 10 is a cross-sectional view of a boundary between an IGBT region and a termination region of a semiconductor device according to a fourth embodiment. [Figure 9] FIG. 11 is a cross-sectional view of a boundary between an IGBT region and a termination region of a semiconductor device according to a fifth embodiment. [Figure 10] FIG. 20 is a cross-sectional view of the boundary between the IGBT region and the termination region of the semiconductor device of the sixth embodiment. [Figure 11] FIG. 20 is a cross-sectional view of a boundary between an IGBT region and a termination region of a semiconductor device according to a seventh embodiment. [Figure 12] FIG. 20 is a cross-sectional view of the boundary between the IGBT region and the termination region of the semiconductor device of the eighth embodiment. [Figure 13] FIG. 20 is a cross-sectional view of a boundary portion between an IGBT region and a termination region of a semiconductor device according to a first modification of the eighth embodiment. [Figure 14] FIG. 20 is a cross-sectional view of a boundary portion between an IGBT region and a termination region of a semiconductor device according to a second modification of the eighth embodiment. [Figure 15] FIG. 20 is a cross-sectional view of a boundary between an IGBT region and a termination region of a semiconductor device according to a ninth embodiment. [Figure 16] FIG. 23 is a cross-sectional view of the boundary between the IGBT region and the termination region of the semiconductor device of the tenth embodiment. [Figure 17] FIG. 10 is a cross-sectional view showing a modified example of a field plate electrode. [Figure 18] FIG. 10 is a cross-sectional view showing a modified example of a field plate electrode. [Figure 19] FIG. 22 is a cross-sectional view of the boundary between the IGBT region and the termination region of the semiconductor device of the eleventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] <Introduction> In the following description, n-type and p-type indicate the conductivity types of semiconductors, and in this disclosure, the first conductivity type will be described as n-type and the second conductivity type as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. - The n type indicates that the impurity concentration is lower than that of the n type. + The p type indicates that the impurity concentration is higher than that of the n type. - The impurity concentration is lower than that of p-type, and p + The type indicates that the impurity concentration is higher than that of the p-type.

[0010] Furthermore, the drawings are schematic, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0011] In addition, in the following description, terms that indicate specific positions and directions, such as "top," "bottom," "side," "front," and "back," may be used. However, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and are not related to the directions in which the embodiments are actually implemented.

[0012] In the following, an example will be described in which the present disclosure is applied to a reverse conducting IGBT (RC-IGBT), in which an insulated gate bipolar transistor (IGBT) and a free wheel diode (FWD) are provided on a common semiconductor substrate. However, the application of the present disclosure is not limited to RC-IGBTs, and it can also be applied to IGBTs and MOSFETs (MOS Field Effect Transistors), etc.

[0013] <RC-IGBTについて> Fig. 1 is a plan view showing an RC-IGBT 100. The RC-IGBT 100 shown in Fig. 1 has IGBT regions 10 and diode regions 20 arranged side by side in a stripe pattern, and is simply referred to as a "stripe type." Note that there is also an RC-IGBT called an "island type" in which multiple diode regions 20 are arranged vertically and horizontally and IGBT regions 10 are arranged around the diode regions 20; however, since the present disclosure is applicable to any arrangement pattern, illustration and description of the "island type" will be omitted.

[0014] In FIG. 1 , the IGBT regions 10 and the diode regions 20 extend from one end to the other end of the RC-IGBT 100 and are arranged in alternating stripes in a direction perpendicular to the extension direction of the IGBT regions 10 and the diode regions 20. In FIG. 1 , three IGBT regions 10 and two diode regions are shown, and all of the diode regions 20 are sandwiched between the IGBT regions 10. However, the number of IGBT regions 10 and the diode regions 20 is not limited to this. The number of IGBT regions 10 may be three or more or less, and the number of diode regions 20 may be two or more or less. Furthermore, the positions of the IGBT regions 10 and the diode regions 20 in FIG. 1 may be interchanged, or all of the IGBT regions 10 may be sandwiched between the diode regions 20. Furthermore, a configuration in which one IGBT region 10 and one diode region 20 are provided adjacent to each other may also be used.

[0015] 1, a pad region 40 is provided adjacent to the IGBT region 10 on the lower side of the page. The pad region 40 is a region where a control pad 41 for controlling the RC-IGBT 100 is provided. The IGBT region 10 and the diode region 20 are collectively called the cell region. A termination region 30 is provided around the combined region of the cell region and pad region 40 to maintain the breakdown voltage of the RC-IGBT 100.

[0016] The present disclosure relates to a termination structure provided in termination region 30 for maintaining a breakdown voltage, and specific examples of the termination structure will be described in the embodiments.

[0017] The control pad 41 may be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, or temperature sense diode pads 41d and 41e. The current sense pad 41a is a control pad for detecting the current flowing in the cell region of the RC-IGBT 100, and is electrically connected to some IGBT cells or diode cells in the cell region so that when a current flows in the cell region of the RC-IGBT 100, a current that is one-several to one-tens-of-thousandth of the current flowing in the entire cell region flows.

[0018] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage is applied for controlling the on / off of the RC-IGBT 100. The Kelvin emitter pad 41b is electrically connected to the p-type base layer of the IGBT cell, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer are connected to the p + The temperature sensing diode pads 41d and 41e may be electrically connected to the anode and cathode of a temperature sensing diode provided in the RC-IGBT 100 via a mold contact layer. The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode (not shown) provided in the cell region, and the temperature of the RC-IGBT 100 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0019] <First Embodiment> In the following description, each embodiment will be explained using a cross-sectional view of RC-IGBT 100 taken along dashed line AA in the direction of the arrows in Fig. 1, and for convenience, the first embodiment shown in Fig. 2 will be explained as RC-IGBT 101. As shown in Fig. 2, termination region 30 is divided into electric field relaxation region 301, RESURF region 302, and channel stopper region 303, in that order from the IGBT region 10 side.

[0020] As shown in FIG. 2, the termination region 30 of the RC-IGBT 101 according to the first embodiment has n-type junctions between the first and second main surfaces of the semiconductor substrate. -The termination region 30 has a first main surface and a second main surface which are flush with the first main surface and the second main surface of the IGBT region 10, which will be described later. - The n-type drift layer 1 is formed by - It has the same configuration as the drift layer 1 and is formed continuously and integrally.

[0021] n - The drift layer 1 is a semiconductor layer containing, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 12 / cm 3 ~1.0×10 15 / cm 3 is.

[0022] n - The first main surface side of the n-type drift layer 1, i.e., the first main surface of the semiconductor substrate, - A p-type termination well layer 50 is provided between the n-type drift layer 1 and the n-type drift layer 1. The p-type termination well layer 50 is a semiconductor layer containing p-type impurities such as boron (B) or aluminum (Al), and the concentration of the p-type impurities is 1.0×10 14 / cm 3 ~1.0×10 19 / cm 3 and is provided surrounding a cell region including the IGBT region 10 and the diode region 20. The p-type termination well layer 50 has a VLD (Variation of Lateral Doping) structure in which the depth gradually decreases toward the edge of the semiconductor substrate, reaching a maximum depth of approximately 6 μm.

[0023] Further, on the outer edge side of the p-type termination well layer 50, an n-type + The n-type channel stopper layer 113, the p-type channel stopper layer 115 and the n-type channel stopper layer 112 are penetrated. - A trench is formed in the n-type drift layer 1. A polysilicon trench electrode 21a is provided in the trench via a trench insulating film 21b, thereby forming a floating trench 21.+ The p-type channel stopper layer 113, the p-type channel stopper layer 115 and the n-type channel stopper layer 112 are formed in the IGBT region 10, which will be described later. + The trench insulating film 21b and the trench electrode 21a can be formed in the same process as the p-type source layer 13, the p-type base layer 15, and the n-type carrier accumulation layer 2. The trench insulating film 21b and the trench electrode 21a can be formed in the same process as the gate trench insulating film 11b and the gate trench electrode 11a provided in the IGBT region 10, which will be described later, but the trench electrode 21a is electrically floating. Note that FIG. 2 is a cross-sectional view taken along dashed line AA in FIG. 1, and is therefore a cross-sectional view of the IGBT region 10 and the termination region 30. However, the cross-section in FIG. 1 may also be a cross-sectional view of the diode region 20 and the termination region 30. The cell region including the IGBT region 10 and the diode region 20 can also be referred to as an active region.

[0024] n - On the second main surface side of the n-type drift layer 1, - The n-type buffer layer 3 has a higher concentration of n-type impurities than the n-type drift layer 1. The n-type buffer layer 3 is formed by doping, for example, phosphorus (P) or protons (H + ) may be injected to form phosphorus (P) and protons (H + The n-type buffer layer 3 may be formed by implanting both the n-type impurity and the n-type impurity. 12 / cm 3 ~1.0×10 18 / cm 3 is.

[0025] A p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3. The p-type collector layer 16 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 16 / cm 3 ~1.0×10 20 / cm 3The p-type collector layer 16 constitutes the second main surface of the semiconductor substrate. The p-type collector layer 16 extends from the IGBT region 10 and can be referred to as a p-type termination collector layer to distinguish it from the p-type collector layer of the IGBT region 10.

[0026] A collector electrode 7 is provided on the second main surface side of p-type collector layer 16. Collector electrode 7 may be made of an aluminum alloy or an aluminum alloy and a plating film. Collector electrode 7 is in ohmic contact with p-type collector layer 16 and is electrically connected to p-type collector layer 16.

[0027] 2, the semiconductor substrate extends from the p-type termination well layer 50 to the p-type collector layer 16. In FIG. 2, the upper end of the p-type termination well layer 50 on the page is called the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the page is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the RC-IGBT101, and the second main surface of the semiconductor substrate is the main surface on the back side of the RC-IGBT101.

[0028] 2, in termination region 30, an interlayer insulating film 22a (first interlayer insulating film) having a thickness of approximately 900 nm is provided on the first main surface of the semiconductor substrate, and a channel stopper electrode 31, a gate wiring 32 (wiring electrode), and a field plate electrode 33 are provided on interlayer insulating film 22a. Field plate electrodes 33 are formed of, for example, polysilicon or amorphous silicon, and are provided in the shape of multiple rings. The number of field plate electrodes 33 provided is appropriately selected depending on the breakdown voltage design of RC-IGBT 101.

[0029] The field plate electrode 33 is covered with an interlayer insulating film 22b (second interlayer insulating film) having a thickness of about 500 nm, and the channel stopper electrode 31 and the gate wiring 32 are electrically isolated from the field plate electrode 33 by the interlayer insulating film 22b. The interlayer insulating film 22b extends to below the emitter electrode 6 in the IGBT region 10.

[0030] A channel stopper electrode 31, which is called a termination electrode, is partially connected to the trench electrode 21a via a contact hole provided in the interlayer insulating film 22a.

[0031] The field plate electrode 33, channel stopper electrode 31, and gate wiring 32, which are covered with interlayer insulating film 22b, are covered with a silicon nitride film 34 having a thickness of approximately 800 nm, which is provided as a first protective film. The silicon nitride film 34 extends beyond the gate wiring 32 onto the edge of the emitter electrode 6 in the IGBT region 10. The silicon nitride film 34 may be composed of an insulating layer, or may be composed of two layers: an insulating layer (Si3N4) and a semi-insulating layer (SInSiN: Semi-Insulating Silicon Nitride).

[0032] A solder layer 51 for bonding to an external electrode is provided on the emitter electrode 6, and the silicon nitride film 34 extends to a position where it does not contact the solder layer 51. The edge portion of the silicon nitride film 34 on the emitter electrode 6 is formed so as to have an inclination of 60° or less with respect to the surface of the emitter electrode 6.

[0033] The field plate electrodes 33 are provided between the gate wiring 32 and the channel stopper electrode 31, and in Fig. 2 three field plate electrodes 33 are provided at intervals from each other, and the region between the left and right field plate electrodes 33 is called an inter-field plate region 121. At least, no electrodes other than the field plate electrodes 33 are provided in this inter-field plate region 121.

[0034] Therefore, by sealing the RC-IGBT101 with resin, even if the termination region 30 is subjected to horizontal stress due to expansion and contraction of the resin, or if the termination region 30 is subjected to horizontal stress from the solder layer 51 due to heating of the solder layer 51 for joining to the external electrode, even if the gate wiring 32 slides horizontally, there is no electrode that comes into contact with the gate wiring 32, so the reliability of the semiconductor device is not reduced.

[0035] Furthermore, by covering termination region 30 with silicon nitride film 34, it is possible to prevent a decrease in breakdown voltage due to the intrusion of moisture from the outside.

[0036] Furthermore, since the edge portions of the silicon nitride film 34 are inclined, when the silicon nitride film 34 is subjected to horizontal stress, the stress is resolved into the horizontal X direction and the vertical Y direction, and the stress on the silicon nitride film 34 is alleviated.

[0037] Here, the thickness of the field plate electrode 33 is 1 μm or less, for example 800 nm, which is thinner than the gate wiring 32, which is about 3 to 5 μm thick, and therefore deformation due to external stress can be suppressed. The thickness of the emitter electrode 6 and the channel stopper electrode 31 is also about 3.6 μm. Like the collector electrode 7, the channel stopper electrode 31, the gate wiring 32, and the emitter electrode 6 can be formed of an aluminum alloy or an aluminum alloy and a plating film.

[0038] <Embodiment 2> Fig. 3 is a cross-sectional view showing the configuration of an RC-IGBT 102 according to the second embodiment, and corresponds to the cross-sectional view taken along dashed line AA in Fig. 1. As shown in Fig. 3, in the RC-IGBT 102, a polyimide film 35 having a thickness of about 9 µm is provided as a second protective film so as to cover a silicon nitride film 34. Note that in Fig. 3, the same components as those in the RC-IGBT 101 described using Fig. 2 are denoted by the same reference numerals, and redundant description will be omitted.

[0039] The polyimide film 35 extends onto the edge of the emitter electrode 6 and is formed so as to have an inclination of 60° or less with respect to the surface of the emitter electrode 6 .

[0040] In the RC-IGBT102, similar to the RC-IGBT101 of the first embodiment, the reliability of the semiconductor device is not reduced even when subjected to horizontal stress. In addition, by further covering the termination region 30 with a polyimide film 35, adhesion to the sealing resin is improved when the RC-IGBT102 is sealed with resin, thereby improving the reliability of the semiconductor device.

[0041] Furthermore, since the edge of the polyimide film 35 on the emitter electrode 6 is inclined, when the polyimide film 35 is subjected to horizontal stress, the stress is resolved into the horizontal X direction and the vertical Y direction, thereby mitigating the stress on the polyimide film 35.

[0042] Here, the configuration of the IGBT region 10 will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view showing the configuration of the IGBT region 10 in a cross-sectional view in the direction of the arrows along dashed line AA in Fig. 1. As shown in Fig. 4, in the IGBT region 10, n - On the first main surface side of the n-type drift layer 1, - The n-type carrier accumulation layer 2 has a higher concentration of n-type impurities than the n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, As or P as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 13 / cm 3 ~1.0×10 17 / cm 3 is.

[0043] A p-type base layer 15 is provided on the first main surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the trench gate 11. On the first main surface side of the p-type base layer 15, a p + A contact layer 14 is provided. +The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 14 is a region having a higher concentration of p-type impurities than the p-type base layer 15. + Instead of the n-type contact layer 14 + In some areas, a source layer 13 is provided. + The source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 17 / cm 3 ~1.0×10 20 / cm 3 is.

[0044] p from the first main surface of the semiconductor substrate + The n-type contact layer 14 and the p-type base layer 15 are penetrated. - A trench is formed in the n-type drift layer 1. A gate trench electrode 11a is provided in the trench via a gate trench insulating film 11b, thereby forming a trench gate 11. The gate trench electrode 11a is electrically connected to a gate wiring 32 in the termination region 30, and a gate drive voltage input from a gate pad 41c is applied via the gate wiring 32. The gate trench electrode 11a is electrically connected to a gate wiring 32 in the termination region 30 via the gate trench insulating film 11b. - The trench gate 11 faces the p-type drift layer 1. An interlayer insulating film 22b is provided on the gate trench electrode 11a of the trench gate 11. The emitter electrode 6 and the p-type drift layer 1 + The metal contact layer 14 is electrically connected to the metal contact layer 14 via a contact hole provided in the interlayer insulating film 22b.

[0045] n - As in the termination region 30, an n-type buffer layer 3, a p-type collector layer 16, and a collector electrode 7 are provided on the second main surface side of the drift layer 1.

[0046] The gate trench electrode 11a can be formed by depositing polysilicon or amorphous silicon doped with n-type or p-type impurities by CVD or the like in a trench having a gate trench insulating film 11b formed on its inner wall.

[0047] Therefore, when the gate trench electrode 11a is formed, the field plate electrode 33 can be formed in the termination region 30 at the same time.

[0048] If field plate electrode 33 is made of polysilicon and emitter electrode 6 is made of an aluminum alloy or the like, the Young's modulus of field plate electrode 33 will be approximately 130 GPa, and the Young's modulus of emitter electrode 6 will be approximately 60 GPa. Because the Young's modulus of field plate electrode 33 is higher than that of emitter electrode 6, field plate electrode 33 is resistant to deformation due to external stress.

[0049] <Third Embodiment> Fig. 5 is a cross-sectional view showing the configuration of an RC-IGBT 103 according to the third embodiment, and corresponds to the cross-sectional view taken along dashed line AA in Fig. 1. As shown in Fig. 5, in the RC-IGBT 103, a slit SL is formed in the polyimide film 35 above the gate wiring 32. Note that in Fig. 5, the same components as those in the RC-IGBT 101 described using Fig. 2 are denoted by the same reference numerals, and redundant description will be omitted.

[0050] The slits SL have a width equivalent to that of the gate wiring 32, and are formed by opening the polyimide film 35 on the gate wiring 32 by etching or the like so as not to open the silicon nitride film 34. Although the width of the slits SL is shown to be equivalent to that of the gate wiring 32 in Fig. 5, the width of the slits SL can be set to about 50 to 70 µm, which is a size that can be stably formed in terms of the manufacturing process, but the width can also be set to be wider.

[0051] By providing the slits SL, it is possible to alleviate horizontal stress on the polyimide film 35 from the IGBT region 10 side, i.e., the active region side, particularly stress from the solder layer 51, thereby improving the reliability of the polyimide film 35. Furthermore, by providing the slits SL on the gate wiring 32, the field plate electrode 33 is protected by the polyimide film 35 and the silicon nitride film 34, improving the reliability of the semiconductor device.

[0052] <Variation 1> Fig. 6 is a cross-sectional view showing the configuration of an RC-IGBT 103A according to a first modification of the third embodiment, and corresponds to the cross-sectional view taken along the dashed line AA in Fig. 1. As shown in Fig. 6, in the RC-IGBT 103A, a slit SL is formed in a polyimide film 35 provided in a region between the gate wiring 32 and the emitter electrode 6.

[0053] The slits SL have a width that does not exceed the area between the gate wiring 32 and the emitter electrode 6, and are provided by opening the polyimide film 35 so as not to open the silicon nitride film 34. The width of the slits SL is set to match the distance between the gate wiring 32 and the emitter electrode 6 and can be about 50 to 70 μm, but if the distance between the gate wiring 32 and the emitter electrode 6 becomes wider, the width can be made wider accordingly.

[0054] By providing the slits SL, it is possible to alleviate horizontal stress on the polyimide film 35 from the IGBT region 10 side, i.e., the active region side, particularly stress from the solder layer 51, thereby improving the reliability of the polyimide film 35. Furthermore, by providing the slits SL in an area other than the area where the field plate electrode 33 is formed, the field plate electrode 33 is protected by the polyimide film 35 and the silicon nitride film 34, improving the reliability of the semiconductor device.

[0055] <Variation 2> Fig. 7 is a cross-sectional view showing the configuration of an RC-IGBT 103B according to Modification 2 of Embodiment 3, and corresponds to the cross-sectional view taken along dashed line AA in Fig. 1. As shown in Fig. 7, in the RC-IGBT 103B, a silicon nitride film 34 extends beyond the edge of the emitter electrode 6 in the IGBT region 10, i.e., the active region, and a polyimide film 35 is provided to cover the silicon nitride film 34. A slit SL is formed in the polyimide film 35 on the emitter electrode 6.

[0056] The slits SL are formed by opening the polyimide film 35 on the silicon nitride film 34 so as not to open the silicon nitride film 34. The width of the slits SL can be set to about 50 to 70 μm, which is a size that can be formed stably in terms of the manufacturing process, but they can also be made wider. In that case, the silicon nitride film 34 will also extend further to the emitter electrode 6.

[0057] By providing the slits SL, it is possible to alleviate horizontal stress on the polyimide film 35 from the IGBT region 10 side, i.e., the active region side, particularly stress from the solder layer 51, thereby improving the reliability of the polyimide film 35. Furthermore, by providing the slits SL in an area other than the area where the field plate electrode 33 is formed, the field plate electrode 33 is protected by the polyimide film 35 and the silicon nitride film 34, improving the reliability of the semiconductor device.

[0058] <Fourth Embodiment> Fig. 8 is a cross-sectional view showing the configuration of an RC-IGBT 104 according to the fourth embodiment, and corresponds to the cross-sectional view taken along dashed line AA in Fig. 1. As shown in Fig. 8, in the RC-IGBT 104, a plurality of protrusions UE are formed on the surface of the polyimide film 35. Note that in Fig. 8, the same components as those in the RC-IGBT 101 described using Fig. 2 are denoted by the same reference numerals, and redundant description will be omitted.

[0059] The multiple protrusions UE protrude from the surface of the polyimide film 35 to a height of about 10 nm, making the surface of the polyimide film 35 uneven. The presence of the multiple protrusions UE further improves the adhesion between the sealing resin and the polyimide film 35 when the RC-IGBT 104 is sealed with resin, suppressing the occurrence of gaps between the sealing resin and the polyimide film 35, thereby improving the reliability of the semiconductor device.

[0060] The reason why an uneven surface is formed on the surface of the polyimide film 35 is that during the process of the back surface of the RC-IGBT 104, there is a process of cleaning the front surface, and during this cleaning process, the surface of the polyimide film 35 is roughened, forming unevenness.

[0061] <Fifth Embodiment> Fig. 9 is a cross-sectional view showing the configuration of an RC-IGBT 105 according to the fifth embodiment, and corresponds to the cross-sectional view taken along the dashed line AA in Fig. 1. As shown in Fig. 9, in the RC-IGBT 105, a gap GP is formed in a polyimide film 35 provided in a region between the gate wiring 32 and the emitter electrode 6.

[0062] The gap GP has a width that does not exceed the area between the gate wiring 32 and the emitter electrode 6 at its maximum, and is provided in the polyimide film 35 so as not to reach the silicon nitride film 34. The maximum width of the gap GP is set to match the distance between the gate wiring 32 and the emitter electrode 6, and can be about 50 to 70 μm, but if the distance between the gate wiring 32 and the emitter electrode 6 is wider, it can be made wider accordingly.

[0063] By providing the gap GP, horizontal stress on the polyimide film 35 from the IGBT region 10 side, i.e., the active region side, particularly stress from the solder layer 51, can be alleviated, and the reliability of the polyimide film 35 can be improved.

[0064] Furthermore, by providing the gap GP in a region other than the region where the field plate electrode 33 is formed, the field plate electrode 33 is protected by the polyimide film 35 and the silicon nitride film 34, thereby improving the reliability of the semiconductor device.

[0065] To form the void GP, the polyimide film 35 is formed so as to cover the silicon nitride film 34, and then the polyimide film 35 is partially removed by etching or the like at the portion where the void GP is to be formed, without penetrating the polyimide film 35, to form an opening. At this time, it is desirable to set the etching conditions so that the top of the opening is narrower than the bottom. Then, the entire polyimide film 35 is heated and cured at a temperature of about 350°C, and the top end is closed, thereby forming the void GP in the polyimide film 35.

[0066] <Sixth Embodiment> Fig. 10 is a cross-sectional view showing the configuration of an RC-IGBT 106 according to the sixth embodiment, and corresponds to the cross-sectional view taken along the dashed line AA in Fig. 1. In Fig. 10, the same components as those in the RC-IGBT 101 described using Fig. 2 are denoted by the same reference numerals, and redundant description will be omitted.

[0067] As shown in FIG. 10 , in the termination region 30 of the RC-IGBT 106, a channel stopper electrode 31, a gate wiring 32, a field plate electrode 33, an active region-side field plate electrode 33a, and an upper field plate electrode 39 are provided on an interlayer insulating film 22a having a thickness of approximately 900 nm on the first main surface of the semiconductor substrate. The field plate electrode 33 and the active region-side field plate electrode 33a are formed of, for example, polysilicon or amorphous silicon and are provided in the shape of multiple rings. The number of field plate electrodes 33 provided is appropriately selected depending on the breakdown voltage design of the RC-IGBT 101. The active region-side field plate electrode 33a is provided closest to the active region and is wider than the field plate electrode 33. The width of the active region-side field plate electrode 33a is more than twice as wide as the field plate electrode 33.

[0068] Field plate electrode 33 and active region-side field plate electrode 33a are covered with interlayer insulating film 22b (second interlayer insulating film) having a thickness of approximately 500 nm, and channel stopper electrode 31, gate wiring 32, and upper field plate electrode 39 are electrically isolated from field plate electrode 33 and active region-side field plate electrode 33a by interlayer insulating film 22b. Interlayer insulating film 22b extends to below emitter electrode 6 in IGBT region 10.

[0069] Field plate electrode 33, active region-side field plate electrode 33a, channel stopper electrode 31, gate wiring 32, and upper field plate electrode 39, which are covered with interlayer insulating film 22b, are covered with silicon nitride film 34, which is about 800 nm thick and serves as a first protective film. Silicon nitride film 34 extends beyond gate wiring 32 to above the edge of emitter electrode 6 in IGBT region 10.

[0070] A solder layer 51 for bonding to an external electrode is provided on the emitter electrode 6, and the silicon nitride film 34 extends to a position where it does not contact the solder layer 51. The edge portion of the silicon nitride film 34 on the emitter electrode 6 is formed so as to have an inclination of 60° or less with respect to the surface of the emitter electrode 6.

[0071] The upper field plate electrode 39 is formed in the same layer as the channel stopper electrode 31, the gate wiring 32, and the emitter electrode 6, and like the collector electrode 7, can be formed from an aluminum alloy or an aluminum alloy and a plating film.

[0072] The upper field plate electrode 39 is disposed between the gate wiring 32 and the channel stopper electrode 31, but since the active region side field plate electrode 33a is sandwiched between the upper field plate electrode 39 and the gate wiring 32, it is located at a position sufficiently distant from the gate wiring 32.

[0073] Therefore, by sealing RC-IGBT106 with resin, even if the termination region 30 is subjected to horizontal stress due to expansion and contraction of the resin, or if the termination region 30 is subjected to horizontal stress from the solder layer 51 due to heating of the solder layer 51 for joining to the external electrode, even if the gate wiring 32 slides horizontally, there is little possibility that the gate wiring 32 will come into contact with the upper field plate electrode 39, and the reliability of the semiconductor device will not be reduced.

[0074] Furthermore, the potential in termination region 30 can be further stabilized by the two-layer field plate formed by upper field plate electrode 39, field plate electrode 33, and active region side field plate electrode 33a.

[0075] Furthermore, by covering termination region 30 with silicon nitride film 34, it is possible to prevent a decrease in breakdown voltage due to the intrusion of moisture from the outside.

[0076] Furthermore, since the edge portions of the silicon nitride film 34 are inclined, when the silicon nitride film 34 is subjected to horizontal stress, the stress is resolved into the horizontal X direction and the vertical Y direction, and the stress on the silicon nitride film 34 is alleviated.

[0077] <Seventh Embodiment> Fig. 11 is a cross-sectional view showing the configuration of an RC-IGBT 107 according to the seventh embodiment, and corresponds to the cross-sectional view taken along dashed line AA in Fig. 1. As shown in Fig. 11, in the RC-IGBT 107, a polyimide film 35 having a thickness of about 9 µm is provided as a second protective film so as to cover the silicon nitride film 34. Note that in Fig. 11, the same components as those in the RC-IGBT 106 described using Fig. 10 are denoted by the same reference numerals, and redundant description will be omitted.

[0078] The polyimide film 35 extends onto the edge of the emitter electrode 6 and is formed so as to have an inclination of 60° or less with respect to the surface of the emitter electrode 6 .

[0079] In the RC-IGBT107, similar to the RC-IGBT101 of the first embodiment, the reliability of the semiconductor device is not reduced even when subjected to horizontal stress, and by further covering the termination region 30 with a polyimide film 35, adhesion to the sealing resin is improved when the RC-IGBT102 is sealed with resin, thereby improving the reliability of the semiconductor device.

[0080] Furthermore, since the edge of the polyimide film 35 on the emitter electrode 6 is inclined, when the polyimide film 35 is subjected to horizontal stress, the stress is resolved into the horizontal X direction and the vertical Y direction, thereby mitigating the stress on the polyimide film 35.

[0081] Furthermore, as described in the second embodiment, when forming the gate trench electrode 11a in the IGBT region 10, the field plate electrode 33 and the active region side field plate electrode 33a in the termination region 30 can be formed simultaneously.

[0082] If field plate electrode 33 and active region-side field plate electrode 33a are made of polysilicon and emitter electrode 6 is made of an aluminum alloy or the like, the Young's modulus of field plate electrode 33 and active region-side field plate electrode 33a will be approximately 130 GPa, and the Young's modulus of emitter electrode 6 will be approximately 60 GPa. Because the Young's modulus of field plate electrode 33 and active region-side field plate electrode 33a is higher than that of emitter electrode 6, field plate electrode 33 and active region-side field plate electrode 33a will be resistant to deformation due to external stress.

[0083] <Embodiment 8> Fig. 12 is a cross-sectional view showing the configuration of an RC-IGBT 108 according to the eighth embodiment, and corresponds to the cross-sectional view taken along dashed line AA in Fig. 1. As shown in Fig. 12, in the RC-IGBT 108, a slit SL is formed in the polyimide film 35 above the gate wiring 32. Note that in Fig. 12, the same components as those in the RC-IGBT 107 described using Fig. 11 are denoted by the same reference numerals, and redundant description will be omitted.

[0084] The slits SL have a width equivalent to that of the gate wiring 32, and are formed by opening the polyimide film 35 on the gate wiring 32 by etching or the like so as not to open the silicon nitride film 34. Note that in Fig. 12, the width of the slits SL is set to be equivalent to that of the gate wiring 32, but the width of the slits SL can be set to about 50 to 70 µm, which is a size that can be formed stably in terms of the manufacturing process, and can also be set to a width greater than that.

[0085] By providing the slits SL, it is possible to alleviate horizontal stress on the polyimide film 35 from the IGBT region 10 side, i.e., the active region side, particularly stress from the solder layer 51, thereby improving the reliability of the polyimide film 35. Furthermore, by providing the slits SL on the gate wiring 32, the active region side field plate electrode 33a is protected by the polyimide film 35 and the silicon nitride film 34, improving the reliability of the semiconductor device.

[0086] <Variation 1> Fig. 13 is a cross-sectional view showing the configuration of an RC-IGBT 108A according to a first modification of the eighth embodiment, and corresponds to the cross-sectional view taken along the dashed line AA in Fig. 1. As shown in Fig. 13, in the RC-IGBT 108A, a slit SL is formed in a polyimide film 35 provided in a region between the gate wiring 32 and the emitter electrode 6.

[0087] The slits SL have a width that does not exceed the area between the gate wiring 32 and the emitter electrode 6, and are provided by opening the polyimide film 35 so as not to open the silicon nitride film 34. The width of the slits SL is set to match the distance between the gate wiring 32 and the emitter electrode 6 and can be about 50 to 70 μm, but if the distance between the gate wiring 32 and the emitter electrode 6 becomes wider, the width can be made wider accordingly.

[0088] Providing slits SL can relieve horizontal stress on polyimide film 35 from IGBT region 10, i.e., the active region side, particularly stress from solder layer 51, improving the reliability of polyimide film 35. Furthermore, by providing slits SL in a region other than the region where active region-side field plate electrode 33a is formed, active region-side field plate electrode 33a is protected by polyimide film 35 and silicon nitride film 34, improving the reliability of the semiconductor device.

[0089] <Variation 2> Fig. 14 is a cross-sectional view showing the configuration of an RC-IGBT 108B according to Modification 2 of Embodiment 8, and corresponds to the cross-sectional view taken along dashed line AA in Fig. 1. As shown in Fig. 14, in the RC-IGBT 108B, a silicon nitride film 34 extends beyond the edge of the emitter electrode 6 in the IGBT region 10, i.e., the active region, and a polyimide film 35 is provided to cover the silicon nitride film 34. A slit SL is formed in the polyimide film 35 on the emitter electrode 6.

[0090] The slits SL are formed by opening the polyimide film 35 on the silicon nitride film 34 so as not to open the silicon nitride film 34. The width of the slits SL can be set to about 50 to 70 μm, which is a size that can be formed stably in terms of the manufacturing process, but they can also be made wider. In that case, the silicon nitride film 34 will also extend further to the emitter electrode 6.

[0091] Providing slits SL can relieve horizontal stress on polyimide film 35 from IGBT region 10, i.e., the active region side, particularly stress from solder layer 51, improving the reliability of polyimide film 35. Furthermore, by providing slits SL in a region other than the region where active region-side field plate electrode 33a is formed, active region-side field plate electrode 33a is protected by polyimide film 35 and silicon nitride film 34, improving the reliability of the semiconductor device.

[0092] <Ninth Embodiment> Fig. 15 is a cross-sectional view showing the configuration of an RC-IGBT 109 according to the ninth embodiment, and corresponds to the cross-sectional view taken along dashed line AA in Fig. 1. As shown in Fig. 15, in the RC-IGBT 109, a plurality of protrusions UE are formed on the surface of the polyimide film 35. Note that in Fig. 15, the same components as those in the RC-IGBT 107 described using Fig. 11 are denoted by the same reference numerals, and redundant description will be omitted.

[0093] The multiple protrusions UE protrude from the surface of the polyimide film 35 to a height of about 10 nm, making the surface of the polyimide film 35 uneven. The presence of the multiple protrusions UE improves the adhesion between the sealing resin and the polyimide film 35 when the RC-IGBT 104 is sealed with resin, suppressing the occurrence of gaps between the sealing resin and the polyimide film 35, and improving the reliability of the semiconductor device.

[0094] The reason why unevenness is formed on the surface of polyimide film 35 is that during the process of the back surface of RC-IGBT109, there is a process of cleaning the front surface, and during this cleaning process, the surface of polyimide film 35 is roughened, forming unevenness.

[0095] <Tenth Embodiment> Fig. 16 is a cross-sectional view showing the configuration of an RC-IGBT 110 according to the tenth embodiment, and corresponds to the cross-sectional view taken along the dashed line AA in Fig. 1. As shown in Fig. 16, in the RC-IGBT 110, a gap GP is formed in a polyimide film 35 provided in a region between the gate wiring 32 and the emitter electrode 6.

[0096] The gap GP has a width that does not exceed the area between the gate wiring 32 and the emitter electrode 6 at its maximum, and is provided in the polyimide film 35 so as not to reach the silicon nitride film 34. The maximum width of the gap GP is set to match the distance between the gate wiring 32 and the emitter electrode 6, and can be about 50 to 70 μm, but if the distance between the gate wiring 32 and the emitter electrode 6 is wider, it can be made wider accordingly.

[0097] By providing the gap GP, horizontal stress on the polyimide film 35 from the IGBT region 10 side, i.e., the active region side, particularly stress from the solder layer 51, can be alleviated, and the reliability of the polyimide film 35 can be improved.

[0098] Furthermore, by providing the gap GP in a region other than the region where the active region side field plate electrode 33a is formed, the active region side field plate electrode 33a is protected by the polyimide film 35 and the silicon nitride film 34, thereby improving the reliability of the semiconductor device.

[0099] To form the void GP, the polyimide film 35 is formed so as to cover the silicon nitride film 34, and then the polyimide film 35 is partially removed by etching or the like at the portion where the void GP is to be formed, without penetrating the polyimide film 35, to form an opening. At this time, it is desirable to set the etching conditions so that the top of the opening is narrower than the bottom. Then, the entire polyimide film 35 is heated and cured at a temperature of about 350°C, and the top end is closed, thereby forming the void GP in the polyimide film 35.

[0100] <Modifications of the field plate electrode> In the first to tenth embodiments described above, the cross-sectional shapes of the field plate electrode 33 and the active region side field plate electrode 33a are shown as rectangular, but the present invention is not limited to this.

[0101] For example, the cross-sectional shape of the field plate electrode 33 and the active region side field plate electrode 33a can be trapezoidal as shown in Fig. 17. This makes the structure more resistant to deformation due to external stress.

[0102] 18, trapezoidal field plate electrode 33 and active region-side field plate electrode 33a can have a recess RP on part of the top surface and a protrusion CP on part of the bottom surface, which provides an anchor effect between the recess RP and the protrusion CP, resulting in a structure that is more resistant to deformation due to external stress.

[0103] <Embodiment 11> Fig. 19 is a cross-sectional view showing the configuration of RC-IGBT 11 according to the eleventh embodiment, and corresponds to the cross-sectional view taken along dashed line AA in Fig. 1. As shown in Fig. 19, in termination region 30 of RC-IGBT 111, interlayer insulating film 22a having a thickness of approximately 900 nm is provided on the first main surface of the semiconductor substrate, and channel stopper electrode 31 and gate wiring 32 are provided on interlayer insulating film 22a. As shown in Fig. 19, termination region 30 is divided into electric field relaxation region 301, no-electrode region 304, and channel stopper region 303, in that order from the IGBT region 10 side.

[0104] A part of the channel stopper electrode 31 is connected to the trench electrode 21a via a contact hole provided in the interlayer insulating film 22a.

[0105] The channel stopper electrode 31 and the gate wiring 32 are covered with a silicon nitride film 34 having a thickness of about 800 nm, which is provided as a first protective film. The silicon nitride film 34 extends beyond the gate wiring 32 onto the edge of the emitter electrode 6 in the IGBT region 10.

[0106] Furthermore, a polyimide film 35 having a thickness of about 9 μm is provided as a second protective film so as to cover the silicon nitride film 34. In Fig. 19, the same components as those in the RC-IGBT 101 described with reference to Fig. 2 are denoted by the same reference numerals, and redundant description will be omitted.

[0107] The polyimide film 35 extends onto the edge of the emitter electrode 6 and is formed so as to have an inclination of 60° or less with respect to the surface of the emitter electrode 6 .

[0108] In the RC-IGBT111, no electrodes are provided over the entire region between the channel stopper electrode 31 and the gate wiring 32. Therefore, when the termination region 30 is subjected to horizontal stress due to expansion and contraction of the resin sealed in the RC-IGBT111, or when the termination region 30 is subjected to horizontal stress from the solder layer 51 due to heating of the solder layer 51 for bonding to an external electrode, even if the gate wiring 32 slides horizontally, there is no electrode that comes into contact with the gate wiring 32, and therefore the reliability of the semiconductor device does not decrease.

[0109] Furthermore, since the edge of the polyimide film 35 on the emitter electrode 6 is inclined, when the polyimide film 35 is subjected to horizontal stress, the stress is resolved into the horizontal X direction and the vertical Y direction, thereby mitigating the stress on the polyimide film 35.

[0110] The slits SL described in the third embodiment with reference to FIGS. 5 to 7 can be provided in the polyimide film 35 of the RC-IGBT 111.

[0111] Furthermore, the plurality of protrusions UE described with reference to FIG. 8 in the fourth embodiment may be provided on the surface of the polyimide film 35 of the RC-IGBT 111, making the surface of the polyimide film 35 uneven.

[0112] Furthermore, the gap GP described in the fifth embodiment with reference to FIG. 9 can be provided in the polyimide film 35 of the RC-IGBT 111.

[0113] It should be noted that, within the scope of the present disclosure, the embodiments can be freely combined, modified, or omitted as appropriate.

[0114] The present disclosure described above will be summarized as an appendix.

[0115] (Appendix 1) A semiconductor device in which a transistor is formed on a semiconductor substrate, The semiconductor substrate is an active region in which the transistor is formed; a termination region surrounding the active region; The termination region is a first interlayer insulating film provided on the semiconductor substrate; a second interlayer insulating film provided on the first interlayer insulating film; a wiring electrode electrically connected to a gate electrode of the transistor; a termination electrode provided closer to an edge portion of the semiconductor substrate than the wiring electrode; a field plate electrode provided between the wiring electrode and the termination electrode in a plan view, the wiring electrode, the field plate electrode, and the termination electrode are provided on the first interlayer insulating film; the field plate electrode is covered with the second interlayer insulating film; the wiring electrode, the field plate electrode covered with the second interlayer insulating film, and the termination electrode are covered with a protective film; The field plate electrode is The semiconductor device has a height lower than that of the wiring electrode and the termination electrode.

[0116] (Appendix 2) A semiconductor device in which a transistor is formed on a semiconductor substrate, The semiconductor substrate is an active region in which the transistor is formed; a termination region surrounding the active region; The termination region is a first interlayer insulating film provided on the semiconductor substrate; a second interlayer insulating film provided on the first interlayer insulating film; a wiring electrode electrically connected to a gate electrode of the transistor; a termination electrode provided closer to an edge portion of the semiconductor substrate than the wiring electrode; a plurality of field plate electrodes provided between the wiring electrode and the termination electrode in a plan view; an upper field plate electrode provided closer to the termination electrode than the wiring electrode; the wiring electrode, the plurality of field plate electrodes, and the termination electrode are provided on the first interlayer insulating film; the plurality of field plate electrodes are covered with the second interlayer insulating film; the upper field plate electrode is provided on the second interlayer insulating film, Among the plurality of field plate electrodes, an active region side field plate electrode arranged closest to the active region has a width wider than the other field plate electrodes, the wiring electrode, the plurality of field plate electrodes covered with the second interlayer insulating film, the upper field plate electrode, and the termination electrode are covered with a protective film; The plurality of field plate electrodes are The semiconductor device has a height lower than that of the wiring electrode and the termination electrode.

[0117] (Appendix 3) A semiconductor device in which a transistor is formed on a semiconductor substrate, The semiconductor substrate is an active region in which the transistor is formed; a termination region surrounding the active region; The termination region is an interlayer insulating film provided on the semiconductor substrate; a wiring electrode electrically connected to a gate electrode of the transistor; a termination electrode provided closer to an edge portion of the semiconductor substrate than the wiring electrode, the wiring electrode and the termination electrode are provided on the interlayer insulating film, the wiring electrode, the termination electrode, and the interlayer insulating film between the wiring electrode and the termination electrode are covered with a protective film.

[0118] (Appendix 4) The protective film is 4. The semiconductor device according to claim 1, further comprising a silicon nitride film.

[0119] (Appendix 5) The protective film is 5. The semiconductor device according to claim 4, further comprising a polyimide film covering the silicon nitride film.

[0120] (Appendix 6) The polyimide film is 6. The semiconductor device according to claim 5, further comprising a slit provided between the wiring electrode and the active region.

[0121] (Appendix 7) The polyimide film is 6. The semiconductor device according to claim 5, wherein the surface is an uneven surface having a plurality of protrusions.

[0122] (Appendix 8) The polyimide film is 6. The semiconductor device according to claim 5, further comprising a gap provided between the wiring electrode and the active region.

[0123] (Appendix 9) The field plate electrode is 2. The semiconductor device of claim 1, wherein the height is 1 μm or less.

[0124] (Appendix 10) The field plate electrode is 2. The semiconductor device according to claim 1, wherein the active region has a Young's modulus higher than that of a main electrode of the transistor.

[0125] (Appendix 11) The field plate electrode is 2. The semiconductor device of claim 1, wherein the semiconductor device is made of polysilicon or amorphous silicon.

[0126] (Appendix 12) The field plate electrode is 2. The semiconductor device according to claim 1, wherein the cross-sectional shape is a trapezoid.

[0127] (Appendix 13) The field plate electrode is 13. The semiconductor device according to claim 12, having a recess on a top surface and a protrusion on a bottom surface.

[0128] (Appendix 14) The plurality of field plate electrodes are 3. The semiconductor device of claim 2, wherein the height is 1 μm or less.

[0129] (Appendix 15) The plurality of field plate electrodes are 2. The semiconductor device according to claim 1, wherein the active region has a Young's modulus higher than that of a main electrode of the transistor.

[0130] (Appendix 16) The plurality of field plate electrodes are 2. The semiconductor device of claim 1, wherein the semiconductor device is made of polysilicon or amorphous silicon.

[0131] (Appendix 17) The protective film is 4. The semiconductor device according to claim 1, wherein the end portion on the active region side has an inclination of 60° or less.

[0132] (Appendix 18) The field plate electrode is 2. The semiconductor device according to claim 1, wherein the cross-sectional shape is a trapezoid.

[0133] (Appendix 19) The field plate electrode is 20. The semiconductor device according to claim 18, wherein the semiconductor device has a recess on the top surface and a protrusion on the bottom surface. [Explanation of symbols]

[0134] 10 IGBT region, 30 termination region, 22a, 22b interlayer insulating film, 31 channel stopper electrode, 32 gate wiring, 33 field plate electrode, 33a active region side field plate electrode, 34 silicon nitride film, 35 polyimide film, 39 upper field plate electrode, CP convex portion, RP concave portion, SL slit, GP void, UE protrusion.

Claims

1. A semiconductor device in which a transistor is formed on a semiconductor substrate, The semiconductor substrate is an active region in which the transistor is formed; a termination region surrounding the active region; The termination region is a first interlayer insulating film provided on the semiconductor substrate; a second interlayer insulating film provided on the first interlayer insulating film; a wiring electrode electrically connected to a gate electrode of the transistor; a termination electrode provided closer to an edge portion of the semiconductor substrate than the wiring electrode; a field plate electrode provided between the wiring electrode and the termination electrode in a plan view, the wiring electrode, the field plate electrode, and the termination electrode are provided on the first interlayer insulating film; the field plate electrode is covered with the second interlayer insulating film; the wiring electrode, the field plate electrode covered with the second interlayer insulating film, and the termination electrode are covered with a protective film; The field plate electrode is The semiconductor device has a height lower than that of the wiring electrode and the termination electrode.

2. A semiconductor device in which a transistor is formed on a semiconductor substrate, The semiconductor substrate is an active region in which the transistor is formed; a termination region surrounding the active region; The termination region is a first interlayer insulating film provided on the semiconductor substrate; a second interlayer insulating film provided on the first interlayer insulating film; a wiring electrode electrically connected to a gate electrode of the transistor; a termination electrode provided closer to an edge portion of the semiconductor substrate than the wiring electrode; a plurality of field plate electrodes provided between the wiring electrode and the termination electrode in a plan view; an upper field plate electrode provided closer to the termination electrode than the wiring electrode; the wiring electrode, the plurality of field plate electrodes, and the termination electrode are provided on the first interlayer insulating film; the plurality of field plate electrodes are covered with the second interlayer insulating film; the upper field plate electrode is provided on the second interlayer insulating film, Among the plurality of field plate electrodes, an active region side field plate electrode arranged closest to the active region has a width wider than the other field plate electrodes, the wiring electrode, the plurality of field plate electrodes covered with the second interlayer insulating film, the upper field plate electrode, and the termination electrode are covered with a protective film; The plurality of field plate electrodes are The semiconductor device has a height lower than that of the wiring electrode and the termination electrode.

3. A semiconductor device in which a transistor is formed on a semiconductor substrate, The semiconductor substrate is an active region in which the transistor is formed; a termination region surrounding the active region; The termination region is an interlayer insulating film provided on the semiconductor substrate; a wiring electrode electrically connected to a gate electrode of the transistor; a termination electrode provided closer to an edge portion of the semiconductor substrate than the wiring electrode, the wiring electrode and the termination electrode are provided on the interlayer insulating film, the wiring electrode, the termination electrode, and the interlayer insulating film between the wiring electrode and the termination electrode are covered with a protective film.

4. The protective film is 4. The semiconductor device according to claim 1, further comprising a silicon nitride film.

5. The protective film is 5. The semiconductor device according to claim 4, further comprising a polyimide film covering said silicon nitride film.

6. The polyimide film is 6. The semiconductor device according to claim 5, further comprising a slit provided between said wiring electrode and said active region.

7. The polyimide film is 6. The semiconductor device according to claim 5, wherein the surface is an uneven surface having a plurality of protrusions.

8. The polyimide film is 6. The semiconductor device according to claim 5, further comprising a gap provided between said wiring electrode and said active region.

9. The field plate electrode is 2. The semiconductor device according to claim 1, wherein the height is 1 [mu]m or less.

10. The field plate electrode is 2. The semiconductor device according to claim 1, wherein said active region has a Young's modulus higher than that of a main electrode of said transistor.

11. The field plate electrode is 2. The semiconductor device according to claim 1, wherein the semiconductor device is made of polysilicon or amorphous silicon.

12. The field plate electrode is 2. The semiconductor device according to claim 1, wherein the cross-sectional shape is trapezoidal.

13. The field plate electrode is 13. The semiconductor device according to claim 12, wherein the semiconductor device has a recess on the top surface and a protrusion on the bottom surface.

14. The plurality of field plate electrodes are 3. The semiconductor device according to claim 2, wherein the height is 1 [mu]m or less.

15. The plurality of field plate electrodes are 2. The semiconductor device according to claim 1, wherein said active region has a Young's modulus higher than that of a main electrode of said transistor.

16. The plurality of field plate electrodes are 2. The semiconductor device according to claim 1, wherein the semiconductor device is made of polysilicon or amorphous silicon.

17. The protective film is 4. The semiconductor device according to claim 1, wherein the end portion on the active region side has an inclination of 60 degrees or less.

18. The field plate electrode is 2. The semiconductor device according to claim 1, wherein the cross-sectional shape is trapezoidal.

19. The field plate electrode is 20. The semiconductor device according to claim 18, wherein the semiconductor device has a recess on the top surface and a protrusion on the bottom surface.

Images