Chiplet head alignment apparatus mounted with x-ray imaging system for aligning semiconductor packaging and method for the same

Abstract

To detect a radiation source in a joining process of a plurality of semiconductor chips to perform fine alignment of the semiconductor chips.SOLUTION: An alignment device for semiconductor packaging includes: a radiation source 120 that irradiates a plurality of semiconductor chips with radiation; a radiation sensor 140 that detects the radiation passing through the plurality of semiconductor chips; a head 130 that is coupled to one of the radiation source and the radiation sensor; and an alignment unit 150 and a processor 110 that, on the basis of detection information obtained by the radiation sensor, aligns and joins the plurality of semiconductor chips to each other. On the basis of identifying, of the plurality of semiconductor chips, a first semiconductor chip coupled to at least part of the head, the processor identifies a second semiconductor chip for coupling to the first semiconductor chip of the plurality of semiconductor chips, and controls at least one of the head, alignment unit, and any combination of them to perform matching of a first reference mark included in the first semiconductor chip and a second reference mark included in the second semiconductor chip.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a chiplet head alignment apparatus and method equipped with an X-ray imaging system for semiconductor packaging alignment. [Background technology]

[0002] With the advancement of AI technology, research and development of AI modules is ongoing, and as a result, research into miniaturization of single chips through process miniaturization is gaining attention in the field of AI modules, as is technology that can package chips with various functions to realize multi-function chips.In addition, advanced packaging technologies, such as hybrid bonding for vertical stacking of wafers or chips to ensure high capacity, are being actively developed.

[0003] For this purpose, 2.5D / 3D integration technologies using silicon interposers and TSVs have been developed, but until now, when bonding semiconductor chips together (chip to chip bonding), the bonding position is confirmed optically, the bonding position is memorized, and then mechanical bonding is performed. Alternatively, a chiplet head equipped with an optical system recognizes the alignment mark on the outer periphery of the lower chip, aligns the upper chip with the lower chip, and then attaches them. Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides an alignment apparatus and method for semiconductor packaging that detects a radiation source during the bonding process of multiple semiconductor chips and continuously performs fine alignment on the semiconductor chips, thereby increasing the bonding accuracy and thereby increasing semiconductor production yields.

[0005] An embodiment of the present invention provides a high-precision X-ray chip alignment head for semiconductor chiplets that can align interconnects or TSVs of upper / lower chips attached to a semiconductor chip using X-rays, which cannot be seen with the naked eye, while visually checking the attachment surface of the semiconductor chip, and an alignment method using the same.

[0006] An embodiment of the present invention aims to provide an alignment apparatus and method for semiconductor packaging that improves alignment accuracy and packaging yield relative to bonding based on optical alignment methods, thereby reducing production costs and improving price competitiveness.

[0007] An embodiment of the present invention aims to provide an alignment apparatus and method for semiconductor packaging that prevents loss of lower chip area due to alignment marks for alignment by an optical system located on the outer periphery of a chiplet head and increases packaging integration, thereby reducing production costs and improving price competitiveness.

[0008] An embodiment of the present invention aims to provide an alignment apparatus and method for semiconductor packaging that can increase the yield of semiconductor chips by accurately bonding interconnects or TSVs that are becoming smaller as the number of bonding parts per area of ​​the upper and lower chips increases.

[0009] Although the present invention can be applied to existing bump processes, it aims to provide a method for improving production yield and semiconductor performance by accurately detecting and bonding junctions during hybrid bonding, a next-generation technology used to bond interconnects or TSVs that are becoming increasingly miniaturized with an increasing number of junctions.

[0010] An embodiment of the present invention aims to provide an alignment device and method for packaging semiconductor chips that prevents damage to the semiconductor chips by irradiating low-dose radiation or by allowing radiation to penetrate only a portion of the semiconductor chip where alignment marks and / or TSVs are located, rather than the entire semiconductor chip area.

[0011] The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0012] According to an embodiment of the present invention, an alignment apparatus for semiconductor packaging includes a radiation source that irradiates radiation onto a plurality of semiconductor chips; a chiplet head coupled to at least a portion of the radiation source and causing at least one of movement, rotation, or any combination thereof of the radiation source; a radiation sensor that detects the radiation that has passed through the plurality of semiconductor chips; an alignment unit that aligns and bonds the plurality of semiconductor chips based on detection information acquired by the radiation sensor; and a processor that controls at least one of the radiation source, the head, the radiation sensor, the alignment unit, or any combination thereof. The processor may identify a second semiconductor chip to be bonded to the first semiconductor chip among the plurality of semiconductor chips based on identification of a first semiconductor chip coupled to at least a portion of the head, and control at least one of the head, the alignment unit, or any combination thereof to match a first reference mark included in the first semiconductor chip with a second reference mark included in the second semiconductor chip. [Effects of the Invention]

[0013] This technology detects radiation sources in interconnects and TSVs on the bonding surface that cannot be seen with the naked eye during the bonding process of multiple semiconductor chips, and continuously performs fine alignment on the semiconductor chips, thereby increasing the bonding accuracy and thereby increasing semiconductor production yields.

[0014] In addition, this technology improves alignment accuracy compared to bonding based on optical alignment methods, increasing packaging yields and reducing production costs, thereby improving price competitiveness.

[0015] In addition, this technology can prevent damage to the semiconductor chip by irradiating low-dose radiation or by allowing radiation to penetrate only a partial area where the alignment marks and / or TSVs are located, rather than the entire area of ​​the semiconductor chip.

[0016] In addition, this technology can increase the integration density of chips by reducing the alignment mark area of ​​the lower chip for the alignment optical system mounted on the outer periphery of the existing chiplet head.

[0017] In addition, various other effects may be provided that can be grasped directly or indirectly through this document. [Brief explanation of the drawings]

[0018] [Figure 1] 1 shows an example of a block diagram of a chiplet alignment apparatus for semiconductor packaging according to an embodiment of the present invention. [Figure 2] 1 is a simplified diagram illustrating an example of a chiplet alignment apparatus for semiconductor packaging according to an embodiment of the present invention. [Figure 3a] 1 illustrates an example of the layout of an alignment device for semiconductor chip packaging according to an embodiment of the present invention. [Figure 3b] 1 illustrates an example of the layout of an alignment device for semiconductor chip packaging according to an embodiment of the present invention. [Figure 4a] 10 shows an example of matching the phase of alignment marks in one embodiment of the present invention. [Figure 4b] 1 illustrates an example of matching the phase of TSVs in one embodiment of the present invention. [Figure 5] 1 shows an example of a flowchart for an alignment method for semiconductor packaging according to an embodiment of the present invention. [Figure 6] 1 shows an example of a flowchart for an alignment method for semiconductor packaging according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, some embodiments of the present invention will be described in detail with reference to the drawings. When assigning reference numerals to components in each drawing, care should be taken to assign the same numerals to identical components even if they appear in different drawings. Furthermore, when describing embodiments of the present invention, if a detailed description of related known structures or functions is deemed to hinder understanding of the embodiments of the present invention, the detailed description will be omitted.

[0020] When describing components of an embodiment of the present invention, terms such as "first," "second," "A," "B," "(a)," and "(b)" may be used. These terms are used to distinguish the component from other components and do not limit the nature, order, or sequence of the components. Furthermore, unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those skilled in the art to which the present invention pertains. Terms similar to those defined in commonly used dictionaries should be interpreted as meanings consistent with the meanings they have in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined in this application.

[0021] Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS.

[0022] FIG. 1 shows an example of a block diagram of a chiplet alignment apparatus for semiconductor packaging according to an embodiment of the present invention.

[0023] 1, an alignment apparatus 100 for semiconductor packaging according to an embodiment of the present invention may include a processor 110, a radiation source 120, a head 130, a radiation sensor 140, and an alignment unit 150. The processor 110, the radiation source 120, the head 130, the radiation sensor 140, or the alignment unit 150 may be electrically and / or operably coupled with each other by electronic components including a communication bus.

[0024] Hereinafter, "hardware operatively coupled" may include hardware in which a direct connection and / or an indirect connection between the hardware is established by wire and / or wirelessly, such that a first piece of hardware controls a second piece of hardware. Although shown as separate blocks, the embodiment is not limited thereto.

[0025] The semiconductor packaging alignment apparatus 100 according to an embodiment may include hardware for processing data based on one or more instructions. The hardware for processing data may include a processor 110.

[0026] For example, the hardware for processing data may include an arithmetic and logic unit (ALU), a floating point unit (FPU), a field programmable gate array (FPGA), a central processing unit (CPU), and / or an application processor (AP). The processor 110 may have a single-core processor structure or a multi-core processor structure, including a dual core, a quad core, a hexa core, or an octa core.

[0027] The following description may include operations performed by other hardware controlled by the processor 110. For example, the operation of the radiation source 120 irradiating radiation may include the operation of the radiation source 120 being controlled by the processor 110 to irradiate radiation. For example, the processor 110 may control at least one of the radiation source 120, the head 130, the radiation sensor 140, the alignment unit 150, or any combination thereof.

[0028] For example, the processor 110 can align multiple semiconductors arranged one above the other with respect to a reference plane by controlling at least one of the radiation source 120, the head 130, the radiation sensor 140, the alignment unit 150, or any combination thereof.

[0029] In one embodiment, the radiation source 120 can irradiate the plurality of semiconductor chips with radiation. The radiation source 120 may include a device that emits radiation from the decay of a radioactive element, or an X-ray generator that generates X-rays by colliding at least one of a substance, accelerated electrons, or any combination thereof with a target. The semiconductor packaging alignment apparatus 100 may include a shield in a direction other than the direction in which the plurality of semiconductor chips are located, so that the radiation emitted from the radiation source 120 can irradiate the plurality of semiconductor chips with radiation.

[0030] For example, the plurality of semiconductor chips may include semiconductor chips. For example, the semiconductor chips may include volatile memory including at least one of dynamic random access memory (DRAM), static random access memory (SRAM), or any combination thereof. For example, the semiconductor chips may include non-volatile memory including at least one of phase-change random access memory (PRAM), magneto-resistive random access memory (MRAM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), or any combination thereof.

[0031] For example, the alignment apparatus 100 can manufacture an artificial intelligence semiconductor by bonding chips having multiple functions to one parent chip. For example, the alignment apparatus 100 can manufacture an HBM by stacking single-layer memory semiconductors.

[0032] Each of the semiconductor chips may include a semiconductor device composed of a plurality of individual devices. The individual devices may include various microelectronic devices. For example, the individual devices may include metal-oxide-semiconductor field effect transistors (MOSFETs) including complementary metal-insulator-semiconductor transistors (CMOS transistors), system large scale integration (LSIs), image sensors including complementary metal-insulator-semiconductor (CIS) imaging sensors, micro-electro-mechanical systems (MEMS), active and / or passive devices, etc.

[0033] The plurality of semiconductor chips may include logic semiconductor chips and / or memory semiconductor chips. For example, the logic semiconductor chips may include an application processor (AP), a microprocessor, a central processing unit (CPU), a controller, a graphic processor unit (GPU), a neural processing unit (NPU), a high bandwidth memory (HBM), a field programmable gate array (FPGA), and / or an application specific integrated circuit (ASIC).

[0034] For example, the embodiments of the present disclosure may be utilized in a process of connecting an upper chip to an interposer in a chip-on-wafer-on-substrate (CoWoS) process, or connecting an interposer with an upper chip connected thereto to a main substrate. The embodiments of the present disclosure may be utilized in processes of attaching various semiconductor chips to at least one of other chips, interposers, substrates, or any combination thereof, including chip-on-chip (CoC) and / or chip-on-wafer (CoW) processes.

[0035] For example, the radiation source 120 may include an X-ray source. The X-ray may have a wavelength of 10 nanometers (nm) to 0.01 nm. Since X-rays pass through semiconductor chips with almost no error caused by the thickness of the semiconductor chips, the radiation sensor 140 can detect the radiation that has passed through the semiconductor chips. Therefore, the semiconductor packaging alignment apparatus 100 can check the alignment of semiconductor chips even in a semiconductor packaging process with nanometer-level accuracy, including micrometer-level accuracy, thereby reducing the defect rate due to alignment errors between semiconductor chips and dramatically increasing the yield.

[0036] In one embodiment, head 130 may be coupled to at least a portion of radiation source 120. For example, head 130 may be coupled to at least a portion of radiation source 120 and may cause radiation source 120 to move, rotate, or any combination thereof.

[0037] In one embodiment, the head 130 and the radiation source 120 may be disposed facing each other. For example, the head 130 may be disposed above the semiconductor to be aligned, and the radiation source 120 may be disposed below the semiconductor to be aligned. When the head 130 is disposed above and the radiation source 120 is disposed below, a radiation sensor 140 for detecting radiation from the radiation source 120 may be coupled to the head 130.

[0038] In one embodiment, the radiation sensor 140 can detect radiation transmitted through the plurality of semiconductor chips. The radiation sensor 140 can include a detector that detects radiation. For example, the radiation sensor 140 can detect radiation by detecting changes in current and / or voltage caused by collisions with particles (e.g., photons) emitted from the radiation source 120.

[0039] For example, the semiconductor chips may be arranged one above the other with respect to a reference plane. For example, the reference plane may include a ground plane. However, the embodiments of the present disclosure are not limited to the above.

[0040] For example, the radiation source 120 may be located above an upper semiconductor chip that is located at the top of the plurality of semiconductor chips.

[0041] For example, the radiation sensor 140 may be located below a lower semiconductor chip that is located at the bottom of the plurality of semiconductor chips.

[0042] For example, the radiation sensor 140 may sense a current due to the impact of particles emitted from the radiation source 120. The integral value of the current sensed by the radiation sensor 140 may be proportional to the radiation energy incident on the radiation sensor 140.

[0043] In one embodiment, the radiation sensor 140 may acquire detection information based on detecting radiation transmitted through the plurality of semiconductor chips. For example, the detection information may include at least one of a radiation count rate, a radiation energy, or any combination thereof. However, the embodiments of the present disclosure are not limited to the above.

[0044] For example, the radiation sensor 140 may detect radiation in a specific region including multiple semiconductor chips. For example, the radiation sensor 140 may detect a count rate of radiation particles incident on a sensing point in the specific region. The multiple semiconductor chips may be included in a phase region that occurs when light is irradiated perpendicularly onto the multiple semiconductor chips. For example, the radiation sensor 140 may generate visualized information (e.g., an image) based on the count rate at each point when light is irradiated perpendicularly onto the multiple semiconductor chips to generate a phase region.

[0045] For example, the radiation sensor 140 may generate visualized information using a shading effect. For example, a higher count rate of the radiation sensor 140 indicates a relatively large amount of radiation transmitted therethrough, and the corresponding area may be displayed in a brighter hue. A lower count rate indicates a relatively small amount of radiation transmitted therethrough, and the corresponding area may be displayed in a darker hue. However, the embodiments of the present disclosure are not limited to the above.

[0046] In one embodiment, the radiation sensor 140 may have a resolution in the nm range, including the um (micrometer) range.

[0047] In one embodiment, the processor 110 can control the head 130 by using the detection information obtained by the radiation sensor 140. For example, the processor 110 can align multiple semiconductor chips based on controlling the head 130 using the detection information.

[0048] The alignment apparatus 100 for semiconductor packaging according to an embodiment may further include a lower plate located below a lower semiconductor chip located at the bottom of the plurality of semiconductor chips and in contact with at least a portion of the lower semiconductor chip.

[0049] For example, the processor 110 may control the lower plate using the detection information acquired by the radiation sensor 140. For example, the processor 110 may align a plurality of semiconductor chips based on controlling the lower plate using the detection information acquired by the radiation sensor 140.

[0050] For example, each of the plurality of semiconductor chips may include at least one of an alignment mark, a through silicon via (TSV), or any combination thereof.

[0051] For example, the detection information may include position information associated with at least one of the alignment marks, the TSVs, or any combination thereof. For example, at least one of the alignment marks, the TSVs, or any combination thereof may be formed of a material having a radiation transmittance lower than a specified value.

[0052] For example, at least one of the alignment marks, the TSVs, or any combination thereof may be formed from a material with low X-ray transmittance and high X-ray absorption, including at least one of nickel, tin, or any combination thereof.

[0053] In this case, when the radiation sensor 140 detects radiation that has passed through multiple semiconductor chips, no radiation or little radiation is detected in the areas corresponding to the positions where the alignment marks and / or TSVs are formed, so that the position information of the alignment marks and TSVs of each of the multiple semiconductor chips 231, 233 can be grasped.

[0054] As a result, the alignment apparatus 100 for semiconductor chip packaging can align the positions of the alignment marks (or phases) or the positions of the TSVs (or phases) to align the multiple semiconductor chips 231, 233. For example, the alignment apparatus 100 for semiconductor packaging can align the multiple semiconductor chips by controlling the head 130.

[0055] In one embodiment, the processor 110 can control the alignment unit 150 based on position information related to at least one of the alignment marks, the TSVs, or any combination thereof. For example, the processor 110 can align multiple semiconductor chips by controlling the alignment unit 150 based on position information related to at least one of the alignment marks, the TSVs, or any combination thereof.

[0056] In one embodiment, the processor may align the alignment marks or align the TSVs based on controlling the alignment unit 150 using position information regarding at least one of the alignment marks, the TSVs, or any combination thereof. For example, the processor may align multiple semiconductor chips by aligning the alignment marks or aligning the TSVs.

[0057] The alignment apparatus 100 for semiconductor packaging according to an embodiment may further include a camera for capturing images of the plurality of semiconductor chips.

[0058] For example, the camera may include one or more optical sensors (e.g., a CCD (Charged Coupled Device) sensor, a CMOS (Complementary Metal Oxide Semiconductor) sensor) that generate electrical signals indicative of the hue and / or brightness of light. The optical sensors included in the camera may be arranged in the form of a two-dimensional array.

[0059] The camera can acquire the electrical signals of each of the multiple photosensors substantially simultaneously to generate an image or frame that includes multiple pixels arranged in a two-dimensional grid corresponding to light reaching the photosensors. For example, photographic data captured using a camera may refer to multiple images acquired from the camera.

[0060] In one embodiment, the processor 110 can control the radiation source 120 to irradiate a designated area that is set based on the positions of at least one of the alignment marks, the TSVs, or any combination thereof, acquired from the camera.

[0061] In one embodiment, the radiation source 120 can emit radiation to a designated area that is set based on the alignment marks and / or the positions of the TSVs obtained from the camera.

[0062] For example, radiation may affect semiconductor elements included in the semiconductor chip by exciting at least some of the electrons during the radiation transmission process. Because semiconductor elements are sensitive components, the semiconductor elements may be damaged when the radiation emitted from the radiation source 120 transmits through them. Therefore, the semiconductor packaging alignment apparatus 100 can prevent damage to the semiconductor chip by transmitting radiation only to a portion of the semiconductor chip where the alignment marks and / or TSVs are located, rather than the entire semiconductor chip. The designated region set based on the positions of the alignment marks and / or TSVs acquired from the camera may include the portion of the semiconductor chip where the alignment marks and / or TSVs are located.

[0063] For example, the designated area may be set differently for each of the plurality of semiconductor chips, and may be set to include the formation positions of the alignment marks and / or TSVs included in each of the plurality of semiconductor chips. The alignment marks and / or TSVs included in each of the plurality of semiconductor chips may be formed to have the same coordinates in a plane perpendicular to the direction in which radiation is irradiated.

[0064] The alignment apparatus 100 for semiconductor packaging according to an embodiment can optically align a plurality of semiconductor chips based on the positions of the plurality of semiconductor chips primarily photographed by a camera.

[0065] The semiconductor packaging alignment apparatus 100 according to an embodiment may further include a memory. For example, the memory may include a storage.

[0066] For example, the alignment apparatus 100 for semiconductor packaging may store in a memory coordinate values ​​indicating the position of each alignment mark and / or each TSV included in each of the plurality of semiconductor chips.

[0067] For example, the processor 110 of the semiconductor packaging alignment apparatus 100 can control the head 130 and / or the alignment unit 150 to align multiple semiconductor chips based on stored alignment marks and / or coordinate values ​​indicating the positions of the TSVs.

[0068] For example, the processor 110 can align the semiconductor chips based on the coordinate values ​​stored in the memory and perform fine alignment of the semiconductor chips using the radiation source 120 .

[0069] The semiconductor packaging alignment apparatus 100 according to an embodiment may further include a display. For example, the display may provide visualized information to a user. For example, the display may be controlled by at least one of the processor 110, a graphics processing unit (GPU), or any combination thereof, and may output visualized information.

[0070] The semiconductor packaging alignment apparatus 100 according to an embodiment may further include an operating unit for operating the alignment unit. For example, the operating unit may control the alignment unit 150 based on receiving an input from a user. For example, the operating unit may send a signal corresponding to the input to the processor 110 based on receiving the input from the user. The processor 110 may control the alignment unit 150 upon receiving the signal corresponding to the input.

[0071] For example, the processor 110 can output the detection information to the user via a display. For example, the processor 110 can control the alignment unit 150 based on an input received from an operation unit.

[0072] In one embodiment, processor 110 can identify a first semiconductor chip from the plurality of semiconductor chips that is coupled to at least a portion of head 130. For example, processor 110 can identify a second semiconductor chip from the plurality of semiconductor chips for coupling with the first semiconductor chip. For example, processor 110 can identify a second semiconductor chip from the plurality of semiconductor chips for coupling with the first semiconductor chip based on identifying a first semiconductor chip from the plurality of semiconductor chips that is coupled to at least a portion of head 130.

[0073] For example, the radiation source 120 can sense radiation transmitted through multiple semiconductor chips. For example, the head 130 can be coupled to one of the radiation sources or the radiation sensor.

[0074] In one embodiment, the processor 110 may control at least one of the head 130, the alignment unit 150, or any combination thereof to match a first reference mark included in the first semiconductor chip with a second reference mark included in the second semiconductor chip. For example, the first reference mark may include at least one of a first alignment mark, a first TSV, or any combination thereof. For example, the second reference mark may include at least one of a second alignment mark, a second TSV, or any combination thereof.

[0075] In one embodiment, the processor 110 may control at least one of the head 130, the alignment unit 150, or any combination thereof to match a first TSV included in a first semiconductor chip with a second TSV included in a second semiconductor chip. In another embodiment, the processor 110 may control at least one of the head 130, the alignment unit 150, or any combination thereof to match a first alignment mark included in the first semiconductor chip with a second alignment mark included in the second semiconductor chip.

[0076] In one embodiment, the processor 110 can control at least one of the head 130, the alignment unit 150, or any combination thereof to bond (or attach) the first semiconductor chip and the second semiconductor chip based on matching at least one of a first TSV, a first alignment mark, or any combination thereof included in the first semiconductor chip with at least one of a second TSV, a second alignment mark, or any combination thereof included in the second semiconductor chip.

[0077] FIG. 2 is a simplified diagram of an example of a chiplet alignment apparatus for semiconductor packaging according to an embodiment of the present invention.

[0078] Referring to FIG. 2, an alignment apparatus 200 for semiconductor packaging (eg, the alignment apparatus 100 for semiconductor packaging of FIG. 1) according to an embodiment may include a radiation source 220 and a head 230.

[0079] A processor (for example, processor 110 in FIG. 1) of the alignment apparatus 200 for semiconductor packaging according to an embodiment can align the plurality of semiconductor chips 231, 233 by controlling an alignment unit (for example, alignment unit 150 in FIG. 1).

[0080] For example, the processor may rotate the head 230 around the optical axis 225 of the radiation source 220 to align the semiconductor chips 231, 233. Although the head 230 is described as being rotated around the optical axis 225 of the radiation source 220, the embodiment is not limited thereto. For example, the processor may rotate the head 230 around the central axis of the head 230 to align the semiconductor chips 231, 233.

[0081] For example, the processor can move the head 230 in at least one direction of the x-axis, the y-axis, the z-axis, or any combination thereof. For example, the processor can align the multiple semiconductor chips 231, 233 by moving the head 230 in at least one direction of the x-axis, the y-axis, the z-axis, or any combination thereof.

[0082] For example, each of the multiple semiconductor chips 231, 233 may include alignment marks 241, 242, 251, 252.

[0083] For example, the processor can control the head 230 so that the first alignment mark 241 included in the first semiconductor chip 231 and the second alignment mark 251 included in the second semiconductor chip 233 are matched.

[0084] For example, the multiple semiconductor chips 231 and 233 may be arranged one above the other with respect to the reference plane 270. For example, the multiple semiconductor chips 231 and 233 may be arranged one above the other in parallel with the reference plane 270.

[0085] For example, the processor can align multiple semiconductor chips 231 and 233 arranged one above the other with respect to the reference surface 270 by controlling the head 230 based on the detection information obtained by the radiation source 220 .

[0086] For example, the processor can control the head 230 so that the third alignment mark 242 included in the first semiconductor chip 231 and the fourth alignment mark 252 included in the second semiconductor chip 233 are matched.

[0087] For example, the processor may rotate the head 230 in a first direction (d1). For example, the processor may rotate the head 230 in the first direction (d1) to align the first semiconductor chip 231 and the second semiconductor chip 233. For example, the first direction (d1) may include a counterclockwise rotation direction based on a reference axis perpendicular to the reference surface 270 when viewed from above. However, the embodiments of the present disclosure are not limited to those described above.

[0088] According to an embodiment, the alignment apparatus 200 for semiconductor packaging may further include a lower plate 260. For example, the alignment apparatus 200 for semiconductor packaging may align the first semiconductor chip 231 and the second semiconductor chip 233 by controlling the lower plate 260.

[0089] For example, the semiconductor packaging alignment apparatus 200 can align the first semiconductor chip 231 and the second semiconductor chip 233 by controlling the lower plate 260 based on the detection information obtained by the radiation source 220 .

[0090] 3a-3b show an example of the layout of an alignment apparatus for semiconductor chip packaging according to an embodiment of the present invention.

[0091] FIG. 4a shows an example of matching the phase of alignment marks in one embodiment of the present invention.

[0092] FIG. 4b illustrates an example of matching the phase of TSVs in accordance with one embodiment of the present invention.

[0093] 3a to 3b, an alignment apparatus for semiconductor packaging (e.g., alignment apparatus for semiconductor packaging 100 of FIG. 1 and / or alignment apparatus for semiconductor packaging 200 of FIG. 2) can align multiple semiconductor chips 311, 313, 361, and 363 in a vertically arranged state.

[0094] For example, the first semiconductor chip 311 of the multiple semiconductor chips 311, 313, 361, and 363 may be disposed closer to the radiation source 300 than the second semiconductor chip 313. For example, the second semiconductor chip 313 of the multiple semiconductor chips 311, 313, 361, and 363 may be disposed closer to the radiation sensor 330 than the first semiconductor chip 311.

[0095] For example, each of the semiconductor chips 311, 313, 361, and 363 may include at least one of alignment marks, TSVs, or any combination thereof. For example, all of the semiconductor chips 311, 313, 361, and 363 may include alignment marks, or all of the semiconductor chips 311, 313, 361, and 363 may include TSVs.

[0096] For example, the alignment marks may include marks formed in specific areas of the multiple semiconductor chips 311, 313, 361, and 363 in order to align the semiconductor chips.

[0097] For example, the TSVs may include through holes formed to electrically connect the semiconductor chips to each other when they are bonded. The TSVs may be connected to electrodes inside the semiconductor chips 311, 313, 361, and 363 through minute holes in the semiconductor chips 311, 313, 361, and 363, thereby transmitting electrical signals. At least one of the alignment marks, the TSVs, or any combination thereof may be formed by a process including an exposure process and / or a deposition process prior to a packaging process using an alignment apparatus for semiconductor chip packaging. However, the embodiments of the present disclosure are not limited to those described above.

[0098] At least one of alignment marks, TSVs, or any combination thereof may be formed at specific positions of each of the semiconductor chips 311, 313, 361, and 363 to align the semiconductor chips 311, 313, 361, and 363. For example, the alignment apparatus for semiconductor packaging may form alignment marks such that, when the positions of the alignment marks (or phases of the alignment marks) are matched, the semiconductor chips 311, 313, 361, and 363 are aligned. For example, the alignment apparatus for semiconductor packaging may form TSVs such that, when the positions of the TSVs (or phases of the TSVs) are matched, the semiconductor chips 311, 313, 361, and 363 are aligned.

[0099] 3a, the first semiconductor chip 311 may include a first alignment mark 321. The second semiconductor chip 313 may include a second alignment mark 323.

[0100] The first alignment mark 321 and the second alignment mark 323 may have a matching pattern to determine whether the position of the first alignment mark 321 and the position of the second alignment mark 323 are aligned. For example, in FIG. 4a, the first alignment mark 401 may be cross-shaped, and the second alignment mark 403 may be square-shaped. For example, the processor may determine whether the top of the first alignment mark 321 contacts the top of the second alignment mark 323, and then align the positions of the first semiconductor chip 311 and the second semiconductor chip 313 by controlling the head (e.g., head 130 of FIG. 1 and / or head 230 of FIG. 2).

[0101] For example, the first semiconductor chip 311 may include an interconnect or a TSV 321-1. For example, the second semiconductor chip 313 may include an interconnect or a TSV 323-1.

[0102] For example, the processor can align the first semiconductor chip 311 and the second semiconductor chip 313 by using the interconnect or TSV 321-1 of the first semiconductor chip 311 and the interconnect or TSV 323-1 of the second semiconductor chip 313 as reference marks.

[0103] Referring to FIG. 3b, the first semiconductor chip 361 may include a first TSV 371. The second semiconductor chip 363 may include a second TSV 373. For example, the first TSV 371 and the second TSV 373 may be formed at substantially the same position, and the first TSV 371 and the second TSV 373 may be vertically connected to align the first semiconductor chip 361 and the second semiconductor chip 363. For example, in FIG. 4b, the first TSV and the second TSV may have a cylindrical structure. For example, the cylindrical structure may be formed in a square or circular shape when viewed from the outside, and the shape is not limited thereto.

[0104] 3b, for example, the phase of the first TSV 371 and the phase of the second TSV 373 detected by the radiation sensor 370 may overlap. For example, radiation emitted from the radiation source 350 passes through the first semiconductor chip 361 and the second semiconductor chip 363, and based on the detection information obtained by the radiation sensor 370, the processor can control the head to align the first semiconductor chip 361 and the second semiconductor chip 363. Although the radiation sensor 370 is shown in FIG. 3b, this may include a lower plate including the radiation sensor 370, and the lower plate may include a detector.

[0105] For example, the alignment device may include a head 355. For example, the head 355 may be referred to as a tiplet head. For example, the head 355 may include a radiation source or a detector.

[0106] 4b, a first example 410 may include an example in which a first connection unit 411 including a first interconnect and / or a first TSV and a second connection unit 413 including a second interconnect and / or a second TSV are not aligned. A second example 420 may include an example in which the first connection unit 421 and the second connection unit 423 are aligned.

[0107] In one embodiment, the processor of the alignment device can change the state in which the first connecting portion 411 and the second connecting portion 413 are not aligned to a state in which the first connecting portion 421 and the second connecting portion 423 are aligned, and can bond the semiconductor chip in the changed state.

[0108] FIG. 5 shows an example of a flowchart for an alignment method for semiconductor packaging according to an embodiment of the present invention.

[0109] Hereinafter, it is assumed that the semiconductor packaging alignment apparatus 100 of Fig. 1 performs the process of Fig. 5. Also, in the description of Fig. 5, the operations described as being performed by the apparatus can be understood to be controlled by the processor 110 of the semiconductor packaging alignment apparatus 100.

[0110] At least one of the operations in Figure 5 may be performed by the semiconductor packaging alignment apparatus 100 of Figure 1. At least one of the operations in Figure 5 may be controlled by the processor 110 of Figure 1. Each of the operations in Figure 5 may be performed sequentially, but is not necessarily performed sequentially. For example, the order of each of the operations may be changed, and at least two of the operations may be performed in parallel.

[0111] Referring to FIG. 5, in operation S501, the alignment method for semiconductor packaging according to an embodiment may include irradiating a plurality of semiconductor chips with radiation.

[0112] For example, an alignment method for semiconductor packaging may include irradiating a plurality of semiconductor chips with radiation using a radiation source.

[0113] In operation S503, an alignment method for semiconductor packaging according to an embodiment may include detecting radiation transmitted through the plurality of semiconductor chips.

[0114] In operation S505, the alignment method for semiconductor packaging according to an embodiment may include an operation of aligning and bonding a plurality of semiconductor chips by controlling the head based on the detection information obtained by the radiation sensor.

[0115] For example, an alignment method for semiconductor packaging may include aligning a plurality of semiconductor chips by controlling a head coupled to at least a portion of a radiation source to cause rotation of the radiation source.

[0116] For example, the alignment method for semiconductor packaging may include an operation of aligning multiple semiconductor chips by controlling a head coupled to at least a portion of the radiation source to cause rotation of the radiation source, or a lower plate (e.g., a stage) on which multiple semiconductor chips are arranged.

[0117] FIG. 6 shows an example of a flowchart for an alignment method for semiconductor packaging according to an embodiment of the present invention.

[0118] Hereinafter, it is assumed that the semiconductor packaging alignment apparatus 100 of Fig. 1 performs the process of Fig. 6. Also, in the description of Fig. 6, the operations described as being performed by the apparatus can be understood to be controlled by the processor 110 of the semiconductor packaging alignment apparatus 100.

[0119] At least one of the operations in Figure 6 may be performed by the semiconductor packaging alignment apparatus 100 of Figure 1. At least one of the operations in Figure 6 may be controlled by the processor 110 of Figure 1. Each of the operations in Figure 6 may be performed sequentially, but is not necessarily performed sequentially. For example, the order of each of the operations may be changed, and at least two of the operations may be performed in parallel.

[0120] Referring to FIG. 6, an alignment method for semiconductor packaging according to one embodiment may include, in operation S601, an operation of identifying a second semiconductor chip to be coupled to the first semiconductor chip among the plurality of semiconductor chips based on identifying a first semiconductor chip coupled to at least a portion of a head among the plurality of semiconductor chips.

[0121] For example, a first semiconductor chip of the plurality of semiconductor chips coupled to at least a portion of the head may include a first reference mark. For example, the first reference mark may include at least one of a first alignment mark, a first TSV, or any combination thereof.

[0122] For example, each of the multiple semiconductor chips may include at least one of an alignment mark, a TSV, a fan-in interconnect or a fan-out interconnect, an interposer interconnect, or any combination thereof.

[0123] For example, a second semiconductor chip of the plurality of semiconductor chips may include a second reference mark, which may include at least one of a second alignment mark, a second TSV, or any combination thereof.

[0124] In operation S603, an alignment method for a semiconductor package according to one embodiment may include controlling at least one of a head, an alignment unit, or any combination thereof to match a first reference mark included in a first semiconductor chip with a second reference mark included in a second semiconductor chip.

[0125] For example, the alignment method for semiconductor packaging may include an operation of moving or rotating a head. For example, the head may be moved in a plane parallel to the surface on which the second semiconductor chip is arranged. For example, the head may be rotated about a central axis of the head. For example, the head may be rotated about a center axis of the head or moved in a plane parallel to the surface on which the second semiconductor chip is arranged, under the control of at least one of the alignment apparatus for semiconductor packaging, a processor included in the alignment apparatus for semiconductor packaging, or any combination thereof.

[0126] The head may also include a radiation source. As another example, the head may be coupled to at least a portion of the radiation source. For example, the head may include a radiation source to help generate data for determining whether the first semiconductor chip and the second semiconductor chip are matched. For example, an alignment method for semiconductor packaging may include an operation of determining whether at least one of a first alignment mark, a first TSV, or any combination thereof included in the first semiconductor chip is matched to at least one of a second alignment mark, a second TSV, or any combination thereof included in the second semiconductor chip, using a radiation source included in the head or coupled to at least a portion of the head.

[0127] For example, if the first reference mark and the second reference mark do not match, the alignment method for semiconductor packaging may include an operation of controlling the head to match the first reference mark and the second reference mark.

[0128] For example, if at least one of the first alignment mark, the first TSV, or any combination thereof does not match at least one of the second alignment mark, the second TSV, or any combination thereof, the alignment method for semiconductor packaging may include an operation of controlling the head to match at least one of the first alignment mark, the first TSV, or any combination thereof with at least one of the second alignment mark, the second TSV, or any combination thereof.

[0129] For example, an alignment method for semiconductor packaging may include an operation of matching a first alignment mark included in the first semiconductor chip with a second alignment mark included in the second semiconductor chip by moving or rotating a head to which a first semiconductor chip is bonded (or attached).

[0130] For example, an alignment method for semiconductor packaging may include an operation of matching a first TSV included in the first semiconductor chip with a second TSV included in the second semiconductor chip by moving or rotating a head to which a first semiconductor chip is bonded (or attached).

[0131] For example, the alignment method for semiconductor packages may include an operation of identifying at least one of a first alignment mark, a first TSV, or any combination thereof included in a first semiconductor chip. For example, the alignment method for semiconductor packages may include an operation of identifying at least one of a second alignment mark, a second TSV, or any combination thereof included in a second semiconductor chip.

[0132] For example, an alignment method for semiconductor packaging may include adjusting a head so that a first alignment mark and a second alignment mark are aligned.

[0133] For example, the alignment method for semiconductor packaging may include adjusting the head so that the first TSV and the second TSV are matched.

[0134] For example, adjusting the head may include rotating or moving the head relative to a central axis of the head.

[0135] As described above, an alignment method for semiconductor packaging according to one embodiment may include an operation of identifying whether at least one of a first alignment mark, a first TSV, or any combination thereof included in a first semiconductor chip matches with at least one of a second alignment mark, a second TSV, or any combination thereof included in a second semiconductor chip using a radiation source included in or coupled to the head.

[0136] The alignment method for semiconductor packaging may include, when at least one of the first alignment mark, the first TSV, or any combination thereof does not match at least one of the second alignment mark, the second TSV, or any combination thereof, controlling a head to which the first semiconductor chip is coupled to match at least one of the first alignment mark, the first TSV, or any combination thereof with at least one of the second alignment mark, the second TSV, or any combination thereof. For example, the alignment method for semiconductor packaging may include coupling the first semiconductor chip and the second semiconductor chip based on matching at least one of the first alignment mark, the first TSV, or any combination thereof with at least one of the second alignment mark, the second TSV, or any combination thereof. The alignment method for semiconductor packaging may include aligning and coupling (or attaching) the first semiconductor chip and the second semiconductor chip by performing the above-described operations.

[0137] The semiconductor packaging alignment apparatus described above may be implemented using hardware components, software components, and / or a combination of hardware and software components. For example, the apparatus and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as a processor, controller, arithmetic logic unit (ALU), digital signal processor, microcomputer, field programmable gate array (FPGA), programmable logic unit (PLU), microprocessor, or other device capable of executing instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, the processing device may be described as being a single processing element. However, those skilled in the art will recognize that the processing device may include multiple processing elements and / or multiple types of processing elements. For example, the processing device may include multiple processors or one processor and one controller. Other processing configurations are also possible, such as parallel processors.

[0138] Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure or, independently or collectively, instruct a processing device to operate as desired. The software and / or data may be embodied in some type of machine, component, physical device, computer storage medium, or device to be interpreted by or provide instructions or data to a processing device. The software may be distributed across network-coupled computer systems and stored or executed in a distributed manner. The software and data may be stored on one or more computer-readable storage media.

[0139] The method according to the embodiment may be embodied in the form of program instructions that can be executed by various computer means and recorded on a computer-readable medium. In this case, the medium may be a medium that permanently stores a computer-executable program or a medium that temporarily stores the program for execution or download. The medium may be various recording or storage means in the form of a single or multiple pieces of hardware, and is not limited to a medium directly connected to a computer system but may also be distributed over a network. Examples of media that can store program instructions include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and ROM, RAM, flash memory, etc. Other examples of media include recording or storage media managed by app stores that distribute applications, or by websites or servers that provide or distribute various software.

[0140] Although the embodiments have been described above using limited examples and drawings, those skilled in the art will appreciate that various modifications and variations may be made from the above description. For example, the described techniques may be performed in a different order than described, and / or the described system, structure, device, circuit, or other components may be combined or combined in a different manner than described, or may be substituted or replaced by other components or equivalents, while still achieving suitable results. Therefore, other implementations, other embodiments, and equivalents to the claims are also intended to be encompassed within the scope of the following claims. [Explanation of symbols]

[0141] 100 Alignment device for semiconductor packaging 110 processors 120 Radiation Source 130 head 140 Radiation Sensor 150 Alignment Section 200 Semiconductor packaging alignment device 220 Radiation Source 225 Optical axis 230 head 231 First Semiconductor Chip 233 Second Semiconductor Chip 241 First Alignment Mark 242 Third Alignment Mark 251 Second Alignment Mark 252 4th Alignment Mark 260 Lower plate 270 Reference plane 300 radiation source 311 First Semiconductor Chip 313 Second semiconductor chip 321 First Alignment Mark 321-1 TSV 323 Second Alignment Mark 323-1 TSV 330 Radiation Sensor 350 Radiation Source 355 head 361 First Semiconductor Chip 363 Second Semiconductor Chip 370 Radiation Sensor 371 1st TSV 373 2nd TSV 401 First Alignment Mark 403 Second Alignment Mark 410 First Example 411 1st connection part 413 2nd connection part 420 Second Example 421 1st connection part 423 2nd connection part

Claims

1. a radiation source for irradiating a plurality of semiconductor chips with radiation; a radiation sensor that detects the radiation that has passed through a plurality of semiconductor chips; a head coupled to one of the radiation source or the radiation sensor; an alignment unit that aligns and bonds the plurality of semiconductor chips based on the detection information acquired by the radiation sensor; a processor that controls at least one of the radiation source, the head, the radiation sensor, the alignment unit, or any combination thereof; The processor: identifying a second semiconductor chip to be coupled to the first semiconductor chip from the plurality of semiconductor chips based on identifying a first semiconductor chip coupled to at least a portion of the head; an alignment device for packaging semiconductor chips, configured to match a first reference mark included in the first semiconductor chip with a second reference mark included in the second semiconductor chip by controlling at least one of the head, the alignment unit, or any combination thereof.

2. a lower plate located below a lower semiconductor chip located at the bottom of the plurality of semiconductor chips and in contact with at least a portion of the lower semiconductor chip; The processor: The alignment apparatus for semiconductor packaging according to claim 1 , configured to align the plurality of semiconductor chips based on controlling the lower plate using the detection information.

3. Each of the plurality of semiconductor chips 10. The alignment apparatus for semiconductor packaging according to claim 1, comprising at least one of an alignment mark, a through silicon via (TSV), a fan-in interconnect or a fan-out interconnect, an interposer interconnect, or any combination thereof.

4. The detection information is position information associated with at least one of the alignment marks, the TSVs, or any combination thereof; The processor:

4. The alignment apparatus for semiconductor packaging according to claim 3, configured to align the plurality of semiconductor chips by controlling the alignment unit based on the position information.

5. The processor:

5. The semiconductor packaging alignment device of claim 4, wherein the alignment unit is controlled using the position information to align the plurality of semiconductor chips by matching the phases of the alignment marks or matching the phases of the TSVs.

6. At least one of the alignment mark, the TSV, or any combination thereof 4. The alignment device for semiconductor packaging according to claim 3, wherein the alignment device is made of a material having a radiation transmittance lower than a specified value.

7. further comprising a camera for acquiring images of the plurality of semiconductor chips; The processor:

4. The alignment apparatus for semiconductor packaging of claim 3, configured to control the radiation source to irradiate the radiation onto a designated area that is set based on the position of at least one of the alignment mark, the TSV, or any combination thereof acquired from the camera.

8. The plurality of semiconductor chips include: They are arranged vertically based on the reference plane, The radiation source is an upper semiconductor chip located at the top of the plurality of semiconductor chips; The radiation sensor comprises:

2. The alignment apparatus for semiconductor packaging according to claim 1, wherein the alignment apparatus is located below a lower semiconductor chip that is located at the bottom of the plurality of semiconductor chips.

9. The display and an operating unit for operating the alignment unit, The processor: outputting the detected information to a user through the display; The alignment apparatus for semiconductor packaging according to claim 1 , configured to control the alignment unit based on an input received from the operation unit.

10. The radiation source is 10. The semiconductor packaging alignment apparatus of claim 1, including an X-ray source.

11. The radiation sensor comprises:

2. The alignment apparatus for semiconductor packaging according to claim 1, having a resolution in the order of nm (nanometer) including um (micrometer).

12. irradiating the plurality of semiconductor chips with radiation by a processor; detecting the radiation transmitted through the plurality of semiconductor chips; and controlling the head based on the detection information obtained by the radiation sensor to align and bond the plurality of semiconductor chips, an operation of identifying a second semiconductor chip from the plurality of semiconductor chips to be coupled to the first semiconductor chip based on identification of a first semiconductor chip from the plurality of semiconductor chips coupled to at least a portion of the head in order to align the plurality of semiconductor chips; and controlling at least one of the head, the alignment unit, or a combination thereof to match a first reference mark included in the first semiconductor chip with a second reference mark included in the second semiconductor chip.

Images