Semiconductor device

Abstract

To suppress the noise at switching.SOLUTION: In a semiconductor device according to an embodiment, a first end of a first transistor on a first lead frame is connected to the first lead frame, a first end of a second transistor on a second lead frame is connected to a third lead frame, a first end and a second end of a third transistor on the third lead frame are connected to the third lead frame and a second end of the first transistor, respectively, a first end and a second end of a fourth transistor on the second lead frame are connected to the second lead frame and a second end of the second transistor, respectively, a first end and a second end of a capacitor are connected to the first and second lead frames, respectively, sealing resin seals the first to fourth transistors and the capacitor, the first and second transistors and the third and fourth transistors are GaN transistors and MOS transistors, respectively, and the first, third, second, and fourth transistors are arranged in this order.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Power semiconductors including gallium nitride (GaN) transistors are known. GaN transistors are capable of high-speed switching and are used in power conversion devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-167869 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of suppressing noise during switching is provided. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first lead frame, a second lead frame, and a third lead frame; a first transistor provided on the first lead frame and having a first end electrically connected to the first lead frame; a second transistor provided on the second lead frame and having a first end electrically connected to the third lead frame; a third transistor provided on the third lead frame and having a first end electrically connected to the third lead frame and a second end electrically connected to the second end of the first transistor; and a third transistor provided on the second lead frame and having a first end electrically connected to the second lead frame and a second end electrically connected to the second transistor. a fourth transistor having a second end electrically connected to the second end of the first transistor; a capacitor having a first end electrically connected to the first lead frame and a second end electrically connected to the second lead frame; and a sealing resin that seals the first transistor, the second transistor, the third transistor, the fourth transistor, and the capacitor, wherein the first transistor and the second transistor are GaN transistors, and the third transistor and the fourth transistor are MOS transistors, and the first transistor, the third transistor, the second transistor, and the fourth transistor are arranged in this order in a first direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of the semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a perspective view showing an example of an internal structure of the semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a plan view showing an example of a planar layout of the semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a diagram showing main paths of high-frequency components of current in the semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a diagram showing the main flow paths of the DC component of current in the semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a plan view showing an example of a planar layout of a semiconductor device according to a first modified example of the embodiment. [Figure 8] FIG. 8 is a plan view showing an example of a planar layout of a semiconductor device according to a second modification of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals.

[0008] In the following description, when a first element is "connected" to a second element, this includes the first element being indirectly connected to the second element via an intermediate element that is always or selectively conductive, or directly connected to the second element without an intermediate element.

[0009] In the following, a power semiconductor will be described as an example of a semiconductor device according to an embodiment. The power semiconductor is applied to a power conversion device such as an inverter or a converter.

[0010] First, the configuration of the semiconductor device according to the embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the configuration of the semiconductor device according to the embodiment.

[0011] The semiconductor device 1 includes a configuration in which multiple semiconductor chips are integrated into one package. As shown in FIG. 1, the semiconductor device 1 includes a switching unit 10 and a control unit 50. The switching unit 10 converts and outputs an input signal by performing switching. For example, the switching unit 10 converts an input direct current (DC) into an alternating current (AC) and outputs the converted signal. The control unit 50 controls the switching operation of the switching unit 10.

[0012] Next, the circuit configuration of the semiconductor device according to the embodiment will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing an example of the circuit configuration of the semiconductor device according to the embodiment.

[0013] 2, the switching unit 10 includes terminals P, N, and OUT, a high-side transistor HTr, a low-side transistor LTr, and a capacitor 41. The control unit 50 includes control circuits 51 and 52.

[0014] Terminals P and N are input terminals. Terminal P is connected to the positive terminal (P) of an external DC power supply. Terminal N is connected to the negative terminal (N) of an external DC power supply.

[0015] The terminal OUT is an output terminal through which the semiconductor device 1 outputs a current to an external device.

[0016] One end of the high-side transistor HTr and one end of the low-side transistor LTr are connected in series via a node N1. The other end of the high-side transistor HTr is connected to a terminal P. The other end of the low-side transistor LTr is connected to a terminal N. A terminal OUT is also connected to the node N1. As described above, the high-side transistor HTr and the low-side transistor LTr form a half-bridge circuit. The semiconductor device 1 is a package including the half-bridge circuit.

[0017] The high-side transistor HTr includes a GaN transistor 21 and MOS transistors 31 and 32. The low-side transistor LTr includes a GaN transistor 22 and MOS transistors 33 and .

[0018] The GaN transistors 21 and 22 are, for example, GaN-HEMTs (High Electron Mobility Transistors) using gallium nitride (GaN). The GaN transistors 21 and 22 have normally-on characteristics. That is, when the potential difference between the gate and source is 0 V, the drain terminal and the source terminal are electrically connected.

[0019] The MOS transistors 31, 32, 33, and 34 are, for example, silicon-based MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The MOS transistors 31, 32, 33, and 34 include P-type MOSFETs. The MOS transistors 31, 32, 33, and 34 have normally-off characteristics. That is, when the potential difference between the gate and source is 0 V, the drain terminal and the source terminal are electrically insulated. The gate threshold voltages of the MOS transistors 31 and 32 are approximately equal. The gate threshold voltages of the MOS transistors 33 and 34 are approximately equal.

[0020] The high-side transistor HTr has a configuration in which a GaN transistor 21 and MOS transistors 31 and 32 connected in parallel are connected in series via a node N2.

[0021] The drain terminal of the GaN transistor 21 is connected to the terminal P. The source terminal of the GaN transistor 21 is connected to the node N2. The gate terminal of the GaN transistor 21 is connected to the control circuit 51.

[0022] The drain terminals of the MOS transistors 31 and 32 are connected to a node N1, the source terminals of the MOS transistors 31 and 32 are connected to a node N2, and the gate terminals of the MOS transistors 31 and 32 are connected to a control circuit 51.

[0023] The low-side transistor LTr has a configuration in which a GaN transistor 22 and MOS transistors 33 and 34 connected in parallel are connected in series via a node N3.

[0024] The drain terminal of the GaN transistor 22 is connected to the node N1. The source terminal of the GaN transistor 22 is connected to the node N3. The gate terminal of the GaN transistor 22 is connected to the control circuit 52.

[0025] The drain terminals of the MOS transistors 33 and 34 are connected to the terminal N. The source terminals of the MOS transistors 33 and 34 are connected to a node N3. The gate terminals of the MOS transistors 33 and 34 are connected to the control circuit 52.

[0026] The capacitor 41 has a first end connected to the terminal P and a second end connected to the terminal N. That is, the capacitor 41 is provided in parallel with the high-side transistor HTr and the low-side transistor LTr that are connected in series.

[0027] The control circuits 51 and 52 are, for example, gate driver circuits. The control circuit 51 controls the driving of the high-side transistor HTr. The control circuit 52 controls the driving of the low-side transistor LTr. In this embodiment, the high-side transistor HTr and the low-side transistor LTr are controlled by different control circuits 51 and 52, respectively, but they may also be controlled by a common control circuit.

[0028] The control circuit 51 includes a GaN gate control terminal 51a, a MOS gate control terminal 51b, and a source control terminal 51c. The GaN gate control terminal 51a is connected to the gate terminal of the GaN transistor 21. The GaN gate control terminal 51a controls the operation of the GaN transistor 21 depending on the magnitude of the gate voltage applied thereto. The MOS gate control terminal 51b is connected to the gate terminals of the MOS transistors 31 and 32. The MOS gate control terminal 51b controls the operation of the MOS transistors 31 and 32 depending on the magnitude of the gate voltage applied thereto. The gate voltages applied to the gate terminals of the MOS transistors 31 and 32 are substantially the same in magnitude. The source control terminal 51c is connected to a node N2. The source control terminal 51c is, for example, a terminal that determines the reference potential of the voltages applied by the GaN gate control terminal 51a and the MOS gate control terminal 51b.

[0029] The control circuit 52 includes a GaN gate control terminal 52a, a MOS gate control terminal 52b, and a source control terminal 52c. The GaN gate control terminal 52a is connected to the gate terminal of the GaN transistor 22. The GaN gate control terminal 52a controls the operation of the GaN transistor 22 depending on the magnitude of the gate voltage applied thereto. The MOS gate control terminal 52b is connected to the gate terminals of the MOS transistors 33 and 34. The MOS gate control terminal 52b controls the operation of the MOS transistors 33 and 34 depending on the magnitude of the gate voltage applied thereto. The magnitudes of the gate voltages applied to the gate terminals of the MOS transistors 33 and 34 are approximately the same. The source control terminal 52c is connected to a node N3. The source control terminal 52c is, for example, a terminal that determines the reference potential of the voltages applied by the GaN gate control terminal 52a and the MOS gate control terminal 52b.

[0030] Next, the internal structure of the switching section in the semiconductor device according to the embodiment will be described with reference to FIGS.

[0031] Fig. 3 is a perspective view showing an example of the internal structure of the semiconductor device according to the embodiment. Fig. 4 is a plan view showing an example of the planar layout of the semiconductor device according to the embodiment. Note that the control unit 50 is omitted in Figs. 3 and 4.

[0032] As shown in FIGS. 3 and 4, the semiconductor device 1 further includes lead frames 11, 12, and 13, wirings 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, and 74, and electrodes 81, 82, and 83.

[0033] The lead frames 11, 12, and 13 are flat conductors and are arranged in approximately the same plane. Each of the lead frames 11 and 12 has a substantially L-shape. Specifically, the lead frame 11 includes a first portion 11-1 and a second portion 11-2 that extend in directions that are approximately perpendicular to each other. The lead frame 12 includes a third portion 12-1 and a fourth portion 12-2 that extend in directions that are approximately perpendicular to each other. The lead frames 11 and 12 are arranged to form a substantially U-shape. Specifically, the end portions of the second portion 11-2 and the fourth portion 12-2 of the lead frames 11 and 12 face each other and are spaced apart from each other. The lead frame 13 has a substantially rectangular shape. The lead frame 13 is arranged between the first portion 11-1 and the third portion 12-1 and is spaced apart from each other.

[0034] Hereinafter, the plane on which the lead frames 11, 12, and 13 are arranged is referred to as the XY plane. The direction in which the first portion 11-1 and the third portion 12-1 extend is referred to as the X direction. The direction in which the second portion 11-2 and the fourth portion 12-2 extend is referred to as the Y direction. The direction that intersects the XY plane and in which the GaN transistors 21 and 22, the MOS transistors 31, 32, 33, and 34, and the capacitor 41 are provided as viewed from the lead frames 11, 12, and 13 is referred to as the Z direction or upward direction. The direction opposite to the Z direction is referred to as the downward direction.

[0035] The capacitor 41 is, for example, a chip-type MLCC (Multi-Layer Ceramic Capacitor). The capacitor 41 is provided so as to straddle the second portion 11-2 and the fourth portion 12-2 in the Y direction. A first end of the capacitor 41 is connected to the upper surface of the second portion 11-2. A second end of the capacitor 41 is connected to the upper surface of the fourth portion 12-2. Note that, although two capacitors 41 are provided in the examples of FIGS. 3 and 4, one or more capacitors 41 may be provided.

[0036] The GaN transistor 21 has, for example, a rectangular shape. The GaN transistor 21 is provided on the upper surface of the first portion 11-1 with its longitudinal direction aligned with the X direction. The GaN transistor 21 includes, for example, a drain terminal, a source terminal, and a gate terminal on its upper surface. The source terminal of the GaN transistor 21 is provided, for example, on the upper surface of the GaN transistor 21, extending along the long side on the lead frame 13 side. The drain terminal of the GaN transistor 21 is provided, for example, on the upper surface of the GaN transistor 21, extending along the long side opposite to the source terminal.

[0037] The GaN transistor 22 has, for example, a rectangular shape. The GaN transistor 22 is provided on the upper surface of the third portion 12-1 with its longitudinal direction aligned with the X direction. The GaN transistor 22 includes, for example, a drain terminal, a source terminal, and a gate terminal on its upper surface. The drain terminal of the GaN transistor 22 is provided, for example, on the upper surface of the GaN transistor 22, extending along the long side facing the lead frame 13. The source terminal of the GaN transistor 22 is provided, for example, on the upper surface of the GaN transistor 22, extending along the long side opposite the drain terminal. The GaN transistors 21 and 22 are arranged, for example, such that the centers of their drain terminals in the X direction are aligned on the same straight line in the Y direction.

[0038] The MOS transistor 31 has, for example, a rectangular shape. For example, the longitudinal length of the MOS transistor 31 is shorter than the longitudinal lengths of the GaN transistors 21 and 22. The MOS transistor 31 is provided on the upper surface of the lead frame 13 so that its longitudinal direction is along the X direction and it is sandwiched in the Y direction between the GaN transistors 21 and 22. For example, the MOS transistor 31 has a drain terminal on its lower surface and a source terminal and a gate terminal on its upper surface. The drain terminal of the MOS transistor 31 is connected to the lead frame 13.

[0039] The MOS transistor 32 has, for example, a rectangular shape. For example, the longitudinal length of the MOS transistor 32 is approximately equal to the lateral length of the MOS transistor 31. The MOS transistor 32 is provided on the upper surface of the lead frame 13 so that its longitudinal direction is along the Y direction, it is sandwiched in the Y direction by the GaN transistors 21 and 22, and is sandwiched in the X direction by the MOS transistor 31 and the capacitor 41. For example, the MOS transistor 32 has a drain terminal on its lower surface and a source terminal and a gate terminal on its upper surface. The drain terminal of the MOS transistor 32 is connected to the lead frame 13.

[0040] The MOS transistor 33 has, for example, a rectangular shape. For example, the longitudinal length of the MOS transistor 33 is shorter than the longitudinal lengths of the GaN transistors 21 and 22. The MOS transistor 33 is provided on the upper surface of the third portion 12-1 so as to sandwich the GaN transistor 22 together with the MOS transistor 31 in the Y direction. That is, the GaN transistor 21, the MOS transistor 31, the GaN transistor 22, and the MOS transistor 32 are aligned in this order in a straight line in the Y direction. The MOS transistor 33 has, for example, a drain terminal on the lower surface and a source terminal and a gate terminal on the upper surface. The drain terminal of the MOS transistor 33 is connected to the third portion 12-1.

[0041] The MOS transistor 34 has, for example, a rectangular shape. For example, the longitudinal length of the MOS transistor 34 is approximately equal to the lateral length of the MOS transistor 33. The MOS transistor 34 is provided on the upper surface of the fourth portion 12-2 so that its longitudinal direction is along the Y direction, aligned with the GaN transistor 22 in the X direction, and aligned with the capacitor 41 in the Y direction. The MOS transistor 34 has, for example, a drain terminal on its lower surface and a source terminal and a gate terminal on its upper surface. The drain terminal of the MOS transistor 34 is connected to the fourth portion 12-2.

[0042] The wiring 61 includes, for example, a plurality of bonding wires. Each of the plurality of bonding wires included in the wiring 61 extends in the Y direction so that one end contacts the first portion 11-1 and the other end contacts the drain end of the GaN transistor 21, connecting the two. The other end of the plurality of bonding wires included in the wiring 61 is provided near the center of the drain end of the GaN transistor 21 so as not to be biased in the X direction.

[0043] The wiring 62 includes, for example, a plurality of bonding wires. Each of the plurality of bonding wires included in the wiring 62 extends in the Y direction so that one end contacts the source end of the GaN transistor 21 and the other end contacts the source end of the MOS transistor 31, connecting the two. One end of each of the plurality of bonding wires included in the wiring 62 is provided near the center of the source end of the GaN transistor 21, with as little deviation in the X direction as possible.

[0044] The wiring 63 includes, for example, a bonding wire. The wiring 63 extends in the Y direction so that one end contacts the source terminal of the GaN transistor 21 and the other end contacts the source terminal of the MOS transistor 32, connecting them together.

[0045] The wiring 64 includes, for example, a bonding wire. One end of the wiring 64 contacts the gate terminal of the GaN transistor 21, and the other end contacts the GaN gate control terminal 51a of the control circuit 51, connecting the two.

[0046] The wiring 65 includes, for example, a plurality of bonding wires. One end of each of the plurality of bonding wires included in the wiring 65 contacts the source terminal of the GaN transistor 21 and the other end contacts the source control terminal 51c of the control circuit 51, connecting the two. Note that one end of each of the plurality of bonding wires included in the wiring 65 may contact the source terminal of the MOS transistor 31 instead of the source terminal of the GaN transistor 21.

[0047] The wiring 66 is, for example, a bonding wire. One end of the wiring 66 contacts the gate terminal of the MOS transistor 31, and the other end contacts the MOS gate control terminal 51b of the control circuit 51, connecting the two.

[0048] The wiring 67 includes, for example, a bonding wire. One end of the wiring 67 contacts the gate end of the MOS transistor 32, and the other end contacts the MOS gate control terminal 51b of the control circuit 51, connecting the two. The other end of the wiring 67 may contact the gate end of the MOS transistor 31 instead of the MOS gate control terminal 51b of the control circuit 51.

[0049] The wiring 68 includes, for example, a plurality of bonding wires. Each of the plurality of bonding wires included in the wiring 68 extends in the Y direction so that one end contacts the lead frame 13 and the other end contacts the drain end of the GaN transistor 22, connecting the two. For example, one of the plurality of bonding wires included in the wiring 68 is provided so as to be sandwiched between the GaN transistor 22 and the MOS transistor 32 in the Y direction. The other ends of the plurality of bonding wires included in the wiring 68, except for one bonding wire that is provided so as to be sandwiched between the GaN transistor 22 and the MOS transistor 32 in the Y direction, are provided near the center of the drain end of the GaN transistor 22 so as not to be biased in the X direction as much as possible.

[0050] The wiring 69 includes, for example, a plurality of bonding wires. Each of the plurality of bonding wires included in the wiring 69 extends in the Y direction so that one end contacts the source end of the GaN transistor 22 and the other end contacts the source end of the MOS transistor 33, connecting the two. One end of each of the plurality of bonding wires included in the wiring 69 is provided near the center of the source end of the GaN transistor 22, with as little deviation in the X direction as possible.

[0051] The wiring 70 is, for example, a bonding wire. The wiring 70 extends in the X direction so that one end contacts the source terminal of the GaN transistor 22 and the other end contacts the source terminal of the MOS transistor 34, connecting them together.

[0052] The wiring 71 includes, for example, a bonding wire. One end of the wiring 71 contacts the gate terminal of the GaN transistor 22, and the other end contacts the GaN gate control terminal 52a of the control circuit 52, connecting the two.

[0053] The wiring 72 includes, for example, a plurality of bonding wires. One end of each of the plurality of bonding wires included in the wiring 72 contacts the source terminal of the MOS transistor 33 and the other end contacts the source control terminal 52c of the control circuit 52, connecting the two. Note that one end of each of the plurality of bonding wires included in the wiring 72 may contact the source terminal of the GaN transistor 22 instead of the source terminal of the MOS transistor 33.

[0054] The wiring 73 includes, for example, a bonding wire. One end of the wiring 73 contacts the gate terminal of the MOS transistor 33, and the other end contacts the MOS gate control terminal 52b of the control circuit 52, connecting the two.

[0055] The wiring 74 includes, for example, a bonding wire. One end of the wiring 74 contacts the gate end of the MOS transistor 34, and the other end contacts the MOS gate control terminal 52b of the control circuit 52, connecting the two. The other end of the wiring 74 may contact the gate end of the MOS transistor 33 instead of the MOS gate control terminal 52b of the control circuit 52.

[0056] It is desirable that each of the wirings 61, 62, 63, 68, 69, and 70 be provided so as to have a substantially shortest distance from the viewpoint of suppressing ringing, which will be described later.

[0057] The electrodes 81, 82, and 83 are flat conductors provided on the lower surface of the semiconductor device 1. The electrodes 81, 82, and 83 function as terminals that electrically connect devices external to the semiconductor device 1 with the internal circuit configuration.

[0058] The electrode 81 is provided on and in contact with the lower surface of the lead frame 11. The electrode 81 is connected to the positive electrode of an external DC power supply.

[0059] The electrode 82 is provided on and in contact with the lower surface of the lead frame 12. The electrode 82 is connected to the negative pole of an external DC power supply. That is, the electrode 82 functions as a terminal N.

[0060] The electrode 83 is provided on and in contact with the lower surface of the lead frame 13. The electrode 83 functions as an output terminal, and a current is output from the semiconductor device 1 to an external device via the electrode 83. In other words, the electrode 83 has the function of a terminal OUT.

[0061] The semiconductor device 1 has a housing structure sealed with a sealing resin (not shown). The sealing resin seals the switching unit 10 and the control unit 50 and insulates unconnected conductors within the semiconductor device 1. The sealing resin also protects the components of the semiconductor device 1 from physical disturbances.

[0062] With the configuration according to the embodiment, the half-bridge circuit and the capacitor 41 can be integrated into one package. As a result, the path of the current flowing in a ring shape through the half-bridge circuit and the capacitor 41 during switching can be shortened. This makes it possible to suppress noise caused by ringing during switching. This will be described in detail below.

[0063] Power semiconductors using GaN transistors are characterized by their high-speed switching capability compared to transistors using silicon (Si). This increases the switching frequency and eliminates the need for inductors for inductance compensation, enabling smaller packages and higher efficiency.

[0064] However, because of their fast switching speeds, ringing is likely to occur during switching. This ringing can become a noise source and can be superimposed on the output signal. Noise is undesirable because it degrades the quality of the transmitted signal, increases the possibility of unintended signals being output, and increases the possibility of damage to surrounding components.

[0065] In a power semiconductor using a GaN transistor and a MOS transistor, when the GaN transistor switches, the high-frequency component of the current is supplied from the high-voltage terminal of the capacitor to charge the output capacitance of the GaN transistor. The high-frequency component of the current passes through the GaN transistor and the MOS transistor and flows through a path that returns to the low-voltage terminal of the capacitor. If the inductance in the path through which this high-frequency component of the current flows (hereinafter referred to as loop inductance) is large, ringing occurs due to the high-speed switching of the GaN transistor, and noise is superimposed on the output signal.

[0066] One way to suppress noise is to reduce loop inductance. Reducing loop inductance can suppress ringing and therefore noise generation. It is known that inductance increases in proportion to the length of the current path, so loop inductance can be reduced by shortening the path through which the high-frequency components of the current flow.

[0067] On the other hand, simply shortening the distance between each transistor and capacitor can cause uneven flow paths for the DC component of the current flowing through the GaN transistor, potentially resulting in areas where the current concentrates, causing localized heat generation and potentially reducing the reliability of the chip and wires.

[0068] In the configuration according to the embodiment, the half-bridge circuit and the capacitor 41 are integrated into one package. This configuration eliminates the need for terminals and wiring for connecting the individual packages, and reduces the current path accordingly, thereby reducing loop inductance and suppressing noise generation.

[0069] Furthermore, in the configuration of the embodiment, two MOS transistors are connected in parallel to each GaN transistor. This configuration allows the main flow paths of the high-frequency component and the DC component of the current to be separated. This will be explained using Figures 5 and 6.

[0070] Fig. 5 is a diagram showing the main flow paths of high-frequency components of current in a semiconductor device according to an embodiment. Fig. 6 is a diagram showing the main flow paths of DC components of current in a semiconductor device according to an embodiment. In Figs. 5 and 6, the main flow paths of each current are indicated by arrows on the planar layout of the semiconductor device shown in Fig. 4.

[0071] High-frequency components of current flow through a path that minimizes loop inductance. In other words, the path of the high-frequency components of current is the loop that provides the shortest path. Therefore, as shown in FIG. 5, the high-frequency components of current mainly flow from the first end of capacitor 41 through lead frame 11, wiring 61, GaN transistor 21, wiring 63, MOS transistor 32, lead frame 13, wiring 68, GaN transistor 22, wiring 70, MOS transistor 34, and lead frame 12 in this order, to the second end of capacitor 41. Note that if wiring 61 and 68 include multiple bonding wires, the current will pass through the bonding wire with the shortest path, i.e., the bonding wire located closest to capacitor 41.

[0072] On the other hand, as shown in Figure 6, the DC component of the current mainly flows from electrode 81 in contact with the underside of lead frame 11, through lead frame 11, wiring 61, GaN transistor 21, wiring 62, MOS transistor 31, lead frame 13, wiring 68, GaN transistor 22, wiring 69, MOS transistor 33, and lead frame 12 in this order, to electrode 82 in contact with the underside of lead frame 12.

[0073] By separating the main paths of the high-frequency and DC components of the current, the path of the high-frequency component of the current can be shortened. This reduces loop inductance and enables noise suppression. Furthermore, in the path of the DC component of the current, the GaN transistors 21 and 22 and the MOS transistors 31 and 33 are aligned in a straight line, and the wiring connecting each transistor is arranged near the center of the drain or source end without biasing in the X direction. This allows current to flow approximately uniformly through the GaN transistors 21 and 22 and the MOS transistors 31 and 33, preventing reliability degradation due to current concentration.

[0074] The semiconductor device according to the embodiment described above can be modified in various ways.

[0075] 7 is a plan view showing an example of a planar layout of a semiconductor device according to a first modified example of the embodiment, in which the control unit 50 and the sealing resin are omitted.

[0076] 7 does not include the MOS transistor 32 and the wirings 63 and 67. It includes a MOS transistor 31A instead of the MOS transistor 31. The MOS transistor 31A has a structure that is longer in the longitudinal direction than the MOS transistor 31. The arrangement and connection relationship of the MOS transistor 31A are the same as the arrangement and connection relationship of the MOS transistor 31 in the embodiment.

[0077] The MOS transistor 31A extends in the X direction to the region where the MOS transistor 32 was disposed in the embodiment. Therefore, the MOS transistor 31A complements the effect of the MOS transistor 32, which serves as a path for the high-frequency component of the current in the embodiment. That is, the high-frequency component of the current mainly flows from the first end of the capacitor 41 through the lead frame 11, the wiring 61, the GaN transistor 21, the wiring 62, the MOS transistor 31A, the lead frame 13, the wiring 68, the GaN transistor 22, the wiring 70, the MOS transistor 34, and the lead frame 12, in this order, to the second end of the capacitor 41. When the wirings 61, 62, and 68 include multiple bonding wires, the current passes through the bonding wire with the shortest path, i.e., the bonding wire closest to the capacitor 41.

[0078] The configuration according to the first modification, like the embodiment, can shorten the path of the high-frequency component of the current, thereby reducing the loop inductance and suppressing noise.

[0079] 8 is a plan view showing an example of a planar layout of a semiconductor device according to a second modified example of the embodiment, in which the control unit 50 and the sealing resin are omitted.

[0080] 8, among the multiple bonding wires included in the wiring 61, wiring 61B is included instead of the bonding wire provided at a position closest to the capacitor 41. Wiring 61B includes, for example, a bonding wire. One end of wiring 61B is in contact with second portion 11-2 and the other end is in contact with the drain end of GaN transistor 21, and wiring 61B extends from the drain end of GaN transistor 21 toward capacitor 41.

[0081] The wiring 61B mainly serves as a flow path for the high frequency components of the current output from the first terminal of the capacitor 41 to be input to the drain terminal of the GaN transistor 21.

[0082] The configuration according to the second modification makes it possible to shorten the path of the high-frequency component of the current, thereby reducing the loop inductance and suppressing noise.

[0083] In addition to the above-described modifications, various other modifications are possible. For example, some or all of the bonding wires included in the wirings 61 to 74 may be replaced with clip connectors.

[0084] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0085] 1...Semiconductor device 10...Switching section 11, 12, 13...Lead frame 11-1…First part 11-2…Second part 12-1...Third part 12-2…4th part 21, 22...GaN transistors 31, 31A, 32, 33, 34...MOS transistors 41...Capacitor 50...Control unit 51, 52...Control circuit 51a, 52a...GaN gate control terminals 51b, 52b...MOS gate control terminals 51c, 52c...Source control terminals 61, 61B, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74...Wiring 81, 82, 83...electrode P, N, OUT…terminal

Claims

1. a first lead frame, a second lead frame, and a third lead frame; a first transistor disposed on the first lead frame and having a first end electrically connected to the first lead frame; a second transistor disposed on the second lead frame and having a first end electrically connected to the third lead frame; a third transistor disposed on the third lead frame, the third transistor having a first end electrically connected to the third lead frame and a second end electrically connected to the second end of the first transistor; a fourth transistor disposed on the second lead frame, the fourth transistor having a first end electrically connected to the second lead frame and a second end electrically connected to the second end of the second transistor; a capacitor having a first end electrically connected to the first lead frame and a second end electrically connected to the second lead frame; a sealing resin that seals the first transistor, the second transistor, the third transistor, the fourth transistor, and the capacitor; Equipped with the first transistor and the second transistor are GaN transistors, the first transistor, the third transistor, the second transistor, and the fourth transistor are arranged in this order in a first direction; Semiconductor device.

2. a fifth transistor provided on the second lead frame, the fifth transistor having a first end electrically connected to the second lead frame, a second end electrically connected to the second end of the second transistor, and a gate end electrically connected to a gate end of the fourth transistor; the capacitor is provided on the first lead frame and the second lead frame so as to be aligned with the third transistor in a second direction intersecting the first direction; the fifth transistor is arranged closer to the capacitor than the second transistor is, and is aligned in the second direction; The semiconductor device according to claim 1.

3. a sixth transistor provided on the third lead frame, the sixth transistor having a first end electrically connected to the third lead frame, a second end electrically connected to the second end of the first transistor, and a gate end electrically connected to a gate end of the third transistor; the sixth transistor is provided so as to be sandwiched between the third transistor and the capacitor in the second direction; 3. The semiconductor device according to claim 2.

4. the first transistor and the second transistor are GaN-HEMTs, the first transistor and the second transistor have normally-on characteristics. The semiconductor device according to claim 1.

5. the third transistor and the fourth transistor are MOSFETs, the third transistor and the fourth transistor have normally-off characteristics. The semiconductor device according to claim 1.

6. the fifth transistor is a MOSFET, the fifth transistor has a normally-off characteristic.

3. The semiconductor device according to claim 2.

7. a threshold voltage of the fifth transistor is substantially the same as a threshold voltage of the fourth transistor; 3. The semiconductor device according to claim 2.

8. the sixth transistor is a MOSFET, the sixth transistor has a normally-off characteristic.

4. The semiconductor device according to claim 3.

9. a threshold voltage of the sixth transistor is substantially the same as a threshold voltage of the third transistor; 4. The semiconductor device according to claim 3.

10. the first lead frame and the first terminal of the first transistor are connected via a plurality of bonding wires; the plurality of bonding wires include a first wire and a second wire extending in a direction different from that of the first wire; the second wire connects the first terminal of the first transistor and the first terminal of the capacitor over a shorter distance than the first wire; The semiconductor device according to claim 1 .

11. further including a control circuit that controls driving of the first transistor, the second transistor, the third transistor, and the fourth transistor; the control circuit is sealed with the sealing resin; The semiconductor device according to claim 1 .

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