Semiconductor device

Abstract

To improve the characteristics of a semiconductor device.SOLUTION: A semiconductor device of an embodiment includes: a first conductive layer 90 provided on a substrate 9; a second conductive layer 92 supplied with a first voltage and provided on the substrate 9; a third conductive layer 91 corresponding to an output node and provided on the substrate 9 between the first conductive layer 90 and the second conductive layer 92; a first switching device 1A including a first terminal 11A supplied with a second voltage higher than the first voltage and a second terminal 12A connected to the third conductive layer 91, and provided above the first conductive layer 90; and a second switching device 1B including a third terminal 11B connected to the third conductive layer 91 and a fourth terminal 12B connected to the second conductive layer 92, and provided above the second conductive layer 92.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] 2. Description of the Related Art Power devices using semiconductor elements are used in various electrical appliances. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6520871 Specification [Patent Document 2] Patent No. 7200825 specification [Patent Document 3] Patent No. 5447453 specification Summary of the Invention [Problem to be solved by the invention]

[0004] Improve the characteristics of semiconductor devices. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a first conductive layer provided on a substrate, a second conductive layer provided on the substrate and supplied with a first voltage, a third conductive layer corresponding to an output node and provided on the substrate between the first conductive layer and the second conductive layer, a first switching device provided above the first conductive layer and including a first terminal supplied with a second voltage higher than the first voltage and a second terminal connected to the third conductive layer, and a second switching device provided above the second conductive layer and including a third terminal connected to the third conductive layer and a fourth terminal connected to the second conductive layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram showing an example of a circuit configuration of an apparatus including a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view showing an example of the structure of a semiconductor device according to a first embodiment. [Figure 3] FIG. 1 is a plan view showing an example of the structure of a semiconductor device according to a first embodiment. [Figure 4] FIG. 1 is a plan view showing an example of the structure of a semiconductor device according to a first embodiment. [Figure 5] FIG. 1 is a plan view showing an example of the structure of a semiconductor device according to a first embodiment. [Figure 6] FIG. 10 is a cross-sectional view showing an example of the structure of a semiconductor device according to a second embodiment. [Figure 7] FIG. 10 is a plan view showing an example of the structure of a semiconductor device according to a second embodiment. [Figure 8] FIG. 10 is a circuit diagram showing an example of a circuit configuration of an apparatus including a semiconductor device according to a third embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing an example of the structure of a semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is a plan view showing an example of the structure of a semiconductor device according to a third embodiment. [Figure 11] FIG. 10 is a plan view showing an example of the structure of a semiconductor device according to a third embodiment. [Figure 12] FIG. 10 is a plan view showing an example of the structure of a semiconductor device according to a third embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing an example of the structure of a semiconductor device according to a fourth embodiment. [Figure 14] FIG. 10 is a plan view showing an example of the structure of a semiconductor device according to a fourth embodiment. [Figure 15] FIG. 10 is a plan view showing an example of the structure of a semiconductor device according to a fifth embodiment. [Figure 16] FIG. 13 is a plan view showing an example of the structure of a semiconductor device according to a sixth embodiment. [Figure 17] FIG. 10 is a cross-sectional view showing an example of the structure of a modified example of the semiconductor device of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] 1 to 17, semiconductor devices according to embodiments will be described. In the following description, elements having the same function and configuration will be given the same reference numerals. Furthermore, in the following embodiments, when components (e.g., circuits, wiring, various voltages and signals, etc.) that are given reference numerals with distinguishing numbers / letters at the end are not necessarily distinguished from one another, the reference numerals will be omitted.

[0008] (Embodiment) (1) First embodiment A semiconductor device according to a first embodiment will be described with reference to FIGS.

[0009] (a) Circuit example FIG. 1 is a circuit diagram showing an example of the circuit configuration of an electrical device including a semiconductor device according to this embodiment.

[0010] The electric device 900 in FIG. 1 is, for example, a half-bridge converter.

[0011] The half-bridge converter 900 includes the semiconductor device 100 of this embodiment, capacitors 30A and 30B, a transformer 31, diodes 32A and 32B, a coil 33, and a capacitor .

[0012] The semiconductor device 100 of this embodiment includes a first node NdVDC+, a second node NdVDC-, and a third node NdVSW. The first node NdVDC+ is electrically connected to a power supply node Vin on the high potential side (high side) of the input of the half-bridge converter 900. The second node NdVDC- is electrically connected to a power supply node GNDP on the low potential side (low side) of the input of the half-bridge converter 900. The third node NdVSW is a switching node (output node) of the semiconductor device 100. A positive power supply voltage (hereinafter also referred to as voltage Vin) is applied to the power supply node Vin. The voltage applied to the power supply node Vin is, for example, a DC voltage. A ground voltage is applied to the power supply node GNDP. Hereinafter, the power supply node GNDP will also be referred to as ground node GNDP.

[0013] The first node NdVDC+ is a node (voltage node) to which a voltage (e.g., a power supply voltage) on the high potential side of the semiconductor device 100 is applied. The second node NdVDC− is a node to which a voltage (ground voltage) on the low potential side of the semiconductor device 100 is applied. The voltage applied to the second node NdVDC− is lower than the voltage applied to the first node NdVDC+.

[0014] The internal configuration of the semiconductor device 100 will be described in detail later.

[0015] One terminal of the capacitor 30A is electrically connected to the power supply node Vin, and the other terminal of the capacitor 30A is electrically connected to the node Nd1.

[0016] One terminal of the capacitor 30B is electrically connected to the node Nd1, and the other terminal of the capacitor 30B is electrically connected to the ground node GNDP.

[0017] The transformer 31 includes a first coil 311, a second coil 312, and a third coil 313. The first coil 311 is a coil on the primary side of the transformer 30. The second and third coils 312, 313 are coils on the secondary side of the transformer 30. One terminal of the first coil 311 is electrically connected to a switching node NdVSW. The other terminal of the first coil 311 is electrically connected to a node Nd1. One terminal of the second coil 312 is electrically connected to one terminal of a first diode 32A. The other terminal of the second coil 312 is electrically connected to a node Nd2. One terminal of the third coil 313 is electrically connected to a node Nd2. The other terminal of the third coil 313 is electrically connected to one terminal of a second diode 32B. For example, the node Nd2 is an internal node on the secondary side of the transformer 30.

[0018] One terminal (for example, the cathode) of the diode 32A is electrically connected to one terminal of the second coil 312. The other terminal (for example, the anode) of the diode 32A is electrically connected to the node Nd3.

[0019] One terminal (for example, the cathode) of the diode 32B is electrically connected to the other terminal of the third coil 313. The other terminal (for example, the anode) of the diode 32B is electrically connected to the node Nd3.

[0020] One terminal of the coil 33 is electrically connected to the node Nd2, and the other terminal of the coil 33 is electrically connected to the node Nd4.

[0021] One terminal of the capacitor 34 is connected to the node Nd4. The other terminal of the capacitor 34 is electrically connected to the node Nd3. The voltage of the capacitor 34 is output to the outside of the half-bridge converter 900 as the output of the converter 900. The output voltage of the half-bridge converter 900 is a DC voltage.

[0022] The node Nd4 is electrically connected to a high-potential power supply node Vout on the output side of the half-bridge converter 900. The node Nd3 is electrically connected to a low-potential power supply node GNDO on the output side of the half-bridge converter 900. The low-potential power supply node GNDO to which the ground voltage is applied is also called a ground node GNDO.

[0023] In the half-bridge converter 900, the semiconductor device 100 of this embodiment is a power module with a totem-pole configuration. More specifically, the semiconductor device 100 of this embodiment is a switching power supply module.

[0024] The power module 100 includes two switching devices 1 (1A, 1B), two transistors (switching devices) 2 (2A, 2B), a plurality of drivers 4 (4A, 4B, 4C, 4D), and a capacitor 7.

[0025] A plurality of switching devices 1 and a plurality of transistors 2 are electrically connected so that the current path of the switching device 1 is connected in series with the current path of the transistor 2. The switching device 1 and the transistor 2 have the function of opening and closing the current path between the power supply node Vin and the ground node GNDP. In the current path between the power supply node Vin and the ground node GNDP, the high-side switching device 1A and the transistor 2A have the function of setting the direction of current flow in the current path by a rectification function. For example, the transistor 2 realizes safe operation of the power module 100 in a transient state of the power supply.

[0026] One terminal of the high-side switching device 1A is electrically connected to the node NdVDC+. The other terminal of the switching device 1A is electrically connected to one terminal of the transistor 2A. The other terminal of the transistor 2A is electrically connected to the node NdVSW. Hereinafter, the high side of the power module 100 will also be referred to as the VDC+ side.

[0027] One terminal of the low-side switching device 1B is electrically connected to the node NdVSW. The other terminal of the switching device 1B is electrically connected to one terminal of the transistor 2B. The other terminal of the transistor 2B is electrically connected to the node NdVDC-. Hereinafter, the low side of the power module 100 will also be referred to as the VDC- side.

[0028] When the switching device 1 is an N-channel switching device, one terminal of the switching device 1 is, for example, a drain of the transistor, and the other terminal of the switching device 1 is, for example, a source of the transistor. When the transistor 2 is a P-channel transistor, one terminal of the transistor 2 is, for example, a source of the transistor, and the other terminal of the transistor 2 is, for example, a drain of the transistor.

[0029] The switching device 1 is a semiconductor element using gallium nitride (GaN) (hereinafter also referred to as a GaN device). An example of the switching device 1 is a transistor using GaN (hereinafter also referred to as a GaN transistor). The GaN transistor is, for example, a normally-on transistor (e.g., a high electron mobility transistor (HEMT)). The switching device 1 may be a field effect transistor using silicon (Si) or silicon carbide (SiC), or may be an insulated gate bipolar transistor (IGBT).

[0030] The transistor 2 is, for example, a normally-off P-channel field effect transistor. The transistor 2 is a MOS (Metal-Oxide-Semiconductor) transistor using Si or SiC. The transistor 2 may also be an IGBT.

[0031] The combination of the normally-on switching device 1 and the normally-off transistor 2 forms a quasi-normally-off switching device.

[0032] The quasi-normally-off switching device may be formed from a normally-on P-channel switching device 1 and a normally-off N-channel field effect transistor 2.

[0033] The drivers 4A and 4B are gate drivers. The gate driver 4A is electrically connected to the gate of the switching device 1A. The gate driver 4B is electrically connected to the gate of the switching device 1B. Each of the gate drivers 4A and 4B controls the gate voltage of the corresponding switching device 1A or 1B. This controls the operation (on and off) of the switching device 1.

[0034] The drivers 4C and 4D are drive circuits that drive the transistors 2A and 2B to realize quasi-normally-off switching devices. For example, the drivers 4C and 4D are called QN-off (Quasi Normally-off) drivers. The QN-off driver 4C is electrically connected to the gate of the transistor 2A. The QN-off driver 4D is electrically connected to the gate of the transistor 2B. The QN-off drivers 4C and 4D set the corresponding transistors 2A and 2B to an on state or an off state depending on the operation of the power module 100 (or the operation of the half-bridge converter 900). This controls the operation (on and off) of the corresponding transistors 2A and 2B. The drivers 4C and 4D may be UVLO (Under Voltage Lock Out) drivers.

[0035] The capacitor 7 is connected between the node NdVDC+ and the node NdVDC-. One terminal of the capacitor 7 is electrically connected to the node NdVDC+. The other terminal of the capacitor 7 is electrically connected to the node NdVDC-. The capacitor 7 is connected in parallel to the current path formed by the switching device 1 and the transistor 2 between the power supply node Vin and the ground node GNDP. The capacitor 7 functions as a snubber capacitor (snubber circuit) in the power module 100.

[0036] The half-bridge converter 900 of FIG. 1 operates according to well-known techniques as follows.

[0037] In the semiconductor device 100 as a power module, the on and off of two transistors 2A and 2B are controlled so that the high-side switching device 1A and the low-side switching device 1B alternately output current (are set to the on state). In response to the current from the switching device 1A, the power module 100 outputs a current from a switching node NdVSW. In response to the current output from the switching node NdVSW, the capacitors 30A and 30B are charged or discharged.

[0038] In response to charging and discharging of the capacitors 30A and 30B, an excitation current is generated on the primary side of the transformer 31. When both of the two switching devices 1 are set to the off state, a current is generated on the secondary side of the transformer 31.

[0039] The capacitor 34 is charged and discharged by the current generated on the secondary side of the transformer 31. As a result, the output voltage of the half-bridge converter 900 is generated.

[0040] In this way, by the operation of the semiconductor device 100 of the power module, the half-bridge converter 900 outputs a voltage converted from the input voltage of the power supply node Vin by voltage conversion (e.g., DC-DC conversion) from the power supply node Vout and ground node GNDO on the output side.

[0041] The electric device 900 is not limited to a half-bridge converter, but may be a converter having another circuit configuration.

[0042] (b) Structure example 2 to 5 are diagrams showing an example of the structure of the semiconductor device 100 of this embodiment.

[0043] FIG. 2 is a cross-sectional view showing the cross-sectional structure of the semiconductor device 100 of this embodiment. FIGS. 3 to 5 are plan views showing the planar structure of the semiconductor device 100 of this embodiment. FIG. 3 shows a plan view of the layer corresponding to line AA in FIG. 2 as seen from the top surface side of the semiconductor device 100 in the Z direction. FIG. 4 shows a plan view of the layer corresponding to line BB in FIG. 2 as seen from the top surface side of the semiconductor device 100 in the Z direction. FIG. 5 shows a plan view of the layer corresponding to line CC in FIG. 2 as seen from the top surface side of the semiconductor device 100 in the Z direction.

[0044] As shown in Figures 2 to 5, the semiconductor device 100 includes a switching device 1 (1A, 1B), a transistor 2 (2A, 2B), a capacitor 7 (7A, 7B), a plurality of plugs (contacts, connectors) 80, 81 (81A, 81B), 82 (82A, 82B), 83 (83A, 83B), 84, 85 (85A, 86B), 86 (86A, 86B), 88, and a plurality of conductive layers (wiring) 90, 91, 92, 93, 94 (94A, 94B), 95, 97, 98.

[0045] The semiconductor device 100 is provided on the surface of a substrate 9. The substrate 9 is a multilayer wiring board (e.g., a motherboard) including multiple layers of wiring (not shown). The substrate 9 may be a substrate including a single layer of wiring, or may be an insulating substrate. The substrate 9 may be an insulating substrate provided with a heat sink. Hereinafter, the surface of the substrate 9 is also referred to as the XY plane. The X direction is a direction parallel to the XY plane. The Y direction is a direction parallel to the XY plane and intersects (e.g., perpendicular to) the X direction. The Z direction is a direction intersecting the XY plane (e.g., a direction perpendicular to the XY plane).

[0046] The switching device 1 and the transistor 2 are arranged in the same layer (height) in the Z direction.

[0047] A semiconductor device 100 includes semiconductor chips (or semiconductor packages) of multiple switching devices (GaN transistors) 1.

[0048] Switching device 1A includes a drain layer (also called a drain electrode) 11A, a source layer (also called a source electrode) 12A, and a gate layer (also called a gate electrode) 10A. Switching device 1B includes a drain layer 11B, a source layer 12B, and a gate layer 10A.

[0049] The switching device 1 is a horizontal transistor. In the switching device 1 (1A, 1B) which is a horizontal transistor, the drain layer 11 (11A, 11B), the source layer 12 (12A, 12B), and the gate layer 10 (10A, 10B) are provided on the front surface (upper side) of the semiconductor chip of the switching device 1. Two gate layers 13 are provided so that each is adjacent to one end and the other end of the source layer 12 in the Y direction. In the switching device 1 which is a horizontal GaN transistor, the drain layer 11 is aligned with the source layer 12 in the X direction. The drain current of the switching device 1 flows in a direction parallel to the front surface of the semiconductor chip (for example, the X direction). The back surface of the semiconductor chip of the switching device 1 is insulated.

[0050] A semiconductor chip (or a semiconductor package) of a plurality of transistors (MOS transistors) 2 is provided in a semiconductor device 100.

[0051] The transistor 2A includes a drain layer (also called a drain electrode) 21A, a source layer (also called a source electrode) 22A, and a gate layer (also called a gate electrode) (not shown). The transistor 2B includes a drain layer 21B, a source layer 22B, and a gate layer.

[0052] The transistor 2 is a vertical transistor. In the vertical transistor 2 (2A, 2B), the drain layer 21 (21A, 21B) is provided on the back side (lower side) of the semiconductor chip of the transistor 2, and the source layer 22 (22A, 22B) and the gate layer (not shown) are provided on the front side (upper side) of the semiconductor chip of the transistor 2. In the transistor 2, which is a vertical transistor, the drain layer 21 overlaps the source layer 22 vertically in the Z direction. The drain current of the transistor 2 flows in a direction perpendicular to the surface of the semiconductor chip (Z direction). For example, the gate layer (not shown) is provided on the front side of the transistor 2A. The transistor 2 may be a horizontal transistor.

[0053] Transistor 2A is adjacent to switching device 1A in the X direction in the space between plug 80 and plug 84. Transistor 2B is adjacent to switching device 1B in the X direction in the space between plug 84 and plug 88. Transistor 2A is provided between switching device 1A and switching device 1B in the X direction. Switching device 1B is provided between transistor 2A and transistor 2B in the X direction.

[0054] The capacitor (snubber capacitor) 7 is provided above the switching device 1A in the Z direction.

[0055] 2 and 3, conductive layers 97 and 98 are provided in a layer (layer along line AA) above the layer in which the switching device 1 and the transistor 2 are provided. The conductive layers 97 and 98 are layers containing copper (Cu) (e.g., Cu layers).

[0056] The conductive layer 98 is aligned with the conductive layer 97 in the X direction.

[0057] One end of the conductive layer 97 in the X direction overlaps with the plurality of plugs 80 in the Z direction.

[0058] The conductive layer 97 is electrically connected to a conductive layer 90 on the substrate 9 via a plug 80 extending in the Z direction. The conductive layer 90 is an electrode of a high-side node NdVDC+ of the power module 100. A positive voltage (VDC+) corresponding to the power supply voltage is supplied to the conductive layer 90. The conductive layer 97 is electrically connected to the drain layer 11A of the switching device 1A via a plug 81A extending in the Z direction. As a result, a positive voltage (VDC+) corresponding to the power supply voltage is supplied to the drain layer 11A.

[0059] One end of the conductive layer 98 in the X direction overlaps with the source layer 12A and gate layer 10A of the switching device 1 A. The other end of the conductive layer 98 in the X direction overlaps with the multiple plugs 88 in the Z direction.

[0060] The conductive layer 98 is electrically connected to a conductive layer 92 on the substrate via a plug 88 extending in the Z direction. The conductive layer 92 is an electrode of a low-side node NdVDC− of the power module 100. A voltage (VDC−) corresponding to the ground voltage is supplied to the conductive layer 92. The voltage supplied to the conductive layer 92 is lower than the voltage supplied to the conductive layer 90.

[0061] The dimension in the Y direction of the conductive layer 97 is larger than the dimension in the Y direction of the switching device 1. The dimension in the Y direction of the conductive layer 98 is larger than the dimension in the Y direction of the switching device 1.

[0062] The plug 80 is disposed on the conductive layer 90. The plug 81A is disposed on the drain layer 11A of the switching device 1A. The plug 88 is disposed on the conductive layer 92. The plugs 80, 81A, and 88 are conductors. The number of each of the plugs 80, 81A, and 88 may be one or more depending on the size of the plug.

[0063] The semiconductor device 100 includes electronic components such as capacitors 7A and 7B. The capacitors 7A and 7B are arranged above the switching device 1A in the Z direction, straddling two conductive layers 97 and 98. One terminal of each of the capacitors 7A and 7B is electrically connected to the conductive layer 90 via the conductive layer 97 and the plug 80. The other terminal of each of the capacitors 7A and 7B is electrically connected to the conductive layer 92 via the conductive layer 98 and the plug 88. The capacitors 7A and 7B are connected in parallel between the conductive layer 90 serving as the node NdVDC+ and the conductive layer 92 serving as the node NdVDC−. While an example is shown in which two capacitors 7A and 7B are provided, the number of capacitors 7A and 7B is arbitrary. The shape and size of the conductive layer 97 and the shape and size of the conductive layer 98 can be changed as appropriate depending on the positions of the capacitors 7 and the number of capacitors 7.

[0064] 2 and 4, a plurality of conductive layers 93, 94A, 94B, and 95 are provided in an intermediate layer between the layer of the conductive layers 97 and 98 and the layer of the switching device 1. The plurality of conductive layers 93, 94A, 94B, and 95 are aligned in the X direction. The conductive layers 93, 94A, 94B, and 95 are layers containing Cu (e.g., Cu layers).

[0065] The conductive layer 93 is provided below the conductive layer 97 in the Z direction. The conductive layer 93 overlaps the conductive layer 97 in the vertical direction. One end of the conductive layer 93 covers the drain layer 11A of the switching device 1A in the Z direction. For example, the plug 80 and the plug 81A penetrate the conductive layer 93. One end of the conductive layer 93 in the X direction is electrically connected to the conductive layer 90 via the plug 80. The other end of the conductive layer 93 in the X direction is electrically connected to the drain layer 11A via the plug 81A. Note that each of the plugs 80 and 81A may be divided into a portion between the conductive layer 93 and the conductive layer 97 and a portion between the conductive layers 90 and 90 without penetrating the conductive layer 93.

[0066] The conductive layer 94A is provided, for example, below the conductive layer 98 in the Z direction. The conductive layer 94A is provided between the conductive layer 93 and the conductive layer 95 in the X direction. The conductive layer 94A extends from the switching device 1A to the transistor 2A. The conductive layer 94A spans the source layer 12A of the switching device 1A and the source layer 22A of the transistor 2A. One end of the conductive layer 94A in the X direction is electrically connected to the source layer 12A of the switching device 1A via a plurality of plugs 82A extending in the Z direction. The other end of the conductive layer 94A in the X direction is electrically connected to the source layer 22A provided on the front surface side of the transistor 2A via a plurality of plugs 85A extending in the Z direction. The conductive layer 94A does not vertically overlap the gate layer 10 in the Z direction. Depending on the position of the capacitor 7, the conductive layer 94A may be disposed so as to overlap the conductive layer 97 in the Z direction without overlapping the conductive layer 98.

[0067] The dimension of the conductive layer 94A in the Y direction is smaller than the dimension of the switching device 1 in the Y direction and larger than the dimension of the transistor 2 in the Y direction.

[0068] The plugs 82A are arranged in an array on the source layer 12A of the switching device 1 A. The plugs 85A are arranged in an array on the source layer 22A of the transistor 2 A. The plugs 82A and 85A are conductors.

[0069] The conductive layer 94B is provided below the conductive layer 98 in the Z direction. The conductive layer 94B extends from the switching device 1B to the transistor 2B. The conductive layer 94B spans the source layer 12B of the switching device 1B and the source layer 22B of the transistor 2B. One end of the conductive layer 94B in the X direction is electrically connected to the source layer 12B of the switching device 1B via a plurality of plugs 82B extending in the Z direction. The other end of the conductive layer 94B in the X direction is electrically connected to the source layer 22B provided on the front surface side of the transistor 2B via a plurality of plugs 85B extending in the Z direction.

[0070] The dimension of the conductive layer 94B in the Y direction is smaller than the dimension of the switching device 1 in the Y direction and larger than the dimension of the transistor 2 in the Y direction.

[0071] The plugs 82B are arranged in an array on the source layer 12B of the switching device 1B. The plugs 85B are arranged in an array on the source layer 22B of the transistor 2B. The plugs 82B and 85B are conductors.

[0072] The conductive layer 95 is provided below the conductive layer 98 in the Z direction. The conductive layer 95 is provided between the conductive layer 94A and the conductive layer 94B in the X direction. The conductive layer 95 straddles the conductive layer 91 on the substrate 9 and the switching device 1B in the Z direction. One end of the conductive layer 95 in the X direction overlaps with the conductive layer 91 in the Z direction. The other end of the conductive layer 95 in the X direction overlaps with the drain layer 11B of the switching device 1B in the Z direction. Depending on the position of the capacitor 7, the conductive layer 95 may be arranged so as to overlap with the conductive layer 97 in the Z direction without overlapping with the conductive layer 98.

[0073] One end of the conductive layer 95 in the X direction is electrically connected to the conductive layer 91 via a plurality of plugs 84 extending in the Z direction. The other end of the conductive layer 95 is electrically connected to the drain layer 11B of the switching device 1B via a plurality of plugs 81B extending in the Z direction.

[0074] The plugs 81B are arranged in an array on the drain layer 11B of the switching device 1B. The plugs 84 are arranged in an array on the conductive layer 91. The plugs 84 are provided between the switching device 1B and the transistor 2A in the X direction. The plugs 81B and 84 are conductors.

[0075] The gate drivers 4A and 4B are provided within an area on the surface of the substrate 9. The gate drivers 4A and 4B are provided above the substrate 9. For example, the gate drivers 4A and 4B are provided in the same layer (height from the surface of the substrate 9) as the switching devices 1. The gate drivers 4A and 4B are connected to the gate layers 10A and 10B of the switching devices 1A and 1B, respectively. For example, the QN-off drivers 4C and 4D (not shown) are provided on the substrate 9, similar to the gate driver 4. Note that each driver 4 may be provided on the substrate 9, on the conductive layers 97 and 98, or outside the substrate 9, depending on the design of the power module 100.

[0076] 2 and 5, a plurality of conductive layers 90, 91, and 92 are provided in a layer between the switching device 1 and the substrate 9. The conductive layers 90, 91, and 92 are provided on the substrate 9. The conductive layer 91 is provided between the conductive layer 90 and the conductive layer 92 in the X direction. As described above, the conductive layer 90 is an electrode (node ​​NdVDC+) on the high side (+VDC side) of the power module 100, and the conductive layer 92 is an electrode (node ​​NdVDC-) on the low side (-VDC side) of the power module 100. The conductive layer 91 is an electrode of the switching node (output node) NdVSW of the power module 100. The conductive layers 90, 91, and 92 are layers containing Cu (for example, Cu layers).

[0077] The conductive layer 90 is provided below the switching device 1A in the Z direction. One end of the conductive layer 90 in the X direction vertically overlaps a portion of the conductive layer 97 in the Z direction. One end of the conductive layer 90 in the X direction is electrically connected to the conductive layer 97 (and the conductive layer 93) via a plug 80. The other end of the conductive layer 90 in the X direction vertically overlaps the switching device 1A in the Z direction. A plurality of plugs 83A extending in the Z direction are provided between the back surface of the semiconductor chip of the switching device 1A and the other end of the conductive layer 90 in the X direction.

[0078] The plug 83A is disposed on the conductive layer 90. The plug 83A is a conductor. The plug 83A contacts the back surface of the switching device 1A. The back surface of the lateral transistor switching device 1A is insulated. Therefore, the plug 83A does not form a current path between the switching device 1A and the conductive layer 90. The plug 83A transfers heat generated from the switching device 1A to the conductive layer 90. The number of plugs 83A may be one or more depending on the size of the plug.

[0079] The conductive layer 91 is provided below the transistor 2A and a portion of the conductive layer 95 in the Z direction. One end of the conductive layer 91 in the X direction vertically overlaps the transistor 2A in the Z direction. One end of the conductive layer 91 in the X direction is electrically connected to the drain layer 21A provided on the back surface side of the transistor 2A via a plug 86A extending in the Z direction. The plug 86A is a conductor. The drain current of the transistor 2A flows between the transistor 2A and the conductive layer 91 via the plug 86A.

[0080] The multiple plugs 86A are arranged in an array on the conductive layer 91. The other end of the conductive layer 91 in the X direction vertically overlaps a portion of the conductive layer 95 in the Z direction. The other end of the conductive layer 91 in the X direction is electrically connected to the conductive layer 95 via the plug 84.

[0081] The other end of the conductive layer 91 in the X direction vertically overlaps in the Z direction with one end of the conductive layer 95 in the X direction. The other end of the conductive layer 91 in the X direction is electrically connected to one end of the conductive layer 95 in the X direction via a plug 84.

[0082] The potential of the conductive layer 91 varies depending on the switching frequency of the power module 100. The conductive layer 91 is a source-side electrode of the high-side switching device 1A of the power module 100. The conductive layer 91 is a drain-side electrode of the low-side switching device 1B of the power module 100.

[0083] The conductive layer 92 is provided below the switching device 1B and the transistor 2B in the Z direction. One end of the conductive layer 92 in the X direction vertically overlaps the switching device 1B in the Z direction. A plurality of plugs 83B extending in the Z direction are provided between the back surface of the semiconductor chip of the switching device 1B and one end of the conductive layer 92 in the X direction.

[0084] A plurality of plugs 83B are arranged in an array on the conductive layer 92. The plugs 83B are conductors. The plugs 83B contact the back surface of the switching device 1B. The back surface of the lateral transistor switching device 1B is insulated. Therefore, the plugs 83B do not form a current path between the switching device 1B and the conductive layer 92. The plugs 83B transfer heat generated from the switching device 1B to the conductive layer 92.

[0085] The other end of the conductive layer 92 in the X direction vertically overlaps in the Z direction with a portion of the conductive layer 98. The other end of the conductive layer 92 in the X direction is electrically connected to the conductive layer 98 via the plug 88.

[0086] A portion of the conductive layer 92 between one end and the other end in the X direction (hereinafter referred to as the intermediate portion) is provided below the transistor 2B in the Z direction. The intermediate portion of the conductive layer 92 vertically overlaps the transistor 2B in the Z direction. The intermediate portion of the conductive layer 92 is electrically connected to the drain layer 21B provided on the back surface side of the transistor 2B via a plug 86B extending in the Z direction. A voltage (VDC-) corresponding to the ground voltage is supplied to the drain layer 21B. A drain current of the transistor 2B flows between the transistor 2B and the conductive layer 92 via the plug 86B.

[0087] A plurality of plugs 86B are arranged in an array on the conductive layer 92. The plugs 86B are conductors.

[0088] The conductive layers 90 and 92 function as heat sinks for heat generated by the switching devices 1A and 1B.

[0089] The conductive layer 91, which functions as a switching node, is separated from the conductive layers 90 and 92, which function as heat sinks. The conductive layer 91 does not function as a heat sink.

[0090] In the semiconductor device 100 of this embodiment, the heat-generating switching devices 1A and 1B are provided above the conductive layers 90 and 92 of the voltage nodes via the plugs 83, without being provided on the conductive layer 91 of the switching node.

[0091] In this way, the semiconductor device 100 of this embodiment shares the heat sink of the switching device 1 with the voltage nodes NdVDC (NdVDC+, NdVDC−) 90, 92, which are substantially not affected by noise.

[0092] (c) Summary To improve the efficiency of a power module including a switching device, it is desirable to improve the heat dissipation performance of the switching device. To ensure a heat dissipation path for the switching device 1, the conductive layer below the switching device is used as a heat sink. To improve the heat dissipation efficiency of the switching device, the area (and volume) of the conductive layer serving as a heat sink is increased.

[0093] Generally, the source of a switching device is set as the reference potential terminal for switching operation. The potential of the source of a switching device on the high side (high potential side) of a power module fluctuates depending on the switching frequency of the switching device. For this reason, the source of the high-side switching device becomes a radiation source that generates large switching noise. The source of the high-side switching device is connected to the switching node of the power module.

[0094] When the conductive layer of the switching node is used as a heat sink for heat generation from the switching device 1, noise is applied to the conductive layer of the switching node. In this case, if the area of ​​the conductive layer of the switching node is reduced to suppress the noise, the heat dissipation characteristics of the switching device will be reduced.

[0095] In the semiconductor device 100 of this embodiment, the high-side switching device 1A of the power module 100 is provided above the conductive layer 90 serving as the voltage node NdVDC+. The conductive layer 90 functions as a heat sink for the switching device 1A. In this manner, in this embodiment, the heat dissipation path for the high-side switching device 1A is ensured by the conductive layer 90 serving as the voltage node NdVDC+.

[0096] The conductive layer 90 serving as a heat sink for the high-side switching device 1A is separated from the conductive layer 91 of the switching node (output node) NdVSW of the power module 100. The conductive layer 90 of the voltage node NdVDC+ is not affected by noise from the switching device 1A. Furthermore, the voltage node NdVDC+ does not become a source of noise for the output of the power module 100. Therefore, in this embodiment, by ensuring a large area for the conductive layer 90, the heat dissipation characteristics of the switching device 1A can be improved.

[0097] Therefore, the semiconductor device 100 of this embodiment can improve the operating efficiency of the semiconductor device.

[0098] In this embodiment, the conductive layer 91 serving as the switching node NdVSW is not used as a heat sink for the switching device 1A. This allows the area and volume of the conductive layer 91 serving as the switching node NdVSW to be reduced. As a result, the semiconductor device 100 of this embodiment can reduce noise generated at the switching node NdVSW.

[0099] In this embodiment, the conductive layer 91 of the switching node NdVSW only needs to satisfy the electrical requirements of the power module (for example, the allowable current and voltage). Therefore, the semiconductor device 100 of this embodiment can relatively easily achieve noise countermeasures for the power module.

[0100] Furthermore, the semiconductor device 100 of this embodiment can suppress the influence of heat on the switching node NdVSW.

[0101] As described above, the semiconductor device 100 of this embodiment can improve the heat dissipation performance of the semiconductor device and reduce noise.

[0102] Therefore, the semiconductor device 100 of this embodiment can improve the characteristics of the semiconductor device.

[0103] (2) Second embodiment A semiconductor device according to a second embodiment will be described with reference to FIGS.

[0104] FIG. 6 is a cross-sectional view showing the cross-sectional structure of the semiconductor device 100 of this embodiment. FIG. 7 is a plan view showing the planar structure of the semiconductor device 100 of this embodiment. FIG. 7 shows a plane of the layer corresponding to line CC in FIG. 6 as viewed from the top side of the semiconductor device 100 in the Z direction. The planar structure of the layer corresponding to line AA in FIG. 6 is substantially the same as the example in FIG. 3. The planar structure of the layer corresponding to line BB in FIG. 6 is substantially the same as the example in FIG. 4.

[0105] As shown in FIGS. 6 and 7, a high-side switching device (e.g., a GaN transistor) 1A of the power module 100 may be provided on a conductive layer 92A corresponding to the low-side voltage node NdVDC− of the power module 100.

[0106] The conductive layer 92A has a U-shaped planar shape when viewed from the Z direction. The conductive layer 92A includes a first portion 921, a second portion 922, and a third portion 923. The first portion 921 is continuous with the second portion 922 via the third portion 923.

[0107] The switching device 1A is provided above the first portion 921 in the Z direction. A plug 83A is provided between the back surface of the switching device 1A and the first portion 921. The switching device 1A is electrically isolated from the first portion 921. No current path is formed between the switching device 1A and the first portion 921 via the plug 83A.

[0108] The switching device 1B and the transistor 2B are provided above the second portion 922 in the Z direction. A plug 83B is provided between the back surface of the switching device 1B and the second portion 922. The switching device 1B is electrically isolated from the second portion 922. No current path is formed between the switching device 1B and the second portion 922 via the plug 83B. A plug 86B is provided between the back surface of the transistor 2B and the second portion 922. The drain layer 21B on the back surface of the transistor 2B is electrically connected to the second portion 922 via the plug 86B. The drain current of the transistor 2B flows between the transistor 2B and the second portion 922 via the plug 86B.

[0109] The third portion (connecting portion) 923 is provided between the first portion 921 and the second portion 922 in the X direction. The third portion 923 connects (connects) the first portion 921 to the second portion 922. The third portion 923 is adjacent to one end in the Y direction of the conductive layer 91 of the switching node NdVSW. The third portion 923 connects the first portion 921 to the second portion 922.

[0110] The dimension D3 in the Y direction of the third portion is smaller than the dimension D1 in the Y direction of the first portion 921 and the dimension D2 in the Y direction of the second portion 922. The dimension D2 is substantially equal to the dimension D1. For example, the dimension Da in the Y direction of the conductive layer 90 is equal to the dimensions D1 and D2 and larger than the dimension D3. For example, the dimension Db in the Y direction of the conductive layer 91 is larger than the dimension D3 and smaller than the dimensions D1 and D2. Note that the dimension Da may be equal to or smaller than the dimension D3 depending on the layout design of each conductive layer.

[0111] As described above, in the semiconductor device 100 of this embodiment, the high-side switching device 1A of the power module 100 is provided on the conductive layer 92 of the low-side voltage node NdVDC−, which functions as a heat sink. Even in this case, the semiconductor device 100 of this embodiment can achieve substantially the same effects as those of the other embodiments.

[0112] Furthermore, in this embodiment, the conductive layer 91 of the switching node NdVSW is surrounded by the conductive layer 92 of the voltage node NdVDC− on the low potential side (ground side). The conductive layer 92 functions as an electrical shield (ground guard) for the conductive layer 91. This makes it relatively easy to shield the switching node NdVSW of the power module 100. As a result, the semiconductor device 100 of this embodiment can further reduce the influence of noise on the switching node NdVSW.

[0113] As described above, the semiconductor device 100 of the second embodiment can improve the characteristics of the semiconductor device.

[0114] (3) Third embodiment A semiconductor device according to a second embodiment will be described with reference to FIGS.

[0115] (a) Circuit example FIG. 8 is a circuit diagram showing the circuit configuration of the semiconductor device 100 of this embodiment.

[0116] If the switching device 1 is a normally-off transistor, the totem-pole power module 100 does not need to include a field-effect transistor to form a quasi-normally-off switching device.

[0117] 8, the power module 100 includes two switching devices 1. The switching devices 1 are normally-off type transistors.

[0118] One end of the switching device 1A is electrically connected to a node NdVDC+ on the high side of the power module 100. The other end of the switching device 1A is electrically connected to a switching node NdVSW of the power module 100.

[0119] One end of the switching device 1B is electrically connected to the switching node NdVSW, and the other end of the switching device 1B is electrically connected to the node NdVDC− on the low side of the power module 100.

[0120] For example, the switching device 1 is a normally-off field effect transistor (MOS transistor) using Si or SiC, but may also be a normally-off transistor using GaN.

[0121] The half-bridge converter 900 including the semiconductor device 100 of FIG. 8 operates in a well-known manner.

[0122] (b) Structure example 9 to 12 are diagrams illustrating an example of the structure of the semiconductor device 100 of this embodiment. FIG. 9 is a cross-sectional view illustrating the cross-sectional structure of the semiconductor device 100 of this embodiment. FIGS. 10 to 12 are plan views illustrating the planar structure of the semiconductor device 100 of this embodiment. FIG. 10 illustrates a plan view of the layer corresponding to line AA in FIG. 9 as viewed from the top surface of the semiconductor device 100 in the Z direction. FIG. 11 illustrates a plan view of the layer corresponding to line BB in FIG. 9 as viewed from the top surface of the semiconductor device 100 in the Z direction. FIG. 12 illustrates a plan view of the layer corresponding to line CC in FIG. 9 as viewed from the top surface of the semiconductor device 100 in the Z direction.

[0123] 9 to 12, switching device 1A is provided between plug 80 and plug 84 in the X direction. Switching device 1B is provided between plug 84 and plug 88 in the X direction.

[0124] The conductive layers 97 and 98 are provided above the switching devices 1A and 1B in the Z direction. The conductive layer 97 extends in the X direction from the drain layer 11A of the switching device 1A to a region in the conductive layer 90 where the plug 80 is provided. The conductive layer 98 extends in the X direction from the source layer 12A of the switching device 1A to a region in the conductive layer 92 where the plug 88 is provided. The conductive layer 98 is electrically connected to the source layer 12B of the switching device 1B via the plug 82B. The shape and size of the conductive layer 97 and the shape and size of the conductive layer 98 can be changed as appropriate depending on the position where the capacitor 7 is arranged.

[0125] The conductive layers 95A and 99 are provided in a layer between the conductive layer 98 and the surface of the switching device 1 in the Z direction. The conductive layer 95A is adjacent to the conductive layer 93 in the X direction. The conductive layers 95A and 99 overlap the conductive layer 98 in the Z direction. The conductive layer 95A passes above the conductive layer 91 in the Z direction and extends between the source layer 12A of the switching device 1A and the drain layer 11B of the switching device 1B.

[0126] One end of the conductive layer 95A in the X direction is electrically connected to the source layer 12A of the switching device 1A via a plug 82A. The other end of the conductive layer 95A in the X direction is electrically connected to the drain layer 11B of the switching device 1B via a plug 81B. A portion (intermediate portion) between the two ends of the conductive layer 95A is electrically connected to the conductive layer 91 via a plug 84.

[0127] The dimension in the Y direction of conductive layer 95A is smaller than the dimension in the Y direction of conductive layer 93. The dimension in the Y direction of conductive layer 99 is substantially equal to the dimension in the Y direction of conductive layer 95A. Note that the dimension in the Y direction of conductive layer 95A may be equal to or larger than the dimension in the Y direction of conductive layer 93.

[0128] The conductive layer 99 is adjacent to the conductive layer 95A in the X direction. One end of the conductive layer 99 in the X direction vertically overlaps the source layer 12B of the switching device 1B in the Z direction. The plug 82B penetrates through a region at one end of the conductive layer 99 in the X direction. The plug 88 penetrates through a region at the other end of the conductive layer 99 in the X direction.

[0129] One end of the conductive layer 99 in the X direction is electrically connected to the source layer 12B of the switching device 1B via the plug 82B. The other end of the conductive layer 99 in the X direction is electrically connected to the conductive layer 92 via the plug 88. As a result, a voltage (VDC-) corresponding to the ground voltage is supplied to the source layer 12B.

[0130] Note that plug 82B may be divided into a portion between conductive layer 98 and conductive layer 99 and a portion between conductive layer 99 and source layer 12B without penetrating conductive layer 99. Plug 88 may be divided into a portion between conductive layer 98 and conductive layer 99 and a portion between conductive layer 92 and conductive layer 99 without penetrating conductive layer 99.

[0131] In this embodiment, the switching device 1A is provided above a conductive layer 90 serving as a high-side node NdVDC+ via a plug 83A. The conductive layer 90 and the plug 83A function as a heat sink for the switching device 1A.

[0132] As a result, even when the semiconductor device 100 is formed using a normally-off switching device 1, the semiconductor device 100 of this embodiment can achieve substantially the same effects as those of the other embodiments.

[0133] Therefore, the semiconductor device 100 of the third embodiment can improve the characteristics of the semiconductor device.

[0134] (4) Fourth embodiment A semiconductor device according to a fourth embodiment will be described with reference to FIGS.

[0135] FIG. 13 is a cross-sectional view showing the cross-sectional structure of the semiconductor device 100 of this embodiment. FIG. 14 is a plan view showing the planar structure of the semiconductor device 100 of this embodiment. FIG. 14 shows a plane of the layer corresponding to line CC in FIG. 13 as viewed from the top side of the semiconductor device 100 in the Z direction. The planar structure of the layer corresponding to line AA in FIG. 13 is substantially the same as the example in FIG. 10. The planar structure of the layer corresponding to line BB in FIG. 13 is substantially the same as the example in FIG. 11.

[0136] As shown in FIGS. 13 and 14, a high-side switching device (eg, a GaN transistor) of the power module 100 may be provided on the conductive layer 92B of the low-side voltage node NdVDC− of the power module 100.

[0137] The conductive layer 92B has a U-shaped planar shape when viewed in the Z direction. The conductive layer 92B includes a first portion 925, a second portion 926, and a third portion 927.

[0138] Switching device 1A is provided above first portion 925 in the Z direction. Plug 83A is provided between the back surface of switching device 1A and first portion 925. Switching device 1A is electrically isolated from first portion 925. No current path is formed between switching device 1A and first portion 925 via plug 83A.

[0139] Switching device 1B is provided above second portion 926 in the Z direction. Plug 83B is provided between the back surface of switching device 1B and second portion 926. Switching device 1B is electrically isolated from second portion 926. No current path is formed between switching device 1B and second portion 926 via plug 83B.

[0140] The third portion (connecting portion) 927 is provided between the first portion 925 and the second portion 926 in the X direction. The third portion 927 is adjacent to one end in the Y direction of the conductive layer 91 of the switching node NdVSW. The third portion 927 connects the first portion 925 to the second portion 926.

[0141] The dimension D7 in the Y direction of the third portion 927 is smaller than the dimension D5 in the Y direction of the first portion 925 and the dimension D6 in the Y direction of the second portion 926. The dimension D6 is substantially equal to the dimension D5. For example, the dimension Da in the Y direction of the conductive layer 90 is equal to the dimensions D5 and D6 and larger than the dimension D7. For example, the dimension Db in the Y direction of the conductive layer 91 is larger than the dimension D7 and smaller than the dimensions D5 and D6. However, the dimension Db may be smaller than the dimension D7. The dimension Db may be larger than the dimensions D5 and D6.

[0142] In the semiconductor device 100 of this embodiment, the high-side switching device 1A of the power module 100 is provided on the conductive layer 92 of the low-side voltage node NdVDC−, which functions as a heat sink. Even in this case, the semiconductor device 100 of this embodiment can achieve substantially the same effects as those of the other embodiments.

[0143] Furthermore, the semiconductor device 100 of this embodiment can further reduce noise in the conductive layer 91 of the switching node NdVSW by shielding the low-potential side voltage node NdVDC− with the conductive layer 91.

[0144] As described above, the semiconductor device 100 of the fourth embodiment can improve the characteristics of the semiconductor device.

[0145] (5) Fifth embodiment A semiconductor device according to a fifth embodiment will be described with reference to FIG.

[0146] FIG. 15 is a plan view showing an example of the structure of the semiconductor device 100 of this embodiment.

[0147] 15 includes a lead frame 5 as a substrate on which a switching device 1 is mounted. The switching device 1 and the transistor 2 are provided on the lead frame 5.

[0148] The lead frame 5 includes a plurality of lead layers 50, 51, and 52. The lead layers 50, 51, and 52 are conductive layers (for example, Cu layers).

[0149] The lead layer 50 corresponds to the electrode of the high-side node NdVDC+ of the power module 100. The lead layer 51 corresponds to the electrode of the switching node NdVSW of the power module 100. The lead layer 52 corresponds to the electrode of the low-side node NdVDC- of the power module 100.

[0150] For example, the lead frame 5 includes lead layers 53 and 54. The lead layers 53 and 54 are conductive layers. An electronic component 500A is provided on the lead layer 53. The electronic component 500A is electrically connected to the lead layer 53 and other lead layers by bonding wires (not shown) or conductive adhesives (not shown). An electronic component 500B is provided on the lead layer 54. The electronic component 500B is electrically connected to the lead layer 54 and other lead layers by bonding wires (not shown) or conductive adhesives (not shown). The electronic components 500A and 500B are semiconductor devices such as drivers, passive elements such as capacitors, or the like.

[0151] The high-side switching device 1A is provided on a lead layer 50 corresponding to the node NdVDC+ via an adhesive layer (not shown). The transistor 2A is provided on a lead layer 51 corresponding to the node NdVSW. The drain layer 11A of the switching device 1A is electrically connected to the lead layer 50 via a bonding wire 59A. The source layer 12A of the switching device 1A is electrically connected to the source layer 22A of the transistor 2A via a bonding wire 59B. The drain layer (not shown) of the transistor 2A is electrically connected to the lead layer 51 via a solder layer (not shown) provided between the back surface of the transistor 2A and the lead layer 51.

[0152] The low-side switching device 1B and transistor 2B are provided on a lead layer 52 corresponding to node NdVDC−. A drain layer 11B of the switching device 1B is electrically connected to the lead layer 51 via a bonding wire 59C. For example, an insulating adhesive layer (not shown) is provided between the back surface of the switching device 1B and the lead layer 52. A source layer 12B of the switching device 1B is electrically connected to a source layer 22B of the transistor 2B via a bonding wire 59D. A drain layer (not shown) of the transistor 2A is electrically connected to the lead layer 52 via a solder layer (not shown) provided between the back surface of the transistor 2A and the lead layer 51.

[0153] The lead layers 50 and 52 function as heat sinks for the heat generated by the switching devices 1A and 1B.

[0154] For example, the capacitor 7 is provided on the lead layers 50 and 52 so as to straddle the two lead layers 50 and 52. The capacitor 7 is a snubber capacitor.

[0155] When the switching device 1 is a normally-off transistor, the transistor 2 for forming a quasi-normally-off switching device does not need to be provided on a lead frame. In this case, the source layer 12A of the switching device 1A is electrically connected to the lead layer 51 via the wire 59B, and the source layer 12B of the switching device 1B is electrically connected to the lead layer 52 via the wire 59D.

[0156] As described above, in the semiconductor device 100 of this embodiment, the switching device 1 is provided on the lead frame 5. The high-side switching device 1A of the power module 100 is disposed on the lead layer 50, of the multiple lead layers 50, 51, and 52 in the lead frame 5, which corresponds to the high-side voltage node NdVDC+.

[0157] As a result, the semiconductor device 100 of this embodiment can achieve substantially the same effects as those of the other embodiments.

[0158] Therefore, the semiconductor device 100 of the fifth embodiment can improve the characteristics of the semiconductor device.

[0159] (6) Sixth embodiment A semiconductor device according to a sixth embodiment will be described with reference to FIG.

[0160] FIG. 16 is a plan view showing an example of the structure of the semiconductor device 100 of this embodiment.

[0161] As shown in FIG. 16, the high-side switching device 1A of the power module 100 may be provided on the lead layer 52 of the low-side node NdVDC− of the power module 100.

[0162] The lead layer 52 includes a first portion 521, a second portion 522, and a third portion 523. The first portion 521 and the second portion 522 sandwich the lead layer 51 in the X direction. The first portion 521 is adjacent to the lead layer 51 at one end of the lead layer 51 in the X direction. The second portion 522 is adjacent to the lead layer 51 at the other end of the lead layer 51 in the X direction. The third portion 523 is provided between the first portion 521 and the second portion 522 in the X direction. The third portion 523 is adjacent to the lead layer 51 at one end of the lead layer 51 in the Y direction.

[0163] The lead layer 20 corresponding to the high-side node NdVDC+ is adjacent to the first portion 521 of the lead layer 51 in the X direction. For example, no switching device or other components are provided on the lead layer 50. The lead layer 50 is electrically connected to the drain layer 11A of the switching device 1A via a wire 59A.

[0164] In this embodiment as well, when the switching device 1 is a normally-off type transistor, the transistor 2 for forming a quasi-normally-off switching device does not need to be provided on the lead frame.

[0165] In the switching device 1 on the lead frame 5 of the semiconductor device 100 of this embodiment, the high-side switching device 1A of the power module 100 is provided on the lead layer 52 of the low-side voltage node NdVDC−, which functions as a heat sink. Even in this case, substantially the same effects as those of the other embodiments can be obtained.

[0166] Therefore, the semiconductor device 100 of the sixth embodiment can improve the characteristics of the semiconductor device.

[0167] (7) Variations A modified example of the semiconductor device of the embodiment will be described with reference to FIG.

[0168] FIG. 17 is a cross-sectional view showing the cross-sectional structure of a modified example of the semiconductor device 100 of this embodiment.

[0169] As shown in FIG. 17, in the semiconductor device 100 of the embodiment, the transistor 2A may be connected between the switching device 1A and the high-side voltage node NdVDC+, and the transistor 2B may be connected between the switching device 1B and the switching node NdVSW.

[0170] The semiconductor device 100 of the modified example further includes conductive layers 63A, 63B, 64A, and 64B and plugs 65A and 65B.

[0171] The conductive layers 63A and 63B are provided on the substrate 9. For example, the conductive layer 63A is provided between the first and second portions of the conductive layer 90 in the X direction. The conductive layer 63B is provided between the conductive layer 91 and the conductive layer 92 in the X direction.

[0172] Conductive layers 64A and 64B are provided in the same level as conductive layers 93, 95A, and 99. Conductive layer 64A is electrically connected to drain layer 11A of switching device 1A via plug 81A. Conductive layer 64B is electrically connected to drain layer 11B of switching device 1B via plug 81B.

[0173] A plug 65A is provided between switching device 1A and transistor 2A in the X direction. The plug 65A electrically connects conductive layer 63A to conductive layer 64A. A plug 65B is provided between switching device 1B and transistor 2B in the X direction. The plug 65B electrically connects conductive layer 63B to conductive layer 64B.

[0174] The transistor 2A is disposed between the plug 80 and the switching device 1A in the X direction. The transistor 2A is disposed above the conductive layer 63A via the plug 86A in the Z direction. The source layer 22A of the transistor 2A is electrically connected to the conductive layer 90 of the high-side voltage node NdVDC+ via the conductive layer 93 and the plugs 80 and 85A. The drain layer 21A of the transistor 2A is electrically connected to the conductive layer 63A via the plug 86A. The drain layer 21A of the transistor 2A is electrically connected to the drain layer 11A of the switching device 1A via the conductive layers 63A and 64A and the plugs 65A, 81A, and 86A.

[0175] The transistor 2B is provided between the plug 84 and the switching device 1B in the X direction. The transistor 2B is provided above the conductive layer 63B via the plug 86B in the Z direction. The source layer 22B of the transistor 2B is electrically connected to the conductive layer 91 of the switching node NdVSW via the conductive layer 95A and the plugs 84 and 85B. The drain layer 21B of the transistor 2B is electrically connected to the conductive layer 63B via the plug 86B. The drain layer 21B of the transistor 2B is electrically connected to the drain layer 11B of the switching device 1B via the conductive layers 63B and 64B and the plugs 65B, 81B, and 86B.

[0176] Switching device 1A may be provided above conductive layer 63A via plug 83A instead of being provided above conductive layer 90. Switching device 1B may be provided above conductive layer 63B via plug 83B instead of being provided above conductive layer 92.

[0177] In the semiconductor device 100 of this modification, the high-side switching device 1 of the power module 100 is provided above a conductive layer 90 different from the conductive layer 91 of the switching node NdVSW of the power module 100.

[0178] Therefore, the semiconductor device 100 of this modification can obtain substantially the same effects as those of the above-described embodiment.

[0179] (8) Other The semiconductor device of the embodiment may be a device other than a power module, and may be used in an electric device other than a converter (for example, an inverter).

[0180] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0181] 1, 1A, 1B: switching devices, 2, 2A, 2B: transistors, 90, 91, 92: conductive layers.

Claims

1. a first conductive layer provided on a substrate; a second conductive layer provided on the substrate and supplied with a first voltage; a third conductive layer corresponding to an output node and provided on the substrate between the first conductive layer and the second conductive layer; a first switching device provided above the first conductive layer, the first switching device including a first terminal supplied with a second voltage higher than the first voltage and a second terminal connected to the third conductive layer; a second switching device disposed above the second conductive layer, the second switching device including a third terminal connected to the third conductive layer and a fourth terminal connected to the second conductive layer; A semiconductor device comprising:

2. a first transistor provided on the third conductive layer; a second transistor provided on the second conductive layer; a fourth conductive layer disposed above the first switching device and the first transistor; a fifth conductive layer disposed above the second switching device and the second transistor; Further comprising: the first transistor includes a fifth terminal connected to the second terminal via the fourth conductive layer and a sixth terminal connected to the third conductive layer; the second transistor includes a seventh terminal connected to the fourth terminal via the fifth conductive layer and an eighth terminal connected to the second conductive layer; The semiconductor device of claim 1 .

3. the first and second switching devices are normally-on transistors including gallium nitride; the first and second transistors are normally-off transistors; The semiconductor device of claim 2 .

4. a sixth conductive layer disposed above the first and second switching devices; Furthermore, the second and third terminals are connected to the third conductive layer via the sixth conductive layer; The semiconductor device of claim 1 .

5. the second voltage is applied to the first conductive layer; the first terminal is connected to the first conductive layer; The semiconductor device of claim 1 .

6. a seventh conductive layer provided on the substrate and supplied with the second voltage; Furthermore, the seventh conductive layer is connected to the first terminal; the first conductive layer is continuous with the second conductive layer; the first voltage is supplied to the first conductive layer; The semiconductor device of claim 1 .

7. a portion connecting the first conductive layer to the second conductive layer; Furthermore, the third conductive layer is provided between the first conductive layer and the second conductive layer in a first direction parallel to a surface of the substrate; the portion is adjacent to the third conductive layer in a second direction that is parallel to the surface of the substrate and intersects with the first direction; The semiconductor device of claim 6.

8. an eighth conductive layer provided above the first switching device and supplied with the second voltage; a ninth conductive layer disposed above the second switching device and connected to the second conductive layer; a capacitor provided on the eighth and ninth conductive layers; The semiconductor device of claim 1 further comprising:

9. The substrate is a lead frame. The semiconductor device of claim 1 .

10. each of the first and second conductive layers being a heat sink; The semiconductor device of claim 1 .

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