Electro-optical device and electronic apparatus

Abstract

To provide an electro-optical device suitable for miniaturization.SOLUTION: An electro-optical device comprises: a plurality of data lines 6; a data line driving circuit 20 having a plurality of sampling transistors 23; and routed wiring lines 51 that are arranged between a display area A1 and the data line driving circuit 20 and electrically connect the data lines 6 and the sampling transistors 23. The spacing 6D between a data line 6a arranged at one end and a data line 6b arranged at the other end is narrower than the spacing 20D between a sampling transistor 231 arranged at one end and a sampling transistor 232 arranged at the other end in the data line driving circuit 20. With respect to the spacing 513D1 and spacing 513D2 between a routed wiring line 511 and a routed wiring line 513 that are adjacent to each other, the spacing 513D2 at the display area A1 side is narrower than the spacing 513D1 at the data line driving circuit 20 side.SELECTED DRAWING: Figure 7A

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic apparatus equipped with the electro-optical device. [Background technology]

[0002] A conventional electro-optical device is known, for example, from Patent Document 1. The electro-optical device of Patent Document 1 has pixels provided in a display area and a drive circuit provided outside the display area, and the drive circuits include a data line drive circuit and two scanning line drive circuits. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-8150 Summary of the Invention [Problem to be solved by the invention]

[0004] In such electro-optical devices, there is a strong demand for higher resolution and / or smaller size, and miniaturization of pixel circuits and driver circuits has been a challenge. However, the transistors that make up the driver circuits have a greater driving load requirement than the transistors that make up the pixel circuits, making it difficult to achieve a narrower pitch as the devices are miniaturized. In other words, handling the driver circuits, in particular, has been a challenge when miniaturizing electro-optical devices. [Means for solving the problem]

[0005] An electro-optical device according to one embodiment of the present application comprises a plurality of first wirings arranged along a first direction in a display area, a first drive circuit arranged outside the display area along a second direction intersecting the first direction and having a plurality of first unit circuits, and a plurality of first routing wirings arranged between the display area and the first drive circuit, each electrically connecting one of the plurality of first wirings to one of the plurality of first unit circuits, wherein the distance between the first wiring arranged at one end of the plurality of first wirings and the first wiring arranged at the other end is narrower than the distance between the first unit circuit arranged at one end of the plurality of first unit circuits and the first unit circuit arranged at the other end, and the distance between adjacent first routing wirings among the plurality of first routing wirings is narrower on the display area side than on the first drive circuit side.

[0006] An electronic device according to one aspect of the present application includes the electro-optical device described above. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view of an electro-optical device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view of the electro-optical device taken along line II-II in FIG. [Figure 3] FIG. 2 is a wiring diagram showing a circuit configuration of the electro-optical device. [Figure 4] FIG. 2 is a wiring diagram showing the circuit configuration of a scanning line driving circuit. [Figure 5A] FIG. 2 is a wiring diagram showing an example of a circuit configuration of a data line driving circuit. [Figure 5B] FIG. 10 is a wiring diagram showing another example of the circuit configuration of the data line driving circuit. [Figure 6A] FIG. 2 is a plan view showing the arrangement of a scanning line driving circuit, routing wiring, and scanning lines. [Figure 6B] FIG. 6B is a partially enlarged plan view of FIG. 6A. [Figure 7A] FIG. 2 is a plan view showing the arrangement of a data line driving circuit, routing wiring, and data lines. [Figure 7B] FIG. 7B is a partially enlarged plan view of FIG. 7A. [Figure 8]FIG. [Figure 9] FIG. 10 is a schematic diagram showing an example of an electronic device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings below, the dimensions of the components may be shown on different scales to make them easier to see. For ease of explanation, the three mutually orthogonal axes will be referred to as the X-axis, Y-axis, and Z-axis below, and the direction parallel to the X-axis will be referred to as the "X-axis direction," the direction parallel to the Y-axis as the "Y-axis direction," and the direction parallel to the Z-axis as the "Z-axis direction." The tip of each axis in the direction of the arrow will also be referred to as the "plus side," and the opposite side as the "minus side." In the following, viewing in the Z-axis direction will be referred to as "planar view."

[0009] Furthermore, in the following description, for example, the expression "on a substrate" with respect to a substrate means that the substrate is disposed in contact with the substrate, that the substrate is disposed via another structure, or that a portion of the substrate is disposed in contact with the substrate and a portion of the substrate is disposed via another structure.

[0010] 1. Embodiment 1 In this embodiment, a liquid crystal device 300 will be described as an example of an electro-optical device. The liquid crystal device 300 is an active-drive transmissive liquid crystal device that includes a TFT (Thin Film Transistor) as a switching element for each pixel P. The liquid crystal device 300 is used as a light modulation device in, for example, a projection display device 1000 described below. In this embodiment, the projection display device 1000 is an example of an electronic device.

[0011] 1.1. Planar and cross-sectional structures of liquid crystal devices Fig. 1 is a plan view showing the planar structure of a liquid crystal device 300. Fig. 2 is a cross-sectional view showing the cross-sectional structure of the liquid crystal device 300, and shows a schematic cross-sectional structure of the liquid crystal device 300 taken along line II-II in Fig. 1. Note that the counter substrate 200 is not shown in Fig. 1.

[0012] 1 and 2, the liquid crystal device 300 includes a light-transmitting element substrate 100, a light-transmitting counter substrate 200 disposed opposite the element substrate 100, a frame-shaped seal member 90 provided between the element substrate 100 and the counter substrate 200, and a liquid crystal layer Lc. Note that "light-transmitting" refers to transparency to visible light, and preferably refers to a visible light transmittance of 50% or more.

[0013] As shown in FIG. 1, the liquid crystal device 300 has a display area A1 for displaying an image and a peripheral area A2 located outside the display area A1. The display area A1 is provided with a plurality of pixels P arranged in a matrix. The pixels P are provided at intersections with scanning lines 5 and data lines 6, which will be described later.

[0014] The peripheral area A2 is provided with the scanning line driving circuit 10, the data line driving circuit 20, the inspection circuit 30, the wirings 41, 51, 61, 62, 63, 71, the terminals 81, and the inter-substrate conductive portion 91. Although the liquid crystal device 300 and the display area A1 shown in FIG. 1 are rectangular, they may be of another shape, such as a circle.

[0015] The scanning line drive circuit 10 supplies scanning signals to the pixels P. In this embodiment, the scanning line drive circuit 10 includes a scanning line drive circuit 10a and a scanning line drive circuit 10b, which are provided along two opposing short sides of the display area A1. The scanning line drive circuit 10 may be configured with only one of the scanning line drive circuit 10a and the scanning line drive circuit 10b. However, configuring the scanning line drive circuit 10 with two circuits, the scanning line drive circuit 10a and the scanning line drive circuit 10b, allows the required drive load to be distributed, and therefore the size of the transistors constituting the scanning line drive circuits 10a and 10b can be reduced, making it more suitable for miniaturization.

[0016] A wiring area 40a between the scanning line driving circuit 10a and the display area A1 is provided with a plurality of wiring lines 41. Scanning signals are output to the plurality of wiring lines 41 from the scanning line driving circuit 10a.

[0017] A plurality of wiring lines 42 are arranged in a wiring area 40b between the scanning line driving circuit 10b and the display area A1. Scanning signals are output to the plurality of wiring lines 42 from the scanning line driving circuit 10b.

[0018] The distance 5D between both ends of the display region A1 in the Y-axis direction is narrower than the distance 10D between both ends of the scanning line driving circuit 10a in the Y-axis direction. Therefore, the planar shape of the routing wiring region 40a is trapezoidal, with the scanning line driving circuit 10a side having a larger area than the display region A1 side. Specifically, the distance 5D is the distance between the scanning line 5a arranged at one end of the display region A1 and the scanning line 5b arranged at the other end, as described below. Specifically, the distance 10D is the distance between the inverter circuit 151 corresponding to the scanning line 5a and the inverter circuit 152 corresponding to the scanning line 5b, among the multiple inverter circuits 15 constituting the scanning line driving circuit 10a, as described below.

[0019] In this embodiment, since the interval 10D is wider than the interval 5D, it is possible to use large-sized transistors that can handle the required driving load as the transistors that make up the scanning line driving circuit 10a. This will be described in detail later.

[0020] Similar to the scanning line driving circuit 10a, the scanning line driving circuit 10b also has a gap 10D. Therefore, the planar shape of the wiring region 40b is trapezoidal, with the scanning line driving circuit 10b side having a larger area than the display region A1 side.

[0021] In this embodiment, the interval 10D between the scanning line driving circuits 10b is wider than the interval 5D in the display area A1, so the arrangement pitch of the multiple unit circuits constituting the scanning line driving circuit 10b can be wider in the display area A1 than the arrangement pitch of the scanning lines 5. Therefore, in this embodiment, transistors having a size that can handle the required driving load can be used as the transistors constituting the scanning line driving circuit 10b, so that the liquid crystal device 300 can be made higher in resolution or smaller in size.

[0022] The data line driving circuit 20 supplies the pixels P with image signals. A plurality of lead wires 51 are arranged in a lead wire area 50 between the data line driving circuit 20 and the display area A1. Image signals are output from the data line driving circuit 20 to the plurality of lead wires 51.

[0023] The distance 6D between opposite ends of the display region A1 in the X-axis direction is narrower than the distance 20D between opposite ends of the data line driving circuit 20 in the X-axis direction. Therefore, the planar shape of the routing wiring region 50 is trapezoidal, with the area on the data line driving circuit 20 side being larger than that on the display region A1 side. Specifically, the distance 6D is the distance between the data line 6 arranged at one end of the display region A1 and the data line 6 arranged at the other end, as described below. Specifically, the distance 20D is the distance between the sampling transistor 231 serving as a unit circuit corresponding to the data line 6a arranged at one end of the data line driving circuit 20 and the sampling transistor 232 corresponding to the data line 6b arranged at the other end, as described below.

[0024] In this embodiment, because the interval 20D is wider than the interval 6D, the arrangement pitch of the multiple unit circuits that make up the data line driving circuit 20 can be wider in the display area A1 than the arrangement pitch of the data lines 6. Therefore, in this embodiment, transistors that are large enough to handle the required driving load can be used as transistors that make up the data line driving circuit 20, making it possible to achieve higher resolution or a smaller size for the liquid crystal device 300.

[0025] The inspection circuit 30 supplies inspection signals to the pixels P via a plurality of wiring lines 71 arranged in the wiring line region 70. The inter-substrate conductive portions 91 are arranged at the four corners of the peripheral area A2, and electrically connect the element substrate 100 and the counter substrate 200.

[0026] A plurality of terminals 81 are arranged in the terminal area 80. The terminals 81 are mounting terminals to which external connection lines such as FPCs (Flexible Printed Circuits) (not shown) are mounted. Various signals such as image signals, synchronization signals, inspection signals, common potentials, and power supply potentials are supplied to the terminals 81 from the outside via the external connection lines.

[0027] The plurality of terminals 81 are electrically connected to the scanning line driving circuit 10, the data line driving circuit 20, the inspection circuit 30, the inter-substrate conductive section 91, etc. via a plurality of routing wires 61, 62, 63 arranged in the routing wiring area 60. The plurality of routing wires 61 are electrically connected to the scanning line driving circuit 10. The plurality of routing wires 62 are electrically connected to the data line driving circuit 20. The plurality of routing wires 63 are electrically connected to the inspection circuit 30, the inter-substrate conductive section 91, etc.

[0028] As shown in FIG. 2, the element substrate 100 and the counter substrate 200 are disposed with a liquid crystal layer Lc interposed therebetween. In this embodiment, the counter substrate 200 is disposed on the light incident side of the liquid crystal layer Lc, and the element substrate 100 is disposed on the light emitting side of the liquid crystal layer Lc. Incident light IL incident on the counter substrate 200 is modulated by the liquid crystal layer Lc and emitted from the element substrate 100 as modulated light ML.

[0029] The element substrate 100 has a base 3, and pixel electrodes 1, a scanning line driving circuit 10, a data line driving circuit 20, an inspection circuit 30, wirings 41, 51, 61, 62, 63, 71, terminals 81, and inter-substrate conductive portions 91 provided on the base 3.

[0030] The base 3 is a flat plate having optical transparency and insulating properties. The base 3 is, for example, a glass substrate or a quartz substrate. A plurality of interlayer insulating layers (not shown) are provided on the base 3, and between the plurality of interlayer insulating layers, scanning lines 5, data lines 6, capacitance lines 7, transistors 8, and transistors 15n, 15p, 23, etc. constituting each of the driving circuits 10 and 20, which will be described later, are arranged.

[0031] A pixel electrode 1 is provided for each pixel P. The pixel electrode 1 is made of ITO (Indium Tin Oxide), which is light-transmitting. Alternatively, the pixel electrode 1 may be made of a transparent conductive material such as IZO (Indium Zinc Oxide) or FTO (Fluorine-doped tin oxide). A pixel potential corresponding to an image signal is supplied to the pixel electrode 1 via a data line 6.

[0032] The counter substrate 200 has a base 4, a common electrode 2 provided on the surface of the base 4 facing the pixel electrodes 1, and an inter-substrate conductive portion 91. The substrate 4 is a flat plate having light-transmitting and insulating properties, and is, for example, a glass substrate or a quartz substrate.

[0033] The common electrode 2 is an electrode disposed opposite the plurality of pixel electrodes 1, and can also be called a counter electrode. The common electrode 2 is made of a transparent conductive material such as ITO, IZO, or FTO. A common potential is supplied to the common electrode 2 from the outside via the terminal 81 and the inter-substrate conductive portion 91. The common electrode 2 and the pixel electrodes 1 apply an electric field corresponding to the common potential and the pixel potential to the liquid crystal layer Lc.

[0034] The sealing member 90 is disposed between the element substrate 100 and the counter substrate 200. The sealing member 90 is formed using an adhesive containing various curable resins such as epoxy resin. The sealing member 90 may also contain a gap material made of an inorganic material such as glass.

[0035] The liquid crystal layer Lc is disposed within an area surrounded by the element substrate 100, the counter substrate 200, and the sealing member 90. The liquid crystal layer Lc is an electro-optical layer whose optical properties change in response to the electric field generated by the pixel electrodes 1 and the common electrode 2. The liquid crystal layer Lc contains liquid crystal molecules with positive or negative dielectric anisotropy. The orientation of the liquid crystal molecules changes in response to the electric field applied to the liquid crystal layer Lc. The liquid crystal layer Lc modulates incident light IL in response to the applied electric field.

[0036] 1.2.Circuit configuration of LCD device FIG. 3 is a wiring diagram showing the circuit configuration of the liquid crystal device 300. As shown in FIG. As shown in FIG. 3, n scanning lines 5 and m data lines 6 are provided in the display region A1 of the element substrate 100, and pixels P are provided at each intersection of the n scanning lines 5 and the m data lines 6. The n scanning lines 5 are arranged along the X-axis direction, and the m data lines 6 are arranged along the Y-axis direction. n and m are each an integer of 2 or greater. In this embodiment, the m data lines 6 arranged along the Y-axis direction are an example of first wirings arranged along the first direction. Furthermore, the n scanning lines 5 arranged along the X-axis direction are an example of second wirings arranged along the second direction.

[0037] Scanning signal G1, G2, G3, G4, ..., Gn are respectively supplied from scanning line driving circuits 10a and 10b to the n scanning lines 5. In this embodiment, the scanning signals G1, G2, G3, G4, ..., Gn are supplied to the n scanning lines 5 in a line-sequential manner.

[0038] Image signals D1, D2, D3, D4, D5, ..., Dm are supplied to the m data lines 6 from the data line driving circuit 20. In this embodiment, the image signals D1, D2, D3, D4, D5, ..., Dm are supplied to the m data lines 6 by a phase expansion method or a demultiplexing method.

[0039] Inspection signals t1, t2, t3, t4, t5, . . . , tm are supplied to each of the m data lines 6 from an inspection circuit 30. The inspection circuit 30 is used during the manufacturing process or maintenance of the liquid crystal device 300 to detect defects in the pixels P.

[0040] 1.2.1. Circuit configuration of the scanning line driver circuit 4 is a wiring diagram showing the circuit configuration of the scanning line driving circuit 10a. Although not shown, the scanning line driving circuit 10b is also configured in the same way. As shown in FIG. 4, the scanning line driving circuit 10a is composed of a selection signal output circuit 11 and a plurality of logic circuits 18 provided corresponding to each output stage of the selection signal output circuit 11.

[0041] The scanning line driving circuit 10a is supplied with enable signals ENBY1 and ENBY2, a start signal DY, a clock signal CLY, a high potential power supply VDDY, and a low potential power supply VSSY via wiring 61.

[0042] The selection signal output circuit 11 is a shift register that sequentially transfers the start signal DY based on the clock signal CLY and outputs the transferred signal to the logic circuit 18 as a selection signal.

[0043] The logic circuit 18 includes a NAND circuit 12, an inverter circuit 13, a NAND circuit 14, and an inverter circuit 15, and performs waveform shaping on each selection signal output from the selection signal output circuit 11, and outputs it to each scanning line 5 as a scanning signal G1, etc.

[0044] Either the enable signal ENBY1 or the enable signal ENBY2 is input to the NAND circuit 14. The enable signals ENBY1 and ENBY2 are used to shape the waveform of the selection signal. This makes it possible to limit the pulse width of the selection signal to the pulse width of the enable signal ENBY1 or ENBY2, for example.

[0045] The scanning signals G1 and the like output from the inverter circuit 15 are supplied to the scanning lines 5 via the routing wiring 41. The scanning signals G1 and the like supplied to the scanning lines 5 are applied to the gate electrodes of the transistors 8 constituting the pixels P, thereby bringing the data lines 6 and the pixel electrodes 1 into conduction. In this embodiment, the inverter circuit 15 is an example of a second unit circuit. The scanning line driving circuit 10a is an example of a second driving circuit. The routing wiring 41 is an example of a second routing wiring.

[0046] A potential corresponding to an image signal D1 or the like is applied to the pixel electrode 1 via a data line 6. The potential applied to the pixel electrode 1 is held by a storage capacitor 9. One electrode of the storage capacitor 9 is electrically connected to the pixel electrode 1, and the other electrode is electrically connected to a capacitance line 7.

[0047] 1.2.2. Circuit configuration of the data line driver circuit 1.2.2.1. Demultiplexer Method Fig. 5A is a wiring diagram showing an example of the circuit configuration of the data line driving circuit 20. The data line driving circuit 20 shown in Fig. 5A is a demultiplexer type driving circuit. The data line driving circuit 20 divides the time-division multiplexed image signals D1 to D6 supplied to the image signal supply line 26 via the wiring 62 into six parts and supplies the divided parts to the respective data lines 6.

[0048] The sampling transistors 231, 232, 233, 234, 235, and 236 electrically connected to the same image signal supply line 26 are turned on in response to selection signals S1, S2, S3, S4, S5, and S6, and divide the time-division multiplexed image signals D1 to D6 into six, supplying the image signals D1, D2, D3, D4, D5, and D6 to the data lines 6, respectively. In this embodiment, the data line driving circuit 20 is an example of a first driving circuit. The sampling transistor 231 is an example of a first unit circuit. The number of time-division multiplexed image signals and the number of divisions are not limited to six. For example, they may be 12.

[0049] The data line driving circuit 20 includes a selection signal output circuit 21 and a sampling circuit 22. A start signal DX, a clock signal CLX, a high potential power supply VDDX, and a low potential power supply VSSX are supplied to the data line driving circuit 20 via wiring 62.

[0050] The selection signal output circuit 21 is a shift register. The selection signal output circuit 21 sequentially transfers the start signal DX based on the clock signal CLX, and outputs selection signals S1, S2, S3, S4, S5, and S6 to the group selection signal line group 25 via the selection signal output line 24. In this embodiment, the group selection signal line group 25 has group selection signal lines 251, 252, 253, 254, 255, and 256. The group selection signal line 251 is supplied with a selection signal S1, which is supplied to multiple data lines 6 of the same group electrically connected to the group selection signal line 251. The group selection signal line 252 is supplied with a selection signal S2, which is supplied to multiple data lines 6 of the same group electrically connected to the group selection signal line 252. The group selection signal lines 253, 254, 255, and 256 are configured in a similar manner.

[0051] The sampling circuit 22 includes a plurality of sampling transistors 23. The plurality of sampling transistors 23 configure a plurality of demultiplexers, each of which includes six sampling transistors. The sampling transistors 231, 232, 233, 234, 235, and 236 configure one demultiplexer.

[0052] Selection signals S1, S2, S3, S4, S5, and S6 are supplied from the selection signal output circuit 21 to the gates of the sampling transistors 231, 232, 233, 234, 235, and 236 via a selection signal output line 24 and a group selection signal line group 25.

[0053] The sources of the sampling transistors 231, 232, 233, 234, 235, and 236 are electrically connected to the same image signal supply line 26. Time-division multiplexed image signals D1 to D6 are input to the image signal supply line 26 from the wiring 62.

[0054] 1.2.2.2.Phase expansion method FIG. 5B is a wiring diagram showing another example of the circuit configuration of the data line driving circuit 20. As shown in FIG. 5B is a phase-expansion type drive circuit. The data line drive circuit 20 simultaneously supplies time-division multiplexed image signals, which are supplied to six image signal supply lines 26 via six wirings 62, to six adjacent data lines 6 at the timing of selection signals S1, S2, etc.

[0055] The sampling transistors 231, 232, 233, 234, 235, and 236 electrically connected to the same selection signal output line 24 are turned on in response to the selection signal S1, and supply image signals D1, D2, D3, D4, D5, and D6 to the data lines 6 from the image signal supply lines 26 to which they are electrically connected. In this embodiment, the number of adjacent data lines to which image signals are simultaneously supplied is not limited to six. It may be, for example, 30.

[0056] 1.3. Configuration and layout of scanning line driving circuit, wiring, and scanning lines Fig. 6A is a plan view showing the configuration and arrangement of the scanning line driving circuit 10a, the lead wiring 41, and the scanning lines 5. Fig. 6B is a partially enlarged plan view of Fig. 6A. Fig. 8 is a partially enlarged plan view of the display region A1.

[0057] FIG. 6A shows the configuration and arrangement of a plurality of inverter circuits 15 arranged in the output stage of the scanning line driving circuit 10a. 6A, the inverter circuit 15 includes an N-type transistor 15n and a P-type transistor 15p. The N-type transistor 15n and the P-type transistor 15p each include a semiconductor layer 17 having a drain region 17d, a source region 17s, and a channel region 17c.

[0058] A high-potential power supply VDDY is electrically connected to the source region 17s of the P-type transistor 15p via a contact hole 182. A low-potential power supply VSSY is electrically connected to the source region 17s of the N-type transistor 15n via a contact hole 182.

[0059] The channel regions 17c of the N-type transistor 15n and the P-type transistor 15p overlap with the gate line 16. The gate line 16 is electrically connected to the output terminal of the NAND circuit 14, and receives a selection signal from the NAND circuit 14. A lead wiring 41 is electrically connected to each drain region 17d of the N-type transistor 15n and the P-type transistor 15p via a contact hole 181.

[0060] Of the multiple inverter circuits 15, the inverter circuit 151 is arranged at the end on the positive side in the Y-axis direction. The inverter circuit 151 is electrically connected to the scanning line 5a via the routing wiring 411. The routing wiring 411 is arranged at the end on the positive side in the Y-axis direction of the multiple routing wirings 41, and the scanning line 5a is arranged at the end on the positive side in the Y-axis direction of the multiple scanning lines 5 arranged in the display region A1. In this embodiment, the multiple routing wirings 41 are an example of multiple second routing wirings.

[0061] Of the multiple inverter circuits 15, the inverter circuit 152 is arranged at the end on the negative side in the Y-axis direction. The inverter circuit 152 is electrically connected to the scanning line 5b via the routing wiring 412. The routing wiring 412 is arranged at the end on the negative side in the Y-axis direction of the multiple routing wirings 41, and the scanning line 5b is arranged at the end on the negative side in the Y-axis direction of the multiple scanning lines 5 arranged in the display region A1.

[0062] In the multiple inverter circuits 15, a distance 10D between the inverter circuit 151 arranged at one end and the inverter circuit 152 arranged at the other end is wider than a distance 5D between the scanning line 5a arranged at one end and the scanning line 5b arranged at the other end in the multiple scanning lines 5. In other words, the distance 5D is narrower than the distance 10D.

[0063] As described above, the N-type transistor 15n and the P-type transistor 15p that constitute the inverter circuit 15 have a higher driving load requirement than the transistor 8 that constitutes the pixel P. Therefore, the N-type transistor 15n and the P-type transistor 15p have a larger size than the transistor 8 that constitutes the pixel P. As shown in FIG. 6B, N-type transistor 15n and P-type transistor 15p have a channel length 17cL and a channel width 17cW.

[0064] 8 is a partially enlarged plan view of the display region A1. In FIG. 8, the transistor 8 of the pixel P is provided at a position corresponding to the intersection of the data line 6 and the scanning line 5. The source region 8s of the transistor 8 is electrically connected to the data line 6. The drain region 8d of the transistor 8 is electrically connected to the pixel electrode 1. The channel region 8c of the transistor 8 overlaps with a gate electrode 5G electrically connected to the scanning line 5. Transistor 8 has a channel length 8cL and a channel width 8cW.

[0065] The channel length 17cL and the channel width 17cW of the N-type transistor 15n and the P-type transistor 15p are greater than the channel length 8cL and the channel width 8cW of the transistor 8 that constitutes the pixel P, respectively.

[0066] In this embodiment, when the pixel pitch PD is 6 μm, the channel length 17cL of the N-type transistor 15n and the P-type transistor 15p is 2 μm to 3 μm, and preferably 2.25 μm. The N-type transistor 15n and the P-type transistor 15p are required to withstand a higher voltage than the sampling transistor 23 described below. Therefore, the channel length 17cL of the N-type transistor 15n and the P-type transistor 15p is longer than the channel length 27cL of the sampling transistor 23 described below.

[0067] In this embodiment, when the pixel pitch PD is 6 μm, the channel width 17cW of the N-type transistor 15n and the P-type transistor 15p is 3 μm to 100 μm, and preferably 50 μm.

[0068] In this embodiment, when the pixel pitch PD is 6 μm, the channel length 8cL of the transistor 8 is 1.0 μm to 1.5 μm, and preferably 1.3 μm, and the channel width 8cW of the transistor 8 is 0.3 μm.

[0069] Thus, N-type transistor 15n and P-type transistor 15p are larger in size than transistor 8 constituting pixel P. However, because distance 10D between inverter circuit 151 arranged at one end and inverter circuit 152 arranged at the other end is wider than distance 5D between scanning line 5a arranged at one end and scanning line 5b arranged at the other end, inverter circuit 15 capable of handling a high driving load can be provided in peripheral region A2.

[0070] 6A, the interval 10D is larger than the interval 5D. Therefore, the planar shape of the routing wiring region 40a where the plurality of routing wirings 41 are arranged is trapezoidal, with the area on the scanning line driving circuit 10a side being larger than that on the display region A1 side.

[0071] The plurality of routing wires 41 are arranged in such a trapezoidal routing wire region 40a such that the interval between adjacent routing wires 41 is narrower on the display region A1 side than on the inverter circuit 15 side. Specifically, of the intervals 413D1 and 413D2 between the routing wires 411 and the routing wires 413 adjacent to the routing wires 411, the interval 413D2 on the display region A1 side is narrower than the interval 413D1 on the inverter circuit 15 side.

[0072] In this manner, in this embodiment, the length of the routing wiring 41 can be shortened by arranging the wiring 41 so that the distance between adjacent wirings 41 is narrower on the display area A1 side than on the inverter circuit 15 side. This prevents the electrical resistance of the routing wiring 41 from increasing, and reduces the driving load of the scanning line driving circuit 10. This makes it possible to realize a configuration suitable for miniaturization.

[0073] Since the plurality of routing wires 41 are arranged in such a trapezoidal routing wire region 40a, the wiring width of each of the plurality of routing wires 41 arranged at one end and the other end of the plurality of routing wires 41 is wider than the wiring width of the routing wire 41 arranged in the middle of the plurality of routing wires 41. Specifically, the wiring width 411W of the routing wire 411 and the wiring width 412W of the routing wire 412 are wider than the wiring width 414W of the routing wire 414 arranged between the routing wire 411 and the routing wire 412.

[0074] Of the plurality of routing wires 41, the routing wires 411 and 412 arranged at the ends have a longer wiring length than the routing wire 414 arranged between the routing wires 411 and 412. However, in this embodiment, by making the wiring width 411W of the routing wire 411 and the wiring width 412W of the routing wire 412 wider than the wiring width 414W of the routing wire 414, it is possible to prevent the electrical resistance of the routing wires 411 and 412 from increasing, and to reduce the driving load of the scanning line driving circuit 10. Therefore, a configuration suitable for miniaturization can be realized.

[0075] 6A and 6B, the multiple inverter circuits 15 are arranged at a predetermined interval 15D. The interval 15D is larger than the interval 413D2 and the pixel pitch PD shown in FIG. 8. In other words, the interval 413D2 between adjacent routing wirings 411 and 413 on the display region A1 side is smaller than the interval 15D between adjacent inverter circuits 151 and 153 in the scanning line driving circuit 10. Therefore, even if the arrangement pitch of the pixels P and the arrangement pitch of the inverter circuits 15 are configured to be different, the multiple routing wirings 41 can be efficiently arranged between them, resulting in a configuration suitable for miniaturization. In this embodiment, when the pixel pitch PD is 6 μm, the interval 15D is 7 μm to 8.5 μm.

[0076] 6B, inverter circuit 151 and inverter circuit 153 adjacent to inverter circuit 151 share source region 17s. In other words, inverter circuit 151 and inverter circuit 153 have a configuration inverted with respect to source region 17s. This configuration allows for smaller intervals 15D and 10D, making it possible to configure multiple inverter circuits 15 in a manner suitable for miniaturization.

[0077] 4, 6A, and 6B, the inverter circuit 15 is used as the output stage of the scanning line driving circuit 10, but the NAND circuit 14 may be used as the output stage of the scanning line driving circuit 10. In this case, the arrangement pitch of the NAND circuits 14 and the channel length and channel width of the transistors constituting the NAND circuits 14 are configured in the same manner as the inverter circuit 15.

[0078] 1.4. Configuration and layout of data line driving circuit, routing wiring, and data lines Fig. 7A is a plan view showing the configuration and arrangement of the data line driving circuit 20, the routing wiring 51, and the data lines 6. Fig. 7B is a partially enlarged plan view of Fig. 7A.

[0079] FIG. 7A shows the configuration and arrangement of the sampling circuit 22 of the demultiplexer type data line driving circuit 20 shown in FIG. 5A. 7A, the sampling circuit 22 includes a plurality of sampling transistors 23. Each of the plurality of sampling transistors 23 includes a semiconductor layer 27 having a drain region 27d, a source region 27s, and a channel region 27c.

[0080] An image signal supply line 26 is electrically connected to a source region 27s of the sampling transistor 23. A selection signal output line 24 overlaps a channel region 27c of the sampling transistor 23. The selection signal output line 24 is electrically connected to a selection signal output circuit 21 and a group selection signal line group 25, and receives a selection signal S1 and the like from the selection signal output circuit 21.

[0081] Of the multiple sampling transistors 23, the sampling transistor 231 is arranged at the end on the negative side in the X-axis direction. The sampling transistor 231 is electrically connected to the data line 6a via a routing wiring 511. The routing wiring 511 is arranged at the end on the negative side in the X-axis direction of the multiple routing wirings 51, and the data line 6a is arranged at the end on the negative side in the X-axis direction of the multiple data lines 6 arranged in the display area A1. In this embodiment, the multiple routing wirings 51 are an example of multiple first routing wirings.

[0082] Of the multiple sampling transistors 23, the sampling transistor 232 is arranged at the end on the positive side in the X-axis direction. The sampling transistor 232 is electrically connected to the data line 6b via a routing wiring 512. The routing wiring 512 is arranged at the end on the positive side in the X-axis direction of the multiple routing wirings 51, and the data line 6b is arranged at the end on the positive side in the X-axis direction of the multiple data lines 6 arranged in the display region A1.

[0083] In the plurality of sampling transistors 23, a distance 20D between the sampling transistor 231 arranged at one end and the sampling transistor 232 arranged at the other end is wider than a distance 6D between the data line 6a arranged at one end and the data line 6b arranged at the other end in the plurality of data lines 6. In other words, the distance 6D is narrower than the distance 20D.

[0084] As described above, the sampling transistor 23 constituting the sampling circuit 22 requires a higher driving load than the transistor 8 constituting the pixel P. Therefore, the sampling transistor 23 has a larger size than the transistor 8 constituting the pixel P.

[0085] As shown in FIG. 7B, the sampling transistor 23 has a channel length 27cL and a channel width 27cW. In this embodiment, when the pixel pitch PD is 6 μm, the channel length 27cL of the sampling transistor 23 is 1.5 μm to 3 μm, and preferably 1.6 μm, and the channel width 27cW of the sampling transistor 23 is 5 μm to 400 μm, and preferably 200 μm.

[0086] In this way, the sampling transistor 23 has a size larger than the transistor 8 that constitutes the pixel P. However, since the distance 20D between the sampling transistor 231 arranged at one end and the sampling transistor 232 arranged at the other end is wider than the distance 6D between the data line 6a arranged at one end and the data line 6b arranged at the other end, it is possible to provide the sampling transistor 23 in the peripheral region A2 with the ability to handle a high driving load.

[0087] 7A, the interval 20D is larger than the interval 6D. Therefore, the planar shape of the routing wiring area 50 in which the multiple routing wirings 51 are arranged is trapezoidal, with the area on the data line driving circuit 20 side being larger than that on the display area A1 side.

[0088] The plurality of routing wires 51 are arranged in such a trapezoidal routing wire region 50 such that the interval between adjacent routing wires 51 is narrower on the display region A1 side than on the sampling circuit 22 side. Specifically, of the intervals 513D1 and 513D2 between the routing wires 511 and the routing wires 513 adjacent to the routing wires 511, the interval 513D2 on the display region A1 side is narrower than the interval 513D1 on the sampling circuit 22 side.

[0089] In this manner, in this embodiment, the length of the routing lines 51 can be shortened by arranging the spacing between adjacent routing lines 51 so that it is narrower on the display area A1 side than on the sampling circuit 22 side. This prevents the electrical resistance of the routing lines 51 from increasing, and reduces the driving load of the sampling circuit 22 of the data line driving circuit 20. This makes it possible to realize a configuration that is suitable for miniaturization.

[0090] Since the plurality of routing wires 51 are arranged in such a trapezoidal routing wire region 50, the wiring width of each of the plurality of routing wires 51 arranged at one end and the other end of the plurality of routing wires 51 is wider than the wiring width of the routing wire 51 arranged in the middle of the plurality of routing wires 51. Specifically, the wiring width 511W of the routing wire 511 and the wiring width 512W of the routing wire 512 are wider than the wiring width 514W of the routing wire 514 arranged between the routing wire 511 and the routing wire 512.

[0091] Among the plurality of routing lines 51, the routing lines 511 and 512 arranged at the ends have a longer wiring length than the routing line 514 arranged between the routing lines 511 and 512. However, in this embodiment, the wiring width 511W of the routing line 511 and the wiring width 512W of the routing line 512 are wider than the wiring width 514W of the routing line 514. This prevents the electrical resistance of the routing line 511 and the routing line 512 from increasing, thereby reducing the driving load of the data line driving circuit 20. This provides a configuration suitable for miniaturization.

[0092] 7A and 7B, the plurality of sampling transistors 23 are arranged at a predetermined interval 23D. The interval 23D is larger than the interval 513D2 and the pixel pitch PD shown in FIG. 8. In other words, the interval 513D2 between adjacent routing lines 511 and 513 on the display region A1 side is narrower than the interval 23D between adjacent sampling transistors 231 and 233 in the data line driving circuit 20. Therefore, even if the arrangement pitch of the pixels P and the arrangement pitch of the sampling transistors 23 are configured to differ, the plurality of routing lines 51 can be efficiently arranged between them, resulting in a configuration suitable for miniaturization. In this embodiment, when the pixel pitch PD is 6 μm, the interval 23D is 7 μm to 8.5 μm.

[0093] 7B , the sampling transistor 231 and the sampling transistor 233 adjacent to the sampling transistor 231 share the source region 27s. In other words, the sampling transistor 233 and the sampling transistor 231 have a configuration inverted with respect to the source region 27s. This configuration can reduce the interval 23D and the interval 20D, and therefore can provide a configuration suitable for miniaturization of the multiple sampling transistors 23.

[0094] 7A shows the configuration and arrangement of the sampling circuit 22 of the demultiplexer type data line driving circuit 20 shown in FIG. 5A, but the same applies to the phase expansion type data line driving circuit 20 shown in FIG. 5B.

[0095] As described above, the liquid crystal device 300 as an electro-optical device of this embodiment can provide the following effects. The liquid crystal device 300 of this embodiment includes a plurality of data lines 6 as a plurality of first wirings arranged along the Y-axis direction as a first direction in the display region A1, a data line driving circuit 20 as a first driving circuit arranged along the X-axis direction as a second direction intersecting the Y-axis direction in a peripheral region A2 outside the display region A1 and having a plurality of sampling transistors 23 as a plurality of first unit circuits, and a plurality of sampling transistors 23 arranged between the display region A1 and the data line driving circuit 20. and a plurality of routing wires 51 as a plurality of first routing wires electrically connecting the data line driving circuit 20 and the data line 6a arranged at one end of the plurality of data lines 6 and the data line 6b arranged at the other end, a distance 6D between the data line 6a arranged at one end of the plurality of data lines 6 and the data line 6b arranged at the other end is narrower than a distance 20D between the sampling transistor 231 arranged at one end of the plurality of sampling transistors 23 and the sampling transistor 232 arranged at the other end, and with regard to distances 513D1 and 513D2 between adjacent routing wires 511 and 513 of the plurality of routing wires 51, the distance 513D2 on the display area A1 side is narrower than the distance 513D1 on the data line driving circuit 20 side.

[0096] Thus, the interval 6D is narrower than the interval 20D. In other words, the interval 20D is wider than the interval 6D. Therefore, the peripheral region A2 can be provided with a sampling transistor 23 capable of supporting a higher driving load than the transistor 8 of the pixel P. Furthermore, with regard to the intervals 513D1 and 513D2 between adjacent routing lines 511 and 513, the interval 513D2 on the display area A1 side is narrower than the interval 513D1 on the data line driving circuit 20 side. Therefore, the routing lines 51 can be efficiently arranged between the data line driving circuit 20 and the display area A1, and the routing lines 51 are prevented from becoming long. Therefore, the driving load of the sampling circuit 22 can be reduced, and a configuration suitable for miniaturization can be realized. As described above, according to this embodiment, the display area A1, the data line driving circuit 20, and the plurality of wirings 51 can be configured to be suitable for miniaturization, thereby realizing a liquid crystal device 300 with high resolution and / or miniaturization.

[0097] In the liquid crystal device 300 of this embodiment, the wiring width 511W of the wiring 511 arranged at one end of the multiple wirings 51 and the wiring width 512W of the wiring 512 arranged at the other end are each wider than the wiring width 514W of the wiring 514 arranged between the wiring 511 arranged at one end and the wiring 512 arranged at the other end.

[0098] Since the interval 6D is narrower than the interval 20D, the routing lines 511 and 512 have a longer wiring length than the routing line 514. However, in this embodiment, the wiring width 511W of the routing line 511 and the wiring width 512W of the routing line 512 are wider than the wiring width 514W of the routing line 514. This prevents the electrical resistance of the routing lines 511 and 512 from increasing, thereby reducing the driving load of the data line driving circuit 20. Therefore, according to this embodiment, the configuration of the multiple routing lines 51 can be made suitable for miniaturization.

[0099] In the liquid crystal device 300 of this embodiment, the interval 513D2 between adjacent wiring lines 51 on the display area A1 side of the plurality of wiring lines 51 is narrower than the interval 23D between adjacent sampling transistors 23 among the plurality of sampling transistors 23. Therefore, the plurality of lead wirings 51 can be efficiently arranged between the display area A1 and the data line driving circuit 20, and a configuration suitable for miniaturization can be realized.

[0100] The liquid crystal device 300 of this embodiment comprises a transistor 8 as a first transistor arranged in the display area A1 and electrically connected to the data line 6, and a sampling transistor 23 as a second transistor arranged in the peripheral area A2 and constituting a first unit circuit, and the channel length 8cL of the transistor 8 is shorter than the channel length 27cL of the sampling transistor 23. Therefore, the display area A1 can be miniaturized while maintaining the voltage resistance of the sampling transistor 23.

[0101] The liquid crystal device 300 of this embodiment comprises a transistor 8 as a first transistor electrically connected to a data line 6, and a sampling transistor 23 as a second transistor arranged in the peripheral region A2 and constituting a first unit circuit, and the channel width 8cW of the transistor 8 is narrower than the channel width 27cW of the sampling transistor 23. Therefore, the display area A1 can be miniaturized while maintaining the current resistance of the sampling transistor 23.

[0102] In the liquid crystal device 300 of this embodiment, in the display region A1, a plurality of scanning lines 5 as a plurality of second wirings arranged along the X-axis direction, a scanning line driving circuit 10 as a second driving circuit arranged along the Y-axis direction in the peripheral region A2 and having a plurality of inverter circuits 15 as a plurality of second unit circuits, and inverter circuits 15 are arranged between the display region A1 and the scanning line driving circuit 10, each of which electrically connects one of the plurality of scanning lines 5 to one of the plurality of inverter circuits 15. and routing wirings 41 as a plurality of second routing wirings, a distance 5D between a scanning line 5a arranged at one end of the plurality of routing wirings 41 and a scanning line 5b arranged at the other end is narrower than a distance 10D between an inverter circuit 151 arranged at one end of the plurality of inverter circuits 15 and an inverter circuit 152 arranged at the other end, and distances 413D1 and 413D2 between adjacent routing wirings 411 and 413 of the plurality of routing wirings 41 are narrower on the display area A1 side than on the scanning line driving circuit 10 side.

[0103] Thus, the interval 5D is narrower than the interval 10D. In other words, the interval 10D is wider than the interval 5D. Therefore, the inverter circuit 15 capable of supporting a higher driving load than the transistor 8 of the pixel P can be provided in the peripheral area A2. Furthermore, with respect to the intervals 413D1 and 413D2 between adjacent routing lines 411 and 413, the interval 413D2 on the display area A1 side is narrower than the interval 413D1 on the scanning line driving circuit 10 side. Therefore, the routing lines 41 can be efficiently arranged between the scanning line driving circuit 10 and the display area A1, and the routing lines 41 are prevented from becoming long. Therefore, the driving load of the inverter circuit 15 can be reduced, and a configuration suitable for miniaturization can be realized. As described above, according to this embodiment, the display area A1, the scanning line driving circuit 10, and the plurality of wirings 41 can be configured to be suitable for miniaturization, thereby realizing a liquid crystal device 300 with high resolution and / or miniaturization.

[0104] In the liquid crystal device 300 of this embodiment, the wiring width 411W of the wiring 411 arranged at one end of the multiple wirings 41 and the wiring width 412W of the wiring 412 arranged at the other end are each wider than the wiring width 414W of the wiring 414 arranged between the wiring 411 arranged at one end and the wiring 412 arranged at the other end.

[0105] Since the interval 5D is narrower than the interval 10D, the routing wires 411 and 412 have a longer wiring length than the routing wire 414. However, in this embodiment, the wiring width 411W of the routing wire 411 and the wiring width 412W of the routing wire 412 are wider than the wiring width 414W of the routing wire 414. Therefore, the electrical resistance of the routing wires 411 and 412 is prevented from increasing, and the driving load of the scanning line driving circuit 10 can be reduced. Therefore, according to this embodiment, the configuration of the plurality of routing wires 41 can be made suitable for miniaturization.

[0106] In the liquid crystal device 300 of this embodiment, the distance 413D2 between adjacent wiring lines 41 on the display area A1 side of the plurality of wiring lines 41 is narrower than the distance 15D between adjacent inverter circuits 15 among the plurality of inverter circuits 15. Therefore, the plurality of wiring lines 41 can be efficiently arranged between the display area A1 and the scanning line driving circuit 10, and a configuration suitable for miniaturization can be realized.

[0107] The liquid crystal device 300 of this embodiment includes a transistor 8 as a third transistor arranged in the display area A1 and electrically connected to the scanning line 5, and an N-type transistor 15n and a P-type transistor 15p as fourth transistors arranged in the peripheral area A2 and constituting the inverter circuit 15, and the channel length 8cL of the transistor 8 is shorter than the channel length 17cL of the N-type transistor 15n and the P-type transistor 15p. Therefore, the display area A1 can be miniaturized while maintaining the voltage resistance of the N-type transistor 15n and the P-type transistor 15p.

[0108] The liquid crystal device 300 of this embodiment includes a transistor 8 as a third transistor arranged in the display area A1 and electrically connected to the scanning line 5, and an N-type transistor 15n and a P-type transistor 15p as fourth transistors arranged in the peripheral area A2 and constituting the inverter circuit 15, and the channel width 8cW of the transistor 8 is narrower than the channel width 17cW of the N-type transistor 15n and the P-type transistor 15p. Therefore, the display area A1 can be miniaturized while maintaining the current resistance of the N-type transistor 15n and the P-type transistor 15p.

[0109] In the liquid crystal device 300 of this embodiment, the first unit circuit is composed of one sampling transistor 23 that constitutes a sampling circuit serving as a selection circuit, and the second unit circuit is composed of an inverter circuit 15 or a NAND circuit 14. Therefore, according to this embodiment, it is possible to satisfy the required driving load and realize a configuration suitable for miniaturization.

[0110] 2. Embodiment 2 FIG. 9 is a schematic diagram showing an example of an electronic device, and is a schematic diagram showing a schematic configuration of a projection display device 1000 as the electronic device. The projection display device 1000 is, for example, a three-panel projector equipped with three of the above-described liquid crystal devices 300. The liquid crystal device 300R corresponds to the display color red, the liquid crystal device 300G corresponds to the display color green, and the liquid crystal device 300B corresponds to the display color blue. The control unit 1005 includes, for example, a processor and memory, and controls the operations of the liquid crystal devices 300R, 300G, and 300B.

[0111] The illumination optical system 1001 supplies red light ILR of the light emitted from the illumination device 1002, which is a light source, to the liquid crystal device 300R, green light ILG to the liquid crystal device 300G, and blue light ILB to the liquid crystal device 300B. Each of the liquid crystal devices 300R, 300G, and 300B functions as a light modulation device that modulates the color light ILR, ILG, and ILB supplied from the illumination optical system 1001 in accordance with the displayed image. The projection optical system 1003 combines the light emitted from the liquid crystal device 300R, the liquid crystal device 300G, and the liquid crystal device 300B, and projects the combined light onto the screen 1004.

[0112] As described above, the projection display device 1000 serving as the electronic device of this embodiment includes the liquid crystal device 300 described above. Therefore, by employing the liquid crystal device 300 of this embodiment, the performance of the projection display device 1000 can be improved.

[0113] The electronic device is not limited to the exemplified three-panel projector. For example, it may be a single-panel projector, a two-panel projector, or a projector equipped with four or more liquid crystal devices 300. The electronic device may also be a smartphone, a PDA (Personal Digital Assistant), a camera, a television, a car navigation device, a personal computer, a display, electronic paper, a calculator, a videophone, a POS (Point of Sale), a printer, a scanner, a copier, a video player, or a device equipped with a touch panel.

[0114] Although the preferred embodiment has been described above, the present invention is not limited to the above embodiment. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above embodiment, and any configuration can be added. [Explanation of symbols]

[0115] 1...pixel electrode, 2...common electrode, 3, 4...base, 5, 5a, 5b...scanning line, 5D...interval, 5G...gate electrode, 6, 6a, 6b...data line, 6D...interval, 7...capacitor line, 8...transistor, 8c...channel region, 8cL...channel length, 8cW...channel width, 8d...drain region, 8s...source region, 9...storage capacitor, 10, 10a, 10b...scanning line drive circuit, 10D...interval, 11...selection signal output circuit, 12...NAND circuit, 13...inverter circuit, 14...NAND circuit, 15...inverter circuit, 15D...interval, 15n...N-type transistor, 15p...P-type transistor Transistor, 151, 152, 153... inverter circuit, 181, 182... contact hole, 16... gate line, 17... semiconductor layer, 17cL... channel length, 17cW... channel width, 17c... channel region, 17d... drain region, 17s... source region, 18... logic circuit, 20... data line driving circuit, 20D... spacing, 21... selection signal output circuit, 22... sampling circuit, 23, 231, 232, 233, 234, 235, 236... sampling transistor, 23D... spacing, 24... selection signal output line, 25... series selection signal line group, 251, 252, 253, 2 54, 255, 256...series selection signal lines, 26...image signal supply line, 27...semiconductor layer, 27cL...channel length, 27cW...channel width, 27c...channel region, 27d...drain region, 27s...source region, 30...inspection circuit, 40a, 40b...routing wiring area, 41...routing wiring, 411, 412, 413, 414...routing wiring, 413D1, 413D2...spacing, 411W, 412W, 414W...wiring width, 42...routing wiring, 50...routing wiring area, 51...routing wiring, 511, 512, 513, 514...routing wiring, 511W, 512W...wiring width, 513D 1,513D2...spacing, 60...routing wiring area, 61, 62, 63...routing wiring, 70...routing wiring area, 71...routing wiring, 80...terminal area, 81...terminal, 90...sealing member, 91...inter-substrate conductive portion, 100...element substrate, 200...opposing substrate, 300, 300B, 300G, 300R...liquid crystal device, 1000...projection display device, 1001...illumination optical system, 1002...illumination device, 1003...projection optical system, 1004...screen, 1005...control unit, ENBY1, ENBY2...enable signal, DX, DY...start signal, CLX, CLY...clock signal, VDDX,VDDY...high potential power supply, VSSX, VSSY...low potential power supply, A1...display area, A2...peripheral area, D1, D2, D3, D4, D5, D6, Dm...image signal, G1, G2, G3, G4, Gn...scanning signal, S1, S2, S3, S4, S5, S6...selection signal, t1, t2, t3, t4, t5, tm...inspection signal, Lc...liquid crystal layer, IL...incident light, ILR...red light, ILG...green light, ILB...blue light, ML...modulated light, P...pixel, PD...pixel pitch

Claims

1. a plurality of first wirings arranged along a first direction in a display region; a first driving circuit arranged outside the display area along a second direction intersecting the first direction, the first driving circuit having a plurality of first unit circuits; a plurality of first routing wirings arranged between the display area and the first drive circuit, each of which electrically connects one of the plurality of first wirings to one of the plurality of first unit circuits; a distance between a first wiring arranged at one end of the plurality of first wirings and a first wiring arranged at the other end is narrower than a distance between a first unit circuit arranged at one end of the plurality of first unit circuits and a first unit circuit arranged at the other end; a distance between adjacent first routing wires among the plurality of first routing wires is narrower on the display area side than on the first drive circuit side; Electro-optical device.

2. a wiring width of the first wiring wiring arranged at one end of the plurality of first wiring wirings and a wiring width of the first wiring wiring arranged at the other end are each wider than a wiring width of the first wiring wiring arranged between the first wiring wiring arranged at the one end and the first wiring wiring arranged at the other end; The electro-optical device according to claim 1 .

3. a distance between adjacent first routing wirings on the display area side among the plurality of first routing wirings is narrower than a distance between adjacent first unit circuits among the plurality of first unit circuits; The electro-optical device according to claim 1 .

4. a first transistor disposed in the display region and electrically connected to the first wiring; a second transistor that is disposed outside the display area and that constitutes the first unit circuit; The channel length of the first transistor is shorter than the channel length of the second transistor. The electro-optical device according to claim 1 .

5. a first transistor disposed in the display region and electrically connected to the first wiring; a second transistor that is disposed outside the display area and that constitutes the first unit circuit; The channel width of the first transistor is narrower than the channel width of the second transistor. The electro-optical device according to claim 1 .

6. a plurality of second wirings arranged along the second direction in the display region; a second driving circuit arranged along the first direction outside the display area and including a plurality of second unit circuits; a plurality of second routing wirings arranged between the display area and the second drive circuit, each of which electrically connects one second wiring of the plurality of second wirings to one second unit circuit of the plurality of second unit circuits; a distance between a second wiring arranged at one end of the plurality of second wirings and a second wiring arranged at the other end is narrower than a distance between a second unit circuit arranged at one end of the plurality of second unit circuits and a second unit circuit arranged at the other end; a distance between adjacent second routing lines among the plurality of second routing lines is narrower on the display area side than on the second drive circuit side; The electro-optical device according to claim 1 .

7. a wiring width of the second routing wire arranged at one end of the plurality of second routing wires and a wiring width of the second routing wire arranged at the other end are each wider than a wiring width of the second routing wire arranged between the second routing wire arranged at the one end and the second routing wire arranged at the other end; 7. The electro-optical device according to claim 6.

8. a distance between adjacent second routing lines on the display area side among the plurality of second routing lines is narrower than a distance between adjacent second unit circuits among the plurality of second unit circuits; 7. The electro-optical device according to claim 6.

9. a third transistor disposed in the display region and electrically connected to the second wiring; a fourth transistor that is disposed outside the display area and that constitutes the second unit circuit; The channel length of the third transistor is shorter than the channel length of the fourth transistor.

7. The electro-optical device according to claim 6.

10. a third transistor disposed in the display region and electrically connected to the second wiring; a fourth transistor that is disposed outside the display area and that constitutes the second unit circuit; The channel width of the third transistor is narrower than the channel width of the fourth transistor.

7. The electro-optical device according to claim 6.

11. the first unit circuit is configured by one transistor that configures a selection circuit, the second unit circuit is configured by an inverter circuit or a NAND circuit; 7. The electro-optical device according to claim 6.

12. 12. An electronic device comprising the electro-optical device according to claim 1.

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