Photoelectric conversion device and photoelectric conversion system

Abstract

To provide a photoelectric conversion device and a photoelectric conversion system that can reduce chip area and power consumption.SOLUTION: A photoelectric conversion device includes a photoelectric conversion unit and an output unit that outputs a signal based on charges generated in the photoelectric conversion unit, and includes a pixel to which a first power supply voltage is supplied at the output unit, a signal output line connected to the pixel, a level shift circuit which is connected to the signal output line to level-shift the output signal of the pixel in a direction that decreases the voltage and outputs it, and a signal processing circuit connected to the level shift circuit to perform predetermined signal processing on the output signal of the level shift circuit, and a second power supply voltage supplied to the signal processing circuit is lower than the first power supply voltage.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system. [Background technology]

[0002] In a photoelectric conversion device such as a CMOS image sensor, pixel signals output from each column of a pixel array are subjected to signal processing such as predetermined amplification processing and analog-to-digital conversion processing in a column circuit provided corresponding to each column. Patent Document 1 describes a solid-state imaging device having column circuits including analog-to-digital conversion circuits and amplification circuits. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-030002 Summary of the Invention [Problem to be solved by the invention]

[0004] As the size of pixel arrays increases, the size of peripheral circuits, including column circuits, also increases. Therefore, from the perspective of reducing the chip area and power consumption of photoelectric conversion devices, there is a demand for smaller area and lower power consumption for column circuits as well.

[0005] An object of the present invention is to provide a photoelectric conversion device and a photoelectric conversion system that can realize a smaller chip area and lower power consumption. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a photoelectric conversion device comprising: a pixel having a photoelectric conversion unit and an output unit that outputs a signal based on charges generated by the photoelectric conversion unit, wherein a first power supply voltage is supplied to the output unit; a signal output line connected to the pixel; a level shift circuit connected to the signal output line that level-shifts the output signal of the pixel in a direction decreasing the voltage and outputs the signal; and a signal processing circuit connected to the level shift circuit that performs predetermined signal processing on the output signal of the level shift circuit, wherein a second power supply voltage supplied to the signal processing circuit is lower than the first power supply voltage.

[0007] According to another disclosure of this specification, there is provided a photoelectric conversion device having a pixel having a photoelectric conversion unit and an output unit that outputs a signal based on charges generated in the photoelectric conversion unit, a signal output line connected to the pixel, a level shift circuit connected to the signal output line that level-shifts the output signal of the pixel in a direction that decreases the voltage and outputs the signal, and a signal processing circuit connected to the level shift circuit and having a capacitive element to which the output signal of the level shift circuit is input. [Effects of the Invention]

[0008] According to the present invention, it is possible to reduce the area and power consumption of a photoelectric conversion device. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment. [Figure 2] 1 is a circuit diagram showing an example of the configuration of a pixel in a photoelectric conversion device according to a first embodiment. [Figure 3] 2 is a circuit diagram showing an example of the configuration of a column circuit in the photoelectric conversion device according to the first embodiment. FIG. [Figure 4] 2 is a circuit diagram showing a configuration example of an AD conversion circuit in the photoelectric conversion device according to the first embodiment. FIG. [Figure 5] 1 is a schematic diagram illustrating an example of the configuration of a photoelectric conversion device according to a first embodiment. [Figure 6]FIG. 3 is a timing chart showing the operation of the photoelectric conversion device according to the first embodiment. [Figure 7] FIG. 2 is a schematic cross-sectional view showing the structure of a capacitive element. [Figure 8] FIG. 4 is a circuit diagram (part 1) showing another example of the configuration of the column circuit in the photoelectric conversion device according to the first embodiment. [Figure 9] FIG. 4 is a circuit diagram (part 2) showing another example of the configuration of the column circuit in the photoelectric conversion device according to the first embodiment. [Figure 10] FIG. 10 is a circuit diagram (part 3) showing another example of the configuration of the column circuit in the photoelectric conversion device according to the first embodiment. [Figure 11] FIG. 10 is a circuit diagram (part 4) showing another example of the configuration of the column circuit in the photoelectric conversion device according to the first embodiment. [Figure 12] FIG. 10 is a circuit diagram showing an example of the configuration of a level shift circuit in a photoelectric conversion device according to a second embodiment. [Figure 13] FIG. 10 is a circuit diagram showing an example of the configuration of a level shift circuit in a photoelectric conversion device according to a third embodiment. [Figure 14] FIG. 10 is a circuit diagram showing an example of the configuration of a level shift circuit in a photoelectric conversion device according to a fourth embodiment. [Figure 15] FIG. 10 is a circuit diagram showing an example of the configuration of a current source and a level shift circuit in a photoelectric conversion device according to a fifth embodiment. [Figure 16] FIG. 13 is a circuit diagram showing an example of the configuration of a level shift circuit in a photoelectric conversion device according to a sixth embodiment. [Figure 17] FIG. 13 is a circuit diagram showing another example of the configuration of the current source and the level shift circuit in the photoelectric conversion device according to the sixth embodiment. [Figure 18] FIG. 13 is a block diagram showing a schematic configuration of a photoelectric conversion system according to a seventh embodiment. [Figure 19] FIG. 13 is a diagram illustrating an example of the configuration of a photoelectric conversion system and a moving body according to an eighth embodiment. [Figure 20] FIG. 13 is a block diagram showing a schematic configuration of a device according to a ninth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, an apparatus for image capture will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to this apparatus for image capture, and can also be applied to other examples of photoelectric conversion devices. For example, there are distance measurement devices (devices for measuring distance using focus detection or TOF (Time Of Flight)), photometry devices (devices for measuring the amount of incident light, etc.), etc.

[0011] Note that the conductivity types of the transistors described in the following embodiments are merely examples and are not limited to the conductivity types described in the embodiments. The conductivity types described in the embodiments can be changed as appropriate, and the potentials of the gate, source, and drain of the transistor can be changed as appropriate in accordance with this change. For example, in the case of a transistor that operates as a switch, the low and high levels of the potential supplied to the gate can be reversed in accordance with the change in conductivity type compared to the description in the embodiments. Note that in this specification, the source and drain of each node of a transistor may be referred to as the main node, and the gate as the control node.

[0012] In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being connected to each other unless otherwise specified.

[0013] [First embodiment] A photoelectric conversion device and a method for driving the same according to a first embodiment of the present invention will be described with reference to FIGS.

[0014] Fig. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to this embodiment. As shown in Fig. 1, the photoelectric conversion device 100 according to this embodiment includes a pixel array section 10, a vertical scanning circuit 20, readout circuits 40A and 40B, reference signal output circuits 52A and 52B, and counter circuits 64A and 64B. The photoelectric conversion device 100 also includes horizontal scanning circuits 70A and 70B, processing circuits 80A and 80B, output circuits 82A and 82B, and a control circuit 90.

[0015] The pixel array unit 10 has a plurality of pixels 12 arranged in a matrix across a plurality of rows and a plurality of columns. Each pixel 12 includes a photoelectric conversion unit formed of a photoelectric conversion element such as a photodiode, and outputs a pixel signal corresponding to the amount of incident light. The number of rows and columns of the pixel array arranged in the pixel array unit 10 is not particularly limited. In addition to effective pixels that output pixel signals corresponding to the amount of incident light, the pixel array unit 10 may also include optical black pixels whose photoelectric conversion units are shielded from light, dummy pixels that do not output signals, and the like. The specific configuration of the pixels 12 will be described later.

[0016] Control lines 14 are arranged in each row of the pixel array section 10, extending in a first direction (the horizontal direction in FIG. 1). Each of the control lines 14 is connected to the pixels 12 aligned in the first direction and serves as a signal line common to these pixels 12. Each of the control lines 14 may include multiple signal lines. The first direction in which the control lines 14 extend may be referred to as the row direction or horizontal direction. The control lines 14 are connected to a vertical scanning circuit 20.

[0017] In each column of the pixel array section 10, a signal output line 16A or a signal output line 16B is arranged, extending in a second direction (vertical direction in FIG. 1) intersecting the first direction. The signal output lines 16A and 16B are arranged alternately in each column. For example, the signal output lines 16A are arranged in odd-numbered columns, and the signal output lines 16B are arranged in even-numbered columns. The signal output line 16A is connected to a readout circuit 40A. The signal output line 16B is connected to a readout circuit 40B. The signal output lines 16A and 16B may include multiple signal lines.

[0018] The vertical scanning circuit 20 has a function of generating control signals for driving the pixels 12 in response to control signals from the control circuit 90 and outputting the generated control signals to the pixel array unit 10. The vertical scanning circuit 20 may use logic circuits such as a shift register and an address decoder. The vertical scanning circuit 20 sequentially outputs control signals to the control lines 14 of each row, and performs an operation known as vertical scanning, which sequentially drives the pixels 12 of the pixel array unit 10 row by row. The signals read out from the pixels 12 row by row are input to a readout circuit 40A or a readout circuit 40B via a signal output line 16A or a signal output line 16B arranged in each column of the pixel array unit 10.

[0019] The readout circuit 40A has a plurality of column circuits 42 corresponding to the number of columns on which the signal output lines 16A are arranged. Each of the column circuits 42 of the readout circuit 40A is connected to the signal output line 16A of the corresponding column. Similarly, the readout circuit 40B has a plurality of column circuits 42 corresponding to the number of columns on which the signal output lines 16B are arranged. Each of the column circuits 42 of the readout circuit 40B is connected to the signal output line 16B of the corresponding column. The column circuits 42 are signal processing circuits that perform predetermined processing on pixel signals read out from the pixels 12 of the corresponding column. Examples of processing performed by the column circuits 42 include signal processing such as amplification and analog-to-digital conversion (AD conversion). The column circuits 42 have a signal holding circuit (memory) for holding the processed pixel signals.

[0020] The reference signal output circuit 52A is connected to the readout circuit 40A. The reference signal output circuit 52A has a function of outputting a reference signal used for AD conversion to the readout circuit 40A in response to a control signal from the control circuit 90. Similarly, the reference signal output circuit 52B is connected to the readout circuit 40B. The reference signal output circuit 52B has a function of outputting a reference signal used for AD conversion to the readout circuit 40B in response to a control signal from the control circuit 90. Note that the reference signal output circuits 52A and 52B may be configured to generate and output a reference signal, or may be configured to buffer and output a reference signal generated outside the photoelectric conversion device.

[0021] The reference signal used in AD conversion may be a signal having a predetermined amplitude according to the range of the pixel signal and whose signal level changes over time. The reference signal is not particularly limited, but for example, a ramp signal whose signal level monotonically increases or decreases over time may be applied. Note that the change in signal level does not necessarily have to be continuous, but may be step-like. Furthermore, the change in signal level does not necessarily have to be linear with respect to time, but may be curved with respect to time (for example, a sine wave or cosine wave).

[0022] The counter circuit 64A is connected to the readout circuit 40A. The counter circuit 64A performs a counting operation in response to a control signal from the control circuit 90 and has the function of outputting a count signal indicating the count value to the readout circuit 40A. The counter circuit 64A starts its counting operation in synchronization with the timing at which the signal level of the reference signal supplied from the reference signal output circuit 52A starts to change. Similarly, the counter circuit 64B is connected to the readout circuit 40B. The counter circuit 64B performs a counting operation in response to a control signal from the control circuit 90 and has the function of outputting a count signal indicating the count value to the readout circuit 40B. The counter circuit 64B starts its counting operation in synchronization with the timing at which the signal level of the reference signal supplied from the reference signal output circuit 52B starts to change. Note that the functions of the counter circuits 64A and 64B may be provided in each of the column circuits 42.

[0023] Although the present embodiment mainly illustrates an example in which a slope-type AD conversion circuit is used for AD conversion of pixel signals, the AD conversion circuit is not limited to the slope-type AD conversion circuit. In addition to the slope-type AD conversion circuit, other types of AD conversion of pixel signals, such as a SAR (Successive Approximation Register) type AD conversion circuit, a ΔΣ type AD conversion circuit, and a pipeline type AD conversion circuit, can also be applied. In these cases, the reference signal output circuits 52A and 52B and the counter circuits 64A and 64B are not required.

[0024] The horizontal scanning circuit 70A has a function of generating control signals for reading out pixel signals from the column circuits 42 of the readout circuit 40A in response to control signals from the control circuit 90 and outputting the generated control signals to the readout circuit 40A. The horizontal scanning circuit 70A sequentially scans the column circuits 42 of the readout circuit 40A and outputs the pixel signals held therein to the processing circuit 80A via horizontal output lines 72A, a so-called horizontal scanning operation. Similarly, the horizontal scanning circuit 70B has a function of generating control signals for reading out pixel signals from the column circuits 42 of the readout circuit 40B in response to control signals from the control circuit 90 and outputting the generated control signals to the readout circuit 40B. The horizontal scanning circuit 70B performs horizontal scanning on the column circuits 42 of the readout circuit 40B in the same manner as the horizontal scanning circuit 70A. Logic circuits such as shift registers and address decoders may be used in the horizontal scanning circuits 70A and 70B.

[0025] The processing circuit 80A is composed of a buffer amplifier, a differential amplifier, etc., and has the function of performing predetermined signal processing on pixel signals of a column selected by the horizontal scanning circuit 70A and outputting the processed pixel data to the output circuit 82A. Similarly, the processing circuit 80B is composed of a buffer amplifier, a differential amplifier, etc., and has the function of performing predetermined signal processing on pixel signals of a column selected by the horizontal scanning circuit 70B and outputting the processed pixel data to the output circuit 82B. Examples of signal processing performed by the processing circuits 80A and 80B include correction processing using correlated double sampling (CDS) and amplification processing.

[0026] The output circuit 82A has an external interface circuit and has a function of outputting image data input from the processing circuit 80A to the outside of the photoelectric conversion device 100. Similarly, the output circuit 82B has an external interface circuit and has a function of outputting image data input from the processing circuit 80B to the outside of the photoelectric conversion device 100. The external interface circuits provided in the output circuits 82A and 82B are not particularly limited. For example, a SerDes (SERializer / DESerializer) transmission circuit such as an LVDS (Low Voltage Differential Signaling) circuit or an SLVS (Scalable Low Voltage Signaling) circuit can be used as the external interface circuit.

[0027] The control circuit 90 has a function of generating control signals for controlling the operation of each of the above-mentioned functional blocks and outputting the generated control signals to these functional blocks. Note that at least some of the control signals for controlling the operation of these functional blocks may be configured to be supplied from outside the photoelectric conversion device 100.

[0028] 1 shows an example in which two readout circuit blocks are provided: a readout circuit block including a readout circuit 40A, a horizontal scanning circuit 70A, a processing circuit 80A, etc., and a readout circuit block including a readout circuit 40B, a horizontal scanning circuit 70B, a processing circuit 80B, etc. However, the number of readout circuit blocks does not necessarily have to be two, and one readout circuit block may also be provided.

[0029] 2 is a circuit diagram showing an example of the configuration of a pixel in the photoelectric conversion device according to this embodiment. Each of the pixels 12 constituting the pixel array unit 10 can be configured with a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4, for example, as shown in FIG.

[0030] The photoelectric conversion element PD is, for example, a photodiode, and has an anode connected to a ground voltage line and a cathode connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. A node FD, to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected, is a so-called floating diffusion. The floating diffusion includes a capacitance component (floating diffusion capacitance) and functions as a charge storage portion. The floating diffusion capacitance may include transistor gate capacitance, pn junction capacitance, wiring capacitance, etc. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a node to which a power supply voltage (e.g., voltage VDD) is supplied. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the signal output line 16A (or signal output line 16B).

[0031] In the pixel configuration of FIG. 2, the control line 14 for each row includes three signal lines connected to the gate of the transfer transistor M1, the gate of the reset transistor M2, and the gate of the selection transistor M4. A control signal PTX is supplied to the gate of the transfer transistor M1 from the vertical scanning circuit 20. A control signal PRES is supplied to the gate of the reset transistor M2 from the vertical scanning circuit 20. A control signal PSEL is supplied to the gate of the selection transistor M4 from the vertical scanning circuit 20. When each transistor is an N-type transistor, the corresponding transistor turns on when a high-level control signal is supplied from the vertical scanning circuit 20. On the other hand, the corresponding transistor turns off when a low-level control signal is supplied from the vertical scanning circuit 20.

[0032] In this embodiment, the description will be given assuming that electrons, among electron-hole pairs generated in the photoelectric conversion element PD by incident light, are used as signal charges. When electrons are used as signal charges, each transistor constituting the pixel 12 may be configured as an N-type transistor. However, the signal charges are not limited to electrons; holes may also be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor will be the opposite conductivity type to that described in this embodiment. Furthermore, the names of the source and drain of a MOS transistor may vary depending on the transistor's conductivity type and the focused function. Some or all of the names of the source and drain used in this embodiment may be reversed. In this specification, one of the source and drain may be referred to as a first main node, the other of the source and drain as a second main node, and the gate as a control node.

[0033] The photoelectric conversion element PD converts incident light into an electric charge in an amount corresponding to the amount of light (photoelectric conversion) and accumulates the generated electric charge. When the transfer transistor M1 is turned on, it transfers the electric charge held by the photoelectric conversion element PD to the node FD. The electric charge transferred from the photoelectric conversion element PD is held in the capacitance (floating diffusion capacitance) of the node FD. As a result, the node FD has a potential corresponding to the amount of electric charge transferred from the photoelectric conversion element PD due to charge-voltage conversion by the floating diffusion capacitance.

[0034] When the selection transistor M4 is turned on, it connects the amplification transistor M3 to the signal output line 16A (or signal output line 16B). The amplification transistor M3 is configured so that a voltage VDD is supplied to its drain and a bias current is supplied to its source from a current source (current source 44, described below) not shown via the selection transistor M4. This causes the amplification transistor M3 to form an amplifier (source follower circuit) with its gate as an input node, and outputs a signal based on the potential of node FD to the signal output line 16A (or signal output line 16B) via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 form an output unit that outputs a pixel signal according to the amount of charge held at node FD.

[0035] The reset transistor M2 has a function of controlling the supply of a voltage (voltage VDD) to the FD node for resetting the node FD as a charge storage unit. When the reset transistor M2 is turned on, it resets the node FD to a voltage corresponding to the voltage VDD.

[0036] FIG. 3 is a circuit diagram showing an example of the configuration of column circuits in a photoelectric conversion device according to this embodiment. FIG. 3 shows four of the multiple column circuits 42 that make up the readout circuit 40A. The signal output line 16A of each column is connected to the column circuit 42 of the corresponding column. Each column circuit 42 may be configured, for example, as shown in FIG. 3, with a current source 44, a level shift circuit 46, an AD conversion circuit 50, and memories 68W and 68R. As described above, the current source 44 serves as a load current source for the amplification transistor M3 of the pixel 12. The level shift circuit 46 includes a transistor M6 and a current source 48.

[0037] One node of the current source 44 is connected to the signal output line 16A. The other node of the current source 44 is connected to a ground voltage node. The drain of the transistor M6 is connected to a node to which a power supply voltage (e.g., voltage VDD) is supplied. The source of the transistor M6 is connected to one node of the current source 48 and an input node of the AD conversion circuit 50. The other node of the current source 48 is connected to the ground voltage node. The gate of the transistor M6 is connected to the signal output line 16A. The transistor M6 is configured so that voltage VDD is supplied to its drain and a bias current is supplied from the current source 48 to its source, forming a source follower circuit with its gate as an input node and a connection node between the transistor M6 and the current source 48 as an output node. The gate of the transistor M6 is the input node of the level shift circuit 46, and the connection node between the source of the transistor M6 and one node of the current source 48 is the output node of the level shift circuit 46.

[0038] A level shift circuit is a circuit that outputs a signal that has the same waveform as an input signal but a different voltage level. The level shift circuit 46 of this embodiment level-shifts the input signal in a direction that decreases the voltage and outputs the signal. Here, the direction that decreases the voltage refers to the direction that decreases the potential difference with respect to a voltage that serves as a reference for the power supply voltage (herein referred to as the reference voltage). The reference voltage is generally a ground voltage, but is not necessarily limited to a ground voltage. When the pixel circuit is configured with N-type transistors as described above, the level shift circuit 46 level-shifts the signal on the signal output line 16A in a direction that decreases the signal level and outputs the signal.

[0039] The output node of the AD conversion circuit 50 is connected to the input node of the memory 68W. The memory 68R has two input nodes and one output node. One input node of the memory 68R is connected to the output node of the memory 68W. The other input node of the memory 68R is connected to the horizontal scanning circuit 70A. The output node of the memory 68R is connected to the horizontal output line 72A.

[0040] The signal VOUT on the signal output line 16A is input to the level shift circuit 46. The signal VOUT is level-shifted to a lower voltage in the level shift circuit 46 and output to the AD conversion circuit 50. The output of the level shift circuit 46 is the signal VLS. The amount of level shift in the level shift circuit 46 is the gate-source voltage of the transistor M6.

[0041] The AD conversion circuit 50 converts the analog signal VLS and outputs the converted signal to the memory 68W. The memory 68W stores the signal output from the AD conversion circuit 50 as digital pixel signal data. The memory 68R stores the digital pixel signal data transferred from the memory 68W. The digital data stored in the memory 68R is transferred to the processing circuit 80A via the horizontal output line 72A, column by column, in response to a control signal supplied from the horizontal scanning circuit 70A. By providing the memory 68R after the memory 68W, it is possible to perform AD conversion in the AD conversion circuit 50 in parallel with the transfer operation to the processing circuit 80A. The digital data transferred to the processing circuit 80A undergoes predetermined signal processing in the processing circuit 80A and is then output off-chip via the output circuit 82A.

[0042] The column circuits 42 of the readout circuit 40B are the same as the column circuits 42 of the readout circuit 40A except that they are arranged in a different column from the column circuits 42 of the readout circuit 40A, and therefore will not be described again. Hereinafter, the description will focus on the column circuits 42 of the readout circuit 40A, but the same applies to the column circuits 42 of the readout circuit 40B. In the following description, when the signal output lines 16A, 16B, readout circuits 40A, 40B, etc. are commonly described, the distinction between A and B may be omitted and they may be referred to as signal output lines 16, readout circuits 40, etc. In addition, when a plurality of similar components are provided, consecutive numbers such as 1, 2, 3, etc. may be added to each reference numeral to distinguish them from one another.

[0043] 4 is a circuit diagram showing a configuration example of an AD conversion circuit 50 in the case where a slope-type AD conversion circuit is applied as the AD conversion circuit 50. The slope-type AD conversion circuit 50 can be configured with a reference signal output circuit 52A, a counter circuit 64A, a comparison circuit 54, capacitance elements C1 and C2, and switches SW1 and SW2, as shown in FIGS.

[0044] The comparison circuit 54 is configured, for example, by a differential amplifier circuit, and has a non-inverting input node (+), an inverting input node (-), a non-inverting output node (+), and an inverting output node (-). The inverting input node of the comparison circuit 54 is connected to the output line of the level shift circuit 46 via a capacitance element C1. The inverting input node of the comparison circuit 54 receives a signal VLS from the level shift circuit 46 via the capacitance element C1. The non-inverting input node of the comparison circuit 54 is connected to a reference signal line 56 via a capacitance element C2. The non-inverting input node of the comparison circuit 54 receives a reference signal VRAMP output from the reference signal output circuit 52A via the reference signal line 56 and the capacitance element C2. A switch SW1 is connected between the inverting input node and the non-inverting output node of the comparison circuit 54. A switch SW2 is connected between the non-inverting input node and the inverting output node of the comparison circuit 54. The switches SW1 and SW2 are controlled by a control signal AZ supplied from the control circuit 90 via an AZ signal line 58. The switches SW1 and SW2 are reset switches for resetting the threshold voltage of the comparison circuit .

[0045] The memories 68W and 68R each have two input nodes and one output node. One input node of the memory 68W is connected to the non-inverting output node of the comparison circuit 54. The other input node of the memory 68W is connected to a count signal line 66. A count signal COUNT is supplied to the other input node of the memory 68W from the counter circuit 64A via the count signal line 66. One input node of the memory 68R is connected to the output node of the memory 68W. The other input node of the memory 68R is connected to the horizontal scanning circuit 70A. The output node of the memory 68R is connected to a horizontal output line 72A.

[0046] The comparator circuit 54 compares the level of the signal VLS supplied from the level shift circuit 46 via the capacitive element C1 with the level of the reference signal VRAMP supplied from the reference signal line 56 via the capacitive element C2, and outputs a signal according to the comparison result. For example, the comparator circuit 54 outputs a high-level signal when the level of the reference signal VRAMP is lower than the level of the signal VLS. On the other hand, the comparator circuit 54 outputs a low-level signal when the level of the reference signal VRAMP is higher than the level of the signal VLS. Note that the relationship between the magnitude of the input signal and the level of the output signal may be reversed.

[0047] The memory 68W holds, as digital data of the pixel signal, the count value indicated by the count signal COUNT supplied from the counter circuit 64A at the timing when the level of the non-inverting output node of the comparison circuit 54 is inverted. The memory 68R holds the digital data of the pixel signal transferred from the memory 68W. The digital data held in the memory 68R is transferred to the processing circuit 80A via the horizontal output line 72A sequentially for each column in response to a control signal supplied from the horizontal scanning circuit 68A.

[0048] Instead of providing the counter circuit 64A, the memory 68W of the column circuit 42 may have the function of a counter circuit. In this case, the memory 68W of the column circuit 42 of each column receives a common clock signal output from the control circuit 90 and counts pulses of the clock signal. The count value at the timing when the level of the output signal of the comparison circuit 54 is inverted becomes digital data held in the memory 68W.

[0049] The photoelectric conversion device 100 of this embodiment may be configured so that all of the above-mentioned functional blocks are arranged on a single substrate, or may be configured as a stacked type in which multiple substrates are stacked together and functional blocks are created on each substrate.

[0050] FIG. 5 is a schematic diagram showing an example of the configuration of a photoelectric conversion device according to this embodiment. FIG. 5(a) is a schematic diagram showing a case where a pixel substrate 110 on which a pixel array section 10 is arranged and a circuit substrate 120 on which other functional blocks are arranged are stacked. By arranging the pixel substrate 110 and the circuit substrate 120 on separate substrates, it is possible to reduce the size of the photoelectric conversion device 100 without sacrificing the area of ​​the pixel array section 10. FIG. 5(b) is a schematic diagram showing a case where the pixel substrate 110 on which the pixel array section 10 is arranged and circuit substrates 120, 130 on which other functional blocks are arranged are stacked. In this case as well, it is possible to reduce the size of the photoelectric conversion device 100 without sacrificing the area of ​​the pixel array section 10.

[0051] It should be noted that the circuit elements that make up one functional block do not necessarily have to be arranged on the same substrate, and may be arranged on separate substrates.

[0052] Next, the operation of the photoelectric conversion device 100 according to this embodiment will be described with reference to Fig. 6. Fig. 6 is a timing diagram illustrating the operation of the photoelectric conversion device according to this embodiment. The timing diagram in Fig. 6 shows waveforms of the control signals PTX, PRES, AZ, the reference signal VRAMP, and the signal VLS of the output line of the level shift circuit 46. Here, when the control signals PTX, PRES, AZ are at a high level, the corresponding transistor or switch is turned on, and when the control signals PTX, PRES, AZ are at a low level, the corresponding transistor or switch is turned off.

[0053] Just before time t0, the control signal PSEL (not shown) for the row to be read is at a high level. This turns on the selection transistors M4 of the pixels 12 in that row, and each of these pixels 12 is ready to output a pixel signal to the signal output line 16A of the corresponding column. Also, just before time t0, the control signals PTX, PRES, and AZ for the row to be read are at a low level, and the reference signal VRAMP is at a predetermined reference voltage.

[0054] During the period from time t0 to time t1, the vertical scanning circuit 20 controls the control signal PRES of the row to be read out to a high level. This turns on the reset transistor M2 of the pixel 12 belonging to that row, and resets the node FD to a voltage corresponding to the voltage VDD. A signal VOUT (pixel signal at a reset level) having a voltage corresponding to the reset voltage of the node FD is output to the signal output line 16A. In addition, the signal VLS of the output line of the level shift circuit 46 also becomes a predetermined reset level corresponding to the signal VOUT. At time t1, the control signal PRES transitions to a low level, turning off the reset transistor M2, thereby releasing the reset state of the node FD.

[0055] Furthermore, during the period from time t0 to time t2, the control circuit 90 controls the control signal AZ to a high level. This turns on the switches SW1 and SW2 of the column circuits 42 of each column, and the inverting input node and the non-inverting input node of the comparison circuit 54 are reset to a reset level voltage. That is, at time t2, one node of the capacitance element C1 is at the reset level voltage of the signal VLS, and the other node of the capacitance element C1 is at the reset level voltage of the comparison circuit 54. Furthermore, one node of the capacitance element C2 is at the reference voltage of the reference signal VRAMP, and the other node of the capacitance element C2 is at the reset level voltage of the comparison circuit 54. The threshold voltage of the comparison circuit 54 is reset to a voltage corresponding to the potential difference between the reset level voltage of the signal VLS and the reference voltage of the reference signal VRAMP.

[0056] The threshold voltage of the comparison circuit 54 is a voltage corresponding to the difference between the signal level of the signal VLS and the signal level of the reference signal VRAMP when the level of the comparison signal output from the comparison circuit 54 changes. That is, the comparison circuit 54 outputs a comparison signal that indicates a different level when the difference between the signal level of the signal VLS and the signal level of the reference signal VRAMP is smaller than the threshold voltage and when it is larger than the threshold voltage.

[0057] At the next time t2, the control circuit 90 sets the control signal AZ to a low level, which turns off the switches SW1 and SW2 of the column circuit 42 of each column, clamps the reset level of the signal VLS to the capacitive element C1, and clamps the reference level corresponding to the reference voltage of the reference signal VRAMP to the capacitive element C2.

[0058] At the next time t4, the reference signal output circuit 52A increases the reference signal VRAMP from the base voltage to a predetermined start voltage. Then, at the next time t5, the reference signal output circuit 52A starts a slope operation in which the voltage of the reference signal VRAMP changes over time. The counter circuit 64A also starts counting up at the same time as the slope operation starts, and outputs a count signal COUNT indicating the count value to the column circuit 42 of each column via the count signal line 66.

[0059] The comparator circuit 54 compares the level of the signal VLS input via the capacitive element C1 with the level of the reference signal VRAMP input via the capacitive element C2. The comparator circuit 54 then inverts the level of its output signal at the timing when the magnitude relationship between the level of the signal VLS and the level of the reference signal VRAMP changes, for example, at time t6 in FIG.

[0060] The memory 68W holds the count value indicated by the count signal COUNT output from the counter circuit 64A at the timing when the level of the output signal of the comparison circuit 54 is inverted, as digital data of the pixel signal of the reset level of the pixel 12. In this way, AD conversion is performed on the pixel signal of the reset level of the pixel 12. The digital data held in the memory 68W is transferred to the memory 68R, and then transferred to the processing circuit 80A in response to a control signal from the horizontal scanning circuit 70A.

[0061] At the following time t7, the reference signal output circuit 52A resets the reference signal VRAMP to the level of the reference voltage.

[0062] During the subsequent period from time t8 to time t9, the vertical scanning circuit 20 controls the control signal PTX for the row to be readout to a high level. This turns on the transfer transistor M1 of the pixel 12 belonging to that row, and the charge accumulated in the photoelectric conversion element PD during the predetermined exposure period is transferred to the node FD. This causes the voltage of the node FD to decrease in accordance with the amount of charge transferred from the photoelectric conversion element PD, and the levels of the signal VOUT of the signal output line 16A and the signal VLS of the output line of the level shift circuit 46 also decrease. A signal VOUT (pixel signal at the optical signal level) with a voltage corresponding to the voltage of the node FD is output to the signal output line 16A. Furthermore, the signal VLS of the output line of the level shift circuit 46 also becomes a predetermined level corresponding to the signal VOUT.

[0063] At the next time t10, the reference signal output circuit 52A increases the reference signal VRAMP from the base voltage to a predetermined start voltage. Then, at the next time t11, the reference signal output circuit 52A starts a slope operation in which the voltage of the reference signal VRAMP changes over time. The counter circuit 64A also starts counting up at the same time as the slope operation starts, and outputs a count signal COUNT indicating the count value to the column circuit 42 of each column via the count signal line 66.

[0064] The comparator circuit 54 compares the level of the signal VLS input via the capacitive element C1 with the level of the reference signal VRAMP input via the capacitive element C2. The comparator circuit 54 then inverts the level of its output signal at the timing when the magnitude relationship between the level of the signal VLS and the level of the reference signal VRAMP changes, for example, at time t12 in FIG.

[0065] The memory 68W holds, as digital pixel signal data, the count value indicated by the count signal COUNT supplied from the counter circuit 64A at the timing when the level of the output signal from the comparator circuit 54 is inverted. In this manner, AD conversion is performed on the pixel signal of the optical signal level. The digital data held in the memory 68W is transferred to the memory 68R and then transferred to the processing circuit 80A in response to a control signal from the horizontal scanning circuit 70A.

[0066] The digital data of the pixel signals obtained in this way is subjected to CDS correction processing in the downstream processing circuit 80A. In the CDS correction processing, the digital data of the pixel signals at the reset level is subtracted from the digital data of the pixel signals at the optical signal level, and noise components superimposed on the pixel signals at the optical signal level are removed.

[0067] As described above, in this embodiment, the signal VOUT on the signal output line 16A is level-shifted to a lower voltage by the level shift circuit 46, and the level-shifted signal VLS is output to the AD conversion circuit 50. This configuration makes it possible to reduce the chip area, for example. This point will be described below.

[0068] Here, in the pixel circuit of FIG. 2, it is assumed that the power supply voltage (voltage VDD) is 3V and the reset level of node FD is 3V. In this case, if the gate-source voltage of amplifier transistor M3 is 0.5V, the reset level of signal output line 16A will be 2.5V. Furthermore, when signal charge equivalent to the maximum amount of charge that can be held in photoelectric conversion element PD is transferred to node FD, the voltage of signal output line 16A will drop to 1.5V in response to the drop in voltage of node FD. In this case, the voltage range that signal output line 16A can take is 1.5V to 2.5V.

[0069] When the level shift amount in the level shift circuit 46 is 1.25V and the gain is 1, the voltage range that the output (signal VLS) of the level shift circuit 46 can take is 0.25V to 1.25V. In other words, the maximum value of the voltage output to the AD conversion circuit 50 by the level shift circuit 46 is halved from 2.5V to 1.25V. This makes it possible to reduce the size of the capacitive element C1 and the chip area. This point will be explained in more detail below.

[0070] 7 shows an example of the cross-sectional structure of the capacitance element C1. + Diffusion layer 152 and P + A diffusion layer 154 is provided. + A polysilicon electrode 158 is provided on the diffusion layer 152 via an insulating film 156. This allows the polysilicon electrode 158 to be used as one electrode, N + A capacitance element C1 is formed with the diffusion layer 152 as the other electrode and the insulating film 156 as the capacitor dielectric film. For example, one electrode formed by the polysilicon electrode 158 is connected to the level shift circuit 46, and N + The other electrode formed by the diffusion layer 152 can be connected to the comparison circuit 54. The P well 150 is + It is connected to the ground voltage node via the diffusion layer 154 .

[0071] The capacitance value C per unit area of ​​this capacitance element ox is the dielectric constant of the insulating film 156, ε ox (=ε0×ε r ), thickness is t ox As, C ox =ε ox / t ox Assuming that the insulating film 156 is made of silicon oxide with a thickness of 10 nm, the capacitance value C ox is 8.854 x 10 -12 x3.9 / 10x10 -9 =3.45×10 -3 [F / m 2In the circuit configuration of FIG. 4, the capacitance elements C1 and C2 often have a relatively large capacitance value for the purpose of reducing kTC noise when the switches SW1 and SW2 are turned off. For example, the capacitance value C ox If 345 fF is required, the electrode area of ​​the capacitance elements C1 and C2 is 100 μm 2 This becomes:

[0072] When the maximum voltage input from the level shift circuit 46 to the polysilicon electrode 158 is reduced by half from 2.5 V to 1.25 V as described above, the thickness t ox For example, if the thickness of the insulating film 156 is halved from 10 nm to 5 nm, the capacitance value per unit area doubles. 2 to 50 μm 2 It is possible to reduce it to

[0073] Since it is desirable that the capacitance elements C1 and C2 connected to a pair of differential input nodes of the comparison circuit 54 have the same configuration in consideration of differential characteristics, it is possible to further reduce the area by thinning the insulating film of the capacitance element C2 as well. The size of the transistor M6 and the transistors constituting the current source 48 is, for example, 1 μm 2 Since this can be realized in an area of ​​about 100 sq. m, even if the level shift circuit 46 is added, the total area can be made sufficiently small.

[0074] It is possible to lower the voltage level of the input signal to the AD conversion circuit 50 by lowering the power supply voltage of the pixel circuit from 3 V to, for example, 1.75 V and lowering the voltage range that the signal output line 16A can take from 0.25 V to 1.25 V. However, if the voltage range that the signal output line 16A can take is shifted too low, the leakage current of the selection transistor M4 of the pixels 12 in the non-readout row that are connected to the signal output line 16A increases, which may cause degradation of image quality such as degradation of linearity.

[0075] In this regard, in this embodiment, instead of lowering the voltage level of the signal output line 16A, the level shift circuit 46 shifts the signal of the signal output line 16A to a lower voltage and outputs it to the AD conversion circuit 50. Therefore, according to this embodiment, it is possible to reduce the chip area while suppressing deterioration in image quality.

[0076] The reduction in chip area due to the reduction in size of the capacitive elements C1 and C2 is one example of the effect obtained by providing the level shift circuit 46. By providing the level shift circuit 46, various effects can be achieved depending on the configuration of the column circuit 42.

[0077] For example, as shown in FIG. 8, the column circuit 42 may further include a sample-and-hold circuit 160 having a capacitance element C3 and a switch SW3, and a buffer circuit 162, between the level shift circuit 46 and the comparison circuit 54. That is, one node of the switch SW3 is connected to the output line of the level shift circuit 46. The other node of the switch SW3 is connected to one node of the capacitance element C3 and the input node of the buffer circuit 162. The other node of the capacitance element C3 is connected to the ground voltage node. The output node of the buffer circuit 162 is connected to the inverting input node of the comparison circuit 54. In this column circuit 42, the voltage range of the signal VLS is narrowed, allowing the size of the capacitance element C3 used for signal sample-and-hold to be reduced. This, like the capacitance element C1, allows for a reduced chip area.

[0078] Alternatively, as shown in FIG. 9, the column circuit 42 may further include a gain amplifier between the level shift circuit 46 and the comparator circuit 54, the gain amplifier being composed of an amplifier 164 and capacitive elements C4 and C5. Specifically, one node of the capacitive element C4 is connected to the output line of the level shift circuit 46. The other node of the capacitive element C4 is connected to the inverting input node of the amplifier 164 and one node of the capacitive element C5. The output node of the amplifier 164 is connected to the other node of the capacitive element C5 and the inverting input node of the comparator circuit 54. By connecting the gain amplifier between the level shift circuit 46 and the comparator circuit 54, a gain determined by the ratio of the capacitance values ​​of the capacitive elements C4 and C5 can be applied to the signal VLS before inputting it to the comparator circuit 54. In this case, the voltage range of the signal VLS is narrowed, thereby enabling the size of the capacitive elements C4 and C5 to be reduced. This, as with the capacitive element C1, allows for a reduction in chip area. It is also possible to configure the capacitance value of at least one of the capacitance elements C4 and C5 to be variable, thereby configuring a gain amplifier with variable gain.

[0079] Alternatively, the column circuit 42 may be configured, for example, as shown in FIG. 10 , such that the output line of the level shift circuit 46 is connected to the inverting input node of the comparator circuit 54 without the capacitor C1. If the maximum voltage of the signal VLS output from the level shift circuit 46 decreases from, for example, 2.5 V to 1.25 V, the power supply voltage of the comparator circuit 54 can also be reduced from 2.5 V to 1.25 V. To improve the accuracy of AD conversion, a high slew rate is required when the output of the comparator circuit 54 is inverted, and the current flowing through the AD conversion circuit 50 is set to, for example, approximately 10 μA. In this case, reducing the power supply voltage of the comparator circuit 54 from 2.5 V to 1.25 V can reduce power by 12.5 μW. Therefore, when the power supply voltage of the level shift circuit 46 is 2.5 V, power can be reduced if the current of the current source 48 is 5 μA or less. In other words, the level shift circuit 46 reduces the power supply voltage supplied to the comparator circuit, thereby reducing power consumption. In this specification, the magnitude of a power supply voltage refers to the potential difference between the power supply voltage and a voltage (reference voltage) that serves as a reference for that power supply voltage. When the reference voltage is the ground voltage, the magnitude of the power supply voltage is the same as the absolute value of the power supply voltage.

[0080] Furthermore, in the above description, a slope-type AD conversion circuit has been assumed as the AD conversion circuit 50, but the AD conversion circuit 50 is not limited to a slope-type AD conversion circuit. For example, even when a successive approximation AD conversion circuit using a capacitive DAC in the input section is applied, the effect of reducing the chip size by reducing the size of the capacitive element can be obtained.

[0081] The AD conversion circuit 50 may also be a ΔΣ AD conversion circuit. In a ΔΣ AD conversion circuit, for example, as shown in FIG. 11 , an integrator including a switched capacitor circuit 166, an amplifier 168, and a capacitance element C7 is connected to a level shift circuit 46. The switched capacitor circuit 166 may include a capacitance element C6 and switches SW4, SW5, SW6, and SW7. That is, one node of the switch SW4 is connected to the output line of the level shift circuit 46. The other node of the switch SW4 is connected to one node of the capacitance element C7 and one node of the switch SW5. The other node of the capacitance element C7 is connected to one node of the switch SW6 and one node of the switch SW7. The other node of the switch SW7 is connected to the inverting input node of the amplifier 168 and one node of the capacitance element C7. The output node of the amplifier 168 is connected to the other node of the capacitance element C7. In the case of such a column circuit 42, not only can the chip size be reduced by reducing the size of the capacitance element C6, but also the deterioration of image quality can be reduced by suppressing the current fluctuation of the pixel 12.

[0082] In the circuit of FIG. 11, the non-inverting input node of amplifier 168 is grounded, and the inverting input node is also at a potential near 0 V. Because the switched capacitor circuit 166 acts like a resistor, a current that varies in response to the output signal of the level shift circuit 46 flows into the capacitive element C7 via the inverting input node of amplifier 168, performing an integration operation. Without the level shift circuit 46, the current flowing through the pixel 12 would vary in response to the pixel signal, which could cause image quality degradation. In this regard, in this embodiment, an input current that varies in response to the pixel signal is supplied from the level shift circuit 46, making it possible to suppress current fluctuations in the pixel 12.

[0083] In this way, in an AD conversion circuit 50 having a current input type configuration such as the ΔΣ AD conversion circuit shown in FIG. 11, not only can the chip size be reduced, but also image quality degradation can be suppressed by suppressing fluctuations in pixel current.

[0084] Furthermore, when the AD conversion circuit 50 is an oversampling type AD conversion circuit such as a ΔΣ type AD conversion circuit, the random noise generated in the level shift circuit 46 can be suppressed by oversampling, thereby reducing the disadvantage of adding the level shift circuit 46.

[0085] As described above, according to this embodiment, a level shift circuit that level-shifts pixel signals in the direction of decreasing voltage and outputs them is provided at the input section of the column circuit, thereby realizing a smaller area and lower power consumption of the photoelectric conversion device.

[0086] [Second embodiment] A photoelectric conversion device and a driving method thereof according to a second embodiment of the present invention will be described with reference to Fig. 12. Components similar to those in the photoelectric conversion device according to the first embodiment are given the same reference numerals, and their description will be omitted or simplified. Fig. 12 is a circuit diagram showing an example of the configuration of a level shift circuit 46 in the photoelectric conversion device according to this embodiment.

[0087] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first embodiment except for the configuration of the level shift circuit 46. In this embodiment, differences from the photoelectric conversion device according to the first embodiment will be mainly described, and descriptions of similarities with the photoelectric conversion device according to the first embodiment will be omitted as appropriate.

[0088] As shown in FIG. 12, the level shift circuit 46 of the photoelectric conversion device according to this embodiment includes a current source 48 configured with a current source transistor M8 and a cascode transistor M7 cascode-connected to the current source transistor M8. The level shift circuit 46 also includes a capacitance element C8 and a switch SW8. The gate of the transistor M6 is connected to one node of the switch SW8 and one node of the capacitance element C8. The other node of the switch SW8 is connected to a node to which a predetermined voltage is supplied. The other node of the capacitance element C8 is connected to the signal output line 16A. The source of the transistor M6 is connected to the drain of the cascode transistor M7. The source of the cascode transistor M7 is connected to the drain of the current source transistor M8. The source of the current source transistor M8 is connected to a ground voltage node. The connection node between the source of the transistor M6 and the drain of the cascode transistor M7 is the output node of the level shift circuit 46, from which the signal VLS is output. A predetermined bias voltage is applied to the gate of the cascode transistor M7 and the gate of the current source transistor M8.

[0089] The capacitive element C8 and the switch SW8 form a clamp circuit. After the noise signal output from the pixel 12 is clamped by the capacitive element C8, the pixel 12 outputs a photoelectric conversion signal, thereby eliminating variations in the threshold voltage of the amplification transistor M3 for each pixel 12. This makes it possible to reduce variations in the output voltage of the level shift circuit 46. Furthermore, by controlling the voltage supplied via the switch SW8, it is possible to control the voltage range of the signal output to the AD conversion circuit 50.

[0090] Furthermore, when the threshold voltage of transistor M6 increases and the voltage of the output signal decreases, the voltage supplied via switch SW8 can be controlled to increase, thereby further reducing the variation in the output voltage. In other words, making the voltage supplied via switch SW8 variable can further reduce the variation in the output voltage. The voltage supplied via switch SW8 may be configured to change in conjunction with the threshold voltage of transistor M6.

[0091] As described above, according to this embodiment, a level shift circuit that level-shifts pixel signals in the direction of decreasing voltage and outputs them is provided at the input section of the column circuit, thereby realizing a smaller area and lower power consumption of the photoelectric conversion device.

[0092] [Third embodiment] A photoelectric conversion device and a driving method thereof according to a third embodiment of the present invention will be described with reference to Fig. 13. Components similar to those of the photoelectric conversion device according to the first or second embodiment are given the same reference numerals, and their description will be omitted or simplified. Fig. 13 is a circuit diagram showing an example of the configuration of a level shift circuit 46 in the photoelectric conversion device according to this embodiment.

[0093] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first or second embodiment, except for the configuration of the level shift circuit 46. In this embodiment, differences from the photoelectric conversion device according to the second embodiment will be mainly described, and descriptions of similarities with the photoelectric conversion device according to the second embodiment will be omitted as appropriate.

[0094] 13, the level shift circuit 46 of the photoelectric conversion device according to this embodiment is similar to the level shift circuit 46 of the photoelectric conversion device according to the second embodiment, except that the source of the current source transistor M8 is connected to a node to which a voltage VN is supplied. That is, while the current source transistor M8 of the level shift circuit 46 of the second embodiment is connected to a ground voltage node, the current source transistor M8 of the level shift circuit 46 of this embodiment is connected to a node to which a voltage VN is supplied. The voltage VN is a voltage of opposite polarity to the voltage VDD, and is, for example, −0.5 V.

[0095] By configuring the level shift circuit 46 in this manner, the operation of the current source 48 can be maintained even when the voltage range of the signal VLS output to the AD conversion circuit 50 is shifted to a lower voltage by controlling the voltage supplied via the switch SW8. For example, even when the voltage supplied via the switch SW8 is adjusted so that the voltage range of the signal VLS output to the AD conversion circuit 50 is 0 V to 1 V, a voltage difference of 0.5 V can be ensured between the drain of the cascode transistor M7 and the source of the current-source transistor M8. This makes it possible to reduce the maximum voltage of the signal VLS output to the AD conversion circuit 50 while ensuring operation of the cascode transistor M7 and the current-source transistor M8 in their saturation regions, and further reduce the chip area.

[0096] As described above, according to this embodiment, a level shift circuit that level-shifts pixel signals in the direction of decreasing voltage and outputs them is provided at the input section of the column circuit, thereby realizing a smaller area and lower power consumption of the photoelectric conversion device.

[0097] [Fourth embodiment] A photoelectric conversion device and a driving method thereof according to a fourth embodiment of the present invention will be described with reference to Fig. 14. Components similar to those in the photoelectric conversion devices according to the first to third embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 14 is a circuit diagram showing an example of the configuration of a level shift circuit 46 in the photoelectric conversion device according to this embodiment.

[0098] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion devices according to the first to third embodiments, except for the configuration of the level shift circuit 46. In this embodiment, differences from the photoelectric conversion device according to the third embodiment will be mainly described, and descriptions of similarities with the photoelectric conversion device according to the third embodiment will be omitted as appropriate.

[0099] 14, the level shift circuit 46 of the photoelectric conversion device according to this embodiment is similar to the level shift circuit 46 of the photoelectric conversion device according to the second embodiment, except that the source and back gate of the transistor M6 are connected. By configuring the level shift circuit 46 in this way, it is possible to improve the linearity of the source follower circuit formed by the transistor M6 and the current source transistor M8, and suppress deterioration in image quality.

[0100] As described above, according to this embodiment, a level shift circuit that level-shifts pixel signals in the direction of decreasing voltage and outputs them is provided at the input section of the column circuit, thereby realizing a smaller area and lower power consumption of the photoelectric conversion device.

[0101] [Fifth embodiment] A photoelectric conversion device and a driving method thereof according to a fifth embodiment of the present invention will be described with reference to Fig. 15. Components similar to those in the photoelectric conversion devices according to the first to fourth embodiments are given the same reference numerals, and their description will be omitted or simplified. Fig. 15 is a circuit diagram showing an example of the configuration of a level shift circuit 46 in the photoelectric conversion device according to this embodiment.

[0102] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion devices according to the first to fourth embodiments, except for the configurations of the current source 44 and the level shift circuit 46. In this embodiment, the differences from the photoelectric conversion device according to the fourth embodiment will be mainly described, and the description of the similarities between the photoelectric conversion device according to the fourth embodiment will be omitted as appropriate.

[0103] As shown in FIG. 15 , the current source 44 of the photoelectric conversion device according to this embodiment is configured with a current-source transistor M10 and a cascode transistor M9. Furthermore, the level shift circuit 46 of the photoelectric conversion device according to this embodiment further includes a capacitive element C9 in addition to the configuration of the fourth embodiment. The drain of the cascode transistor M9 is connected to the signal output line 16A. The source of the cascode transistor M9 is connected to the drain of the current-source transistor M10. The source of the current-source transistor M10 is connected to a ground voltage node. A connection node between the source of the cascode transistor M9 and the drain of the current-source transistor M10 is connected to the output node of the level shift circuit 46 via the capacitive element C9. A predetermined bias voltage is applied to the gates of the current-source transistor M10 and the cascode transistor M9. Note that the current source 44 is not limited to the configuration shown in the figure. For example, the current source 44 does not necessarily have to include the cascode transistor M9, and may be configured with a single current-source transistor M10.

[0104] According to the above-described configuration of the present embodiment, the output of the source follower connected to the signal output line 16A is connected to the drain of the current source transistor M10, thereby making it possible to increase the signal response speed of the signal output line 16A. In other words, by utilizing the level shift circuit 46 for reducing the area of ​​the AD conversion circuit 50, it is possible to increase the signal response speed of the signal output line 16A.

[0105] As described above, according to this embodiment, a level shift circuit that level-shifts pixel signals in the direction of decreasing voltage and outputs them is provided at the input section of the column circuit, thereby realizing a smaller area and lower power consumption of the photoelectric conversion device.

[0106] [Sixth embodiment] A photoelectric conversion device and a driving method thereof according to a sixth embodiment of the present invention will be described with reference to Figs. 16 and 17. Components similar to those in the photoelectric conversion devices according to the first to fifth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 16 is a circuit diagram showing an example of the configuration of a level shift circuit 46 in a photoelectric conversion device according to this embodiment. Fig. 17 is a circuit diagram showing an example of the configuration of a level shift circuit 46 in a photoelectric conversion device according to a modification of this embodiment.

[0107] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion devices according to the first to fifth embodiments, except for the configuration of the level shift circuit 46. In this embodiment, differences from the photoelectric conversion devices according to the second to fourth embodiments will be mainly described, and descriptions of similarities with the photoelectric conversion devices according to the second to fourth embodiments will be omitted as appropriate.

[0108] The level shift circuit 46 of the photoelectric conversion device according to this embodiment differs from the second to fourth embodiments in that it is configured using an operational amplifier 170 instead of a source follower configured with a transistor M6, a cascode transistor M7, and a current source transistor M8. That is, the level shift circuit 46 of this embodiment can be configured to include an operational amplifier 170, a capacitance element C8, and a switch SW8, as shown in FIG. 16, for example.

[0109] The non-inverting input node of the operational amplifier 170 is connected to one node of a switch SW8 and one node of a capacitance element C8. The other node of the switch SW8 is connected to a node to which a predetermined voltage is supplied. The other node of the capacitance element C8 is connected to a signal output line 16A. The inverting input node of the operational amplifier 170 is connected to the output node of the operational amplifier 170. The inverting input node of the operational amplifier 170 is also the output node of the level shift circuit 46 from which the signal VLS is output.

[0110] By configuring the level shift circuit 46 in this way and controlling the voltage supplied via the switch SW8 to a predetermined voltage lower than the reset level of the signal output line 16A, it becomes possible to level-shift the voltage of the signal VLS output to the AD conversion circuit 50 in a lower direction. Also, while the fourth embodiment was configured such that variations in the threshold voltage of the transistor M6 affected the signal VLS output to the AD conversion circuit 50, in this embodiment, the use of the operational amplifier 170 makes it possible to reduce variations in the signal VLS.

[0111] Furthermore, by using the operational amplifier 170, it is possible to suppress image quality degradation when the AD conversion circuit 50 is a current-input type as shown in FIG. 11 . That is, when the level shift circuit 46 is a type using a source follower as in the second to fourth embodiments, a change in the output voltage and thus a change in the output current to the AD conversion circuit 50 causes a change in the current flowing through the transistor M6. This change in current causes fluctuations in the power supply voltage connected to the drain of the transistor M6, which also affects the power supply voltages supplied to the level shift circuits 46 of the column circuits 42 of other columns. As a result, image quality may be degraded. In this regard, when the operational amplifier 170 is used as in this embodiment, the improved power supply rejection ratio (PSRR) reduces the influence of inter-column interference via the power supply, thereby suppressing image quality degradation.

[0112] The additional configurations described in the third to fifth embodiments can also be applied to this embodiment. For example, in this embodiment, the low-voltage power supply node of the operational amplifier 170 is connected to the ground voltage node, but as shown in Fig. 16, the low-voltage power supply node of the operational amplifier 170 may be connected to a node to which a negative voltage VN is supplied. Furthermore, the current source 44 may be formed of a cascode transistor M9 and a current-source transistor M10, and the connection node between the cascode transistor M9 and the current-source transistor M10 may be connected to the output node of the level shift circuit 46 via a capacitance element C9.

[0113] As described above, according to this embodiment, a level shift circuit that level-shifts pixel signals in the direction of decreasing voltage and outputs them is provided at the input section of the column circuit, thereby realizing a smaller area and lower power consumption of the photoelectric conversion device.

[0114] [Seventh embodiment] A photoelectric conversion system according to a seventh embodiment of the present invention will be described with reference to Fig. 18. Fig. 18 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0115] The photoelectric conversion device 100 described in the first to sixth embodiments can be applied to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photoelectric conversion system. Fig. 18 illustrates a block diagram of a digital still camera as an example of such systems.

[0116] 18 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that adjusts the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any of the first to sixth embodiments, and converts the optical image formed by the lens 202 into image data.

[0117] The photoelectric conversion system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from a digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compressions as necessary and outputs the image data. The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 201 is formed, or may be formed in a semiconductor layer different from the semiconductor layer on which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed in the same semiconductor layer as the imaging device 201.

[0118] The photoelectric conversion system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The photoelectric conversion system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out imaging data from the recording medium 214. The recording medium 214 may be built into the photoelectric conversion system 200 or may be detachable.

[0119] Furthermore, the photoelectric conversion system 200 has an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the image capture device 201 and the signal processing unit 208. Here, timing signals and the like may be input from outside, and the photoelectric conversion system 200 only needs to have at least the image capture device 201 and the signal processing unit 208 that processes the output signal output from the image capture device 201.

[0120] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0121] As described above, according to this embodiment, a photoelectric conversion system can be realized to which the photoelectric conversion device 100 according to the first to sixth embodiments is applied.

[0122] [Eighth embodiment] A photoelectric conversion system and a moving object according to an eighth embodiment of the present invention will be described with reference to Fig. 19. Fig. 19 is a diagram showing the configuration of the photoelectric conversion system and a moving object according to this embodiment.

[0123] FIG. 19(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 includes an image capture device 310. The image capture device 310 is the photoelectric conversion device 100 described in any one of the first to sixth embodiments. The photoelectric conversion system 300 includes an image processing unit 312 that performs image processing on multiple pieces of image data acquired by the image capture device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the image capture device 310. The photoelectric conversion system 300 also includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 318 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0124] The photoelectric conversion system 300 is connected to a vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 318. The photoelectric conversion system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination unit 318. For example, if the determination result of the collision determination unit 318 indicates a high possibility of a collision, the control ECU 330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0125] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 300. Fig. 19(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0126] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0127] [Ninth embodiment] A device according to a ninth embodiment of the present invention will be described with reference to Fig. 20. Fig. 20 is a block diagram showing a schematic configuration of the device according to this embodiment.

[0128] FIG. 20 is a schematic diagram showing equipment EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device 100 of any of the first to sixth embodiments. All or part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometry sensor, or a distance measurement sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC, each including a photoelectric conversion unit, are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0129] The photoelectric conversion device APR may have a structure (chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may also be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected by through-silicon vias (TSVs), inter-chip wiring formed by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

[0130] The photoelectric conversion device APR may include, in addition to the semiconductor device IC, a package PKG that houses the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connecting members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device IC.

[0131] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes signals output from the photoelectric conversion device APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. The device EQP displays the signal output from the photoelectric conversion device APR on a display device DSPL and transmits the signal to the outside using a communication device (not shown) provided in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and arithmetic circuit unit provided in the photoelectric conversion device APR.

[0132] The device EQP shown in FIG. 20 can be an electronic device such as an information terminal with a photographing function (e.g., a smartphone or a wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP can also be transportation equipment (mobile object) such as a vehicle, a ship, or an aircraft. The device EQP can also be medical equipment such as an endoscope or a CT scanner. The device EQP can also be medical equipment such as an endoscope or a CT scanner.

[0133] The mechanical device MCHN in the transportation equipment can be used as a moving device. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device APR and for assisting and / or automating driving (piloting) using a photographing function. The processing device PRCS for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

[0134] The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser, and / or user. Therefore, if the photoelectric conversion device APR is installed in a device EQP, the value of the device EQP can also be increased. Therefore, when manufacturing and selling the device EQP, deciding to install the photoelectric conversion device APR according to this embodiment in the device EQP is advantageous in increasing the value of the device EQP.

[0135] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0136] Furthermore, in the above embodiment, one signal output line 16 is provided for each column of the pixel array section 10, but multiple signal output lines 16 may be provided for each column of the pixel array section 10. In this case, a column circuit 42 may be provided for each of the multiple signal output lines 16. Configuring the photoelectric conversion device in this manner makes it possible, for example, to simultaneously read out multiple rows of pixels 12.

[0137] Furthermore, the circuit configuration of the pixel 12 shown in FIG. 2 is an example and can be modified as appropriate. For example, each pixel 12 may have two or more photoelectric conversion elements. In this case, a configuration in which multiple photoelectric conversion elements share one FD node may be used. Also, a configuration in which multiple photoelectric conversion elements share one microlens, making it possible to detect a phase difference, may be used as a pupil-splitting pixel. Also, the pixel 12 does not necessarily have to have a selection transistor M4. Also, a configuration in which the capacitance value of the node FD is switchable may be used.

[0138] Furthermore, the photoelectric conversion systems shown in the fifth and sixth embodiments are examples of photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied, and photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 11 and 12(a).

[0139] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0140] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features.

[0141] The disclosure of the above embodiment includes the following configurations. (Configuration 1) a pixel including a photoelectric conversion unit and an output unit that outputs a signal based on charges generated by the photoelectric conversion unit, wherein a first power supply voltage is supplied to the output unit; a signal output line connected to the pixel; a level shift circuit connected to the signal output line, which level-shifts the output signal of the pixel in a direction to decrease the voltage, and outputs the signal; a signal processing circuit connected to the level shift circuit and performing predetermined signal processing on the output signal of the level shift circuit, The second power supply voltage supplied to the signal processing circuit is lower than the first power supply voltage. A photoelectric conversion device characterized by: (Configuration 2) The signal processing circuit further includes a comparison circuit to which the output signal of the level shift circuit is input. 2. The photoelectric conversion device according to configuration 1, (Configuration 3) a pixel having a photoelectric conversion unit and an output unit that outputs a signal based on charges generated by the photoelectric conversion unit; a signal output line connected to the pixel; a level shift circuit connected to the signal output line, which level-shifts the output signal of the pixel in a direction to decrease the voltage, and outputs the signal; a signal processing circuit having a capacitance element connected to the level shift circuit and receiving an output signal from the level shift circuit; A photoelectric conversion device comprising: (Configuration 4) The second power supply voltage supplied to the signal processing circuit is lower than the first power supply voltage supplied to the output section. 4. The photoelectric conversion device according to configuration 3. (Configuration 5) The signal processing circuit further includes a comparison circuit to which the output signal of the level shift circuit is input via the capacitance element. 5. The photoelectric conversion device according to configuration 3 or 4. (Configuration 6) The signal processing circuit has a sample-and-hold circuit including the capacitive element. 5. The photoelectric conversion device according to configuration 3 or 4. (Configuration 7) The signal processing circuit has a gain amplifier including the capacitance element. 5. The photoelectric conversion device according to configuration 3 or 4. (Configuration 8) The signal processing circuit has a switched capacitor circuit including the capacitance element. 5. The photoelectric conversion device according to configuration 3 or 4. (Configuration 9) The signal processing circuit has an oversampling type analog-to-digital conversion circuit. 5. The photoelectric conversion device according to configuration 3 or 4. (Configuration 10) The level shift circuit supplies a current to the signal processing circuit. 5. The photoelectric conversion device according to configuration 3 or 4. (Configuration 11) The level shift circuit includes a source follower circuit having an input node to which the pixel signal is input and an output node connected to the signal processing circuit. 11. The photoelectric conversion device according to any one of configurations 1 to 10. (Configuration 12) The back gate of the transistor that constitutes the source follower circuit is connected to the source of the transistor. 12. The photoelectric conversion device according to configuration 11. (Configuration 13) The level shift circuit has an operational amplifier having a pair of differential input nodes and an output node, one of the pair of differential input nodes being an input node to which a signal from the pixel is input, and the other of the pair of differential input nodes and the output node being connected to the signal processing circuit. 11. The photoelectric conversion device according to any one of configurations 1 to 10. (Configuration 14) The level shift circuit has a first power supply node to which a third power supply voltage is supplied and a second power supply node to which a fourth power supply voltage is supplied. 14. The photoelectric conversion device according to any one of configurations 11 to 13. (Configuration 15) The fourth power supply voltage is a ground voltage. 15. The photoelectric conversion device according to configuration 14. (Configuration 16) The fourth power supply voltage has a polarity opposite to that of the third power supply voltage. 15. The photoelectric conversion device according to configuration 14. (Configuration 17) The second power supply voltage supplied to the signal processing circuit is the same as the third power supply voltage. 17. The photoelectric conversion device according to any one of configurations 14 to 16. (Configuration 18) The level shift circuit further includes a clamp circuit provided between the pixel and the input node. 18. The photoelectric conversion device according to any one of configurations 11 to 17. (Configuration 19) The clamp circuit includes a second capacitance element connected between the pixel and the input node, and a switch provided between the input node and a fifth power supply voltage. 19. The photoelectric conversion device according to configuration 18. (Configuration 20) The fifth power supply voltage is variable. 20. The photoelectric conversion device according to configuration 19, (Configuration 21) a current source having a current source transistor connected to the signal output line and supplying a bias current to the output section of the pixel; The level shift circuit further includes a third capacitance element connected between the current source transistor and the output node. 21. The photoelectric conversion device according to any one of configurations 11 to 20. (Configuration 22) a plurality of the pixels arranged in a plurality of columns; a plurality of signal output lines, at least one of which is provided for each of the plurality of columns, each of which is connected to the pixels in the corresponding column; The level shift circuit and the signal processing circuit are provided corresponding to each of the plurality of signal output lines. 22. The photoelectric conversion device according to any one of configurations 1 to 21, (Configuration 23) The photoelectric conversion device according to any one of structures 1 to 22; a signal processing device that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising: (Configuration 24) A mobile object, The photoelectric conversion device according to any one of structures 1 to 22; a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object characterized by having: (Configuration 25) The photoelectric conversion device according to any one of structures 1 to 22; an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on the information obtained by the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; and a storage device that stores information obtained by the photoelectric conversion device; An apparatus characterized by comprising: [Explanation of symbols]

[0142] M6...Transistor 12...pixels 16A, 16B...Signal output line 42...column circuit 44,48…Current source 46...Level shift circuit 50...AD conversion circuit 100...Photoelectric conversion device

Claims

1. a pixel including a photoelectric conversion unit and an output unit that outputs a signal based on charges generated by the photoelectric conversion unit, wherein a first power supply voltage is supplied to the output unit; a signal output line connected to the pixel; a level shift circuit connected to the signal output line, which level-shifts the output signal of the pixel in a direction to decrease the voltage, and outputs the signal; a signal processing circuit connected to the level shift circuit and performing predetermined signal processing on the output signal of the level shift circuit, The second power supply voltage supplied to the signal processing circuit is lower than the first power supply voltage. A photoelectric conversion device characterized by:

2. The signal processing circuit further includes a comparison circuit to which the output signal of the level shift circuit is input.

2. The photoelectric conversion device according to claim 1.

3. a pixel having a photoelectric conversion unit and an output unit that outputs a signal based on charges generated by the photoelectric conversion unit; a signal output line connected to the pixel; a level shift circuit connected to the signal output line, which level-shifts the output signal of the pixel in a direction to decrease the voltage, and outputs the signal; a signal processing circuit having a capacitance element connected to the level shift circuit and receiving an output signal from the level shift circuit; A photoelectric conversion device comprising:

4. The second power supply voltage supplied to the signal processing circuit is lower than the first power supply voltage supplied to the output section.

4. The photoelectric conversion device according to claim 3.

5. The signal processing circuit further includes a comparison circuit to which the output signal of the level shift circuit is input via the capacitance element.

4. The photoelectric conversion device according to claim 3.

6. The signal processing circuit has a sample-and-hold circuit including the capacitive element.

4. The photoelectric conversion device according to claim 3.

7. The signal processing circuit has a gain amplifier including the capacitance element.

4. The photoelectric conversion device according to claim 3.

8. The signal processing circuit has a switched capacitor circuit including the capacitance element.

4. The photoelectric conversion device according to claim 3.

9. The signal processing circuit has an oversampling type analog-to-digital conversion circuit.

4. The photoelectric conversion device according to claim 3.

10. The level shift circuit supplies a current to the signal processing circuit.

4. The photoelectric conversion device according to claim 3.

11. The level shift circuit includes a source follower circuit having an input node to which the pixel signal is input and an output node connected to the signal processing circuit.

11. The photoelectric conversion device according to claim 1.

12. The back gate of the transistor that constitutes the source follower circuit is connected to the source of the transistor.

12. The photoelectric conversion device according to claim 11.

13. The level shift circuit has an operational amplifier having a pair of differential input nodes and an output node, one of the pair of differential input nodes being an input node to which a signal from the pixel is input, and the other of the pair of differential input nodes and the output node being connected to the signal processing circuit.

11. The photoelectric conversion device according to claim 1.

14. The level shift circuit has a first power supply node to which a third power supply voltage is supplied and a second power supply node to which a fourth power supply voltage is supplied.

12. The photoelectric conversion device according to claim 11.

15. The fourth power supply voltage is a ground voltage.

15. The photoelectric conversion device according to claim 14.

16. The fourth power supply voltage has a polarity opposite to that of the third power supply voltage.

15. The photoelectric conversion device according to claim 14.

17. The second power supply voltage supplied to the signal processing circuit is the same as the third power supply voltage.

15. The photoelectric conversion device according to claim 14.

18. The level shift circuit further includes a clamp circuit provided between the pixel and the input node.

12. The photoelectric conversion device according to claim 11.

19. The clamp circuit includes a second capacitance element connected between the pixel and the input node, and a switch provided between the input node and a fifth power supply voltage.

19. The photoelectric conversion device according to claim 18.

20. The fifth power supply voltage is variable.

20. The photoelectric conversion device according to claim 19.

21. a current source having a current source transistor connected to the signal output line and supplying a bias current to the output section of the pixel; The level shift circuit further includes a third capacitance element connected between the current source transistor and the output node.

12. The photoelectric conversion device according to claim 11.

22. a plurality of the pixels arranged in a plurality of columns; a plurality of signal output lines, at least one of which is provided for each of the plurality of columns, each of which is connected to the pixels in a corresponding column; The level shift circuit and the signal processing circuit are provided corresponding to each of the plurality of signal output lines.

11. The photoelectric conversion device according to claim 1.

23. The photoelectric conversion device according to any one of claims 1 to 10, a signal processing device that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

24. A mobile object, The photoelectric conversion device according to any one of claims 1 to 10, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object characterized by having:

25. The photoelectric conversion device according to any one of claims 1 to 10, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on the information obtained by the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; and a storage device that stores information obtained by the photoelectric conversion device; An apparatus characterized by comprising:

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