Novel intelligent power driving chip high-side continuous power supply circuit

Abstract

The invention relates to the technical field of intelligent power driving in analog integrated circuits, in particular to a novel intelligent power driving chip high-side continuous power supply circuit which comprises a novel charge pump bootstrap power supply circuit and a charge pump capacitor Ccharge. According to the novel charge pump bootstrap power supply circuit, an oscillator is integrated at the control end of a voltage withstanding switch S2A, a clock signal CLK is generated through the oscillator to control on and off of the voltage withstanding switch S2A, meanwhile, the dV / dt state of a floating ground end HS of a charge pump circuit is detected, a dV / dt detection adaptive circuit is matched to generate a control signal of a voltage withstanding switch S1A, and the voltage withstanding switch S2A is controlled to be switched on and off. A high-side continuous power supply circuit is formed by combining charge pump diodes D1 and D2 and a charge pump capacitor Ccharge and continuously supplies power to a bootstrap capacitor Cboot; according to the novel charge pump bootstrap power supply circuit, a high-side integrated level shift circuit in the novel charge pump bootstrap power supply circuit is effectively prevented from working in a high-frequency state, and the dynamic power consumption of the circuit is remarkably reduced while the relatively high power supply efficiency is maintained.

Description

Technical Field

[0001] This invention relates to the field of intelligent power drive technology in analog integrated circuits, and specifically to a novel intelligent power drive chip high-side continuous power supply circuit. Background Technology

[0002] With the advancement of microelectronics technology, power semiconductor technology has become the core of modern power electronics. Advanced technologies, represented by intelligent power drives, are increasingly widely used in numerous industrial control fields. Among them, half-bridge drive technology, due to its electrical isolation and ease of implementation, is commonly integrated into intelligent power drive chips. In traditional half-bridge drive architectures, to power the high-side gate drive circuit, a power supply referenced to the floating ground voltage VS is required, ensuring that the voltage difference between the high-side power supply voltage VB and VS remains within the allowable operating range. Currently, bootstrap circuits composed of bootstrap diodes and bootstrap capacitors are widely used, utilizing the characteristic that the voltage across a capacitor cannot change abruptly and the forward conduction characteristic of a diode to provide a floating power supply for the high-side gate drive circuit.

[0003] However, this power supply structure has the following limitations: when the upper arm of the half-bridge circuit is in a state of prolonged conduction and the lower arm is continuously off, the bootstrap capacitor will be in a continuous discharge process. At this time, the high-voltage side power supply structure lacks an effective circuit to charge the bootstrap capacitor, causing the stored energy of the capacitor to be continuously consumed, the high-side power supply voltage VB to continue to drop, and eventually it will be unable to maintain the normal operation of the upper arm. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides a novel high-side continuous power supply circuit for a smart power driver chip, comprising a novel charge pump bootstrap power supply circuit disposed on-chip, and a charge pump capacitor C disposed off-chip. charge The novel charge pump bootstrap power supply circuit includes a level shifting circuit, an oscillator, a clock synchronization control circuit, a delay matching circuit, a dV / dt detection adaptive circuit, a first buffer, a second buffer, and a withstand voltage switch S. 1A and withstand voltage switch S 2A Diodes D1 and D2; the output terminal of diode D1 is connected to the input terminal of diode D2, and this connection point is denoted as the floating power supply terminal HB of the charge pump circuit, with its voltage being the high-side floating power supply VB; withstand voltage switch S. 2A The source and withstand voltage switch S 1A The drain connection is denoted as the floating ground terminal HS of the charge pump circuit, and its voltage is the high-side floating ground VS; where:

[0005] An oscillator is used to generate the clock signal CLK.

[0006] The level shifting circuit is used to receive the high-side control signal HIN and output the control signal Hctrl.

[0007] The clock synchronization control circuit is used to synchronize the control signal Hctrl with the clock signal CLK, and outputs the control signal ZH to control the withstand voltage switch S. 2A Control;

[0008] The delay matching circuit is used to receive the low-side control signal LIN and output the control signal Lctrl to control the withstand voltage switch S. 1A and S 2A The control signal transmission delay prevents the withstand voltage switch S 1A and S 2A Straight-through;

[0009] The dV / dt detection adaptive circuit receives the control signal Lctrl and adaptively generates the control signal ZL by detecting the floating ground terminal HS of the charge pump circuit to control the withstand voltage switch S. 1A Control;

[0010] The first buffer is used to buffer and shape the control signal ZH;

[0011] The second buffer is used to buffer and shape the control signal ZL.

[0012] Furthermore, the clock synchronization control circuit includes a NAND gate NAND1 and a D flip-flop DFF1 connected thereto with enable control;

[0013] The D flip-flop DFF1 and NAND gate NAND1 are powered by the floating power supply terminal HB and the floating ground terminal HS of the charge pump circuit. The input of the D flip-flop is the clock signal CLK. When the control signal Hctrl received by the D flip-flop DFF1 is low, the signal ZH output by the NAND gate NAND1 is constant high. When the control signal Hctrl received by the D flip-flop DFF1 is high, the signal ZH output by the NAND gate NAND1 changes synchronously with the clock signal CLK.

[0014] Furthermore, the dV / dt detection adaptive circuit includes a dV / dt detection circuit and an adaptive clock control circuit, wherein:

[0015] The dV / dt detection circuit is used to detect the dV / dt state of the floating ground terminal HS of the charge pump circuit.

[0016] An adaptive clock control circuit is used to perform logical operations based on the signal output by the dV / dt detection circuit, and outputs a signal ZL.

[0017] Furthermore, the dV / dt detection circuit includes a withstand voltage transistor S. 3A Detection resistor Rs and Zener diode Dz; withstand voltage diode S 3AThe drain of the charge pump circuit is connected to the floating ground terminal HS, and the withstand voltage tube S 3A The gate of the diode is connected to its source; the source of the voltage-depleting diode is connected to one end of the sensing resistor Rs, and the other end of the sensing resistor Rs is grounded; the input of the Zener diode Dz is grounded, and the output of the Zener diode Dz is connected to one end of the sensing resistor. This connection point is denoted as the Vsense node; the Vsense node is connected to the adaptive clock control circuit.

[0018] Furthermore, the adaptive clock control circuit includes a D flip-flop DFF2, an inverter INV1, an inverter INV2, a delay module 1, a delay module 2, a NOR gate NOR1, and a NOR gate NOR2; wherein:

[0019] The D terminal of D flip-flop DFF2 is connected to the power supply voltage VCC. The CLR terminal of D flip-flop DFF2 is connected to the input terminal of delay module 1. The Q terminal of D flip-flop DFF2 is connected to the input terminal of inverter INV1. The output terminal of inverter INV1 is connected to the input terminal of delay module 2. The output terminal of delay module 2 is connected to one input terminal of NOR gate. The output terminal of delay module 1 is connected to the input terminal of inverter INV2. The output terminal of inverter INV2 is connected to the other input terminal of NOR gate NOR1. The Q terminal of D flip-flop DFF2 is also connected to the other input terminal of NOR gate NOR1. The output terminal of NOR gate NOR1 is connected to one input terminal of NOR gate NOR2. The low-side control signal LIN is connected to the other input terminal of NOR gate NOR2. The output terminal of NOR gate NOR2 outputs signal ZL.

[0020] Furthermore, the delay time t of delay module 1 Delay1 The clock frequency f of the oscillator in the novel charge pump bootstrap power supply circuit CLK The relationship is as follows:

[0021] ;

[0022] Delay time t of delay module 2 Delay2 The clock frequency f of the oscillator in the novel charge pump bootstrap power supply circuit CLK The relationship is as follows:

[0023] ;

[0024] In the formula, D is the clock signal CLK controlling the withstand voltage switch S. 2A Duty cycle of conduction, t DT For withstand voltage switch S 2A Turn off to withstand voltage switch S 1A Dead time at startup, t D This is the transmission delay of the clock signal CLK to the Vsense node.

[0025] The beneficial effects of this invention are:

[0026] This invention discloses a novel high-side continuous power supply circuit for an intelligent power driver chip. It employs clock synchronization control technology, charge pump floating ground dV / dt detection technology, and adaptive clock control technology to reduce the dynamic power consumption of the charge pump bootstrap power supply circuit under high-frequency operation. Through the high-side integrated oscillator of the charge pump bootstrap power supply circuit, the synchronous oscillator outputs a clock signal CLK to control the withstand voltage switch S. 2A Control, and adaptively generate withstand voltage switch S for charge pump floating ground dV / dt detection. 1A Control signals prevent the high-voltage level shift circuit in the charge pump bootstrap power supply circuit from operating at high frequency, enabling the high-side continuous power supply circuit of the new intelligent power drive chip to maintain high power supply efficiency while having low dynamic power consumption. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a traditional half-bridge drive structure for a smart power drive chip.

[0028] Figure 2 This is a schematic diagram of a typical intelligent power driver chip's high-side continuous power supply circuit.

[0029] Figure 3 These are simulation results of the high-side constant-on state of a typical intelligent power drive chip's high-side continuous power supply circuit.

[0030] Figure 4 This is a schematic diagram of a novel intelligent power drive chip high-side continuous power supply circuit according to some embodiments of the present invention;

[0031] Figure 5 This is a schematic diagram of the clock synchronization control circuit shown in some embodiments of the present invention;

[0032] Figure 6 This is a schematic diagram of the dV / dt detection adaptive circuit shown in some embodiments of the present invention;

[0033] Figure 7 These are simulation results of the clock synchronization control circuit and dV / dt detection adaptive circuit shown in some embodiments of the present invention;

[0034] Figure 8 These are simulation results of the high-side continuous power supply circuit of the novel intelligent power drive chip shown in some embodiments of the present invention;

[0035] Figure 9 These are schematic diagrams of delay module circuits shown in some embodiments of the present invention;

[0036] Figure 10 These are schematic diagrams of level shifting circuits shown in some embodiments of the present invention;

[0037] Figure 11 These are schematic diagrams of delay matching circuits shown in some examples of the present invention. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] Figure 1 A schematic diagram of a traditional half-bridge drive structure for a smart power drive chip is shown. Figure 2 This is a schematic diagram of a typical intelligent power drive chip's high-side continuous power supply circuit.

[0040] Traditional half-bridge drive structure, such as Figure 1 As shown, it mainly includes a low-side gate drive circuit, a high-side gate drive circuit, and an on-chip integrated bootstrap diode D. boot Meanwhile, an external bootstrap capacitor C is integrated. boot The upper half-bridge power device S2 and the lower half-bridge power device S1.

[0041] The low-side gate drive circuit mainly consists of a delay matching circuit and a buffer stage circuit. Its function is to match the timing delays of the high-side and low-side control signals to prevent shoot-through risk between the upper arm power device S2 and the lower arm power device S1 of the half-bridge. The high-side gate drive circuit mainly consists of a level shifting circuit and a buffer stage circuit, used to convert the low-side control signal into a high-voltage floating power rail signal, thereby controlling the upper arm power device S2 of the half-bridge. The on-chip bootstrap diode D... boot With external bootstrap capacitor C boot Together they form a bootstrap circuit, providing a floating power supply for the high-side gate drive circuit.

[0042] However Figure 1 The circuit shown has the following problem: when the upper arm of the half-bridge is on for an extended period and the lower arm is off for an extended period, the bootstrap capacitor remains in a discharging state. At this time, the high-voltage side power supply structure lacks a circuit to charge the bootstrap capacitor, causing the energy on the capacitor to be completely depleted. VB will then continuously decrease until the upper arm fails to function properly. Therefore, some have proposed using charge pump bootstrap power supply technology to design a continuous high-side power supply circuit, such as... Figure 2 As shown, a charge pump bootstrap power supply circuit was added on-chip, and a charge pump capacitor C was also added off-chip. chargeThe charge pump bootstrap power supply circuit is the core circuit of the high-side continuous power supply circuit, mainly including an oscillator, a high-voltage level shifting circuit, a delay matching circuit, a buffer stage circuit, and a withstand voltage switch S. 1A and S 2A Combined with the external charge pump capacitor Ccharge, the upper bridge arm S2 is continuously turned on.

[0043] However, Figure 1 The circuit shown has the following problem: when the upper arm power device S2 of the half-bridge is turned on for a long time and the lower arm power device S1 of the half-bridge is turned off for a long time, the external bootstrap capacitor C... boot It will continue to discharge. Due to the lack of an external bootstrap capacitor C in the high-voltage side power supply structure... boot The energy stored in the charging circuit will gradually be depleted, causing the VB voltage to drop continuously, eventually rendering the power device S2 in the upper arm of the half-bridge unable to function properly. To address this, researchers have further proposed a high-side continuous power supply circuit employing charge pump bootstrap power supply technology, such as... Figure 2 As shown in the diagram. This circuit integrates a charge pump bootstrap power supply module inside the chip, and adds a charge pump capacitor C externally to the chip. charge The charge pump bootstrap power supply circuit, as the core component of the high-side continuous power supply, mainly includes an oscillator, a high-voltage level shifting circuit, a delay matching circuit, a buffer stage circuit, and a withstand voltage switch S. 1A and S 2A This circuit is connected to the external charge pump capacitor C. charge Working together, they enable the power device S2 of the upper arm of the half-bridge to remain continuously on.

[0044] Specifically, when the lower arm power device S1 of the half-bridge is turned off and the upper arm power device S2 of the half-bridge is turned on, the bootstrap capacitor C boot When in high-voltage bootstrap mode, the bootstrap diode D... boot Unable to transfer voltage from power supply voltage VCC to C due to reverse voltage. boot Energy is replenished. At this time, the charge pump bootstrap power supply circuit starts working, controlling the withstand voltage switch S through the drive signal generated by the oscillator. 1A and S 2A The switching on and off of the charge pump capacitor C causes the charge pump capacitor C to switch on and off. charge To the bootstrap capacitor C boot Power supply. According to the withstand voltage switch S 1A and S 2A Depending on the conduction state, the operation of the charge pump bootstrap power supply circuit can be divided into the following four stages.

[0045] Phase 1: Withstand Voltage Switch S 1A Open and withstand voltage switch S 2A When the circuit is turned off, the power supply voltage VCC flows through diode D1 and charge pump capacitor C. chargeand withstand voltage switch S 1A A circuit is formed between VCC and ground, and VCC is connected to the charge pump capacitor C through diode D1. charge Charge.

[0046] Phase Two: Withstand Voltage Switch S 1A and withstand voltage switch S 2A All are turned off, at which point the charge pump capacitor C charge The charging path is shut off, and the charge pump capacitor C charge For withstand voltage switches only S 2A Provides operating voltage, charge pump capacitor C charge It is in a low-power standby state.

[0047] Phase 3: Withstand Voltage Switch S 1A Off and withstand voltage switch S 2A When the charge pump capacitor C is turned on, charge Diode D2 and bootstrap capacitor C boot A closed loop is formed between them, and the charge pump capacitor C charge Diode D2 serves as the bootstrap capacitor C. boot Charge.

[0048] Phase 4: Withstand Voltage Switch S 1A and withstand voltage switch S 2A All are turned off, at which point the charge pump capacitor C charge and bootstrap capacitor C boot Both are in bootstrap operation mode, and the circuit is in a low-power standby state similar to the second stage, i.e., the charge pump capacitor C... charge For withstand voltage switches only S 2A Provides operating voltage.

[0049] The above four operating stages repeat in this manner. Even if the power device S2 of the upper arm of the half-bridge is turned on for a long time, the bootstrap capacitor C... boot It can still charge continuously, meaning that the operating voltage VB can be continuously powered when the operating voltage VS is at a high level.

[0050] Figure 3 It is based on Figure 2 The simulation results are shown for a typical intelligent power drive chip high-side continuous power supply circuit.

[0051] Figure 3 The left figure shows the bootstrap capacitor C of the intelligent power drive chip with and without high-side continuous power supply circuit in the constantly open state of the power device S2 on the upper arm of the half-bridge. boot As shown in the voltage simulation results, the intelligent power drive chip with integrated high-side continuous power supply circuit can achieve high-side continuous power supply function when the power device S2 in the upper arm of the half-bridge is always on, and the high-side power supply voltage is relatively stable. However, the key to its realization is the withstand voltage switch S. 1AS 2A High-frequency operation. Due to the withstand voltage switch S 1A S 2A The control signals are all generated by the oscillator in the low-voltage domain, and the withstand voltage switch S 2A The control of the oscillator needs to be achieved by converting the low-voltage control signal through a high-voltage level shift circuit. Therefore, as the operating frequency of the oscillator increases, the dynamic power consumption of the high-voltage level shift circuit will increase rapidly. However, the power supply efficiency is low when operating at low frequency. Figure 3 The right figure shows the simulation results of dynamic power consumption of the high-side continuous power supply circuit at different oscillator frequencies. As can be seen from the figure, as the operating frequency increases from 10kHz to 1MHz, the dynamic power consumption of the circuit increases from 2.4738mW to 215.72mW. Therefore, the typical intelligent power drive chip's high-side continuous power supply circuit has a contradictory problem between dynamic power consumption and power supply efficiency, and further improvements are still needed.

[0052] Figure 4 This is a schematic diagram of a novel intelligent power drive chip high-side continuous power supply circuit, as shown in some embodiments of the present invention.

[0053] This invention specification provides a novel high-side continuous power supply circuit for a smart power driver chip in some embodiments, such as... Figure 4 As shown, the charge pump bootstrap power supply circuit is further optimized on the high-side continuous power supply circuit of a typical intelligent power driver chip, and a novel charge pump bootstrap power supply circuit is proposed to replace it.

[0054] The novel charge pump bootstrap power supply circuit includes a level shifting circuit, an oscillator, a clock synchronization control circuit, a delay matching circuit, a dV / dt detection adaptive circuit, a first buffer, a second buffer, and a withstand voltage switch S. 1A and withstand voltage switch S 2A Diodes D1 and D2, where:

[0055] A level shifting circuit is used to receive the high-side control signal HIN and convert it into a control signal Hctrl for starting the new charge pump bootstrap power supply circuit.

[0056] An oscillator is used to generate the clock signal CLK.

[0057] The clock synchronization control circuit is used to synchronize the control signal Hctrl with the clock signal CLK, and outputs the control signal ZH to control the withstand voltage switch S. 2A Control;

[0058] The delay matching circuit is used to receive the low-side control signal LIN and output the control signal Lctrl to control the withstand voltage switch S. 1A and S 2A The control signal transmission delay causes the withstand voltage switch S to...1A and S 2A The control signal transmission delay is consistent to avoid direct transmission between the two;

[0059] The dV / dt detection adaptive circuit receives the control signal Lctrl and adaptively generates the control signal ZL by detecting the floating ground terminal HS of the charge pump circuit to control the withstand voltage switch S. 1A Control;

[0060] The first buffer is used to buffer and shape the control signal ZH to improve the driving capability, so that the shaped control signal ZH can better control the withstand voltage switch S. 2A On and off;

[0061] The second buffer is used to buffer and shape the control signal ZL, improving its driving capability and enabling the shaped control signal ZL to better control the withstand voltage switch S. 1A Turning it on and off.

[0062] Meanwhile, the input terminal of diode D1 is connected to the power supply voltage VCC and the bootstrap diode D. boot The input terminal of diode D1 is connected to the input terminal of diode D2; this connection point is denoted as the floating power supply terminal HB of the charge pump circuit, and its voltage is the high-side floating power supply VB; the output terminal of diode D2 is connected to the bootstrap diode D. boot The output terminal and high-side gate drive circuit. Withstand voltage switch S 2A The source and withstand voltage switch S 1A The drain connection is denoted as the charge pump circuit floating ground HS, and its voltage is the high-side floating ground VS; the withstand voltage switch S 2A The gate is connected to the first buffer, and the withstand voltage switch S 2A The drain is connected to the high-side gate drive circuit. The withstand voltage switch S... 1A The gate is connected to the second buffer, and the withstand voltage switch S 1A The source is connected to the low-side gate drive circuit. The charge pump capacitor C... charge The two ends are respectively connected to the floating power terminal HB of the charge pump circuit and the floating ground terminal HS of the charge pump circuit.

[0063] The novel charge pump bootstrap power supply circuit uses a withstand voltage switch S 2A The control unit integrates an oscillator, which generates a clock signal CLK to control the withstand voltage switch S. 2A The switch is turned on and off, and to prevent accidental triggering of the withstand voltage switch S other than the clock signal CLK. 2A The system is now enabled, and a clock synchronization control circuit has been added to connect to the oscillator. Furthermore, the new charge pump bootstrap power supply circuit detects the dV / dt state of the floating ground terminal HS of the charge pump circuit, and in conjunction with the dV / dt detection adaptive circuit, generates a withstand voltage switch S.1A The control signal, combined with the charge pump diodes D1 and D2 and the charge pump capacitor C charge This forms a high-side continuous power supply circuit, continuously supplying power to the bootstrap capacitor C. boot Provides power. This design effectively avoids the high-side integrated level shifting circuit in novel charge pump bootstrap power supply circuits operating at high frequencies, significantly reducing the circuit's dynamic power consumption while maintaining high power supply efficiency.

[0064] Figure 5 This is a schematic diagram of the clock synchronization control circuit shown in some embodiments of the present invention. Figure 6 This is a schematic diagram of the dV / dt detection adaptive circuit shown in some embodiments of the present invention.

[0065] In some embodiments, the principle of the clock synchronization control circuit is as follows: Figure 5 As shown, it mainly consists of a D flip-flop DFF1 with enable control and a NAND gate NAND1. The D terminal of the D flip-flop DFF1 is connected to the floating power supply terminal HB of the charge pump circuit, and the CLR terminal of the D flip-flop DFF1 is connected to the control signal Hctr1; the two input terminals of the NAND gate NAND1 are connected to the Q terminal of the D flip-flop DFF1 and the clock signal CLK, respectively.

[0066] The D flip-flop DFF1 and the NAND gate NAND1 are powered by the floating power supply terminal HB and the floating ground terminal HS of the charge pump circuit. The input of the D flip-flop is the clock signal CLK. When the control signal Hctrl received by the D flip-flop DFF1 is low, the enable output of the clock synchronization control circuit, i.e., the signal ZH output by the NAND gate NAND1, is always high. When the control signal Hctrl received by the D flip-flop DFF1 is high, the enable output detects the rising edge of the clock signal CLK, and the signal ZH output by the NAND gate NAND1 changes synchronously with the clock signal CLK. Figure 7 The left figure shows the simulation results of the clock synchronization control circuit.

[0067] In some embodiments, the dV / dt detection adaptive circuit includes a dV / dt detection circuit and an adaptive clock control circuit, such as... Figure 6 As shown, where:

[0068] The dV / dt detection circuit is used to detect the dV / dt state of the floating ground terminal HS of the charge pump circuit.

[0069] An adaptive clock control circuit is used to perform logical operations based on the signal output by the dV / dt detection circuit, and outputs a signal ZL.

[0070] Specifically, the dV / dt detection circuit includes a withstand voltage transistor S. 3A Detection resistor Rs and Zener diode Dz; withstand voltage diode S 3AThe drain of the charge pump circuit is connected to the floating ground terminal HS, and the withstand voltage tube S 3A The gate of the Zener diode is connected to its source; the source of the Zener diode is connected to one end of the sensing resistor Rs, and the other end of the sensing resistor Rs is grounded; the input of the Zener diode Dz is grounded; the output of the Zener diode Dz is connected to the sensing resistor R. S One end of the connection is denoted as the Vsense node; the Vsense node is connected to the adaptive clock control circuit.

[0071] When the high-side control signal HIN and the low-side control signal LIN control the upper arm power device S2 of the half-bridge to be constantly turned on, and at the same time the high-side control signal HIN and the low-side control signal LIN are converted into control signals Hctrl and Lctrl, the new charge pump bootstrap power supply circuit starts to work. At this time, the withstand voltage switch S 1A S 2A From the initial state S 1A Open, S 2A Switching off to S 1A Shutdown, S 2A When activated, the charge pump circuit switches from the floating ground terminal HS to VDC voltage, controlled by the withstand voltage transistor S. 3A The sensing resistor Rs detects the dV / dt signal at the floating ground terminal HS of the charge pump circuit, generating a rising edge at the Vsense node. The Zener diode Dz protects the Vsense node from overvoltage. The detection signal at the Vsense node is further processed by the adaptive clock control circuit, ultimately generating the withstand voltage switch S. 1A The control signal.

[0072] Specifically, such as Figure 6 As shown, the adaptive clock control circuit includes a D flip-flop DFF2, an inverter INV1, an inverter INV2, a delay module 1, a delay module 2, and a NOR gate NOR1 or NOR gate NOR2; wherein:

[0073] The D terminal of D flip-flop DFF2 is connected to the power supply voltage VCC. The CLR terminal of D flip-flop DFF2 is connected to the input terminal of delay module 1. The Q terminal of D flip-flop DFF2 is connected to the input terminal of inverter INV1. The output terminal of inverter INV1 is connected to the input terminal of delay module 2. The output terminal of delay module 2 is connected to one input terminal of NOR gate. The output terminal of delay module 1 is connected to the input terminal of inverter INV2. The output terminal of inverter INV2 is connected to the other input terminal of NOR gate NOR1. The Q terminal of D flip-flop DFF2 is also connected to the other input terminal of NOR gate NOR1. The output terminal of NOR gate NOR1 is connected to one input terminal of NOR gate NOR2. The low-side control signal LIN is connected to the other input terminal of NOR gate NOR2. The output terminal of NOR gate NOR2 outputs signal ZL.

[0074] The D flip-flop DFF2, inverters INV1 and INV2, delay module 1, delay module 2, NOR gate NOR1 and NOR gate NOR2 are all connected to the power supply voltage VCC and the ground terminal, respectively.

[0075] Specifically, the adaptive clock control circuit can be divided into two parts. The first part consists of a D flip-flop DFF2, an inverter INV2, and a delay module 1. This part mainly generates the withstand voltage switch S. 1A The control signal is turned off. When the D flip-flop DFF2 detects the rising edge of the Vsense node, it will toggle its output. After the delay time set by the delay module 1, the output of the D flip-flop DFF2 is reset. The falling edge of its reset output is the withstand voltage switch S. 1A The initial edge of the conduction control signal, the delay time t of delay module 1 Delay1 The clock frequency f of the oscillator in the novel charge pump bootstrap power supply circuit CLK The relationship is as follows:

[0076] (1)

[0077] In the formula, D is the clock signal CLK controlling the withstand voltage switch S. 2A Duty cycle of conduction, t DT For withstand voltage switch S 2A Turn off to withstand voltage switch S 1A Dead time at startup, t D This is the transmission delay of the clock signal CLK to the Vsense node.

[0078] The second part consists of inverter INV1, delay module 2, and NOR gate NOR1. When inverter INV1 and NOR gate NOR1 detect the falling edge of the reset output of D flip-flop DFF2, the delay module 2 and NOR gate NOR1 generate a pulse control signal corresponding to the falling edge, which is the withstand voltage switch S. 1A The conduction control signal, the delay time t of delay module 2 Delay2 The clock frequency f of the oscillator in the novel charge pump bootstrap power supply circuit CLK The relationship is as follows:

[0079] (2)

[0080] Therefore, the withstand voltage switch S can be designed using formulas (1) and (2). 2A The control signal ZH matches the S 1A Control signal ZL, Figure 7 The right figure shows the simulation results of the dV / dt detection adaptive circuit. The novel charge pump bootstrap power supply circuit uses a high-side integrated oscillator circuit and a synchronous clock signal to control the withstand voltage switch S. 2ATurning the switch on and off adaptively generates a withstand voltage switch S by detecting the dV / dt state of the HS node. 1A The control signal avoids the dynamic power consumption generated by the high-voltage level shift circuit in the high-frequency working state, so that the high-side continuous power supply circuit of the new intelligent power drive chip can maintain high power supply efficiency while having low dynamic power consumption.

[0081] Figure 8 The simulation results of the high-side continuous power supply circuit of the novel intelligent power drive chip are shown. With the upper bridge arm S2 constantly on, the novel charge pump bootstrap power supply circuit can effectively supply power to the bootstrap capacitor C. boot Power supply; As the operating frequency of the charge pump bootstrap power supply circuit increases, its dynamic power consumption increases slightly. The dynamic power consumption at the maximum operating frequency of 1MHz is only 1.288mW, which is much smaller than that of the high-side continuous power supply circuit of the traditional intelligent power drive chip.

[0082] Specifically, delay module 1 and delay module 2 have the same circuit structure, and can be adopted as follows: Figure 9 The delay circuit shown.

[0083] In some embodiments, the connection relationship of the circuit proposed in this invention is as follows:

[0084] The power supply voltage VCC is connected to the input terminal of diode D1 and the bootstrap diode D. boot The input terminal of diode D1 is connected to the input terminal of diode D2 and the charge pump capacitor C. charge One end of diode D2 is connected to the bootstrap diode D. boot The output terminal and the bootstrap capacitor C boot One end; charge pump capacitor C charge The other end is connected to the withstand voltage switch S 2A The source; bootstrap capacitor C boot The other end is connected to the withstand voltage switch S 2A The drain of the voltage-resistant switch S 2A The gate of the first buffer is connected to the output terminal of the first buffer. The power / ground pin of the first buffer is connected to the floating power terminal HB of the charge pump circuit and the floating ground terminal HS of the charge pump circuit.

[0085] The high-side control signal HIN connects the level shift circuit in the novel charge pump bootstrap power supply circuit and the level shift circuit in the high-side gate drive circuit. The level shift circuit in the novel charge pump bootstrap power supply circuit is connected to the output of diode D1, the clock synchronization control circuit, the signal input pin of the first buffer, and the withstand voltage switch S. 2A The source is connected; and one end of the level shift circuit in the novel charge pump bootstrap power supply circuit is grounded. The level shift circuit in the high-side gate drive circuit is connected to the output of diode D2 and the withstand voltage switch S. 2AThe drain of the first buffer is connected to the enable terminal of the third buffer. The clock synchronization control circuit is also connected to the enable terminal of the oscillator and the first buffer. The third buffer is a buffer in the high-side gate drive circuit. The signal input pin of the third buffer is connected to the withstand voltage switch S. 2A The drain of the third buffer is connected to the power supply pin of the third buffer, which is connected to the output of the diode D2. The output of the third buffer is connected to the gate of the power device S2 in the upper arm of the half-bridge.

[0086] The low-side control signal LIN connects to the delay matching circuits in both the novel charge pump bootstrap power supply circuit and the low-side gate drive circuit. The delay matching circuit in the novel charge pump bootstrap power supply circuit is connected to the power supply voltage VCC and the dV / dt detection adaptive circuit. The delay matching circuit in the low-side gate drive circuit is connected to the power supply voltage VCC and the enable terminal of the fourth buffer. Both delay matching circuits have a ground terminal. The fourth buffer is a buffer in the low-side gate drive circuit. The signal input pin of the fourth buffer is connected to the withstand voltage switch S. 1A The source of the fourth buffer is connected to the power supply voltage VCC, and the output of the fourth buffer is connected to the gate of the power device S1 in the lower arm of the half-bridge.

[0087] The dV / dt detection adaptive circuit is also connected to the withstand voltage switch S. 2A The source terminal of the first buffer and the enable terminal of the second buffer are connected. The signal input pin of the second buffer is connected to the withstand voltage switch S. 1A The source terminal of the first buffer and the power supply pin of the second buffer are connected to the power supply voltage VCC. The output terminal of the second buffer is connected to the withstand voltage switch S. 1A The gate of the withstand voltage switch S. 1A The source electrode is grounded.

[0088] The drain of the upper bridge arm power device S2 is connected to VDC, the source of the upper bridge arm power device S2 is connected to the drain of the lower bridge arm power device S1, and the source of the lower bridge arm power device S1 is grounded.

[0089] Specifically, the level shifting circuit and delay matching circuit of the present invention adopt existing circuits, wherein the level shifting circuit can adopt, for example, Figure 10 The circuit structure shown can be used with a delay matching circuit as follows: Figure 11 The circuit structure shown is shown.

[0090] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "setting," "connection," "fixing," "rotation," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Unless otherwise explicitly limited, those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0091] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A novel intelligent power drive chip high-side continuous power supply circuit, characterized in that, This includes a novel charge pump bootstrap power supply circuit located on-chip, and a charge pump capacitor C located off-chip. charge The novel charge pump bootstrap power supply circuit includes a level shifting circuit, an oscillator, a clock synchronization control circuit, a delay matching circuit, a dV / dt detection adaptive circuit, a first buffer, a second buffer, and a withstand voltage switch S. 1A and withstand voltage switch S 2A Diodes D1 and D2; the output terminal of diode D1 is connected to the input terminal of diode D2, and this connection point is denoted as the floating power supply terminal HB of the charge pump circuit, with its voltage being the high-side floating power supply VB; withstand voltage switch S. 2A The source and withstand voltage switch S 1A The drain connection is denoted as the floating ground terminal HS of the charge pump circuit, and its voltage is the high-side floating ground VS; where: An oscillator is used to generate the clock signal CLK. The level shifting circuit is used to receive the high-side control signal HIN and output the control signal Hctrl. The clock synchronization control circuit is used to synchronize the control signal Hctrl with the clock signal CLK, and outputs the control signal ZH to control the withstand voltage switch S. 2A Control; The delay matching circuit is used to receive the low-side control signal LIN and output the control signal Lctrl to control the withstand voltage switch S. 1A and S 2A The control signal transmission delay prevents the withstand voltage switch S 1A and S 2A Straight-through; The dV / dt detection adaptive circuit receives the control signal Lctrl and adaptively generates the control signal ZL by detecting the floating ground terminal HS of the charge pump circuit to control the withstand voltage switch S. 1A Control; The first buffer is used to buffer and shape the control signal ZH; The second buffer is used to buffer and shape the control signal ZL.

2. The novel intelligent power drive chip high-side continuous power supply circuit according to claim 1, characterized in that, The clock synchronization control circuit includes a NAND gate NAND1 and a D flip-flop DFF1 with enable control; The D flip-flop DFF1 and NAND gate NAND1 are powered by the floating power supply terminal HB and the floating ground terminal HS of the charge pump circuit. The input of the D flip-flop is the clock signal CLK. When the control signal Hctrl received by the D flip-flop DFF1 is low, the signal ZH output by the NAND gate NAND1 is constant high. When the control signal Hctrl received by the D flip-flop DFF1 is high, the signal ZH output by the NAND gate NAND1 changes synchronously with the clock signal CLK.

3. The novel intelligent power drive chip high-side continuous power supply circuit according to claim 1, characterized in that, The dV / dt detection adaptive circuit includes a dV / dt detection circuit and an adaptive clock control circuit, wherein: The dV / dt detection circuit is used to detect the dV / dt state of the floating ground terminal HS of the charge pump circuit. An adaptive clock control circuit is used to perform logical operations based on the signal output by the dV / dt detection circuit, and outputs a signal ZL.

4. The novel intelligent power drive chip high-side continuous power supply circuit according to claim 3, characterized in that, The dV / dt detection circuit includes a withstand voltage transistor S. 3A Detection resistor Rs and Zener diode Dz; withstand voltage diode S 3A The drain of the charge pump circuit is connected to the floating ground terminal HS, and the withstand voltage tube S 3A The gate of the transistor is connected to its source; the source of the Zener diode is connected to one end of the sensing resistor Rs, and the other end of the sensing resistor Rs is grounded; the input of the Zener diode Dz is grounded; the output of the Zener diode Dz is connected to one end of the sensing resistor, and this connection point is denoted as the Vsense node; the Vsense node is connected to the adaptive clock control circuit.

5. The novel intelligent power drive chip high-side continuous power supply circuit according to claim 4, characterized in that, The adaptive clock control circuit includes a D flip-flop (DFF2), an inverter (INV1), an inverter (INV2), a delay module 1, a delay module 2, and a NOR gate (NOR1 or NOR2); wherein: The D terminal of D flip-flop DFF2 is connected to the power supply voltage VCC. The CLR terminal of D flip-flop DFF2 is connected to the input terminal of delay module 1. The Q terminal of D flip-flop DFF2 is connected to the input terminal of inverter INV1. The output terminal of inverter INV1 is connected to the input terminal of delay module 2. The output terminal of delay module 2 is connected to one input terminal of NOR gate. The output terminal of delay module 1 is connected to the input terminal of inverter INV2. The output terminal of inverter INV2 is connected to the other input terminal of NOR gate NOR1. The Q terminal of D flip-flop DFF2 is also connected to the other input terminal of NOR gate NOR1. The output terminal of NOR gate NOR1 is connected to one input terminal of NOR gate NOR2. The low-side control signal LIN is connected to the other input terminal of NOR gate NOR2. The output terminal of NOR gate NOR2 outputs signal ZL.

6. The novel intelligent power drive chip high-side continuous power supply circuit according to claim 5, characterized in that, Delay time t of delay module 1 Delay1 The clock frequency f of the oscillator in the novel charge pump bootstrap power supply circuit CLK The relationship is as follows: ； Delay time t of delay module 2 Delay2 The clock frequency f of the oscillator in the novel charge pump bootstrap power supply circuit CLK The relationship is as follows: ； In the formula, D is the clock signal CLK controlling the withstand voltage switch S. 2A Duty cycle of conduction, t DT For withstand voltage switch S 2A Turn off to withstand voltage switch S 1A Dead time at startup, t D This is the transmission delay of the clock signal CLK to the Vsense node.

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