Bridge circuit

Abstract

To provide a bridge circuit that controls an ON / OFF state of a transistor with a relatively simple circuit.SOLUTION: A bridge circuit outputs an internal upper voltage on an upper line and an internal lower voltage on a lower line in response to an external power supply supplied to a first input terminal 12a and a second input terminal 12b. A bridge is arranged between the upper and lower lines, consisting of four transistors of a first upper transistor M1, a second lower transistor M2, a third upper transistor M3, and a fourth lower transistor M4. Then, the control terminal of the fourth transistor is connected to the first input terminal, the first transistor is controlled by the level of the control terminal of the fourth transistor or the first transistor is diode-connected, the control terminal of the third transistor is connected to the second input terminal, and the second transistor is controlled by the level of the control terminal of the fourth transistor or the first transistor is diode-connected.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a bridge circuit of a semiconductor integrated circuit that outputs an internal upper voltage and an internal lower voltage in response to an external power supply supplied to a first input terminal and a second input terminal. [Background technology]

[0002] In semiconductor integrated circuits, an external power supply is received at the input terminal and DC power is supplied to the internal circuit. However, problems can occur if the external power supply is reverse-connected to the input terminal. For example, normal circuits are not designed to handle reverse connections. Furthermore, even in a MOS transistor as a single element, when a reverse bias is applied to the semiconductor substrate, a current path for a parasitic bipolar element appears, preventing the expected operation.

[0003] A rectifier using a diode bridge is known to solve this problem. By rectifying the external power supply with a diode bridge and using it as the internal power supply, the problem of reverse connection of the external power supply to the input terminal is resolved.

[0004] Furthermore, a technique has been proposed in which transistors are used instead of diodes to reduce power loss in the diodes. For example, in Patent Document 1, the on / off control of each transistor in a transistor bridge is performed based on a power supply voltage monitoring comparator. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-220351 Summary of the Invention [Problem to be solved by the invention]

[0006] Here, the technology described in Patent Document 1 requires a circuit such as a power supply voltage monitoring comparator, which results in a large-scale circuit. [Means for solving the problem]

[0007] The bridge circuit according to the present disclosure comprises: A bridge circuit of a semiconductor integrated circuit that outputs an internal upper voltage to an upper line and an internal lower voltage to a lower line in response to an external power supply supplied to a first input terminal and a second input terminal, a first transistor connected between the upper line and the first input terminal; a second transistor connected between the lower line and the first input terminal; a third transistor connected between the upper line and the second input terminal; a fourth transistor connected between the lower line and the second input terminal; Including, a control terminal of the fourth transistor is connected to the first input terminal, and the first transistor is controlled by a level of the control terminal of the fourth transistor, or the first transistor is diode-connected; The control terminal of the third transistor is connected to the second input terminal, and the second transistor is controlled by the level of the control terminal of the fourth transistor, or the first transistor is diode-connected. [Effects of the Invention]

[0008] According to the bridge circuit of the present disclosure, it is possible to control the on / off of transistors using a relatively simple circuit. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is a circuit diagram illustrating a configuration of a bridge circuit according to an embodiment. [Figure 2] FIG. 10 is a circuit diagram showing a configuration of a first modified example. [Figure 3] FIG. 10 is a circuit diagram showing a configuration of a second modification. [Figure 4] FIG. 10 is a circuit diagram showing a configuration of a third modified example. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the following embodiments do not limit the present disclosure, and configurations formed by selectively combining multiple examples are also included in the present disclosure.

[0011] "Circuit configuration of embodiment" FIG. 1 is a circuit diagram showing the configuration of a bridge circuit according to an embodiment. The bridge circuit is formed as a semiconductor integrated circuit. A DC voltage from an external power supply 10 is supplied to a first input terminal 12a and a second input terminal 12b. In the illustrated example, the external power supply 10 is a DC power supply, and it is assumed that a positive external upper voltage VIN is supplied to the first input terminal 12a and a negative external lower voltage GND is input to the second input terminal 12b. However, as shown by the dashed line in the figure, there is no problem even if the external power supply 10 is connected in reverse, so that the external lower voltage GND is supplied to the first input terminal 12a and the external upper voltage VIN is input to the second input terminal 12b. Alternatively, an AC voltage may be input.

[0012] Four transistors M1, M2, M3, and M4 are connected to form a transistor bridge. The source of transistor M1 is connected to the drain of transistor M2. The source of transistor M3 is connected to the drain of transistor M4. The drain of transistor M1 is connected to the drain of transistor M3. The source of transistor M2 is connected to the source of transistor M4.

[0013] Here, transistor M1 is called the first transistor, transistor M2 the second transistor, transistor M3 the third transistor, and transistor M4 the fourth transistor. The gate of a MOSFET and the base of a bipolar transistor are called control terminals.

[0014] In this example, the transistors M1, M2, M3, and M4 are n-channel MOSFETs, but it is also possible to use p-channel transistors or a combination of a bipolar transistor and a diode.

[0015] A first input terminal 12a is connected to the connection point between the source of the transistor M1 and the drain of the transistor M2, and a second input terminal 12b is connected to the connection point between the source of the transistor M3 and the drain of the transistor M4.

[0016] The drains of the transistors M1 and M3 are connected to the internal upper line VHI, and the sources of the transistors M2 and M4 are connected to the internal lower line SUB.

[0017] The upper line VHI and the lower line SUB are connected to an internal circuit 14. The internal circuit 14 is a circuit that operates by receiving power supply from the upper line VHI and the lower line SUB, and various types of circuits are adopted depending on the purpose of the semiconductor integrated circuit.

[0018] The first input terminal 12a is connected to the gate of transistor M4 via resistor R2. The gate of transistor M2 is connected to the lower line SUB via transistor Q1. Transistor Q1 is a pnp transistor, and its emitter is connected to the gate of transistor M2 and its collector is connected to the lower line SUB. In this example, transistors Q1 and Q2 are pnp transistors, but p-channel MOSFETs or the like may also be used.

[0019] The second input terminal 12b is connected to the gate of transistor M2 via resistor R1. The gate of transistor M4 is connected to the lower line SUB via transistor Q2. Transistor Q2 is a pnp transistor, and its emitter is connected to the gate of transistor M4 and its collector is connected to the lower line SUB. The bases of transistors Q1 and Q2 are connected to the upper line VHI.

[0020] Here, transistors Q1 and Q2 are called the first and second protection transistors, respectively. Resistors R1 and R2 are called the first and second resistors, respectively. Furthermore, the voltage of the upper line VHI is called the internal upper voltage VHI, and the voltage of the lower line SUB is called the internal lower voltage SUB.

[0021] The gates of the transistors M2 and M4 are connected to an upper gate control circuit 16, which supplies information about the voltages at the gates of the transistors M2 and M4.

[0022] When the potential of the gate of transistor M2 is high and transistor M2 is on, the upper gate control circuit 16 drives the gate of transistor M1 to low level to turn transistor M1 off and drives the gate of transistor M3 to high level to turn transistor M3 on. Also, when the potential of the gate of transistor M4 is high and transistor M4 is on, the upper gate control circuit 16 drives the gate of transistor M3 to low level to turn transistor M3 off and drives the gate of transistor M1 to high level to turn transistor M1 on.

[0023] In the circuit of FIG. 1, when an external upper voltage VIN is input to the first input terminal 12a and an external lower voltage GND is input to the second input terminal 12b, the transistors M4 and M1 are turned on and the transistors M2 and M3 are turned off, so that the external upper voltage VIN is supplied to the upper line VHI and the external lower voltage GND is supplied to the lower line SUB.

[0024] Furthermore, when an external upper voltage VIN is input to the second input terminal 12b and an external lower voltage GND is input to the first input terminal 12a, the transistors M2 and M3 are turned on and the transistors M4 and M1 are turned off, whereby the external upper voltage VIN is supplied to the upper line VHI and the external lower voltage GND is supplied to the lower line SUB.

[0025] Even when transistors M1 and M3 are off, their parasitic diodes cause the upper line VHI to be at a high level, so transistors Q1 and Q2 are normally off. Meanwhile, when an external upper voltage VIN is supplied to either the first input terminal 12a or the second input terminal 12b, the gate voltage of transistor M2 or M4 may rise significantly. In this example, resistor R1 or R2 suppresses this rise, and in such cases, transistor Q1 or Q2 turns on to protect transistor M2 or M4.

[0026] Here, the upper gate control circuit 16 controls the gate voltages of transistors M1 and M3 as described above. Transistors M1 and M3 are n-channel transistors, and to turn on transistor M1 or M3, a control voltage higher than its source voltage by at least a threshold voltage must be supplied to its gate. Therefore, a control voltage can be generated by receiving a DC voltage from an external source or by boosting the voltage of the upper line VHI, and applied to the gate of the transistor M1 or M3 to be turned on. For example, the control voltage to the gate of transistor M1 can be turned on and off by the gate voltage of transistor M4, and the control voltage to the gate of transistor M3 can be turned on and off by the gate voltage of transistor M2. The control voltage can be turned on and off using, for example, a switch transistor. Alternatively, as in Variation 1, transistors M1 and M3 can be diode-connected, eliminating the upper gate control circuit 16.

[0027] "Variation 1" 2 is a circuit diagram showing the configuration of Modification 1. In this circuit, the transistors M2 and M4 are protected using a clamp voltage VST.

[0028] One end of resistor R3 is connected to the upper line VHI, and the other end of resistor R3 is connected to the cathode of Zener diode D2, the anode of which is connected to the lower line SUB. The junction of resistor R3 and Zener diode D2 is connected to the gate of n-channel transistor M7. The drain of transistor M7 is connected to the upper line VHI, and the source is connected to the lower line SUB via resistor R4. A clamp voltage VST is taken from the junction of the source of transistor M7 and resistor R4.

[0029] In this circuit, voltage is applied to Zener diode D2 from the upper line VHI via resistor R3. If the voltage at the cathode of Zener diode D2 is equal to or greater than the breakdown voltage of Zener diode D2, the voltage at the cathode of Zener diode D2 becomes the breakdown voltage Vbr. This causes the gate voltage of transistor M7 to become Vbr, and its source voltage becomes a voltage VST = Vbr - Vgs lower than the gate voltage. In this way, the clamp voltage VST can be set according to the breakdown voltage of Zener diode D2.

[0030] A transistor M5 is disposed between the first input terminal 12a and the resistor R2, and a transistor M6 is disposed between the second input terminal 12b and the resistor R1. The transistors M5 and M6 are n-channel transistors. The gates of the transistors M5 and M6 are connected together, to which a clamp voltage VST is supplied. In this example, the clamp voltage VST is also supplied to the bases of the transistors Q1 and Q2.

[0031] With this circuit, the source voltage of transistors M5 and M6 is clamped to VST-Vgs, and the base voltage of transistors Q1 and Q2 is clamped to VST+Vbe. This clamps the gate voltage of transistors M2 and M4 to a predetermined voltage, protecting transistors M2 and M4. Vbe is the base-emitter voltage.

[0032] In addition, in Modification 1, the upper gate control circuit 16 is omitted, and the gates and sources of the transistors M1 and M3 are short-circuited to function as diodes. As a result, a voltage corresponding to the external upper voltage VIN input to either the first input terminal 12a or the second input terminal 12b is set on the upper line VHI. Note that a forward voltage drop occurs due to the diode in the transistor M1 or the transistor M3, and VHI = VIN - Vf, but the transistors M2 and M4 still function as transistors. Note that the Vf is the voltage drop of the parasitic diode of the transistor M3.

[0033] "Variation 2" 3 is a circuit diagram showing the configuration of Modification 2. In this circuit, charge pumps 20a and 20b are provided instead of the upper gate control circuit 16 of FIG.

[0034] The charge pumps 20a and 20b are connected to the upper line VHI and boost the voltage of the upper line VHI. The charge pumps 20a and 20b may be configured using known capacitors. The charge pumps 20a and 20b may be configured in any manner as long as they can boost the voltage. For example, a boost circuit using a coil and a transistor may be used.

[0035] The gate voltage of transistor M4 is supplied to charge pump 20a, and when the gate voltage of transistor M4 is high, charge pump 20a supplies a boosted voltage to the gate of transistor M1 to turn on transistor M1. The gate voltage of transistor M2 is supplied to charge pump 20b, and when the gate voltage of transistor M4 is high, charge pump 20b turns on transistor M3 with the boosted voltage.

[0036] In this way, the circuit of the second modification can operate in the same manner as the circuit of FIG.

[0037] "Variation 3" 4 is a circuit diagram showing the configuration of Modification 3. This circuit includes charge pumps 20a and 20b and utilizes a clamp voltage VST.

[0038] That is, the configuration in which the gate voltages of the transistors M2 and M4 are clamped by the clamp voltage VST is the same as the configuration in Fig. 2. Also, the configuration of the charge pumps 20a and 20b that turn on and off the transistors M1 and M3 is the same as the second modification in Fig. 3.

[0039] "Effects of the embodiment" According to the bridge circuit of the above embodiment, the transistors constituting the bridge circuit can be turned on and off in accordance with the polarity of an external signal supplied to the input terminals. Therefore, the on and off of the transistors can be controlled using a relatively simple circuit. [Explanation of symbols]

[0040] 10 external power supply, 12a first input terminal, 12b second input terminal, 14 internal circuit, 16 upper gate control circuit, 20a, 20b charge pump.

Claims

1. A bridge circuit of a semiconductor integrated circuit that outputs an internal upper voltage to an upper line and an internal lower voltage to a lower line in response to an external power supply supplied to a first input terminal and a second input terminal, a first transistor connected between the upper line and the first input; a second transistor connected between the lower line and the first input; a third transistor connected between the upper line and the second input terminal; a fourth transistor connected between the lower line and the second input terminal; Including, a control terminal of the fourth transistor is connected to the first input terminal, and the first transistor is controlled by a level of the control terminal of the fourth transistor, or the first transistor is diode-connected; a control terminal of the third transistor is connected to the second input terminal, and the second transistor is controlled by a level of the control terminal of the fourth transistor, or the first transistor is diode-connected; Bridge circuit.

2. 2. The bridge circuit according to claim 1, The first input terminal is connected to a control terminal of the fourth transistor via a first resistor; The second input terminal is connected to the control terminal of the second transistor via a second resistor. Bridge circuit.

3. 2. The bridge circuit according to claim 1, The control end of the fourth transistor is connected to the lower line via a first protection transistor; a control end of the second transistor is connected to the lower line via a second protection transistor; Bridge circuit.

4. 2. The bridge circuit according to claim 1, the first to fourth transistors are n-channel MOSFETs, a charge pump for generating a control voltage higher than the internal upper voltage; the charge pump turns on the first transistor when the voltage of the control end of the fourth transistor is at a high level, and turns on the third transistor when the voltage of the control end of the second transistor is at a high level; Bridge circuit.

Images