Information processing device, information processing method, and program

Abstract

To provide an information processing device, information processing method, and program that can reduce the scale of computations and improve the uniformity of approximation error of a square root of an input value.SOLUTION: An information processing device 1 includes a determination unit configured to calculate the largest integer n that satisfies the expression [1] for an input numerical value x, and a first calculation unit configured to output a numerical value y obtained by performing, on the numerical value x, a computation that includes a term of the expression [2], in which a numerical value α is a predetermined constant. The numerical value α is a predetermined constant close to 1 / 3. The numerical value y obtained in this manner is an approximation of the square root of the numerical value x (i.e., √x).SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an information processing device, an information processing method, and a program. [Background technology]

[0002] Patent Document 1 discloses a device that performs square root approximation based on the Newton-Raphson method. In the method of Patent Document 1, the initial estimated value of the operation is set to a value that is a power of two according to the range of the input value, and division can be performed by bit shifting. Furthermore, Patent Document 1 also proposes limiting the number of iterations to one. In this way, the method of Patent Document 1 reduces the scale of the operation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-005802 Summary of the Invention [Problem to be solved by the invention]

[0004] In the square root approximation method disclosed in Patent Document 1, there are cases where it is required to improve the uniformity of approximation errors for input values. Therefore, an object of the present invention is to provide an information processing device, an information processing method, and a program that can reduce the scale of calculations and improve the uniformity of approximation errors for square roots for input values. [Means for solving the problem]

[0005] According to one disclosure of the present specification, For the input number x,

number

number

[0006] According to one disclosure of the present specification, An information processing method executed by an information processing device, For the input number x,

number

number

[0007] According to one disclosure of the present specification, For the input number x,

number

number

[0008] According to the present invention, there are provided an information processing device, an information processing method, and a program that can reduce the scale of calculations and improve the uniformity of the approximation error of the square root for an input value. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a hardware configuration of an information processing device according to a first embodiment. [Figure 2] FIG. 2 is a functional block diagram of a square root approximation process performed by the information processing device according to the first embodiment. [Figure 3] 1 is a graph showing a linear approximation of a square root function. [Figure 4] 1 is a graph showing linear approximation and piecewise linear approximation of a square root function. [Figure 5] 10 is a graph showing errors in linear approximation and piecewise linear approximation of a square root function. [Figure 6] 10 is a graph showing piecewise linear approximation with an increased number of divisions. [Figure 7] 10 is a graph showing the error of piecewise linear approximation with an increased number of divisions. [Figure 8] 1 is a table showing coordinates of division points of a piecewise linear function. [Figure 9] 10 is a graph showing relative errors according to a comparative example. [Figure 10] 5 is a flowchart showing an example of the operation of a determination unit according to the first embodiment. [Figure 11] FIG. 2 is a block diagram showing an example of the configuration of a first calculation unit according to the first embodiment. [Figure 12] 5 is a flowchart showing an example of the operation of a first calculation unit according to the first embodiment. [Figure 13] 10 is a flowchart showing another example of the operation of the first calculation unit according to the first embodiment. [Figure 14] FIG. 10 is a functional block diagram of a square root approximation process performed by an information processing device according to a second embodiment. [Figure 15] 10 is a flowchart showing an example of the operation of a determination unit according to the second embodiment. [Figure 16] 10 is a flowchart showing an example of the operation of a second calculation unit according to the second embodiment. [Figure 17] FIG. 10 is a block diagram showing a schematic configuration of a device according to a third embodiment. [Figure 18] FIG. 10 is a block diagram showing a schematic configuration of a device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same or corresponding elements in multiple drawings are designated by common reference numerals, and their description may be omitted or simplified.

[0011] [First embodiment] 1 is a block diagram showing the hardware configuration of an information processing device 1 according to this embodiment. The information processing device 1 has a processor 11, a memory 12, and an input / output interface (I / F) 13. These components are connected to each other via a bus or the like.

[0012] The information processing device 1 has a function of outputting an approximation of the square root of an input value. The information processing device 1 is applicable to all information processing applications including the calculation of an approximation of a square root. An example of information processing including the calculation of an approximation of a square root is statistical processing including the calculation of a standard deviation. Since the standard deviation is the square root of a variance, the calculation of the standard deviation may involve processing to obtain an approximation of the square root of the variance.

[0013] The processor 11 is a circuit that performs arithmetic processing including the calculation of an approximate value of a square root. The processor 11 may also control each unit of the information processing device 1. The processor 11 may be a dedicated circuit that calculates an approximate value of a square root, or may be a general-purpose information processing circuit that executes a program for calculating an approximate value of a square root. The processor 11 may be, for example, a circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field-Programmable Gate Array). The processor 11 may also be, for example, a circuit such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or a DSP (Digital Signal Processor).

[0014] The memory 12 is a volatile or non-volatile storage medium. The memory 12 temporarily stores data to be processed by the information processing device 1. The memory 12 may also store a program for operating the information processing device 1. That is, the memory 12 may be a non-transitory storage medium that stores a program for calculating an approximate value of a square root.

[0015] The input / output I / F 13 inputs data to be processed in the information processing device 1 and outputs processed data. The input / output I / F 13 may be a communication interface between the information processing device 1 and other devices connected to the information processing device 1. The input / output I / F 13 may also include a user interface for a user to operate the information processing device 1.

[0016] 2 is a functional block diagram of the square root approximation process performed by the information processing device 1 according to this embodiment. The information processing device 1 has a determination unit 14 and a first calculation unit 15. The functions of the determination unit 14 and the first calculation unit 15 can be realized by the processor 11 and the memory 12. A numerical value x input to the information processing device 1 is input to the determination unit 14 and the first calculation unit 15.

[0017] The determination unit 14 calculates the largest integer n that satisfies the following formula (1) for the numerical value x, and outputs it to the first calculation unit 15.

number

[0018] The first calculation unit 15 calculates an equation including the following equation (2) for the numerical value x using the integer n input from the determination unit 14 and the numerical value α, and outputs the obtained numerical value y. Note that the calculation equation in the first calculation unit 15 may include coefficients, constant terms, etc. other than those shown in equation (2).

number

[0019] The value y obtained in this way is an approximation value of the square root of the value x (that is, √x). The derivation of the above-mentioned formulas (1) and (2) and the approximation error will be explained below.

[0020] Figure 3 is a graph showing a linear approximation of a square root function. In Figure 3, the square root function SR is shown by a solid line, and the approximation line L1 is shown by a dashed line. The formula for the square root function SR is y = √x. The range of the x-axis in Figure 3 is from 0 to 65536 (2 16 ), and the y-axis in Figure 3 ranges from 0 to 256 (2 8 ) The approximation line L1 is obtained by linearly approximating the square root function SR within the above range. In other words, the approximation line L1 is the straight line y=x / 256 that connects the origin (0,0) and the point (65536,256) where y is maximum.

[0021] The difference between the y value of the square root function SR and the y value of the approximation line L1 in Figure 3 is the approximation error of the approximation line L1. The x coordinate where the approximation error is maximum is 1 / 4 of the maximum x value of 65536, or 16384.

[0022] FIG. 4 is a graph showing linear approximation and piecewise linear approximation of a square root function. In addition to the square root function SR and approximation line L1 shown in FIG. 3, approximation line L2 is also shown as a dashed line. Point P on the square root function S in FIG. 4 corresponds to the x-coordinate where the approximation error on approximation line L1 is maximum. That is, the coordinates of point P are (16384,128). Approximation line L2 is a line obtained by approximating the square root function SR using a piecewise linear function piecewise-spaced at point P. That is, approximation line L2 is a piecewise linear function formed by combining a line y=x / 128 connecting the origin (0,0) and point P(16384,128) with a line y=(x+32768) / 384 connecting point P(16384,128) and point (65536,256).

[0023] 5(a) and 5(b) are graphs showing the errors of linear approximation and piecewise linear approximation of a square root function. In FIG. 5(a), the absolute error AE1 of linear approximation using approximation line L1 is shown by a dashed line, and the absolute error AE2 of piecewise linear approximation using approximation line L2 is shown by a dashed line. The vertical axis of FIG. 5(a) represents the absolute value of the difference between the approximate value using approximation line L1 or approximation line L2 and the true value of the square root function SR. At the point x=16384, the absolute error AE1 is at its maximum. In contrast, at the point x=16384, the absolute error AE2 is zero. Furthermore, throughout the entire range of x, the absolute error AE2 is smaller than the absolute error AE1. As can be seen, piecewise linear approximation reduces errors compared to linear approximation.

[0024] In Figure 5(b), the relative error RE1 of the linear approximation using approximation line L1 is shown by a dashed line, and the relative error RE2 of the piecewise linear approximation using approximation line L2 is shown by a dashed line. The vertical axis in Figure 5(b) represents the percentage of the value obtained by dividing the absolute errors AE1 and AE2 by the true value of the square root function SR. In the range where the value of x is greater than 16,384, the distribution of the relative error RE2 is gentle, and the relative error RE2 is kept to a relatively small value of less than 6 percent. In contrast, in the range where the value of x is less than 16,384, the value of the relative error RE2 is relatively large.

[0025] By performing piecewise linear approximation with additional division points, it is possible to further reduce errors in intervals where the x value is less than 16384. Specifically, similar to approximation line L2, new division points are repeatedly set at points that are 1 / 4 of the maximum value of the x coordinate of the interval, thereby performing piecewise linear approximation that divides the range of x values ​​from 0 to 16384 into more intervals.

[0026] Figure 6 is a graph showing piecewise linear approximation with an increased number of divisions. In Figure 6, the range of x values ​​from 0 to 64 is shown enlarged. The square root function SR, approximation line L1, and approximation line L2 are the same as those shown in Figure 4. That is, approximation line L1 shown in Figure 6 is part of the line connecting the origin (0,0) and point (65536,256), and approximation line L2 shown in Figure 6 is part of the line connecting the origin (0,0) and point (16384,128).

[0027] The approximation line L3 is part of a piecewise linear function obtained by further dividing the interval between x=0 and x=16384 by x=4096. In other words, the approximation line L3 shown in Fig. 6 is part of a straight line connecting the origin (0,0) and the point (4096,64).

[0028] The approximation line L4 is part of a piecewise linear function obtained by further dividing the interval between x=0 and x=4096 by x=1024. In other words, the approximation line L4 shown in Fig. 6 is part of a straight line connecting the origin (0,0) and the point (1024,32).

[0029] The approximation line L5 is part of a piecewise linear function obtained by further dividing the interval between x = 0 and x = 1024 by x = 256. In other words, the approximation line L5 shown in Fig. 6 is part of a straight line connecting the origin (0,0) and the point (256,16).

[0030] The approximation line L6 is part of a piecewise linear function obtained by further dividing the interval between x = 0 and x = 256 by x = 64. In other words, the approximation line L6 shown in Figure 6 is a straight line connecting the origin (0,0) and the point (64,8).

[0031] Approximation line L7 is part of a piecewise linear function obtained by further dividing the interval between x = 0 and x = 64 by x = 16. That is, approximation line L7 shown in Fig. 6 is formed by joining a line connecting the origin (0,0) and point (16,4) with a line connecting point (16,4) and point (64,8).

[0032] Approximation line L8 is part of a piecewise linear function obtained by further dividing the interval between x = 0 and x = 16 by x = 4. That is, approximation line L8 shown in Fig. 6 is formed by joining a line connecting the origin (0,0) and point (4,2), a line connecting point (4,2) and point (16,4), and a line connecting point (16,4) and point (64,8).

[0033] Figures 7(a) and 7(b) are graphs showing the error of piecewise linear approximation with an increased number of divisions. Figure 7(a) shows absolute errors AE1 to AE8 for approximation lines L1 to L8 in Figure 6, respectively. Figure 7(b) shows relative errors RE1 to RE8 for approximation lines L1 to L8 in Figure 6, respectively. The definitions of absolute error and relative error are the same as in Figures 5(a) and 5(b). Figures 7(a) and 7(b) show an expanded range of x values ​​from 0 to 16.

[0034] As can be seen from Figures 7(a) and 7(b), in the piecewise linear approximation, increasing the number of divisions on the side with smaller x values ​​reduces the approximation error. For each piecewise linear function, the relative error is kept below about 6 percent in the range of x values ​​greater than the division point.

[0035] FIG. 8 is a table showing the coordinates of the division points of the piecewise linear function. As shown in FIG. 8, the coordinates of the origin O are (0,0). i (i is an integer between 0 and 8) i ,y i ) is (2 2i ,2 i )

[0036] Below, the division point P of the power of 2 as mentioned above nThe approximate formula for the square root function is derived using a piecewise linear function divided by the following formula (3): When the value x satisfies the following formula, the piecewise linear function is n and point P n+1 The square root function y = √x is approximated by the interpolated value (x, y) from this line. The interpolation formula to find the interpolated value (x, y) is given by the following formula (4).

number

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[0037] Here, the above division point P i As is clear from the definitions and the table of FIG. 8, the following equations (5) to (9) hold.

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number

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[0038] Substituting equations (5) to (9) into equation (4) and rearranging, the following equation (10) is derived.

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[0039] When formula (10) is used as an approximation formula, the coefficient does not need to be exactly 1 / 3. By replacing the coefficient 1 / 3 in formula (10) with a predetermined value α, formula (2) is derived, which is used to approximate the value y in the first calculation unit 15. In formula (2), the error is minimized when the value α is 1 / 3, so it is desirable that the value α be close to 1 / 3.

number

[0040] Furthermore, the following equation (11) is derived from equations (3) and (8).

number

[0041] In other words, equation (11) is "n is the largest integer that satisfies equation (1)", and the judgment condition for the integer n used in the judgment unit 14 is derived.

number

[0042] As described above, in this embodiment, the square root can be approximated by substituting values ​​into the approximation formula shown in Equation (2), so it does not require iterative calculations. Therefore, it is possible to approximate the square root with a smaller calculation scale than algorithms that perform iterative processing, such as CORDIC and Newton's method.

[0043] Fig. 9 is a graph showing relative errors according to a comparative example. Fig. 9 shows an example in which relative errors are calculated using the square root approximation method described in Patent Document 1. The graph in Fig. 9 shows some points where the relative errors change sharply. In this case, depending on the application of the square root approximation value, the non-uniformity of the approximation errors relative to the input values ​​may become a problem.

[0044] In contrast, in this embodiment, as shown in Figures 7(b) and 5(b), the distribution of relative errors is gentle, and the uniformity of approximation errors for input values ​​is improved. Therefore, this embodiment provides an information processing device, information processing method, and program that can reduce the scale of calculations and improve the uniformity of square root approximation errors for input values.

[0045] A specific example of the operation of the determination unit 14 will be described. Fig. 10 is a flowchart showing an example of the operation of the determination unit 14 according to this embodiment. Fig. 10 shows an example of an algorithm for determining the largest integer n that satisfies equation (1) from a numerical value x.

[0046] In step S11, the determination unit 14 determines whether the numerical value x is 16384 (2 2×7 If the numerical value x is 16384 or greater (YES in step S11), the process proceeds to step S12, where n is determined to be 7. If the numerical value x is less than 16384 (NO in step S11), the process proceeds to step S13.

[0047] In step S13, the determination unit 14 determines whether the numerical value x is 4096 (2 2×6 If the numeric value x is 4096 or greater (YES in step S13), the process proceeds to step S14, where n is determined to be 6. If the numeric value x is less than 4096 (NO in step S13), the process proceeds to step S15.

[0048] Similarly, in steps S15 to S24, the largest integer n that satisfies equation (1) is determined based on the numerical value x to be between 5 and 1. These steps are generally similar to the above description, and therefore will not be described again.

[0049] In step S25, the determination unit 14 determines whether the numerical value x is 1 (2 2×0) or greater. If the numerical value x is 1 or greater (YES in step S25), the process proceeds to step S26, where n is determined to be 0. If the numerical value x is less than 1 (i.e., x=0) (NO in step S27), the process proceeds to step S27, where n is determined to be −1. Here, “n=−1” is a special value that is used by the determination unit 14 to notify the first calculation unit 15 that the numerical value x is 0.

[0050] Through the determination processes from step S11 to step S27 described above, the integer n is determined to be any one of −1 to 7. In step S , the determination unit 14 outputs the integer n to the first calculation unit 15.

[0051] 10, the value of the integer n for notifying that the numerical value x is 0 is -1, but this is not limited to this. For example, the processing of FIG. 10 may be modified so that the value of the integer n for notifying that the numerical value x is 0 is defined as 0, and the value of the integer n in other cases is changed to a value that is increased by 1. In this case, the range of the value of the output integer n is 0 to 8. In this modified example, the approximation formula used in the processing by the first calculation unit 15 may be modified as appropriate.

[0052] 10 is an example, and the value of the integer n may be determined by other processes. For example, when the numerical value x is expressed in binary, the value of the integer n may be determined from the most significant bit position among the bits whose value is 1.

[0053] A specific example will be described below regarding the configuration and operation of the first calculation unit 15. Fig. 11 is a block diagram showing an example of the configuration of the first calculation unit 15 according to this embodiment.

[0054] As shown in FIG. 11 , the first arithmetic unit 15 includes an exception processing unit 151, a first shift arithmetic unit 152, an adder 153, a multiplier 154, and a second shift arithmetic unit 155. An integer n is input to the exception processing unit 151, and a numerical value x is input to the first shift arithmetic unit 152. The exception processing unit 151 may include a logic circuit that determines the value of the integer n. The one-shift arithmetic unit 152 and the second shift arithmetic unit 155 are shift arithmetic circuits that perform shift processing to right-shift or left-shift a multi-bit binary number by a predetermined number of bits, and may be digital circuits such as a barrel shifter or a shift register. The adder 153 is an adder circuit that adds multiple input binary numbers and outputs the sum. The multiplier 154 is a multiplier circuit that multiplies multiple input binary numbers and outputs the product.

[0055] 12 is a flowchart showing an example of the operation of the first calculation unit 15 according to this embodiment. The example of the operation of the first calculation unit 15 will be described with reference to FIGS.

[0056] In step S31, the exception processing unit 151 determines whether the input integer n is a negative value. As described above, if the numerical value x is 0, the value of the integer n is −1, and if the numerical value x is greater than 0, the numerical value x is greater than or equal to 0. In other words, the determination process in step S31 can be said to determine whether the numerical value x is 0.

[0057] If the integer n is a negative value (YES in step S31), the process proceeds to step S33, where the exception processing unit 151 sets the value of y to 0. Then, in step S34, the first calculation unit 15 outputs y=0 as the value of the square root of the numeric value x=0.

[0058] If the integer n is not a negative value (NO in step S31), the process proceeds to step S32. Furthermore, the exception processing unit 151 supplies the value of the integer n to the first shift operation unit 152.

[0059] In step S32, the first shift calculation unit 152, the addition unit 153, the multiplication unit 154, and the second shift calculation unit 155 perform a process of calculating an approximate value of the square root.

[0060] Generally, 2 a can be replaced by 1 shifted left by a bits, and b can be replaced by 2 c The division operation by can be replaced with a right shift of b by c bits (a, b, and c are integers). Therefore, equation (2) can be rewritten as equation (12) below.

number

[0061] The first shift calculation unit 152, the adder 153, the multiplier 154, and the second shift calculation unit 155 perform a process of calculating an approximation value of the square root in step S32 using equation (12). FIG. 11 shows the configuration of a circuit block that performs the calculation of equation (12). The first shift calculation unit 152 shifts 1 to the left by 2n+1 bits. The adder 153 adds the calculation result (first binary number) of the first shift calculation unit 152 to the numerical value x. The multiplier 154 multiplies the calculation result (second binary number) of the adder 153 by a numerical value α. The second shift calculation unit 155 shifts the calculation result (third binary number) of the multiplier 154 to the right by n bits. A numerical value y (fourth binary number) is calculated by these processes. Then, in step S34, the first calculation unit 15 outputs the calculated numerical value y as an approximation value of the square root of the numerical value x. As described above, the calculation of the power of 2 is performed by a shift operation rather than a multiplication or division, thereby reducing the scale of the calculation. The order of the processing by the multiplication unit 154 and the processing by the second shift operation unit 155 may be reversed. Also, the number of cases of input and output of the first shift operation unit 152 is small. For example, in this embodiment, since the integer n has eight possible values ​​from 0 to 7, it is possible to store pre-calculated values ​​for all of the cases and to select the stored value according to the value of n.

[0062] 13 is a flowchart showing another example of the operation of the first calculation unit 15 according to this embodiment. In equation (12), a process of multiplying by α is performed. However, since the value of α is typically 1 / 3 or a number close to 1 / 3, this process may require a division circuit with a large circuit scale. Therefore, as an example of further reducing the calculation scale of the process of equation (12), the value of α is multiplied by q / 2. p (p and q are integers) will be described.

[0063] In this modification, equation (12) can be rewritten as equation (13) below.

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[0064] In the flowchart of FIG. 13, step S32 in FIG. 12 is replaced with step S32a. In step S32a, the first shift calculation unit 152, the adder 153, the multiplier 154, and the second shift calculation unit 155 perform processing to calculate an approximation of the square root based on equation (13). The first shift calculation unit 152 shifts 1 to the left by 2n+1 bits. The adder 153 adds the calculation result (first binary number) of the first shift calculation unit 152 to the numerical value x. The multiplier 154 multiplies the calculation result (second binary number) of the adder 153 by an integer q. The second shift calculation unit 155 shifts the calculation result (third binary number) of the multiplier 154 to the right by n+p bits. A numerical value y (fourth binary number) is calculated by these processes. As described above, in this modified example, the value of α is set to q / 2 p Therefore, the calculation scale is further reduced.

[0065] As mentioned above, the closer the value of α is to 1 / 3, the more accurate the approximation of the square root becomes. Therefore, the integers p and q are q / 2 pIt is desirable to set the integer p to be the value closest to 1 / 3. More specifically, the value of the integer p is set appropriately in consideration of the number of bits of the numerical value x or the numerical value y so that the shift amount in the second shift calculation unit 155 does not become too large. p It is desirable to determine the value of the integer q so that is closest to 1 / 3.

[0066] q / 2 p An example of this is 85 / 2 8 , or 85 / 256. This number is approximately 0.3320, which is close enough to 1 / 3 that the square root can be approximated with a relatively high degree of accuracy. In this case, equation (13) can be rewritten as equation (14) below.

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[0067] In equations (12) to (14), the division by a power of 2 is replaced with a right shift operation. This corresponds to an operation of truncating the decimal part after the division. This truncation operation can be transformed to correspond to a rounding operation such as rounding off. One example of a method of transforming a truncation operation into a rounding operation is to add half of the divisor of the division equivalent to the right shift to the number to be shifted before the right shift, as shown in the following equations (15) to (17). Note that the rounding operation in rounding off is just one example, and another rounding operation such as rounding off may also be used. In other words, a rounding operation can be performed by adding a number smaller than the divisor of the division equivalent to the right shift to the number to be shifted before the right shift.

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[0068] In the above explanation, it is assumed that the numerical values ​​x and y are integers, but the processing of this embodiment can also be applied to cases where the numerical values ​​x and y are decimals. For example, if the right shift amount (n+8) in equation (14) is transformed into (n+8-k) (k is an integer equal to or greater than 1), the calculated value is 2 times the original value. k The result of this operation corresponds to a fixed-point number with a k-bit fractional part. If the number x has a fractional part, multiply x by 2. 2j The same calculation can be performed by multiplying the original value (√x) by 2 (j is an integer greater than or equal to 1). j The result of this calculation may be treated as a fixed-point number, or may be appropriately transformed by, for example, shifting it right by j bits.

[0069] In this embodiment, the input value ranges from 0 to 2. 16 However, the range of input values ​​can be changed as appropriate. For example, if the range of input values ​​is set to 0 to 2, 20 The range of input values ​​can be expanded to 0 to 2. 8 The scale of calculation may be reduced by reducing the size of the calculation.

[0070] [Second embodiment] An information processing device according to a second embodiment will be described. In the description of this embodiment, parts having the same functions as those in the first embodiment will be denoted by the same reference numerals, and detailed description may be omitted or simplified.

[0071] 5(b) and 7(b), in the configuration of the first embodiment, the approximation accuracy is relatively low when the input value is small, and there is room for improvement. Therefore, in this embodiment, a method will be described in which the approximation accuracy can be further improved by determining the output value by referring to a lookup table when the input value is small.

[0072] 14 is a functional block diagram of the square root approximation process performed by the information processing device 1 according to this embodiment. The information processing device 1 has a determination unit 14, a first calculation unit 15, a second calculation unit 16, a data holding unit 17, and a selection unit 18. The functions of the determination unit 14, the first calculation unit 15, the second calculation unit 16, the data holding unit 17, and the selection unit 18 can be realized by the processor 11 and the memory 12. A numerical value x input to the information processing device 1 is input to the determination unit 14.

[0073] 15 is a flowchart showing an example of the operation of the determination unit 14 according to this embodiment. The process of step S41 is a process of determining the largest integer n that satisfies equation (1) from the numerical value x. The process of step S41 may be the same as the processes of steps S11 to S27 in FIG. 10, for example, and therefore a description thereof will be omitted.

[0074] In step S42, the determination unit 14 determines whether the integer n is less than a predetermined integer m (m is 0 or greater). If the integer n is less than the integer m (YES in step S42), the process proceeds to step S44. In step S44, the determination unit 14 outputs a numerical value x to the second calculation unit 16. In this case, the second calculation unit 16 performs calculation processing to approximate the numerical value x. If the integer n is greater than or equal to the integer m (NO in step S42), the process proceeds to step S43. In step S43, the determination unit 14 outputs the numerical value x and the integer n to the first calculation unit 15. In this case, the first calculation unit 15 performs calculation processing to approximate the numerical value x.

[0075] An example of this determination process will be described. According to the flowchart in FIG. 10, when the value x is in the range of 0 to 15, n is equal to or less than 1. Therefore, for example, if the integer m is 2, the condition that the integer n is less than the integer m is satisfied when the value x is in the range of 0 to 15. Similarly, if the integer m is 3, the condition that the integer n is less than the integer m is satisfied when the value x is in the range of 0 to 63. In this manner, in this embodiment, depending on the range of the input value x, either the first calculation unit 15 or the second calculation unit 16 performs calculation processing to generate the value y. Furthermore, the integer m is a predetermined threshold value used to determine the range of the value x. Therefore, in the information processing device 1 of this embodiment, when the value x or the integer n is equal to or greater than the threshold value, the value y generated by the first calculation unit 15 is output, and when the value x or the integer n is smaller than the threshold value, the value y generated by the second calculation unit 16 is output.

[0076] The configuration and operation of the first calculation unit 15 of this embodiment may be similar to the configuration and operation of the first calculation unit 15 of the first embodiment. However, in this embodiment, the integer n input to the first calculation unit 15 is always equal to or greater than 0, so steps S31 and S33 in Fig. 12 may be omitted. The first calculation unit 15 outputs the numerical value y obtained by calculation to the selection unit 18.

[0077] 16 is a flowchart showing an example of the operation of the second calculation unit 16 according to this embodiment. The example of the operation of the second calculation unit 16 will be described with reference to FIGS.

[0078] In step S51, the second calculation unit 16 determines a numerical value y from the input numerical value x by referring to a lookup table. The lookup table is data in which the numerical value x and a numerical value y calculated in advance with high precision are associated in a table format, and is stored in advance in the data storage unit 17. The numerical value y stored in the lookup table may be the true value of the square root of the numerical value x rounded to a predetermined number of digits, or may be a value calculated in advance from the numerical value x using an approximation formula other than Equation (2). The second calculation unit 16 can determine the numerical value y by using the input numerical value x as an index to obtain the corresponding numerical value y from the lookup table in the data storage unit 17. For example, if the integer m is 2 and the numerical value x is an integer, the numerical value x that can be input to the second calculation unit 16 has 16 values ​​ranging from 0 to 15. Therefore, even if the numerical value y is calculated in advance with high precision for all numerical values ​​x that can be input to the second calculation unit 16 and stored in the data storage unit 17, the size of the lookup table can be kept relatively small. In step S52, the second calculation unit 16 outputs the value y determined by referring to the lookup table to the selection unit 18.

[0079] In this way, the selection unit 18 receives the numerical value y from either the first calculation unit 15 or the second calculation unit 16. The selection unit 18 outputs the numerical value y received from the first calculation unit 15 or the second calculation unit 16 as an approximation of the square root of the numerical value x.

[0080] According to this embodiment, similarly to the first embodiment, an information processing device, an information processing method, and a program are provided that can reduce the scale of calculations and improve the uniformity of the approximation error of the square root for the input value. Furthermore, in this embodiment, when the input value is small, the approximation accuracy can be further improved by outputting the square root value based on the lookup table.

[0081] In this embodiment, an example is shown in which either the first calculation unit 15 or the second calculation unit 16 operates, but both the first calculation unit 15 and the second calculation unit 16 may output the numerical value y. In this case, the determination unit 14 outputs the numerical value x and the integer n to the first calculation unit 15 and outputs the numerical value x to the second calculation unit 16. The selection unit 18 selects either the numerical value y output from the first calculation unit 15 or the numerical value y output from the second calculation unit 16 and outputs it to the outside. In this example, in the processing of the second calculation unit 16, a numerical value x outside the range of the lookup table may be input. In this case, the numerical value y output by the second calculation unit 16 may be any value. This is because when a numerical value x outside the range of the lookup table is input to the second calculation unit 16, the numerical value y output by the second calculation unit 16 is not selected by the selection unit 18 and does not affect the output signal of the information processing device 1.

[0082] The selection unit 18 may select whether to output the numerical value y output from the first calculation unit 15 or the second calculation unit 16, based on the comparison result of the integer n and the integer m in the determination unit 14. In this case, the determination unit 14 outputs a signal indicating the comparison result of the integer n and the integer m to the selection unit 18.

[0083] Furthermore, the selection unit 18 may select whether to output the numerical value y output from the first calculation unit 15 or the second calculation unit 16 by, for example, acquiring the integer n and comparing it with the integer m. In this case, the determination unit 14 outputs a signal indicating the integer n to the selection unit 18.

[0084] Furthermore, the selection unit 18 may select whether to output the numerical value y output from the first calculation unit 15 or the second calculation unit 16, for example, based on the output signal from the first calculation unit 15. In this case, the first calculation unit 15 may perform a process of comparing the integer n with the integer m. Furthermore, although an example has been shown up to this point in which the integer n is compared with the integer m serving as the judgment threshold, this may be modified so that judgment is made by comparing the numerical value x with the corresponding threshold. When the selection unit 18 is configured to compare the numerical value x with the threshold, the judgment unit 14 may be configured to output the numerical value x to the selection unit 18.

[0085] The above-mentioned lookup table may be a table containing information on numerical values ​​y corresponding to all of the numerical values ​​x that can be input to the second calculation unit 16, or may be a table containing information on numerical values ​​y corresponding to only some of the numerical values ​​x that can be input to the second calculation unit 16. That is, the lookup table may be missing some of the numerical values ​​x that can be input to the second calculation unit 16. In this example, when a numerical value x that is not included in the lookup table is input to the second calculation unit 16, the second calculation unit 16 may calculate and output the numerical value y by interpolation using the numerical values ​​y corresponding to the numerical values ​​x that are close to the input numerical value x.

[0086] The information processing device, information processing method, and program of the above-described embodiments can be applied to any device that requires calculations using an approximation of a square root. For example, an example of the device is a signal processing device for image signals acquired by a photoelectric conversion device. Another example of the device is a photoelectric conversion system including a photoelectric conversion device and the above-described signal processing device. Statistical processing of image signals may involve calculation of standard deviation, and the process of calculating the standard deviation may include a process of calculating an approximation of the square root of variance. Therefore, the information processing device, information processing method, and program of the above-described embodiments can be suitably used for processing image signals. Furthermore, the information processing device, information processing method, and program of the above-described embodiments may be incorporated into a photoelectric conversion device having the function of processing the above-described image signals.

[0087] The following third and fourth embodiments illustrate devices including a photoelectric conversion device. The information processing devices, information processing methods, and programs of the above-described embodiments can be applied to the devices of the third and fourth embodiments. That is, the information processing devices, information processing methods, and programs of the above-described embodiments may be applied to at least one of the elements included in the devices of the third and fourth embodiments. By applying the information processing devices, information processing methods, and programs of the above-described embodiments to the devices of the third and fourth embodiments, square root approximation can be more effectively performed, thereby improving the value of the devices.

[0088] [Third embodiment] A device according to a third embodiment of the present invention will be described with reference to Fig. 17. Fig. 17 is a block diagram showing a schematic configuration of the device according to this embodiment.

[0089] FIG. 17 is a schematic diagram showing an apparatus EQP including a photoelectric conversion device APR. All or part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometry sensor, a distance measurement sensor, etc. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including photoelectric conversion units are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0090] The photoelectric conversion device APR may have a structure (chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may also be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected by through-silicon vias (TSVs), inter-chip wiring formed by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

[0091] The photoelectric conversion device APR may include, in addition to the semiconductor device IC, a package PKG that houses the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connecting members such as bonding wires and bumps that connect terminals provided on the base to terminals provided on the semiconductor device IC.

[0092] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes signals output from the photoelectric conversion device APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is, for example, an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is, for example, a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is, for example, a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. The device EQP displays the signal output from the photoelectric conversion device APR on a display device DSPL and transmits the signal to the outside using a communication device (not shown) provided in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and arithmetic circuit unit provided in the photoelectric conversion device APR.

[0093] The device EQP shown in FIG. 17 may be an electronic device such as an information terminal with a photographing function (e.g., a smartphone or a wearable device), a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP may also be a transportation device (mobile object) such as a vehicle, a ship, or an aircraft. The device EQP may also be a medical device such as an endoscope or a CT scanner.

[0094] The mechanical device MCHN in the transportation equipment can be used as a moving device. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device APR, assisting and / or automating driving (piloting) using a photographing function, etc. The processing device PRCS for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

[0095] The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser, and / or user. Therefore, if the photoelectric conversion device APR is installed in a device EQP, the value of the device EQP can also be increased. Therefore, when manufacturing and selling the device EQP, deciding to install the photoelectric conversion device APR according to this embodiment in the device EQP is advantageous in increasing the value of the device EQP.

[0096] [Fourth embodiment] 18(a) and 18(b) are block diagrams of devices related to an in-vehicle camera according to this embodiment. FIGS. 18(a) and 18(b) show an example in which a photoelectric conversion device is applied to a moving body such as a vehicle. Device 80 includes an imaging device 800 (an example of a photoelectric conversion device) and a signal processing device (processing device) that processes signals from the imaging device 800. Device 80 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the imaging device 800, and a parallax calculation unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by device 80. Device 80 also includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, parallax calculation unit 802 and distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to an object. In other words, the distance information includes information on parallax, defocus amount, distance to the object, etc. The collision determination unit 804 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0097] The device 80 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The device 80 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The device 80 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high collision possibility, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel. The device 80 functions as a control means for controlling the operation of controlling the vehicle as described above.

[0098] In this embodiment, the device 80 captures images of the surroundings of the vehicle, for example, the front or rear. Fig. 18(b) shows the device when capturing an image of the area in front of the vehicle (image capturing range 850). A vehicle information acquisition device 810, which serves as an image capturing control means, sends an instruction to the device 80 or the image capturing device 800 to perform an image capturing operation. This configuration can further improve the accuracy of distance measurement.

[0099] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the present invention is not limited to vehicles such as automobiles, but can be applied to moving objects (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present invention can be applied to a wide range of devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, without being limited to moving objects.

[0100] [Modified embodiment] The present invention is not limited to the above-described embodiments and can be modified in various ways. For example, an example in which part of the configuration of one embodiment is added to another embodiment, or an example in which part of the configuration of one embodiment is replaced with part of the configuration of another embodiment, is also an embodiment of the present invention.

[0101] The disclosure of this specification includes the complement of the concepts described in this specification. In other words, if this specification states, for example, that "A is B" (A=B), this specification is deemed to disclose or suggest that "A is not B" even if the statement that "A is not B" (A≠B) is omitted. This is because when "A is B," it is assumed that the case where "A is not B" is taken into consideration.

[0102] The disclosure of this specification includes the following configurations or methods. (Configuration 1) For the input number x,

number

number

number

number

number

number

[0103] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0104] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0105] 1. Information processing equipment 14 Judgment section 15 1st calculation section

Claims

1. For the input number x, [Equation 1] a determination unit that calculates the largest integer n that satisfies When the value α is a predetermined constant, the value x is expressed as follows: [Equation 2] a first calculation unit that outputs a numerical value y obtained by a calculation including the term An information processing device comprising:

2. The numerical value α is q / 2 where p is an integer and q is an integer. ｐ is a number expressed as 2. The information processing apparatus according to claim 1, wherein:

3. The integer q is q / 2 for a given integer p. ｐ is determined to be the value closest to 1 / 3 3. The information processing apparatus according to claim 2, wherein:

4. The value α is 85 / 256 3. The information processing apparatus according to claim 2, wherein:

5. The value α is 1 / 3 2. The information processing apparatus according to claim 1, wherein:

6. The first calculation unit a first shift operation unit that outputs a first binary number obtained by shifting 1 to the left by (2n+1) bits; an adder that adds the first binary number to the numerical value x to calculate a second binary number; a second shift calculation unit that calculates a fourth binary number by right-shifting the second binary number or a third binary number obtained by multiplying the second binary number by the numerical value α by n bits; 2. The information processing apparatus according to claim 1, further comprising:

7. The numerical value α is q / 2 where p is an integer and q is an integer. ｐ is a number expressed as The first calculation unit a first shift operation unit that outputs a first binary number obtained by shifting 1 to the left by (2n+1) bits; an adder that adds the first binary number to the numerical value x to calculate a second binary number; a second shift operation unit that calculates a fourth binary number by right-shifting the second binary number or a third binary number obtained by multiplying the second binary number by an integer q by (n+p) bits; 2. The information processing apparatus according to claim 1, further comprising:

8. The second shift operation unit adds a number smaller than a divisor of a division corresponding to the right shift to the third binary number, and then performs the right shift.

7. The information processing apparatus according to claim 6,

9. a second calculation unit that determines a value y from the value x by referring to a lookup table; The information processing device outputs a numerical value y generated by either the first calculation unit or the second calculation unit according to the value of the numerical value x or the value of the integer n.

2. The information processing apparatus according to claim 1, wherein:

10. When the numerical value x or the integer n is equal to or greater than a threshold, the information processing device outputs the numerical value y generated by the first calculation unit; When the numerical value x or the integer n is smaller than a threshold, the information processing device outputs the numerical value y generated by the second calculation unit.

10. The information processing apparatus according to claim 9,

11. The lookup table includes information on a value y corresponding to all values ​​x that can be input to the second calculation unit.

10. The information processing apparatus according to claim 9,

12. the lookup table includes information on a numerical value y corresponding to a part of the numerical value x that can be input to the second calculation unit, but does not include information on a numerical value y corresponding to another part of the numerical value x that can be input to the second calculation unit; The second calculation unit generates a value y by interpolation when information on a value y corresponding to an input value x is not included in the lookup table.

10. The information processing apparatus according to claim 9,

13. The lookup table stores the square root of the numerical value x or an approximation of the square root of the numerical value x as the numerical value y.

10. The information processing apparatus according to claim 9,

14. When the numerical value x is zero, the information processing device outputs zero without relying on equation (2).

2. The information processing apparatus according to claim 1, wherein:

15. a photoelectric conversion device; an information processing device according to claim 1 , to which a signal acquired by the photoelectric conversion device is input; An apparatus characterized by having:

16. The information processing device performs statistical processing on the signal, including processing to obtain an approximate value of the square root.

16. The device of claim 15.

17. a photoelectric conversion device; an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device; At least one of the photoelectric conversion device, the optical device, the control device, the processing device, the display device, the storage device, and the mechanical device includes the information processing device according to any one of claims 1 to 14. The device characterized by:

18. The device according to claim 17 , wherein the processing device acquires distance information from the photoelectric conversion device to an object.

19. An information processing method executed by an information processing device, For the input number x, [Equation 3] calculating the largest integer n that satisfies When the value α is a predetermined constant, the value x is expressed as follows: [Equation 4] outputting a numerical value y obtained by an operation including the term An information processing method comprising:

20. For the input number x, [Equation 5] calculating the largest integer n that satisfies When the value α is a predetermined constant, the value x is expressed as follows: [Equation 6] outputting a numerical value y obtained by an operation including the term 2. A program for causing an information processing device to execute an information processing method, comprising:

Images