Wiring board, semiconductor device, light-emitting device, method for manufacturing wiring board, and method for manufacturing light-emitting device

Abstract

To provide a wiring board capable of improving performance, a semiconductor device, a light-emitting device, a method for manufacturing the wiring board, and a method for manufacturing the light-emitting device.SOLUTION: A wiring board comprises: an insulating base material 10; a base layer 20 arranged on an upper surface of the insulating base material 10; a first metal layer 31 arranged on an upper surface of the base layer 20 and containing a first metal; a second metal layer 32 arranged on an upper surface of the first metal layer 31 and containing a second metal less noble than the first metal; a third metal layer 33 arranged on an upper surface and side surfaces of the second metal layer 32 and containing the first metal; and a fourth metal layer 34 arranged on an upper surface and side surfaces of the third metal layer 33 and containing a third metal more noble than the first metal. The entire surface of the second metal layer 32 is covered by the first metal layer 31 and the third metal layer 33.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a wiring board, a semiconductor device, a light-emitting device, a method for manufacturing a wiring board, and a method for manufacturing a light-emitting device. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a copper wiring ceramic substrate.

[0003] Patent Document 2 discloses a circuit board having a Ni plating layer, an Au plating layer, a first intermediate plating layer, and a second intermediate plating layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 3-060186 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-117542 Summary of the Invention [Problem to be solved by the invention]

[0005] On the other hand, there is a need to further improve the performance of wiring boards, and therefore there is a need to provide a wiring board, a semiconductor device, a light-emitting device, a method for manufacturing a wiring board, and a method for manufacturing a light-emitting device that can improve performance.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A wiring board according to one embodiment comprises an insulating base material, an underlayer disposed on an upper surface of the insulating base material, a first metal layer disposed on the upper surface of the underlayer and containing a first metal, a second metal layer disposed on the upper surface of the first metal layer and containing a second metal that is less noble than the first metal, a third metal layer disposed on the upper surface and side surfaces of the second metal layer and containing the first metal, and a fourth metal layer disposed on the upper surface and side surfaces of the third metal layer and containing a third metal that is more noble than the first metal, wherein the first metal layer and the third metal layer cover the entire surface of the second metal layer.

[0008] A semiconductor device according to one embodiment includes the wiring substrate and a semiconductor element disposed on the wiring substrate.

[0009] A light emitting device according to one embodiment includes the wiring substrate and a light emitting element disposed on the wiring substrate.

[0010] A method for manufacturing a wiring board according to one embodiment includes the steps of: (a) preparing an insulating substrate having an underlayer formed on its upper surface; (b) forming a resist layer on the upper surface of the underlayer; (c) exposing and developing the resist layer so that at least a portion of the underlayer is exposed from the resist layer; (d) forming a first metal layer containing a first metal on the upper surface of the underlayer exposed from the resist layer; (e) forming a second metal layer containing a second metal less noble than the first metal on the upper surface of the first metal layer; (f) removing the resist layer after the step of forming the second metal layer; (g) removing the underlayer after the step of removing the resist layer; (h) forming a third metal layer containing the first metal on the upper surface and side surfaces of the second metal layer; and (i) forming a fourth metal layer containing a third metal more noble than the first metal on the upper surface and side surfaces of the third metal layer.

[0011] A manufacturing method for a light-emitting device in one embodiment includes the steps of preparing the wiring substrate, arranging a light-emitting element on an insulating substrate, and arranging a reflective member on the upper surface of the insulating substrate, and in the step of arranging the reflective member, the reflective member is arranged so as to be in contact with the fourth metal layer, the third metal layer, and the base layer. [Effects of the Invention]

[0012] According to the above-described embodiment, it is possible to provide a wiring board, a semiconductor device, a light-emitting device, a method for manufacturing a wiring board, and a method for manufacturing a light-emitting device that can improve performance. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a cross-sectional view of a wiring board according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view of a wiring board according to the study example. [Figure 3] FIG. 3 is a plan view of a wiring board according to another embodiment. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Figure 5] FIG. 5 is a cross-sectional view of a semiconductor device according to an embodiment. [Figure 6] FIG. 6 is a cross-sectional view of a semiconductor device according to another embodiment. [Figure 7] FIG. 7 is a cross-sectional view of a light emitting device according to an embodiment. [Figure 8] FIG. 8 is a cross-sectional view showing a process of a method for manufacturing a wiring board according to an embodiment. [Figure 9] FIG. 9 is a cross-sectional view showing a process of a method for manufacturing a wiring board according to an embodiment. [Figure 10] 10A to 10C are cross-sectional views showing steps in a method for manufacturing a wiring board according to an embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a process of a method for manufacturing a wiring board according to an embodiment. [Figure 12]12A to 12C are cross-sectional views showing steps in a method for manufacturing a wiring board according to an embodiment. [Figure 13] 13A to 13C are cross-sectional views showing steps in a method for manufacturing a wiring board according to an embodiment. [Figure 14] 14A to 14C are cross-sectional views showing steps in a method for manufacturing a wiring board according to an embodiment. [Figure 15] FIG. 15 is a cross-sectional view showing a process of a method for manufacturing a wiring board according to an embodiment. [Figure 16] FIG. 16 is a cross-sectional view showing a process of a method for manufacturing a wiring board according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] In this application, the description of the embodiments will be divided into multiple sections, etc., for convenience, as necessary. However, unless otherwise expressly stated, these are not mutually independent and separate, and regardless of the order of description, they are each part of a single example, one being a partial detail of the other, or a partial or complete modification, etc. Furthermore, as a general rule, repeated explanations of similar parts will be omitted. Furthermore, each component in the embodiments is not essential unless otherwise expressly stated, there is a theoretical limit to the number, or it is clearly not essential from the context.

[0015] Similarly, in the description of the embodiments, when a material, composition, etc. is described as "X consisting of A," this does not exclude the inclusion of elements other than A, unless otherwise specified or clearly indicated by the context. For example, when referring to a component, it means "X containing A as a main component."

[0016] Furthermore, even when a specific number or quantity is mentioned, unless otherwise specified, unless it is theoretically limited to that number, or unless the context clearly indicates otherwise, the number may be greater than or less than that specific number.

[0017] Furthermore, in each drawing of the embodiment, the same or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions thereof will not be repeated in principle.

[0018] In the accompanying drawings, hatching may be omitted even in cross sections if it would be too complicated or if the distinction from voids is clear. In relation to this, background contour lines may be omitted even in the case of holes that are closed in plan view if it is clear from the description, etc. Furthermore, hatching or dot patterns may be added even in cases where the drawing is not a cross section to clearly indicate that the hole is not a void or to clearly indicate the boundary of the area.

[0019] <<Wiring board>> First, a wiring board according to one embodiment will be described. FIG. 1 is a cross-sectional view of the wiring board according to one embodiment. As shown in FIG. 1, the wiring board 1 according to this embodiment has an insulating base material 10, a base layer 20, and a wiring layer 30. The wiring layer 30 has a first metal layer 31, a second metal layer 32, a third metal layer 33, and a fourth metal layer 34. The wiring layer 30 of the wiring board 1 according to this embodiment further has an intermediate layer 35.

[0020] <Insulating substrate> The insulating substrate 10 supports the wiring layer 30. The insulating substrate 10 has an upper surface 10a and a lower surface 10b. In this embodiment, the insulating substrate 10 is plate-shaped. The planar shape of the insulating substrate 10 is, for example, a circle, an ellipse, a polygon such as a rectangle or a hexagon, or a polygon with rounded corners. The size of the insulating substrate 10 can be adjusted appropriately depending on the required performance, such as the size and number of the wiring layer 30 to be disposed on the insulating substrate 10.

[0021] The insulating substrate 10 is preferably made of an insulating material. Examples of insulating materials include ceramics such as aluminum oxide, aluminum nitride, silicon oxide, silicon nitride, and silicon carbide, and resins such as phenolic resin, epoxy resin, silicone resin, polyimide resin, BT resin, and polyphthalamide. When using a resin, an inorganic filler may be mixed into the resin as needed, thereby improving mechanical strength and reducing the thermal expansion coefficient. Examples of inorganic fillers include glass fiber, silicon oxide, titanium oxide, and aluminum oxide. The insulating substrate 10 may be a substrate in which a layer of an insulating material is formed on the surface of a metal member.

[0022] <Underlayer> The underlayer 20 is disposed on the upper surface 10a of the insulating base material 10. The underlayer 20 has an upper surface 20a and a lower surface 20b. The lower surface 20b of the underlayer 20 is in contact with the upper surface 10a of the insulating base material 10. The underlayer 20 is a layer that serves as a base for the wiring layer 30. The underlayer 20 functions as an adhesive layer when the wiring layer 30 is formed on the insulating base material 10. The underlayer 20 may be a single layer such as a Ti layer, a Cu layer, an Au layer, or a Ru layer, or may be a laminate or alloy layer containing these. The underlayer 20 is preferably at least one selected from a laminate of Ti and Cu, a laminate of Ti and Au, a laminate of Ti and Ag, an alloy layer of Ti and Ni, an alloy layer of Ti and W, a Cu alloy layer of Ni, an alloy layer of Ni and Cr, a Ti layer and a TiNi layer, a Ti layer and a TiW layer, a Ti layer, a TiW layer and a Cu layer, a Ti layer, a Ru layer and a Cu layer, etc. The TiNi alloy may contain only a small amount of Ti relative to Ni, and the Ni to Ti ratio is preferably about 93:7. Here, for example, a Ti and Cu laminate refers to a layer formed by laminating a layer of Ti and a layer of Cu. For example, a Ti and Ni alloy layer refers to a layer formed by an alloy of Ti and Ni. A Ti layer refers to a layer formed by Ti. The underlayer 20 is preferably formed by laminating multiple layers formed by at least one material selected from a Ti and Cu laminate, a Ti and Au laminate, a Ti and Ag laminate, a Ti and Ni alloy layer, a Ti and W alloy layer, a Cu and Ni alloy layer, a Ni and Cr alloy layer, and a Ti layer. The thickness of the underlayer 20 is preferably 0.1 μm or more and 2.0 μm or less. The underlayer 20 is preferably formed by a Ti layer and a Ti and Ni alloy layer. In this case, the Ti layer is preferably disposed closer to the insulating substrate 10. In this case, the thickness of the Ti layer is preferably 0.03 μm or more and 0.2 μm or less. Furthermore, in this case, the thickness of the Ti-Ni alloy layer is preferably 0.2 μm or more and 1.5 μm or less. For example, the thickness of the Ti layer is 0.05 μm, and the thickness of the TiNi layer is 1.1 μm.

[0023] <Wiring layer> The wiring layer 30 is disposed on the upper surface 20a of the base layer 20. The wiring layer 30 is a layer that conducts electricity and simultaneously efficiently transfers heat to the insulating substrate 10. As shown in FIG. 1, the wiring layer 30 is composed of multiple metal layers.

[0024] (First metal layer 31) The first metal layer 31 is disposed on the upper surface 20a of the underlayer 20. The first metal layer 31 has an upper surface 31a, a lower surface 31b, and a side surface 31c. A portion of the lower surface 31b of the first metal layer 31 contacts the upper surface 20a of the underlayer 20. In the cross-sectional view shown in FIG. 1, the width of the first metal layer 31 is greater than the width of the underlayer 20. The width of the lower surface 31b of the first metal layer 31 is greater than the width of the upper surface 20a of the underlayer 20. Therefore, a portion of the lower surface 31b of the first metal layer 31 is exposed. The thickness of the first metal layer 31 is preferably 1.0 μm or more and 5.0 μm or less.

[0025] When the upper surface 10a of the insulating substrate 10 is viewed from above, a portion of the edge of the upper surface 20a of the underlayer 20 is located more inward than the edge of the lower surface 31b of the first metal layer 31. When the upper surface 10a of the insulating substrate 10 is viewed from above, it is preferable that the entire edge of the upper surface 20a of the underlayer 20 is located more inward than the edge of the lower surface 31b of the first metal layer 31. When the upper surface 10a of the insulating substrate 10 is viewed from above, it is preferable that the edge of the underlayer 20 is located more inward than the edge of the first metal layer 31. When the upper surface 10a of the insulating substrate 10 is viewed from above, it is preferable that the distance from the edge of the upper surface 20a of the underlayer 20 to the edge of the lower surface 31b of the first metal layer 31 is 1.0 μm or more and 5.0 μm or less. At least a portion of the first metal layer 31 is separated from the insulating substrate 10. It is preferable that the first metal layer 31 does not contact the insulating substrate 10 .

[0026] The first metal layer 31 is made of a metal material. In this embodiment, the first metal layer 31 is made of a single first metal. The first metal is, for example, Ni.

[0027] (Second metal layer 32) The second metal layer 32 is disposed on the upper surface 31a of the first metal layer 31. The second metal layer 32 has an upper surface 32a, a lower surface 32b, and a side surface 32c. The lower surface 32b of the second metal layer 32 is in contact with the upper surface 31a of the first metal layer 31. When the upper surface 10a of the insulating substrate 10 is viewed from above, the shape of the lower surface 32b of the second metal layer 32 is substantially the same as the shape of the upper surface 31a of the first metal layer 31. In the cross-sectional view shown in FIG. 1, the width of the second metal layer 32 is substantially the same as the width of the first metal layer 31. The width of the second metal layer 32 is larger than the width of the base layer 20. The width of the lower surface 32b of the second metal layer 32 is larger than the width of the upper surface 20a of the base layer 20. The thickness of the second metal layer 32 is preferably 5 μm or more and 60 μm or less. The thickness of the second metal layer 32 is, for example, 45 μm.

[0028] When the upper surface 10a of the insulating substrate 10 is viewed from above, part of the edge of the upper surface 20a of the underlayer 20 is located more inward than the edge of the lower surface 32b of the second metal layer 32. When the upper surface 10a of the insulating substrate 10 is viewed from above, it is preferable that the entire edge of the upper surface 20a of the underlayer 20 is located more inward than the edge of the lower surface 32b of the second metal layer 32. When the upper surface 10a of the insulating substrate 10 is viewed from above, it is preferable that the edge of the underlayer 20 is located more inward than the edge of the second metal layer 32. When the upper surface 10a of the insulating substrate 10 is viewed from above, it is preferable that the distance from the edge of the upper surface 20a of the underlayer 20 to the edge of the lower surface 32b of the second metal layer 32 is 1.0 μm or more and 5.0 μm or less.

[0029] The second metal layer 32 is made of a metal material. In this embodiment, the second metal layer 32 is made of a single second metal. The second metal has a standard electrode potential that is lower than that of the first metal constituting the first metal layer 31. The second metal is, for example, Cu.

[0030] (Third metal layer 33) The third metal layer 33 is disposed on the upper surface 32a and the side surface 32c of the second metal layer 32. The third metal layer 33 has an upper surface 33a and a side surface 33c. The third metal layer 33 is in contact with the upper surface 32a and the side surface 32c of the second metal layer 32. The third metal layer 33 is disposed on the side surface 31c of the first metal layer 31. The third metal layer 33 is in contact with the side surface 31c of the first metal layer 31. The first metal layer 31 and the third metal layer 33 cover the entire surface of the second metal layer 32. The surface of the second metal layer 32 is in contact with the first metal layer 31 or the third metal layer 33. A portion of the third metal layer 33 is separated from the insulating substrate 10. It is preferable that the third metal layer 33 does not contact the insulating substrate 10. The thickness of the third metal layer 33 is preferably 1.0 μm or more and 10.0 μm or less. The thickness of the third metal layer 33 disposed on the upper surface 32a of the second metal layer 32 is, for example, 2.0 μm or more and 10.0 μm or less.

[0031] The third metal layer 33 is made of a metal material. The third metal layer 33 is made of the same first metal as the first metal layer 31.

[0032] (middle class) The intermediate layer 35 is disposed on the upper surface 33a and the side surface 33c of the third metal layer 33. The intermediate layer 35 has an upper surface 35a and a side surface 35c. The intermediate layer 35 contacts the upper surface 33a and the side surface 33c of the third metal layer 33. The intermediate layer 35 prevents the metal contained in the third metal layer 33 from diffusing into the fourth metal layer 34. The intermediate layer 35 is not essential, and may not be provided in some cases. A portion of the intermediate layer 35 is separated from the insulating substrate 10. It is preferable that the intermediate layer 35 does not contact the insulating substrate 10. The thickness of the intermediate layer 35 is preferably 0.05 μm or more and 0.2 μm or less. The thickness of the intermediate layer 35 is, for example, 0.1 μm.

[0033] The intermediate layer 35 is made of a metal material. In this embodiment, the intermediate layer 35 is made of a single fourth metal. The fourth metal is preferably a metal that prevents the first metal from diffusing into the fourth metal layer 34. The fourth metal is, for example, Pd.

[0034] (Fourth metal layer 34) The fourth metal layer 34 is disposed on the upper surface 35a and the side surface 35c of the intermediate layer 35. The fourth metal layer 34 has an upper surface 34a and a side surface 34c. The fourth metal layer 34 is in contact with the upper surface 35a and the side surface 35c of the intermediate layer 35. However, if the intermediate layer 35 is not provided, the fourth metal layer 34 is disposed on the upper surface 33a and the side surface 33c of the third metal layer 33. Also, if the intermediate layer 35 is not provided, the fourth metal layer 34 is in contact with the upper surface 33a and the side surface 33c of the third metal layer 33. A portion of the fourth metal layer 34 is separated from the insulating substrate 10. It is preferable that the fourth metal layer 34 does not contact the insulating substrate 10. The thickness of the fourth metal layer 34 is preferably 0.05 μm or more and 0.2 μm or less. The thickness of the fourth metal layer 34 is, for example, 0.1 μm.

[0035] The fourth metal layer 34 is made of a metal material. In this embodiment, the fourth metal layer 34 is made of a single third metal. It is preferable that the third metal does not alloy with the first metal and the fourth metal. The third metal has a standard electrode potential that is more noble than the first metal constituting the first metal layer 31 and the second metal constituting the second metal layer 32. The third metal is, for example, Au.

[0036] Next, the configuration and effects of the wiring board 1 according to this embodiment will be described. As shown in FIG. 1, the width of the wiring layer 30 in one direction is greater than the width of the base layer 20 in the same direction. The wiring layer 30 is separated from the insulating base 10. That is, a gap N1 is formed between the wiring layer 30 and the insulating base 10. This exposes the side surface 20c of the base layer 20. Also, a portion of the first metal layer 31, a portion of the third metal layer 33, and a portion of the intermediate layer 35 are exposed. Meanwhile, the second metal layer 32 of the wiring layer 30 is covered by the first metal layer 31 and the third metal layer 33. Therefore, the second metal layer 32 of the wiring layer 30 is not exposed.

[0037] 2 is a cross-sectional view of a wiring board according to the study example. As shown in FIG. 2, second metal layer 32 of wiring board 1F is disposed on the upper surface of base layer 20. In other words, wiring board 1F does not have a layer corresponding to first metal layer 31 of wiring board 1. Except for the fact that a layer corresponding to first metal layer 31 is not formed, the cross-sectional structure of wiring board 1F is the same as the cross-sectional structure of wiring board 1.

[0038] When disposing a wiring layer 30 on an insulating substrate 10, a base layer 20 may be disposed between the insulating substrate 10 and the wiring layer 30 for reasons such as improving adhesion between the wiring layer 30 and the insulating substrate 10. However, when disposing the base layer 20 between the insulating substrate 10 and the wiring layer 30, first, a part or all of the wiring layer 30 is formed on the base layer 20, and then the excess base layer 20 is removed by etching to prevent short circuits. However, as shown in FIG. 2 , when removing the base layer 20 by etching, the base layer 20 may be over-etched. This may result in the width of the base layer 20 being smaller than the width of the wiring layer 30. As a result, a gap N1 is formed between the wiring layer 30 and the insulating substrate 10. Here, to reduce the amount of a third metal used, which has a relatively noble standard electrode potential, it is considered to dispose a second metal layer 32 made of a second metal that is easily corroded and relatively noble on the base layer 20. As described above, when the width of the base layer 20 is smaller than the width of the wiring layer 30, the edge of the upper surface 20a of the base layer 20 may be located inside the edge of the lower surface 32b of the second metal layer 32 when the insulating base material 10 is viewed from above. This may cause the lower surface 32b of the second metal layer 32, which is susceptible to corrosion, to be exposed through the gap N1. When the lower surface 32b of the second metal layer 32 is exposed through the gap N1, it is highly likely to corrode when it comes into contact with, for example, water, salt water, oxygen, or a gas containing sulfur. As a result, in the wiring board 1F shown in FIG. 2, depending on the current flowing through the wiring layer 30, corrosion can locally increase the current density, increasing the likelihood of a break.

[0039] 1, in this embodiment, the fourth metal layer 34 made of a third metal having a relatively noble standard electrode potential is disposed so as to be exposed from the outer surface of the wiring layer 30. The second metal layer 32 made of a second metal having a lower electrical potential than the third metal is disposed inside the wiring layer 30 so as not to be exposed from the outer surface of the wiring layer 30. This allows the amount of the third metal having a relatively noble standard electrode potential to be reduced.

[0040] Furthermore, in the wiring board 1 according to this embodiment, the entire periphery of the second metal layer 32 made of the second metal is covered with the first metal layer 31 and the third metal layer 33 made of the first metal whose standard electrode potential is more noble than that of the second metal. This prevents the second metal layer 32 made of the second metal, which is relatively base and prone to corrosion, from being exposed. As a result, the wiring layer 30 is less susceptible to corrosion. Therefore, even if the amount of the third metal used, whose standard electrode potential is relatively noble, is reduced, a wiring board 1 that is less susceptible to corrosion can be provided.

[0041] Furthermore, in the wiring board 1 according to this embodiment, the entire periphery of the second metal layer 32 made of the second metal is covered with the first metal layer 31 and the third metal layer 33 made of the first metal whose standard electrode potential is more noble than that of the second metal, so that even when the edge of the upper surface 20a of the base layer 20 is located inside the edge of the lower surface 32b of the second metal layer 32 in a plan view of the insulating base material 10, the second metal layer 32 can be prevented from being exposed. This makes it possible to provide a wiring board 1 that is less susceptible to corrosion even when the amount of the third metal whose standard electrode potential is relatively more noble is reduced.

[0042] (Variation) FIG. 3 is a plan view of a wiring board according to another embodiment. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3. As shown in FIG. 3, the wiring board 1A according to another embodiment further includes a pad portion 40, a light-reflecting layer 50, a recognition mark M1, and a hole H1. The pad portion 40 is electrically connected to the wiring layer 30. As shown in FIG. 4, the pad portion 40 is electrically connected to the fourth metal layer 34 of the wiring layer 30. The pad portion 40 includes a first metal layer 311, a third metal layer 331, an intermediate layer 351, and a fifth metal layer 361. The fifth metal layer 361 is electrically connected to the fourth metal layer 34 of the wiring layer 30.

[0043] 4, the pad section 40 is provided on the upper surface 20a of the underlying layer 20. In other words, the pad section 40 and the wiring layer 30 are provided on the upper surface 20a of the same underlying layer 20.

[0044] The first metal layer 311 of the pad portion 40 is provided on the upper surface 20a of the base layer 20. The lower surface 311b of the first metal layer 311 is in contact with the upper surface 20a of the base layer 20. The first metal layer 311 of the pad portion 40 is provided integrally with the first metal layer 31 of the wiring layer 30. In the example shown in FIG. 4, the first metal layer 311 of the pad portion 40 and the first metal layer 31 of the wiring layer 30 are connected by a dotted line. The material of the first metal layer 311 is preferably the same as the material of the first metal layer 31. Since the first metal layer 311 is not essential, there are cases where the first metal layer 311 is not provided. When the upper surface 10a of the insulating substrate 10 is viewed from above, part of the edge of the upper surface 20a of the base layer 20 is located inside the edge of the lower surface 311b of the first metal layer 311. The third metal layer 331 of the pad portion 40 is provided on the upper surface 311a and side surface 311c of the first metal layer 311. The third metal layer 331 of the pad portion 40 is provided integrally with the third metal layer 33 of the wiring layer 30. In the example shown in FIG. 4, the third metal layer 331 of the pad portion 40 and the third metal layer 33 of the wiring layer 30 are connected by dotted lines. It is preferable that the material of the third metal layer 331 is the same as the material of the third metal layer 33. Since the third metal layer 331 is not essential, the third metal layer 331 may not be provided in some cases.

[0045] The intermediate layer 351 is provided on the upper surface 331a and side surface 331c of the third metal layer 331. The intermediate layer 351 of the pad portion 40 is provided integrally with the intermediate layer 35 of the wiring layer 30. In the example shown in FIG. 4, the intermediate layer 351 of the pad portion 40 and the intermediate layer 35 of the wiring layer 30 are connected by dotted lines. The material of the intermediate layer 351 is preferably the same as the material of the intermediate layer 35. The intermediate layer 351 is not essential, so there are cases where the intermediate layer 351 is not provided. The fifth metal layer 361 is provided on the upper surface 351a and side surface 351c of the intermediate layer 351. The fifth metal layer 361 is preferably made of a fifth metal having a standard electrode potential lower than that of the third metal of the fourth metal layer 34. The fifth metal is, for example, Al.

[0046] 4, the pad section 40 does not have a layer corresponding to the second metal layer 32 made of the second metal. In addition, a fourth metal layer 341 made of the third metal may be provided instead of the fifth metal layer 361 of the pad section 40. When the fourth metal layer 341 is provided, the fourth metal layer 341 of the pad section 40 is provided integrally with the fourth metal layer 34 of the wiring layer 30.

[0047] For example, an external power supply member is electrically connected to the pad portion 40. An electronic component may be disposed on the fourth metal layer 34 of the wiring layer 30. The terminal of the electronic component is electrically connected to the fourth metal layer 34, for example. The fifth metal layer 361 of the pad portion 40 is electrically connected to the terminal of the electronic component via the fourth metal layer 34 of the wiring layer 30, for example. The fifth metal layer 361 of the pad portion 40 is not directly connected to the terminal of the electronic component. In other words, a second metal layer 32 made of a second metal is provided in the portion directly connected to the terminal of the electronic component. On the other hand, a second metal layer 32 made of a second metal may not be provided in the portion not directly connected to the terminal of the electronic component.

[0048] Examples of electronic components include two-terminal devices such as semiconductor light-emitting elements, power semiconductors, power supply rectifier diodes, Zener diodes, variable capacitance diodes, PIN diodes, Schottky barrier diodes, photodiodes, solar cells, surge protection diodes, varistors, capacitors, and resistors; three-terminal devices such as transistors, bipolar transistors, field effect transistors, phototransistors, CCD image sensors, thyristors, and light-triggered thyristors; memories such as DRAM and SRAM; and microprocessors.

[0049] 4, the light reflecting layer 50 covers the fourth metal layer 34. When the light reflecting layer 50 is irradiated with light of 450 nm or more and 460 nm or less, the total light reflectance of the light reflecting layer 50 is preferably higher than the total light reflectance of the fourth metal layer 34. Furthermore, when the light reflecting layer 50 is irradiated with light of 430 nm, the total light reflectance is preferably 70% or more. The total light reflectance includes diffuse reflection and specular reflection.

[0050] The light-reflecting layer 50 is, for example, a silicone resin, a modified silicone resin, an epoxy resin, a modified epoxy resin, an acrylic resin, or a hybrid resin containing at least one of these resins. The light-reflecting layer 50 preferably further contains a filler such as a light-reflecting material. Examples of light-reflecting materials include titanium oxide, silicon oxide, zirconium oxide, potassium titanate, aluminum oxide, aluminum nitride, boron nitride, and mullite.

[0051] As shown in FIG. 3, the recognition mark M1 is provided on the upper surface 10a of the insulating base material 10. The recognition mark M1 is provided at a distance from the wiring layer 30. The recognition mark M1 can be used for position recognition of electronic components when secondary mounting the wiring board 1A on which the electronic components are mounted, and for position recognition when forming a resin frame in the manufacturing process. The recognition mark M1 can be formed using the same metal material as the wiring layer 30. The surface of the recognition mark M1 is preferably formed using the same metal material as the fourth metal layer 34. Using the same metal material for the recognition mark M1 and the surface of the wiring layer 30 can suppress metal corrosion due to the potential difference between the different metal materials.

[0052] 3, a hole H1 is provided in the wiring layer 30. It is preferable that the insulating base material 10 is exposed through the hole H1. For example, the hole H1 can hold a frame when the frame is attached to the wiring board 1A. This can improve the adhesion between the frame and the insulating base material 10.

[0053] <<Semiconductor Devices>> Next, a semiconductor device according to this embodiment will be described. Fig. 5 is a cross-sectional view of the semiconductor device according to one embodiment. As shown in Fig. 5, the semiconductor device 100 according to this embodiment includes a wiring substrate 1B, a semiconductor element 110, wires 120, and a die pad 130.

[0054] <Wiring board> The wiring board 1B has an insulating base material 10, a plurality of underlayers 20, and a plurality of wiring layers 30.

[0055] As shown in FIG. 5, the multiple underlayers 20 include an underlayer 21, an underlayer 22, and an underlayer 23. In the cross-sectional view shown in FIG. 5, the underlayer 21, the underlayer 22, and the underlayer 23 are spaced apart from one another. The underlayer 23 is disposed between the underlayer 21 and the underlayer 22. The multiple wiring layers 30 include a wiring layer 30A and a wiring layer 30B. The wiring layer 30A is disposed on an upper surface 21a of the underlayer 21. The wiring layer 30B is disposed on an upper surface 22a of the underlayer 22. In the example shown in FIG. 5, the wiring layer 30A and the wiring layer 30B have the same cross-sectional structure. The cross-sectional structures of the wiring layer 30A and the wiring layer 30B are the same as the cross-sectional structure of the wiring layer 30 shown in FIG. 1. A die pad 130 is disposed on an upper surface 23a of the underlayer 23.

[0056] <Die pad> As shown in Fig. 5, the cross-sectional structure of the die pad 130 is the same as that of the wiring layer 30 shown in Fig. 1. As shown in Fig. 5, the die pad 130 is disposed between the wiring layer 30A and the wiring layer 30B, and is spaced apart from the wiring layer 30A and the wiring layer 30B. The die pad 130 is provided on the upper surface 23a of the base layer 23. The die pad 130 supports the semiconductor element 110.

[0057] The die pad 130 includes a first metal layer 312, a second metal layer 322, a third metal layer 332, a fourth metal layer 342, and an intermediate layer 352. The material and shape of the first metal layer 312 are preferably the same as those of the first metal layer 31 shown in FIG. 1. The material and shape of the second metal layer 322 are preferably the same as those of the second metal layer 32 shown in FIG. 1. The material and shape of the third metal layer 332 are preferably the same as those of the third metal layer 33 shown in FIG. 1. The material and shape of the fourth metal layer 342 are preferably the same as those of the fourth metal layer 34 shown in FIG. 1. The material and shape of the intermediate layer 352 are preferably the same as those of the intermediate layer 35 shown in FIG. 1.

[0058] <Semiconductor element> 5, the semiconductor element 110 is provided on the die pad 130. The semiconductor element 110 is provided on the upper surface 342a of the fourth metal layer 342 of the die pad 130 via an adhesive layer 131. The semiconductor element 110 is fixed onto the upper surface 342a of the fourth metal layer 342 of the die pad 130 by the adhesive layer 131. The semiconductor element 110 has, for example, a plurality of terminals.

[0059] <Wire> As shown in FIG. 5, a plurality of wires 120 are provided. The semiconductor element 110 and the wiring layer 30A are electrically connected by the wires 120. The fourth metal layer 34 of the wiring layer 30A is in contact with one end of the wire 120. One terminal of the semiconductor element 110 is in contact with the other end of the wire 120. The semiconductor element 110 and the wiring layer 30B are electrically connected by the wires 120. The fourth metal layer 34 of the wiring layer 30B is in contact with one end of the wire 120. The other terminal of the semiconductor element 110 is in contact with the other end of the wire 120.

[0060] Next, the effects of the semiconductor device 100 will be described. As shown in FIG. 5, the cross-sectional structure of the die pad 130 is the same as that of the wiring layer 30 shown in FIG. 1. That is, the entire outer surface of the second metal layer 322 made of the second metal is covered with the first metal layer 312 and the third metal layer 332 made of the first metal, which has a standard electrode potential more noble than the second metal. As a result, when the insulating base material 10 is viewed from above, even if the edge of the upper surface 23a of the foundation layer 23 is located inside the edge of the lower surface 322b of the second metal layer 322, the second metal layer 322 is not exposed. This makes the die pad 130 less susceptible to corrosion. As a result, the semiconductor device 100 is less susceptible to corrosion. Therefore, the environmental resistance of the semiconductor device 100 can be improved while reducing the amount of precious metal used.

[0061] Furthermore, although the semiconductor element 110 is a heat source, by increasing the amount of the second metal with high thermal conductivity and low thermal conductivity, the thermal conductivity can be compensated for and the thermal conductivity of the wiring board 1 can be increased even when a material with low thermal conductivity is used for the insulating base material 10. As a result, the heat generated by the semiconductor element 110 can be efficiently dissipated, and the characteristics can be maintained for a long period of time.

[0062] (Variation) 6 is a cross-sectional view of a semiconductor device according to another embodiment. As shown in FIG. 6, a semiconductor device 100A according to this embodiment includes a wiring substrate 1C, a semiconductor element 110, and a sealing body 140.

[0063] <Wiring board> The wiring board 1C has an insulating base material 10, a plurality of foundation layers 20, and a plurality of wiring layers 30.

[0064] As shown in FIG. 6, the multiple base layers 20 include an underlayer 21 and an underlayer 22. In the cross-sectional view shown in FIG. 6, the underlayer 21 and the underlayer 22 are disposed spaced apart from each other. The multiple wiring layers 30 include a wiring layer 30A and a wiring layer 30B. The wiring layer 30A is disposed on an upper surface 21a of the underlayer 21. The wiring layer 30B is disposed on an upper surface 22a of the underlayer 22. In the example shown in FIG. 6, the wiring layer 30A and the wiring layer 30B have the same cross-sectional structure. Furthermore, the cross-sectional structures of the wiring layer 30A and the wiring layer 30B are the same as the cross-sectional structure of the wiring layer 30 shown in FIG. 1.

[0065] <Semiconductor element> As shown in FIG. 6, the semiconductor element 110 has an electrode 111A and an electrode 111B. The electrode 111A and the electrode 111B are, for example, columnar electrodes formed on the semiconductor element 110. The electrode 111A of the semiconductor element 110 is connected to an upper surface 34a of the fourth metal layer 34 of the wiring layer 30A. In the example shown in FIG. 6, the electrode 111A is electrically connected to the fourth metal layer 34 of the wiring layer 30A via a conductive material 150. The electrode 111B of the semiconductor element 110 is connected to an upper surface 34a of the fourth metal layer 34 of the wiring layer 30B. In the example shown in FIG. 6, the electrode 111B is electrically connected to the fourth metal layer 34 of the wiring layer 30B via the conductive material 150. The conductive material 150 is, for example, solder.

[0066] <Sealing body> The sealing body 140 is provided on the upper surface 10a of the insulating base material 10 of the wiring board 1C. The semiconductor element 110 is sealed by the sealing body 140. The conductive material 150 is sealed by the sealing body 140. A portion of the foundation layer 21 and a portion of the foundation layer 22 are sealed by the sealing body 140. A portion of the side surface 21c of the foundation layer 21 and a portion of the side surface 22c of the foundation layer 22 are exposed from the sealing body 140. A portion of the wiring layer 30A and a portion of the wiring layer 30B are sealed by the sealing body 140. A portion of the first metal layer 31 of the wiring layer 30A, a portion of the third metal layer 33 of the wiring layer 30A, a portion of the fourth metal layer 34 of the wiring layer 30A, and a portion of the intermediate layer 35 of the wiring layer 30A are exposed from the sealing body 140. A portion of the first metal layer 31 of the wiring layer 30B, a portion of the third metal layer 33 of the wiring layer 30B, a portion of the fourth metal layer 34 of the wiring layer 30B, and a portion of the intermediate layer 35 of the wiring layer 30B are exposed from the sealing body 140.

[0067] The sealing body 140 is made of, for example, a resin material. The sealing body 140 preferably has insulating properties. An example of the resin material is a thermosetting resin. The sealing body 140 preferably further contains a filler.

[0068] Next, the effects of the semiconductor device 100A will be described. As shown in FIG. 6, the cross-sectional structures of the wiring layer 30A and the wiring layer 30B are the same as those of the wiring layer 30 shown in FIG. 1. As a result, even if portions of the wiring layer 30A and the wiring layer 30B are exposed from the encapsulant 140, the second metal layer 32 of the wiring layer 30A and the second metal layer 32 of the wiring layer 30B can be prevented from being exposed from the outer surface of the semiconductor device 100A. Therefore, even if the entire wiring layer 30A and the wiring layer 30B are not encapsulated with the encapsulant 140, corrosion of the wiring layer 30A and the wiring layer 30B can be prevented. As a result, the semiconductor device 100A is less susceptible to corrosion. Therefore, the environmental resistance of the semiconductor device 100A can be improved while reducing the amount of precious metal used.

[0069] Furthermore, although the semiconductor element 110 is a heat source, by increasing the amount of the second metal with high thermal conductivity and low thermal conductivity, the thermal conductivity can be compensated for and the thermal conductivity of the wiring board 1 can be increased even when a material with low thermal conductivity is used for the insulating base material 10. As a result, the heat generated by the semiconductor element 110 can be efficiently dissipated, and the characteristics can be maintained for a long period of time.

[0070] <<Light-emitting device>> Next, a light emitting device according to this embodiment will be described. Fig. 7 is a cross-sectional view of a light emitting device according to one embodiment. As shown in Fig. 7, a light emitting device 200 according to this embodiment includes a wiring substrate 1D, a light emitting element 210, a conductive material 250, and a reflective member 260.

[0071] <Wiring board> The wiring board 1D has an insulating base material 10, an underlayer 20, a wiring layer 30, and a pad portion 40. The configurations of the insulating base material 10, the underlayer 20, the wiring layer 30, and the pad portion 40 of the wiring board 1D are the same as those of the wiring board 1A shown in FIG.

[0072] <Light-emitting element> The light emitting element 210 is connected to the wiring layer 30 of the wiring board 1D via a conductive material 250. The light emitting element 210 has, for example, a terminal. The terminal of the light emitting element 210 is electrically connected to the fourth metal layer 34 of the wiring layer 30 via the conductive material 250, for example.

[0073] The light-emitting element 210 is, for example, a light-emitting diode. Examples of light-emitting diodes include light-emitting diodes using nitride-based semiconductors, GaAlAs, and AlInGaP. The light-emitting element 210 has, for example, multiple terminals. The light-emitting element 210 preferably has, for example, a pair of positive and negative terminals on the same surface. This allows the light-emitting element 210 to be flip-chip mounted on a mounting substrate. In this case, the surface of the light-emitting element 210 opposite the surface on which the pair of terminals are formed serves as the main light extraction surface. The outermost surface of the terminal of the light-emitting element 210 is preferably made of gold. Gold is chemically stable, and therefore can ensure reliable electrical connection.

[0074] <Conductive material> The conductive material 250 can bond the wiring layer 30 and the light emitting element 210. Examples of the conductive material 250 include tin-bismuth, tin-copper, tin-silver, and gold-tin solders, eutectic alloys such as alloys mainly composed of Au and Sn, alloys mainly composed of Au and Si, and alloys mainly composed of Au and Ge, conductive pastes of silver, gold, palladium, and the like, bumps, anisotropic conductive materials such as ACP (Anisotropic Conductive Paste) and ACF (Anisotropic Conductive Film), brazing materials of low-melting point metals, and conductive adhesives and conductive composite adhesives that are combinations of these.

[0075] <Reflective material> The reflective member 260 is disposed on the upper surface 10a of the insulating substrate 10. The reflective member 260 is in contact with the fourth metal layer 34, the third metal layer 33, and the underlayer 20. The reflective member 260 is preferably formed from a material capable of reflecting light emitted from the light-emitting element 210. This allows the light emitted from the light-emitting element 210 to be reflected back into the light-emitting element 210 at the interface between the light-emitting element 210 and the reflective member 260. As a result, the light propagates within the light-emitting element 210 and is finally emitted to the outside from the light-emitting element. The reflective member 260 can also protect the light-emitting element 210 from external forces, dust, gas, and the like.

[0076] The reflective member 260 may be made of, for example, a silicone resin, a modified silicone resin, an epoxy resin, a modified epoxy resin, an acrylic resin, or a hybrid resin containing at least one of these resins. The reflective member 260 preferably further contains a filler such as a light-reflecting material. Examples of light-reflecting materials include titanium oxide, silicon oxide, zirconium oxide, potassium titanate, aluminum oxide, aluminum nitride, boron nitride, and mullite.

[0077] Next, the effects of the light emitting device 200 will be described. As shown in FIG. 7, the cross-sectional structure of the wiring layer 30 of the light emitting device 200 is the same as that of the wiring layer 30 shown in FIG. 4. This prevents the second metal layer 32 of the wiring layer 30 from being exposed from the outer surface of the light emitting device 200. As a result, the light emitting device 200 is less susceptible to corrosion. This improves the performance of the light emitting device 200. In addition, in this embodiment, the reflective member 260 is in contact with the fourth metal layer 34, the third metal layer 33, and the base layer 20. In other words, the reflective member 260 fills the gap between the wiring layer 30 and the insulating base 10. This prevents the reflective member 260 from lifting up and peeling off.

[0078] <<Wiring Board Manufacturing Method>> Next, a method for manufacturing a wiring board according to this embodiment will be described. Figures 8 to 16 are cross-sectional views showing the method for manufacturing a wiring board according to this embodiment. The method for manufacturing a wiring board according to this embodiment includes the following steps. S1: Step of preparing an insulating substrate 10 having an underlayer 20 formed on the upper surface S2: Step of forming a resist layer 70 on the upper surface of the underlayer 20 S3: A step of exposing and developing the resist layer 70 so that at least a portion of the underlayer 20 is exposed from the resist layer 70. S4: Step of forming a first metal layer 31 on the upper surface of the base layer 20 exposed from the resist layer 70 S5: Step of forming a second metal layer 32 on the upper surface of the first metal layer 31 S6: A step of removing the resist layer 70 and the underlayer 20 after the step of forming the second metal layer 32 S7: Step of forming a third metal layer 33 on the top surface and side surfaces of the second metal layer 32 S8: Step of forming the intermediate layer 35 on the top surface and side surfaces of the third metal layer 33 S9: Step of forming the fourth metal layer 34 on the upper surface and side surfaces of the intermediate layer 35

[0079] <Step of Preparing Insulating Base Material 10 with Underlayer 20 Formed on the Upper Surface> As shown in FIG. 8, in step S1, an insulating base material 10 having an underlayer 20 formed on an upper surface 10a thereof is prepared.

[0080] The underlayer 20 is disposed on the upper surface 10a of the insulating base material 10. The lower surface 20b of the underlayer 20 is in contact with the upper surface 10a of the insulating base material 10. The underlayer 20 is formed on the upper surface 10a of the insulating base material 10 by, for example, sputtering.

[0081] <Step of forming resist layer 70 on the upper surface of underlayer 20> As shown in FIG. 9, in step S2, a resist layer 70 is formed on the upper surface 20a of the base layer 20 prepared in step S1. The resist layer 70 is formed so that the upper surface 20a of the base layer 20 is in contact with the lower surface 70b of the resist layer 70. The resist layer 70 is formed, for example, by applying a resin composition onto the upper surface 20a of the base layer 20. The thickness of the resist layer 70 is preferably greater than the combined thickness of the first metal layer 31 and the second metal layer 32. The resist layer 70 is made of, for example, a photosensitive resin composition containing a photosensitive resin. The photosensitive resin is, for example, a polyimide resin.

[0082] <Step of exposing and developing the resist layer 70 so that at least a portion of the underlayer 20 is exposed from the resist layer 70> As shown in FIG. 10, in step S3, a portion of the resist layer 70 formed in step S2 is removed so as to expose a portion of the base layer 20. In the example shown in FIG. 10, a portion of the upper surface 20a of the base layer 20 is exposed. The portion of the resist layer 70 is removed by exposure and development. For example, the exposure method is to irradiate the portion of the resist layer 70 formed in step S2 with ultraviolet light. For example, the development method is to develop the exposed resist layer 70 with a developer. The developer is composed of, for example, an alkaline component and water.

[0083] <Step of forming first metal layer 31 on the upper surface of base layer 20 exposed from resist layer 70> 11, in step S4, a first metal layer 31 is formed on the upper surface 20a of the base layer 20 exposed in step S3. The first metal layer 31 is formed, for example, by electrolytic plating or electroless plating. A lower surface 31b of the first metal layer 31 contacts the upper surface 20a of the base layer 20. A side surface 31c of the first metal layer 31 contacts the resist layer 70.

[0084] <Step of forming second metal layer 32 on the top surface of first metal layer 31> 12, in step S5, a second metal layer 32 is formed on the upper surface 31a of the first metal layer 31 formed in step S4. The second metal layer 32 is formed, for example, by electrolytic plating. The lower surface 32b of the second metal layer 32 contacts the upper surface 31a of the first metal layer 31. The side surface 32c of the second metal layer 32 contacts the resist layer 70.

[0085] <Step of Removing Resist Layer 70 and Underlayer 20 After Step of Forming Second Metal Layer 32> As shown in FIG. 13, in step S6, after the second metal layer 32 is formed, the resist layer 70 and the underlayer 20 are removed.

[0086] In this embodiment, after forming the second metal layer 32, the resist layer 70 is first removed. The resist layer 70 is removed by, for example, etching. It is preferable that the resist layer 70 is completely removed in step S6.

[0087] In this embodiment, the resist layer 70 is removed, and then the underlayer 20 is removed. The underlayer 20 is removed, for example, by etching. In this case, the first metal layer 31 and the second metal layer 32 function as an etching mask. Therefore, when the upper surface 10a of the insulating substrate 10 is viewed from above, the etching effect extends to the underlayer 20 located inside the edge of the second metal layer 32, and the edge of the underlayer 20 is formed inside the edge of the second metal layer 32. It is preferable to remove the underlayer 20 so that the distance from the edge of the upper surface 20a of the underlayer 20 to the edge of the lower surface 32b of the second metal layer 32 is 1.0 μm or more and 20.0 μm or less.

[0088] <Step of forming third metal layer 33 on the top surface and side surfaces of second metal layer 32> As shown in FIG. 14, in step S7, a third metal layer 33 is formed on the upper surface 32a and the side surface 32c of the second metal layer 32. The third metal layer 33 contacts the upper surface 32a and the side surface 32c of the second metal layer 32. The third metal layer 33 is formed, for example, by electroless plating. In the example shown in FIG. 14, the third metal layer 33 is also formed on the side surface 31c of the first metal layer 31. The third metal layer 33 contacts the side surface 31c of the first metal layer 31.

[0089] <Step of forming intermediate layer 35 on the top surface and side surfaces of third metal layer 33> 15, in step S8, an intermediate layer 35 is formed on the upper surface 33a and the side surface 33c of the third metal layer 33. The intermediate layer 35 contacts the upper surface 33a and the side surface 33c of the third metal layer 33. The intermediate layer 35 is formed by, for example, electroless plating. Step S8 is not an essential step. That is, there are cases where the intermediate layer 35 is not formed.

[0090] <Step of forming the fourth metal layer 34 on the top surface and side surfaces of the intermediate layer 35> 16, in step S9, a fourth metal layer 34 is formed on the upper surface 35a and the side surface 35c of the intermediate layer 35. The fourth metal layer 34 contacts the upper surface 35a and the side surface 35c of the intermediate layer 35. The fourth metal layer 34 is formed by, for example, electroless plating.

[0091] When the intermediate layer 35 is not provided, the fourth metal layer 34 is formed on the upper surface 33a and the side surface 33c of the third metal layer 33. When the intermediate layer 35 is not provided, the fourth metal layer 34 contacts the upper surface 33a and the side surface 33c of the third metal layer 33.

[0092] As described above, the highly reliable wiring board 1 according to this embodiment can be manufactured by a simple manufacturing method.

[0093] (Variation) The method for manufacturing a wiring board according to this embodiment is the same as the above embodiment in steps S1 to S4. However, after step S4 of forming the first metal layer 31, a resist layer other than the resist layer 70 may be formed on a portion of the upper surface 31a of the first metal layer 31. Then, a second metal layer 32 is formed on the upper surface 31a of the first metal layer 31. The second metal layer 32 is not formed on the portion of the upper surface 31a of the first metal layer 31 that is covered with the resist layer. This allows for the formation of a region on the upper surface 31a of the first metal layer 31 where the second metal layer 32 is not formed. As a result, the thickness of the wiring in the portion where the second metal layer 32 is not formed can be reduced. A metal layer made of, for example, Al or Au is formed on the upper surface 31a of the first metal layer 31 where the second metal layer 32 is not formed.

[0094] <<Light Emitting Device Manufacturing Method>> Next, a method for manufacturing a light emitting device according to one embodiment will be described. The method for manufacturing a light emitting device according to this embodiment includes the method for manufacturing the wiring board described above. The method for manufacturing a light emitting device according to this embodiment uses, for example, the wiring board 1D manufactured by the method for manufacturing the wiring board described above.

[0095] The method for manufacturing a light emitting device further includes the steps of arranging a light emitting element 210 on an insulating substrate 10 and arranging a reflecting member 260 on an upper surface 10a of the insulating substrate 10.

[0096] In the step of disposing the light emitting element 210 on the insulating base material 10, for example, the terminal of the light emitting element 210 is electrically connected to the fourth metal layer 34 by the conductive material 250. The conductive material 250 also serves as a bonding member, for example. That is, the light emitting element 210 is fixed onto the fourth metal layer 34 by the conductive material 250.

[0097] In the step of disposing the reflective member 260 on the upper surface 10a of the insulating base material 10, the reflective member 260 is disposed so as to be in contact with the fourth metal layer 34, the third metal layer 33, and the underlayer 20.

[0098] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Industrial Applicability]

[0099] The embodiments of the present invention can provide a wiring board, a semiconductor device, a light-emitting device, a method for manufacturing a wiring board, and a method for manufacturing a light-emitting device that can improve performance. [Explanation of symbols]

[0100] 1, 1A, 1B, 1C, 1D, 1F wiring board 10. Insulating substrate 10a top surface 10b Bottom side 20 Base layer 20a top surface 20b Bottom side 20c side 21 Base layer 21a Top side 21c side 22 Base layer 22a Top side 22c side 23 Base layer 23a Top side 30 wiring layer 30A wiring layer 30B wiring layer 31 First metal layer 31a Top surface 31b Bottom surface 31c side 32 Second Metal Layer 32a top surface 32b Bottom side 32c side 33 Third Metal Layer 33a Top side 33c side 34 Fourth Metal Layer 34a Top 34c side 35 Middle Class 35a top surface 35c side 40 Pad section 50 Light reflective layer 70 resist layer 70b Bottom side 100 Semiconductor device 100A Semiconductor Device 110 Semiconductor elements 111A, 111B electrode 120 wire 130 die pad 131 Adhesive layer 140 Sealing body 150 Conductive materials 200 Light-emitting device 210 Light-emitting element 250 Conductive Materials 260 Reflective material 311 First Metal Layer 311a top side 311b Bottom side 311c side 312 first metal layer 322 Second Metal Layer 322b Bottom side 331 Third Metal Layer 331a top side 331c side 332 Third Metal Layer 341 Fourth Metal Layer 342 Fourth Metal Layer 342a top side 351 Middle Class 351a top side 351c side 352 Middle Class 361 Fifth Metal Layer M1 Recognition Mark H1 hole N1 Gap

Claims

1. an insulating substrate; a base layer disposed on the upper surface of the insulating substrate; a first metal layer disposed on an upper surface of the underlayer and including a first metal; a second metal layer disposed on an upper surface of the first metal layer and including a second metal that is less noble than the first metal; a third metal layer disposed on the top and side surfaces of the second metal layer and including the first metal; a fourth metal layer disposed on an upper surface and a side surface of the third metal layer, the fourth metal layer including a third metal more noble than the first metal; a wiring board, wherein the entire surface of the second metal layer is covered with the first metal layer and the third metal layer;

2. 2. The wiring board according to claim 1, When the upper surface of the insulating base is viewed from above, the edge of the upper surface of the foundation layer is located more inward than the edge of the lower surface of the second metal layer.

3. 3. The wiring board according to claim 2, When the upper surface of the insulating base is viewed from above, the distance from the edge of the upper surface of the underlayer to the edge of the lower surface of the second metal layer is 1.0 μm or more and 20.0 μm or less.

4. 2. The wiring board according to claim 1, Furthermore, an intermediate layer containing a fourth metal is provided between the third metal layer and the fourth metal layer.

5. 2. The wiring board according to claim 1, The underlayer is at least one selected from a single layer selected from a Ti layer, a Cu layer, an Au layer, and a Ru layer, or a laminate containing these, an alloy layer, a laminate of Ti and Cu, a laminate of Ti and Au, a laminate of Ti and Ag, an alloy layer of Ti and Ni, an alloy layer of Ti and W, an alloy layer of Cu and Ni, an alloy layer of Ni and Cr, a Ti layer and a TiNi layer, a Ti layer and a TiW layer, a Ti layer, a TiW layer and a Cu layer, or a Ti layer, a Ru layer, and a Cu layer.

6. 2. The wiring board according to claim 1, The underlayer is a layer formed by laminating multiple layers each made of at least one material selected from a Ti and Cu layer, a Ti and Au layer, a Ti and Ag layer, a Ti and Ni alloy layer, a Ti and W alloy layer, a Cu and Ni alloy layer, a Ni and Cr alloy layer, and a Ti layer.

7. 2. The wiring board according to claim 1, The underlayer has a thickness of 0.1 μm or more and 2.0 μm or less, and the first metal layer and the third metal layer do not contact the insulating substrate.

8. 2. The wiring board according to claim 1, Furthermore, the optical element has a light-reflecting layer covering the fourth metal layer, and when the light-reflecting layer is irradiated with light of 450 nm or more and 460 nm or less, the total light reflectance of the light-reflecting layer is higher than the total light reflectance of the fourth metal layer.

9. 2. The wiring board according to claim 1, Furthermore, it has a pad portion electrically connected to the fourth metal layer.

10. 10. The wiring board according to claim 9, The pad portion includes the insulating substrate and the underlayer disposed on the upper surface of the insulating substrate; the first metal layer disposed on an upper surface of the underlayer; an intermediate layer disposed on a top surface of the first metal layer; The fourth metal layer is disposed on the top surface and side surfaces of the intermediate layer.

11. 10. The wiring board according to claim 9, The pad portion includes the insulating substrate and the underlayer disposed on the upper surface of the insulating substrate; a fifth metal layer disposed on the upper surface of the underlayer and including a fifth metal less noble than the third metal;

12. 2. The wiring board according to claim 1, The first metal is Ni.

13. 2. The wiring board according to claim 1, The second metal is Cu.

14. 2. The wiring board according to claim 1, The third metal is Au.

15. 5. The wiring board according to claim 4, The fourth metal is Pd.

16. The wiring substrate according to any one of claims 1 to 15, a semiconductor element disposed on the wiring substrate.

17. The wiring substrate according to any one of claims 1 to 15, a light-emitting element disposed on the wiring substrate.

18. 18. The light emitting device according to claim 17, the light-emitting device includes a reflecting member disposed on an upper surface of the insulating substrate; The reflecting member is in contact with the fourth metal layer, the third metal layer, and the base layer.

19. (a) providing an insulating substrate having an underlayer formed on an upper surface thereof; (b) forming a resist layer on the upper surface of the underlayer; (c) exposing and developing the resist layer so that at least a portion of the underlayer is exposed from the resist layer; (d) forming a first metal layer containing a first metal on the upper surface of the underlayer exposed from the resist layer; (e) forming a second metal layer on the upper surface of the first metal layer, the second metal layer comprising a second metal less noble than the first metal; (f) removing the resist layer after the step of forming the second metal layer; (g) removing the underlayer after the step of removing the resist layer; (h) forming a third metal layer comprising the first metal on the top surface and side surfaces of the second metal layer; (i) forming a fourth metal layer on the top surface and side surfaces of the third metal layer, the fourth metal layer comprising a third metal more noble than the first metal; A method for manufacturing a wiring board comprising:

20. 20. The method for manufacturing a wiring board according to claim 19, In the process of removing the base layer, the base layer is etched so that, when the upper surface of the insulating substrate is viewed in a plane, the edge of the upper surface of the base layer remaining on the upper surface of the insulating substrate is formed more inward than the edge of the lower surface of the second metal layer.

21. 21. The method for manufacturing a wiring board according to claim 20, In the step of removing the underlayer, when the upper surface of the insulating substrate is viewed in a plane, the distance from the edge of the upper surface of the underlayer to the edge of the lower surface of the second metal layer is 1.0 μm or more and 20.0 μm or less.

22. 20. The method for manufacturing a wiring board according to claim 19, Furthermore, after the step of forming the third metal layer, (h1) forming an intermediate layer containing a fourth metal on the top surface and side surfaces of the third metal layer; In the step of forming the fourth metal layer, the fourth metal layer containing the third metal is formed on the upper surface and side surfaces of the intermediate layer.

23. 20. The method for manufacturing a wiring board according to claim 19, In the step of preparing the insulating base material, the underlayer has a thickness of 0.1 μm or more and 2.0 μm or less.

24. 20. The method for manufacturing a wiring board according to claim 19, The first metal is Ni.

25. 20. The method for manufacturing a wiring board according to claim 19, The second metal is Cu.

26. 20. The method for manufacturing a wiring board according to claim 19, The third metal is Au.

27. 23. The method for manufacturing a wiring board according to claim 22, The fourth metal is Pd.

28. A step of preparing a wiring substrate according to any one of claims 1 to 15; disposing a light emitting element on an insulating substrate; and disposing a reflective member on the upper surface of the insulating substrate; In the step of arranging the reflective member, the reflective member is arranged so as to be in contact with the fourth metal layer, the third metal layer, and the base layer.

Images