Semiconductor element

Abstract

To provide a semiconductor element whose productivity and reliability are improved, and a manufacturing method for the same.SOLUTION: The present invention relates to a semiconductor element, and more specifically, the semiconductor element includes a substrate, source and drain patterns on the substrate, a channel pattern between the source and drain patterns, in which the channel pattern includes a plurality of semiconductor patterns separated from each other and stacked on each other, a gate electrode between the semiconductor patterns, an upper separate structure disposed horizontally apart from the gate electrode and extending in a first direction, a first rear surface separate structure penetrating the substrate and disposed below the gate electrode, and a second rear surface separate structure penetrating the substrate and overlapping vertically with the upper separate structure below the upper separate structure. Each of the first and second rear surface separate structures may extend in the first direction.SELECTED DRAWING: Figure 5A

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices including field effect transistors. [Background technology]

[0002] Semiconductor devices include integrated circuits configured with MOS (Metal Oxide Semiconductor) field effect transistors (FETs). As the size and design rules of semiconductor devices continue to shrink, the scale down of MOS field effect transistors is also accelerating. As the size of MOS field effect transistors shrinks, the operating characteristics of semiconductor devices can deteriorate. Therefore, various methods are being researched to overcome the limitations imposed by the high integration of semiconductor devices and to form semiconductor devices with better performance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Publication No. 2022 / 0139911 A1 Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION One technical problem that embodiments of the present invention aim to achieve is to provide a semiconductor device and a method for manufacturing the same with improved productivity and reliability.

[0005] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] According to an embodiment of the present invention, a semiconductor device includes a substrate, source and drain patterns on the substrate, a channel pattern between the source and drain patterns, the channel pattern including a plurality of stacked semiconductor patterns spaced apart from each other, a gate electrode between the plurality of semiconductor patterns, an upper isolation structure spaced horizontally from the gate electrode and extending in a first direction, a first back isolation structure penetrating the substrate and disposed below the gate electrode, and a second back isolation structure penetrating the substrate and vertically overlapping the upper isolation structure below the upper isolation structure, wherein the first and second back isolation structures may each extend in the first direction.

[0007] According to another embodiment of the present invention, a semiconductor device includes a substrate; source and drain patterns on the substrate; a channel pattern between the source and drain patterns; the channel pattern including a plurality of stacked semiconductor patterns spaced apart from each other; a gate electrode between the plurality of semiconductor patterns; an upper isolation structure disposed horizontally spaced apart from the gate electrode; a first back isolation structure extending through the substrate and below the gate electrode; and a second back isolation structure extending through the substrate and below the upper isolation structure and vertically overlapping the upper isolation structure, wherein bottom surfaces of the first and second back isolation structures may be located at a lower level than a bottom surface of the substrate.

[0008] A semiconductor device according to another embodiment of the present invention includes a substrate including an active pattern, an isolation layer provided on the substrate and defining the active pattern, a channel pattern and source and drain patterns on the active pattern, a gate electrode on the channel pattern, a gate insulating layer interposed between the gate electrode and the channel pattern, gate spacers on sidewalls of the gate electrode, a gate capping pattern on an upper surface of the gate electrode, an upper isolation structure horizontally spaced apart from the gate electrode and extending in a first direction, an interlayer insulating layer covering the source and drain patterns and the gate capping pattern, and a gate insulating layer extending through the interlayer insulating layer to cover the source and drain patterns. a power transmission network layer provided under the substrate; a back active contact that penetrates the substrate and electrically connects the power transmission network layer to another one of the source and drain patterns; a first back isolation structure that penetrates the substrate and is disposed under the gate electrode; and a second back isolation structure that penetrates the substrate and is vertically overlapped with the upper isolation structure below the upper isolation structure, wherein the first and second back isolation structures may each extend in the first direction. [Effects of the Invention]

[0009] A semiconductor device according to the present invention may include an upper isolation structure formed first, followed by a second rear isolation structure connected vertically to the upper isolation structure. By forming the upper isolation structure and then forming the second rear isolation structure connected to the upper isolation structure on the rear surface, the heights of the upper isolation structure and the second rear isolation structure can be relatively reduced compared to when the isolation structures are integrally formed. As a result, when the upper isolation structure and the second rear isolation structure are formed, no internal seam is formed, or the size of the seam can be reduced. This can improve the reliability of the semiconductor device.

[0010] Furthermore, the second rear isolation structure can be formed during the process of forming the first rear isolation structure, which prevents leakage current from flowing through the source and drain patterns, thereby improving the productivity of semiconductor devices. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the present invention; [Figure 2] 1 is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the present invention; [Figure 3] 1 is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the present invention; [Figure 4] 1 is a plan view illustrating a semiconductor device according to an embodiment of the present invention; [Figure 5A] 4B and 4C are cross-sectional views taken along line AA' in FIG. 4A. [Figure 5B] 4B are cross-sectional views taken along line BB' in FIG. 4A. [Figure 5C] 4B and 4C are cross-sectional views taken along line CC' in FIG. 4A. [Figure 5D] 4B and 4C are cross-sectional views taken along line DD' in FIG. 4A. [Figure 6] FIG. 5B is an enlarged view showing a portion P in FIG. 5A. [Figure 7A] 5B is a cross-sectional view corresponding to FIG. 5A illustrating a sequential manufacturing method flow. [Figure 7B] FIG. 5D is a cross-sectional view corresponding to FIG. 5D. [Figure 8A] 5B is a cross-sectional view corresponding to FIG. 5A illustrating a sequential manufacturing method flow. [Figure 8B] FIG. 5D is a cross-sectional view corresponding to FIG. 5D. [Figure 9A] 5B is a cross-sectional view corresponding to FIG. 5A illustrating a sequential manufacturing method flow. [Figure 9B] FIG. 5C is a cross-sectional view corresponding to FIG. 5B. [Figure 9C] FIG. 5D is a cross-sectional view corresponding to FIG. 5C. [Figure 10A]5B is a cross-sectional view corresponding to FIG. 5A illustrating a sequential manufacturing method flow. [Figure 10B] FIG. 5C is a cross-sectional view corresponding to FIG. 5B. [Figure 10C] FIG. 5D is a cross-sectional view corresponding to FIG. 5C. [Figure 11A] 5B is a cross-sectional view corresponding to FIG. 5A illustrating a sequential manufacturing method flow. [Figure 11B] FIG. 5C is a cross-sectional view corresponding to FIG. 5B. [Figure 11C] FIG. 5D is a cross-sectional view corresponding to FIG. 5D. [Figure 12A] 5B is a cross-sectional view corresponding to FIG. 5A illustrating a sequential manufacturing method flow. [Figure 12B] FIG. 5C is a cross-sectional view corresponding to FIG. 5B. [Figure 12C] FIG. 5D is a cross-sectional view corresponding to FIG. 5C. [Figure 12D] FIG. 5D is a cross-sectional view corresponding to FIG. 5D. [Figure 13A] 5B is a cross-sectional view corresponding to FIG. 5A illustrating a sequential manufacturing method flow. [Figure 13B] FIG. 5C is a cross-sectional view corresponding to FIG. 5B. [Figure 13C] FIG. 5D is a cross-sectional view corresponding to FIG. 5C. [Figure 13D] FIG. 5D is a cross-sectional view corresponding to FIG. 5D. [Figure 14] 1 is a plan view illustrating a semiconductor device according to an embodiment of the present invention; [Figure 15A] 5B is a cross-sectional view corresponding to FIG. 5A illustrating a sequential manufacturing method flow. [Figure 15B] FIG. 5C is a cross-sectional view corresponding to FIG. 5B. [Figure 15C] FIG. 5D is a cross-sectional view corresponding to FIG. 5C. [Figure 15D] FIG. 5D is a cross-sectional view corresponding to FIG. 5D. [Figure 16A] 5B is a cross-sectional view corresponding to FIG. 5A illustrating a sequential manufacturing method flow. [Figure 16B] FIG. 5C is a cross-sectional view corresponding to FIG. 5B. [Figure 16C] FIG. 5D is a cross-sectional view corresponding to FIG. 5C. [Figure 16D] FIG. 5D is a cross-sectional view corresponding to FIG. 5D. [Figure 17A] 5B is a cross-sectional view corresponding to FIG. 5A illustrating a sequential manufacturing method flow. [Figure 17B] FIG. 5C is a cross-sectional view corresponding to FIG. 5B. [Figure 17C] FIG. 5D is a cross-sectional view corresponding to FIG. 5C. [Figure 17D] FIG. 5D is a cross-sectional view corresponding to FIG. 5D. DETAILED DESCRIPTION OF THE INVENTION

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more specifically explain the present invention, embodiments of the present invention will be described in more detail below with reference to the accompanying drawings.

[0013] 1 to 3 are conceptual diagrams illustrating logic cells of a semiconductor device according to an embodiment of the present invention.

[0014] 1, a single height cell (SHC) may be provided. Specifically, a first lower power wiring VPR1 and a second lower power wiring VPR2 may be provided under a substrate 100. The first lower power wiring VPR1 may be a path through which a source voltage VSS, for example, a ground voltage, is provided. The second lower power wiring VPR2 may be a path through which a drain voltage VDD, for example, a power voltage, is provided.

[0015] A single-height cell SHC may be defined between the first lower power wiring VPR1 and the second lower power wiring VPR2. The single-height cell SHC may include one PMOSFET region PR and one NMOSFET region NR. Again, the single-height cell SHC may have a CMOS structure provided between the first lower power wiring VPR1 and the second lower power wiring VPR2.

[0016] Each of the PMOSFET region PR and the NMOSFET region NR may have a first width W1 in the first direction D1. The length of the single-height cell SHC in the first direction D1 may be defined as a first height HE1. The first height HE1 may be substantially equal to the distance (e.g., pitch) between the first lower power wiring VPR1 and the second lower power wiring VPR2.

[0017] The single-height cell SHC can constitute one logic cell. As used herein, a logic cell can refer to a logic element (e.g., AND, OR, XOR, XNOR, inverter, etc.) that performs a specific function. That is, a logic cell can include transistors for constituting the logic element and wiring that connects the transistors to each other.

[0018] 2, a double height cell (DHC) may be provided. Specifically, a first lower power wiring VPR1, a second lower power wiring VPR2, and a third lower power wiring VPR3 may be provided on a substrate 100. The second lower power wiring VPR2 may be disposed between the first lower power wiring VPR1 and the third lower power wiring VPR3. The third lower power wiring VPR3 may be a path through which a source voltage VSS is provided.

[0019] A double-height cell DHC may be defined between the first lower power wiring VPR1 and the third lower power wiring VPR3. The double-height cell DHC may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2.

[0020] The first NMOSFET region NR1 may be adjacent to the first lower power wiring VPR1. The second NMOSFET region NR2 may be adjacent to the third lower power wiring VPR3. The first and second PMOSFET regions PR1, PR2 may be adjacent to the second lower power wiring VPR2. In a plan view, the second lower power wiring VPR2 may be disposed between the first and second PMOSFET regions PR1, PR2.

[0021] The length of the double-height cell DHC in the first direction D1 may be defined as a second height HE2. The second height HE2 may be approximately twice the first height HE1 of FIG. 1. The first and second PMOSFET regions PR1 and PR2 of the double-height cell DHC may be bundled together to operate as a single PMOSFET region. Therefore, the channel size of the PMOS transistor of the double-height cell DHC may be larger than the channel size of the PMOS transistor of the single-height cell SHC of FIG. 1.

[0022] For example, the channel size of the PMOS transistor of the double-height cell DHC may be approximately twice the channel size of the PMOS transistor of the single-height cell SHC. As a result, the double-height cell DHC can operate at a higher speed than the single-height cell SHC. In the present invention, the double-height cell DHC shown in FIG. 2 may be defined as a multi-height cell. Although not shown, the multi-height cell may include a triple-height cell whose cell height is approximately three times that of the single-height cell SHC.

[0023] 3, a first single-height cell SHC1, a second single-height cell SHC2, and a double-height cell DHC may be two-dimensionally arranged on a substrate 100. The first single-height cell SHC1 may be arranged between first and second lower power wirings VPR1 and VPR2. The second single-height cell SHC2 may be arranged between second and third lower power wirings VPR2 and VPR3. The second single-height cell SHC2 may be adjacent to the first single-height cell SHC1 in a first direction D1.

[0024] The double-height cell DHC may be disposed between the first and third lower power wirings VPR1 and VPR3, and may be adjacent to the first and second single-height cells SHC1 and SHC2 in the second direction D2.

[0025] An upper isolation structure DB may be provided between the first single height cell SHC1 and the double height cell DHC, and between the second single height cell SHC2 and the double height cell DHC, and the upper isolation structure DB may electrically isolate the active region of the double height cell DHC from the active regions of the first and second single height cells SHC1 and SHC2.

[0026] Figure 4 is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Figures 5A to 5D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' in Figure 4A, respectively. Figure 6 is an enlarged view of part P in Figure 5A.

[0027] 4 and 5A to 5D, a single height cell SHC may be provided on a substrate 100. For example, the single height cell SHC may be one of the single height cell SHC described in FIG. 1 or the first and second single height cells SHC1 and SHC2 described in FIG. 3. A logic transistor constituting a logic circuit may be disposed on the single height cell SHC. For example, the substrate 100 may be a semiconductor substrate including silicon, germanium, silicon germanium, etc., a compound semiconductor substrate, or a silicon substrate. For another example, the substrate 100 may include an insulating layer on a silicon substrate, which may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0028] The substrate 100 may have a PMOSFET region PR and an NMOSFET region NR. Each of the PMOSFET region PR and the NMOSFET region NR may extend in a second direction D2.

[0029] A first active pattern AP1 and a second active pattern AP2 may be defined by trenches TR formed in the upper portion of the substrate 100. The first active pattern AP1 may be provided on a PMOSFET region PR, and the second active pattern AP2 may be provided on an NMOSFET region NR.

[0030] An isolation layer ST may fill the trench TR. The isolation layer ST may cover sidewalls of a back active contact BAC and a first back isolation structure BST1, which will be described later. The isolation layer ST may include a silicon-based insulating material (e.g., a silicon oxide layer). The isolation layer ST may not cover first and second channel patterns CH1 and CH2, which will be described later.

[0031] A first channel pattern CH1 may be provided on the first active pattern AP1. A second channel pattern CH2 may be provided on the second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 that are sequentially stacked. The first to third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in the vertical direction (i.e., the third direction D3).

[0032] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 may include crystalline silicon. Each of the first to third semiconductor patterns SP1, SP2, and SP3 may be a nanosheet.

[0033] A plurality of first source / drain patterns SD1 may be provided on the first active pattern AP1. A plurality of first recesses (RS1 in FIG. 9A) may be formed on the first active pattern AP1. The first source / drain patterns SD1 may be provided in each of the first recesses (RS1 in FIG. 9A). The first source / drain patterns SD1 may be impurity regions of a first conductivity type (e.g., p-type). A first channel pattern CH1 may be interposed between adjacent pairs of first source / drain patterns SD1. In other words, stacked first to third semiconductor patterns SP1, SP2, and SP3 may connect pairs of first source / drain patterns SD1 to each other.

[0034] A plurality of second source / drain patterns SD2 may be provided on the second active pattern AP2. A plurality of second recesses (RS2 in FIG. 9B) may be formed on the second active pattern AP2. The second source / drain patterns SD2 may be provided in each of the second recesses (RS2 in FIG. 9A). The second source / drain patterns SD2 may be impurity regions of a second conductivity type (e.g., n-type). A second channel pattern CH2 may be interposed between adjacent pairs of second source / drain patterns SD2. In other words, stacked first to third semiconductor patterns SP1, SP2, and SP3 may connect a pair of second source / drain patterns SD2 to each other.

[0035] The first and second source / drain patterns SD1 and SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. For example, the top surfaces of the first and second source / drain patterns SD1 and SD2 may be located at substantially the same level as the top surface of the third semiconductor pattern SP3. For another example, the top surfaces of the first and second source / drain patterns SD1 and SD2 may be higher than the top surface of the third semiconductor pattern SP3.

[0036] The first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the first channel pattern CH1. Therefore, the pair of first source / drain patterns SD1 may provide compressive stress to the first channel pattern CH1 between them. The second source / drain pattern SD2 may include the same semiconductor element (e.g., Si) as the second channel pattern CH2.

[0037] Each first source / drain pattern SD1 may include a buffer layer BFL and a main layer MAL on the buffer layer BFL. Referring back to FIG. 5A, the buffer layer BFL may cover the inner wall of the first recess (RS1 in FIG. 9A). The main layer MAL may fill the remaining area of ​​the first recess (RS1 in FIG. 9A) excluding the buffer layer BFL. The volume of the main layer MAL may be larger than the volume of the buffer layer BFL. The buffer layer BFL and the main layer MAL may each include silicon germanium (SiGe). Specifically, the buffer layer BFL may contain a relatively low concentration of germanium (Ge). In another embodiment of the present invention, the buffer layer BFL may contain only silicon (Si) without germanium (Ge). For example, the germanium (Ge) concentration of the buffer layer BFL may be 0 at% to 30 at%.

[0038] The main layer MAL may contain a relatively high concentration of germanium (Ge). For example, the germanium (Ge) concentration of the main layer MAL may be 30 at% to 70 at%. The germanium (Ge) concentration of the main layer MAL may increase in the third direction D3. For example, the main layer MAL adjacent to the buffer layer BFL may have a germanium (Ge) concentration of about 40 at% while the upper portion of the main layer MAL may have a germanium (Ge) concentration of about 60 at%.

[0039] Each of the buffer layer BFL and the main layer MAL may include an impurity (e.g., boron, gallium, or indium) that causes the first source / drain pattern SD1 to have a p-type. The impurity concentration of each of the buffer layer BFL and the main layer MAL may be 1E18 atoms / cm3 to 5E22 atoms / cm3. The impurity concentration of the main layer MAL may be higher than the impurity concentration of the buffer layer BFL.

[0040] The buffer layer BFL can protect the main layer MAL during a process of replacing the second semiconductor layer SAL with the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE, which will be described later. In other words, the buffer layer BFL can prevent an etching material used to remove the second semiconductor layer SAL from penetrating into and etching the main layer MAL.

[0041] Each of the second source / drain patterns SD2 may include silicon (Si). The second source / drain patterns SD2 may further include impurities (e.g., phosphorus, arsenic, or antimony) to cause the second source / drain patterns SD2 to have n-type conductivity. The impurity concentration of the second source / drain patterns SD2 may be 1E18 atoms / cm to 5E22 atoms / cm.

[0042] Gate electrodes GE may be provided extending in a first direction D1 across the first and second channel patterns CH1 and CH2. The gate electrodes GE may be arranged in a second direction D2 according to the first pitch. Each gate electrode GE may vertically overlap the first and second channel patterns CH1 and CH2.

[0043] The gate electrode GE may include a first inner electrode PO1 interposed between the active pattern (first active pattern AP1 or second active pattern AP2) and the first semiconductor pattern SP1, a second inner electrode PO2 interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third inner electrode PO3 interposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and an outer electrode PO4 on the third semiconductor pattern SP3.

[0044] 5D, a gate electrode GE may be provided on the top, bottom, and sidewalls of each of the first to third semiconductor patterns SP1, SP2, and SP3. Again, the transistor according to this embodiment may be a three-dimensional field effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds the channel.

[0045] A pair of gate spacers GS may be disposed on both side walls of the outer electrode PO4 of the gate electrode GE. The gate spacers GS may extend in a first direction D1 along the gate electrode GE. The top surfaces of the gate spacers GS may be higher than the top surface of the gate electrode GE. The top surfaces of the gate spacers GS may be coplanar with the top surface of a first interlayer insulating film 110, which will be described later. The gate spacers GS may include at least one of SiCN, SiCON, and SiN. As another example, the gate spacers GS may include a multi-layer structure made of at least two of SiCN, SiCON, and SiN.

[0046] A gate capping pattern GP may be provided on the gate electrode GE. The gate capping pattern GP may extend in a first direction D1 along the gate electrode GE. The gate capping pattern GP may include a material having etch selectivity with respect to the first and second interlayer insulating layers 110 and 120, which will be described later. Specifically, the gate capping pattern GP may include at least one of SiON, SiCN, SiCON, and SiN.

[0047] A gate insulating film GI may be interposed between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate insulating film GI may cover the top surface, bottom surface, and both sidewalls of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating film GI may cover the top surface of the isolation film ST below the gate electrode GE. The gate insulating film GI may be in contact with the top surface of the backside isolation structure BIST below the gate electrode GE (see FIG. 5D). The gate insulating film GI may be interposed between the first inner electrode PO1 and the first backside isolation structure BST1.

[0048] In one embodiment of the present invention, the gate insulating film GI may include a silicon oxide film, a silicon oxynitride film, and / or a high-k film. The high-k film may include a high-k material having a higher dielectric constant than a silicon oxide film. For example, the high-k material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0049] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be provided on the gate insulating film GI and may be adjacent to the first to third semiconductor patterns SP1, SP2, and SP3. The first metal pattern may include a work function metal that adjusts the threshold voltage of the transistor. A desired threshold voltage of the transistor may be achieved by adjusting the thickness and composition of the first metal pattern. For example, the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE may be formed of the first metal pattern, which is a work function metal.

[0050] The first metal pattern may include a metal nitride film. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). The first metal pattern may further include carbon (C). The first metal pattern may include multiple stacked work function metal films.

[0051] The second metal pattern may include a metal having a lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the outer electrode PO4 of the gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern.

[0052] Referring again to FIG. 5B, inner spacers IP may be provided on the NMOSFET region NR. Again, inner spacers IP may be provided on the second active pattern AP2. The inner spacers IP may be interposed between the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE and the second source / drain pattern SD2, respectively. The inner spacers IP may be in direct contact with the second source / drain pattern SD2. The first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE may be spaced apart from the second source / drain pattern SD2 by the inner spacers IP.

[0053] A first interlayer insulating film 110 may be provided on the substrate 100. The first interlayer insulating film 110 may cover sidewalls of the gate spacers GS and the first and second source / drain patterns SD1 and SD2. The top surface of the first interlayer insulating film 110 may be substantially coplanar with the top surfaces of the gate capping patterns GP and the gate spacers GS. A second interlayer insulating film 120 covering the gate capping patterns GP may be provided on the first interlayer insulating film 110. A third interlayer insulating film 130 may be provided on the second interlayer insulating film 120. For example, the first to third interlayer insulating films 110, 120, and 130 may include silicon oxide films.

[0054] An upper active contact AC may be provided to be electrically connected to the first and second source / drain patterns SD1 and SD2, respectively, through the first and second interlayer insulating layers 110 and 120. In a plan view, the upper active contact AC may have a bar shape extending in a first direction D1.

[0055] The upper active contact AC may be a self-aligned contact. In other words, the upper active contact AC may be formed in a self-aligned manner using the gate capping pattern GP and the gate spacer GS. For example, the upper active contact AC may cover at least a portion of the sidewall of the gate spacer GS.

[0056] The upper active contact AC may include a conductive pattern CP and a barrier pattern BM surrounding the conductive pattern CP. For example, the conductive pattern CP may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the sidewalls and bottom surface of the conductive pattern CP. The barrier pattern BM may include a metal layer / metal nitride layer. The metal layer may include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0057] A metal-semiconductor compound layer SC, e.g., a silicide layer, may be interposed between the upper active contact AC and the first source / drain pattern SD1 and between the upper active contact AC and the second source / drain pattern SD2. The upper active contact AC may be electrically connected to the source / drain patterns SD1 and SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0058] Referring to FIG. 5D, gate contacts GC may be provided, electrically connected to the gate electrodes GE through the second interlayer insulating film 120 and the gate capping pattern GP. The gate contacts GC may be in direct contact with the top surface of the outer electrode PO4. The gate contacts GC may include a gate contact pattern FM and a barrier pattern BM surrounding the gate contact pattern FM. For example, the gate contact pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the sidewalls and bottom surface of the gate contact pattern FM. The barrier pattern BM may include a metal layer / metal nitride layer. The metal layer may include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0059] 4, 5A, 5B, 5D, and 6, a pair of upper isolation structures DB may be provided on both sides of the single-height cell SHC, facing each other in the second direction D2. For example, the pair of upper isolation structures DB may extend in the first direction D1 parallel to the gate electrode GE. The upper isolation structures DB may penetrate the first channel pattern CH1 in the third direction D3.

[0060] More specifically, the upper isolation structure DB may include a first portion DB_1 facing a side surface of the first source / drain pattern SD1 and extending vertically along the third direction D3, a second portion DB_2 protruding horizontally from the first portion DB_1, and a third portion DB_3 connected to the first portion DB_1 and disposed within the substrate 100. The width of the first portion DB_1 may gradually decrease toward the bottom. The second portion DB_2 of the upper isolation structure DB may protrude toward a side surface of the first source / drain pattern SD1. The second portion DB_2 of the upper isolation structure DB may be separated from the first source / drain pattern SD1 by a remaining gate insulating film RGI. The remaining gate insulating film RGI may include the same or a similar material as the gate insulating film GI described above. The third portion DB_3 may be connected to a second rear isolation structure BST2 described below. For example, the third portion DB_3 may cover a portion of a sidewall of the second rear isolation structure BST2. The bottom end of the upper isolation structure DB (i.e., the bottom end of the third portion DB_3) may be located at a level lower than the bottom surface of the gate insulating film GI surrounding the first inner electrode PO1, and may be appropriately changed to a line located at a level higher than the bottom surface of the substrate 100.

[0061] A first back isolation structure BST1 may be provided under the gate electrode GE. The first back isolation structure BST1 may penetrate the substrate 100 and extend to a bottom surface of the gate insulating film GI surrounding the first inner electrode PO1. That is, the first back isolation structure BST1 may directly contact the bottom surface of the gate insulating film GI. The first back isolation structure BST1 may extend along a first direction D1 and fill the trench TR between the isolation films ST.

[0062] The first rear isolation structure BST1 can separate the rear active contacts BAC electrically connected to the source / drain patterns SD1 and SD2 into units within a transistor. That is, the first rear isolation structure BST1 can electrically isolate the rear active contacts BAC so that a drain voltage or a source voltage can be applied to the source / drain patterns SD1 and SD2 individually. In addition, the first rear isolation structure BST1 includes an insulating material and can isolate the substrate 100 along the second direction D2. As a result, the first rear isolation structure BST1 can prevent leakage current between the adjacent source / drain patterns SD1 and SD2 along the second direction D2 from flowing through the substrate 100.

[0063] A second rear isolation structure BST2 may be provided below the upper isolation structure DB and vertically overlap the upper isolation structure DB. The second rear isolation structure BST2 may be connected to the upper isolation structure DB along a third direction D3. The upper isolation structure DB and the second rear isolation structure BST2 may be integral and provided at a boundary portion of a single-height cell (SHC in FIG. 4). The second rear isolation structure BST2 may extend along the first direction D1.

[0064] The first and second backside isolation structures BST1 and BST2 may face each other. The widths of the first and second backside isolation structures BST1 and BST2 may gradually increase toward the bottom. The bottom surface of the first and second backside isolation structures BST1 and BST2 may be substantially coplanar. The bottom surfaces of the first and second backside isolation structures BST1 and BST2 may be located at a lower level than the bottom surface of the substrate 100.

[0065] The first and second backside isolation structures BST1 and BST2 may include an insulating material. For example, the first and second backside isolation structures BST1 and BST2 may each include a silicon-based insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride. For another example, the first and second backside isolation structures BST1 and BST2 may each include a metal-containing insulating material (e.g., AlO, TiO, AlN, etc.).

[0066] A power transmission network layer PDN may be provided below the substrate 100 and the isolation film ST. More specifically, the power transmission network layer PDN may be disposed below first and second backside isolation structures BST1 and BST2 and backside active contacts BAC, which will be described later. The power transmission network layer PDN may include first and second lower power wirings VPR1 and VPR2 that apply a power voltage (e.g., a power supply or ground voltage). The first and second lower power wirings VPR1 and VPR2 may extend parallel to each other in the second direction D2. The power transmission network layer PDN may further include a plurality of lower wirings (not shown) connected to the first and second lower power wirings VPR1 and VPR2.

[0067] In one embodiment of the present invention, the first lower power wiring VPR1 may be vertically overlapped with the PMOSFET region PR, and the second lower power wiring VPR2 may be vertically overlapped with the NMOSFET region NR. The first and second lower power wirings VPR1 and VPR2 may include at least one selected from the group consisting of copper, molybdenum, tungsten, and ruthenium.

[0068] Back active contacts BAC may be provided under the substrate 100. The back active contacts BAC may include a first back active contact BAC1 electrically connected to the first and second source / drain patterns SD1 and SD2 and a second back active contact BAC2 not electrically connected to the first and second source / drain patterns SD1 and SD2. For example, the first and second back active contacts BAC2 may be alternately arranged along the second direction D2.

[0069] The first back active contact BAC1 may be connected to the source / drain patterns SD1 and SD2 that are not connected to the upper active contact AC. The upper portion of the first back active contact BAC1 may be connected to the source / drain patterns SD1 and SD2 through the substrate 100, and the lower portion of the first back active contact BAC1 may have a relatively large width below the substrate 100. The lower portion of the first back active contact BAC1 may contact the sidewalls of the first and second back isolation structures BST1 and BST2.

[0070] The first back active contact BAC1 may have a conductive pillar shape that vertically and electrically connects the power transmission network layer PDN and the source / drain patterns SD1 and SD2. For example, the first back active contact BAC1 may have a conductive pillar shape that vertically and electrically connects the lower power wirings VPR1 and VPR2 and the source / drain patterns SD1 and SD2. A source voltage or a drain voltage may be applied to the source / drain patterns SD1 and SD2 through the first back active contact BAC1.

[0071] A metal-semiconductor compound layer (not shown) may be provided between the first back active contact BAC1 and the first and second source / drain patterns SD1 and SD2. For example, the metal-semiconductor compound layer may be a silicide layer. The first back active contact BAC1 may be electrically connected to the first source / drain pattern SD1 or the second source / drain pattern SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0072] The second back active contact BAC2 may be disposed under the source / drain patterns SD1 and SD2 connected to the upper active contact AC. The second back active contact BAC2 does not need to penetrate the substrate 100. The second back active contact BAC2 may contact sidewalls of the first and second back isolation structures BST1 and BST2.

[0073] The back active contact BAC may include a back conductive pattern BCP and a back barrier pattern BBM surrounding the back conductive pattern BCP. The back barrier pattern BBM may cover the sidewalls and top surface of the back conductive pattern BCP. The back barrier pattern BBM may contact the substrate 100, the liner layer LIN, and the sidewalls of the first and second back isolation structures BST1 and BST2. For example, the back barrier pattern BBM may include a metal layer / metal nitride layer. The metal layer may include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN). The bottom surface of the back conductive pattern BCP may be substantially coplanar with the bottom surfaces of the first and second back isolation structures BST1 and BST2. As an example, the back conductive pattern BCP may include at least one metal from among aluminum, copper, tungsten, molybdenum, and cobalt.

[0074] A lower insulating pattern 140 may be disposed under the isolation layer ST. A sidewall of the lower insulating pattern 140 may contact a sidewall of the back conductive pattern BCP. The lower insulating pattern 140 may include a silicon-based insulating material.

[0075] A liner layer LIN may be interposed between the bottom surface of the substrate 100 and the backside active contact BAC and under the isolation layer ST. For example, the liner layer LIN may include at least one of silicon nitride and silicon oxynitride.

[0076] 4 and 5A to 5D, a metal line MT and a via VI may be provided in the third interlayer insulating film 130. The via VI may be disposed under the metal line MT. The upper active contact AC and the metal line MT may be electrically connected through the via VI.

[0077] 7A through 17D illustrate a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, FIGS. 7A, 8A, 9A, 10A, 11A, 12A, 13A, 15A, 16A, and 17A are cross-sectional views corresponding to FIG. 5A, illustrating the sequential flow of the manufacturing method. FIGS. 9B, 10B, 11B, 12B, 13B, 15B, 16B, and 17B are cross-sectional views corresponding to FIG. 5B. FIGS. 9C, 10C, 12C, 13C, 15C, 16C, and 17C are cross-sectional views corresponding to FIG. 5C. FIGS. 7B, 8B, 11C, 12D, 13D, 15D, 16D, and 17D are cross-sectional views corresponding to FIG. 5D. FIG. 13 is a plan view showing a manufacturing method according to an embodiment of the present invention, and FIGS. 14A to 14D are cross-sectional views taken along lines AA', BB', CC', and DD' in FIG.

[0078] 7A and 7B, a substrate 100 including a PMOSFET region PR and an NMOSFET region NR may be provided. For example, the substrate 100 may be a silicon wafer.

[0079] A first semiconductor layer ACL and a second semiconductor layer SAL may be formed alternately stacked on the substrate 100. The first semiconductor layer ACL may include one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and the second semiconductor layer SAL may include another of silicon (Si), germanium (Ge), and silicon germanium (SiGe).

[0080] The second semiconductor layer SAL may include a material having an etching selectivity relative to the first semiconductor layer ACL. For example, the first semiconductor layer ACL may include silicon (Si), and the second semiconductor layer SAL may include silicon germanium (SiGe). The concentration of germanium (Ge) in each of the second semiconductor layers SAL may be 10 at% to 30 at%.

[0081] Mask patterns may be formed on the PMOSFET region PR and the NMOSFET region NR of the semiconductor substrate 100. The mask patterns may have a line shape or a bar shape extending in the second direction D2.

[0082] A patterning process may be performed using the mask pattern as an etching mask to form trenches TR defining first and second active patterns AP1 and AP2. The first active pattern AP1 may be formed on the PMOSFET region PR. The second active pattern AP2 may be formed on the NMOSFET region NR. In a plan view, the first and second active patterns AP1 and AP2 may have line shapes extending parallel to each other in the second direction D2. Through the patterning process, stack patterns STP may be formed on the first and second active patterns AP1 and AP2, respectively.

[0083] An isolation layer ST may be formed to fill the trench TR. Specifically, an insulating layer covering the first and second active patterns AP1 and AP2 and the stack pattern STP may be formed on the front surface of the semiconductor substrate 100. The insulating layer may be recessed until the stack pattern STP is exposed, thereby forming the isolation layer ST. The isolation layer ST may include an insulating material such as a silicon oxide layer.

[0084] 8A and 8B, sacrificial patterns PP may be formed across stack patterns STP on a semiconductor substrate 100. Each sacrificial pattern PP may be formed in a line shape or a bar shape extending in a first direction D1. The sacrificial patterns PP may be spaced apart from each other along a second direction D2.

[0085] Specifically, forming the sacrificial pattern PP may include forming a sacrificial layer on the front surface of the semiconductor substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer may include polysilicon.

[0086] Thereafter, a pair of gate spacers GS may be formed on both sidewalls of each of the sacrificial patterns PP, and the gate spacer film may include at least one of SiCN, SiCON, and SiN.

[0087] 9A to 9C, a first recess RS1 may be formed in the stack pattern STP on the first active pattern AP1. A second recess RS2 may be formed in the stack pattern STP on the second active pattern AP2. Referring to FIG. 9C, while the first and second recesses RS1 and RS2 are being formed, the isolation layers ST on both sides of each of the first and second active patterns AP1 and AP2 may be further recessed, and fence patterns FNP may be formed on each of the first and second active patterns AP1 and AP2. The fence patterns FNP may be part of the remaining gate spacers GS.

[0088] Specifically, the stack pattern STP on the first active pattern AP1 may be etched using the hard mask pattern MP and the gate spacer GS as an etching mask to form the first recess RS1. The first recess RS1 may be formed between a pair of sacrificial patterns PP. The second recess RS2 in the stack pattern STP on the second active pattern AP2 may be formed in the same manner as forming the first recess RS1.

[0089] During the process of forming the first and second recesses RS1 and RS2, a first channel pattern CH1 and a second channel pattern CH2 may be formed. For example, during the process of forming the first recess RS1, first to third semiconductor patterns SP1, SP2, and SP3 may be sequentially stacked from the first semiconductor layer (ACL in FIG. 8A), respectively, to form the first channel pattern CH1. During the process of forming the second recess RS2, first to third semiconductor patterns SP1, SP2, and SP3 may be sequentially stacked from the first semiconductor layer (ACL in FIG. 8A), respectively, to form the second channel pattern CH1.

[0090] 10A to 10C, first source / drain patterns SD1 may be formed in the first recesses RS1. Specifically, a first SEG process may be performed using the inner walls of the first recesses RS1 as a seed layer to form a buffer layer BFL. The buffer layer BFL may be grown using the first to third semiconductor patterns SP1, SP2, and SP3 exposed by the first recesses RS1 and the substrate 100 as seeds. For example, the first SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0091] The buffer layer BFL may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the semiconductor substrate 100. The buffer layer BFL may include a relatively low concentration of germanium (Ge). In another embodiment of the present invention, the buffer layer BFL may include only silicon (Si) without germanium (Ge). The concentration of germanium (Ge) in the buffer layer BFL may be 0 at% to 30 at%.

[0092] A second SEG process may be performed on the buffer layer BFL to form a main layer MAL. The main layer MAL may be formed to completely fill or substantially fill the first recess RS1. The main layer MAL may contain a relatively high concentration of germanium (Ge). For example, the concentration of germanium (Ge) in the main layer MAL may be 30 at% to 70 at%.

[0093] During the formation of the buffer layer BFL and the main layer MAL, impurities (e.g., boron, gallium, or indium) may be implanted in-situ to cause the first source / drain pattern SD1 to have a p-type. Alternatively, after the first source / drain pattern SD1 is formed, impurities may be implanted into the first source / drain pattern SD1.

[0094] Second source / drain patterns SD2 may be formed in the second recesses RS2. Specifically, the second source / drain patterns SD2 may be formed by performing a selective epitaxial growth (SEG) process using the inner walls of the second recesses RS2 as a seed layer. For example, the second source / drain patterns SD2 may include the same semiconductor element (e.g., Si) as the semiconductor substrate 100.

[0095] During the formation of the second source / drain pattern SD2, impurities (e.g., phosphorus, arsenic, or antimony) may be implanted in-situ to cause the second source / drain pattern SD2 to have n-type conductivity. Alternatively, after the second source / drain pattern SD2 is formed, impurities may be implanted into the second source / drain pattern SD2.

[0096] In one embodiment of the present invention, before forming the second source / drain pattern SD2, a portion of the second semiconductor layer SAL exposed through the second recess RS2 may be replaced with an insulating material to form inner spacers IP, so that the inner spacers IP may be formed between the second source / drain pattern SD2 and the second semiconductor layer SAL.

[0097] 11A to 11C, a first interlayer insulating layer 110 may be formed to cover the first and second source / drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacers GS. For example, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0098] The first interlayer insulating film 110 may be planarized until the top surface of the sacrificial pattern (PP in FIG. 10A) is exposed. Planarization of the first interlayer insulating film 110 may be performed using an etch-back or CMP (Chemical Mechanical Polishing) process. During the planarization process, the hard mask pattern MP may be entirely removed. As a result, the top surface of the first interlayer insulating film 110 may be coplanar with the top surfaces of the sacrificial pattern PP and the gate spacers GS.

[0099] The exposed sacrificial pattern (PP in FIG. 10A) may be selectively removed. Removing the sacrificial pattern PP may include wet etching using an etchant that selectively etches polysilicon. Referring to FIG. 11C, by removing the sacrificial pattern (PP in FIG. 10A), an outer region ORG that exposes the first and second channel patterns CH1 and CH2 may be formed.

[0100] 11A and 11B, the second semiconductor layer SAL exposed through the outer region ORG may be selectively removed to form the inner region IRG. Specifically, an etching process that selectively etches the second semiconductor layer SAL may be performed to remove only the second semiconductor layer SAL while leaving the first to third semiconductor patterns SP1, SP2, and SP3 intact. The etching process may have a high etching rate for silicon germanium having a relatively high germanium concentration. For example, the etching process may have a high etching rate for silicon germanium having a germanium concentration greater than 10 at%.

[0101] The etching process can completely remove the second semiconductor layer (SAL in FIG. 10A) on the PMOSFET region PR and the NMOSFET region NR. For example, the etching process can be performed by wet etching. The etchant used in the etching process can quickly remove the second semiconductor layer SAL, which has a relatively high germanium concentration. Meanwhile, the first source / drain pattern SD1 on the PMOSFET region PR can be protected during the etching process by the buffer layer BFL, which has a relatively low germanium concentration.

[0102] The second semiconductor layer SAL is removed to form first to third inner regions IRG1, IRG2, and IRG3. Specifically, the first inner region IRG1 may be formed between the active patterns AP1 and AP2 and the first semiconductor pattern SP1, the second inner region IRG2 may be formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and the third inner region IRG3 may be formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3.

[0103] Referring again to FIG. 11C, the second semiconductor layer SAL is selectively removed, so that only the first to third semiconductor patterns SP1, SP2, and SP3 stacked on each of the first and second active patterns AP1 and AP2 remain.

[0104] 12A to 12D, a gate insulating film GI may be conformally formed on the exposed first, second, and third semiconductor patterns SP1, SP2, and SP3. A gate electrode GE may be formed on the gate insulating film GI. The gate electrode GE may include first, second, and third inner electrodes PO1, PO2, and PO3 formed in the first, second, and third inner regions IRG1, IRG2, and IRG3, respectively, and an outer electrode PO4 formed on the inner electrodes PO1, PO2, and PO3. A gate capping pattern GP may be formed on the gate electrode GE.

[0105] Then, the upper isolation structure DB may be formed. Forming the upper isolation structure DB may include patterning the gate capping pattern GP, ​​the gate electrode GE, the first to third semiconductor patterns SP1, SP2, and SP3, and a portion of the substrate 100 to form a trench, removing the gate electrode GE in the trench through an etching process, and filling the trench with an insulating material. The trench may extend along a first direction D1. A portion of the substrate 100 may be removed during the trench formation process, and the gate electrode GE may be selectively removed through a wet etching process during the etching process. The insulating material may fill a space where the substrate 100 and the gate electrode GE have been removed.

[0106] According to an embodiment of the present invention, the bottom surface of the upper isolation structure DB may be located at a higher level than the bottom surface of the substrate 100 and may be formed to have a relatively smaller width and height than an isolation structure that penetrates the substrate 100. In other words, the depth of the trench (or recess) may be reduced during the process of forming the upper isolation structure DB. As a result, the insulating characteristics of the upper isolation structure DB may be improved during the process of filling the trench (or recess) with an insulating material. For example, a seam may not be formed in the upper isolation structure DB.

[0107] A second interlayer insulating film 120 may be formed on the first interlayer insulating film 110. For example, the second interlayer insulating film 120 may include a silicon oxide film.

[0108] An upper active contact AC may be formed through the second interlayer insulating film 120 and the first interlayer insulating film 110 to be electrically connected to at least one of the first and second source / drain patterns SD1 and SD2. Forming the active contact AC may include etching the first and second interlayer insulating films 110 and 120 to form trenches, depositing a barrier pattern BM in the trenches, and forming a conductive pattern CP on the barrier pattern BM. The barrier pattern BM may be conformally formed and may include a metal layer / metal nitride layer, and the conductive pattern CP may include a low-resistance metal.

[0109] A gate contact GC electrically connected to the gate electrode GE may be formed through the second interlayer insulating film 120 and the gate capping pattern GP. Forming the gate contact GC may include etching the second interlayer insulating film 120 and the gate capping pattern GP to form a trench, depositing a barrier pattern BM in the trench, and forming a gate contact pattern FM on the barrier pattern BM.

[0110] The substrate 100 described with reference to Figures 8A to 12D may be inverted. In the following description with reference to Figures 13A to 17D, the terms 'upper surface' and 'upper portion' may refer to the 'lower surface' and 'lower portion', respectively, in terms of the three-dimensional semiconductor device whose fabrication has been completed as described with reference to Figures 5A to 5D, and the terms 'lower surface' and 'lower portion' may refer to the 'upper surface' and 'upper portion', respectively, in terms of the three-dimensional semiconductor device whose fabrication has been completed as described with reference to Figures 5A to 5D.

[0111] 13A to 13D, the substrate 100 may be inverted to expose the top surface of the substrate 100. A portion of the exposed semiconductor substrate 100 may be removed. For example, a portion of the substrate 100 may be removed through a planarization process SAF, thereby reducing the thickness of the substrate 100. Furthermore, the top surface of the isolation layer ST may be exposed.

[0112] Thereafter, another etching process may be performed to selectively remove silicon (Si). Referring to Figure 13C, a portion of the first active pattern AP1 may be etched in the PMOSFET region PR to form a first residual active pattern RPAP1. Referring to Figure 13D, a portion of the second active pattern AP2 may be etched in the NMOSFET region NR to form a second residual active pattern RPAP2. Because the separate etching process selectively removes silicon, the device isolation layer ST may not be removed during the etching process.

[0113] 14 and 15A to 15D, a liner layer LIN may be conformally coated on an upper surface of the substrate 100. The liner layer LIN may conformally cover the substrate 100, the first and second residual active patterns RPAP1 and RPAP2, and the isolation layer ST. For example, the liner layer LIN may include at least one of silicon nitride and silicon oxynitride.

[0114] A mask pattern MK may then be formed on the liner layer LIN. The mask pattern MK may extend along a first direction D1 and be spaced apart from each other in a second direction D2. The substrate 100 may be patterned through the mask pattern MK to form first and second isolation trenches ITR1 and ITR2. The first and second isolation trenches ITR1 and ITR2 may extend along the first direction D1 and be spaced apart from each other in the second direction D2. During the patterning process, portions of the first and second residual active patterns RPAP1 and RPAP2 and an upper portion of the upper isolation structure DB may be removed. The first isolation trench ITR1 may vertically overlap the gate electrode GE to expose the gate insulating film GI surrounding the uppermost inner electrode PO1. The second isolation trench ITR2 may vertically overlap the upper isolation structure DB to expose an upper surface of the upper isolation structure DB.

[0115] 16A to 16D, first and second rear isolation structures BST1 and BST2 may be formed. The first and second rear isolation structures BST1 and BST2 may be formed by filling the first and second isolation trenches ITR1 and ITR2 between the mask patterns (MK in FIG. 15A) with an insulating material and removing the mask patterns (MK in FIG. 15A). The first rear isolation structure BST1 may extend along a first direction D1 and fill the trenches TR where the first and second residual active patterns RPAP1 and RPAP2 have been removed. The second rear isolation structure BST2 may extend along the first direction D1 and be connected to the upper isolation structure DB.

[0116] After forming the first and second back isolation structures BST1 and BST2, the mask pattern (MK in FIG. 15A) may be removed, thereby allowing the first and second back isolation structures BST1 and BST2 to protrude above the liner film LIN.

[0117] According to an embodiment of the present invention, the upper isolation structure DB and the second back isolation structure BST2 may be formed separately and connected to each other, and may have a relatively lower height than when an isolation structure is integrally formed to isolate a single-height cell (SHC in FIG. 4). In other words, the depth of the trench (or recess) may be reduced during the process of forming the upper isolation structure DB and the second back isolation structure BST2. This may improve the insulating characteristics of the upper isolation structure DB and the second back isolation structure BST2. For example, no seam may be formed in the upper isolation structure DB and the second back isolation structure BST2. This may improve the reliability of the semiconductor device.

[0118] Furthermore, the first and second backside isolation structures BST1 and BST2 can be formed simultaneously. The second backside isolation structure BST2 can be formed during the process of forming the first backside isolation structure BST1, which prevents leakage current from flowing between adjacent source / drain patterns, thereby improving the productivity of semiconductor devices.

[0119] Next, a lower insulating pattern 140 may be formed on the isolation layer ST. The lower insulating pattern 140 may extend in the second direction D2 and may be formed on regions other than the PMOSFET region PR and the NMOSFET region NR.

[0120] Thereafter, an anisotropic etching process may be performed to form a back contact hole BCH exposing the source / drain patterns SD1 and SD2. A portion of the substrate 100, a portion of the isolation layer ST, and the first and second residual active patterns RPAP1 and RPAP2 may be removed through the anisotropic etching process. The back contact hole BCH may expose the first source / drain pattern SD1 and the second source / drain pattern SD2. Specifically, the back contact hole BCH may expose the source / drain patterns SD1 and SD2 that are not connected to the upper active contact AC.

[0121] 17A to 17D, a back active contact BAC may be formed between the first and second back isolation structures BST1 and BST2. Forming the back active contact BAC may include depositing a back barrier pattern BBM covering sidewalls and top surfaces of the first and second back isolation structures BST1 and BST2 and inner walls of the back contact holes (BCH in FIG. 16A ), forming a back conductive pattern BCP on the back barrier pattern BBM to fill the back contact holes (BCH in FIG. 16A ) and between the first and second back isolation structures BST1 and BST2, and performing a planarization process to expose the top surfaces of the first and second back isolation structures BST1 and BST2, thereby isolating the first and second back active contacts BAC1 and BAC2 from each other. For example, the back barrier pattern BBM may include a metal layer / metal nitride layer, and the back conductive pattern BCP may include at least one metal selected from the group consisting of aluminum, copper, tungsten, molybdenum, and cobalt. The planarization process may partially remove the lower insulating pattern 140, the back active contact BAC, and the top surfaces of the first and second back isolation structures BST1 and BST2, and the top surfaces of the first and second back active contacts BAC1 and BAC2 and the first and second back isolation structures BST1 and BST2 may be substantially coplanar with each other.

[0122] Referring again to Figures 4 and 5A to 5D, a power transmission network layer PDN including first and second lower power wirings VPR1 and VPR2 can be formed below the back active contacts BAC and the first and second back isolation structures BST1 and BST2.

[0123] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0124] 100 boards SD1 1st source / drain pattern SD2 Second source / drain pattern DB upper separation structure BST1 1st back separation structure BST2 2nd back separation structure BAC Back Active Contact

Claims

1. A substrate; a source and drain pattern on the substrate; a channel pattern between the source and drain patterns, the channel pattern including a plurality of semiconductor patterns stacked and spaced apart from each other; a gate electrode between the plurality of semiconductor patterns; an upper isolation structure disposed horizontally spaced apart from the gate electrode and extending in a first direction; a first backside isolation structure extending through the substrate and disposed below the gate electrode; a second rear isolation structure that penetrates the substrate and vertically overlaps the upper isolation structure below the upper isolation structure; The first and second rear isolation structures extend in the first direction.

2. The semiconductor device of claim 1 , wherein bottom surfaces of the first and second backside isolation structures are substantially coplanar with each other.

3. a backside active contact electrically connected to one of the source and drain patterns through the substrate; 2. The semiconductor device of claim 1, wherein a portion of the backside active contact contacts sidewalls of the first and second backside isolation structures.

4. 4. The semiconductor device of claim 3, wherein a bottom surface of the backside active contact is substantially coplanar with bottom surfaces of the first and second backside isolation structures.

5. the rear active contact includes a rear conductive pattern and a rear barrier pattern covering the rear conductive pattern; The semiconductor device of claim 3 , wherein a portion of the backside barrier pattern contacts the sidewalls of the first and second backside isolation structures.

6. 4. The semiconductor device of claim 3, further comprising a power transmission network layer disposed under the first and second rear isolation structures and the rear active contacts and coupled to the rear active contacts.

7. 2. The semiconductor device of claim 1, wherein the upper isolation structure includes a first portion extending vertically, a second portion protruding from the first portion toward a side of the source and drain patterns, and a third portion connected to the first portion and disposed within the substrate.

8. The semiconductor device of claim 7 , wherein the third portion covers a portion of the sidewall of the second backside isolation structure.

9. a gate insulating layer interposed between the gate electrode and the plurality of semiconductor patterns, the gate electrode includes a first inner electrode, a second inner electrode, and a third inner electrode interposed between adjacent semiconductor patterns among the plurality of semiconductor patterns, and an outer electrode on a top semiconductor pattern, The semiconductor device of claim 1 , wherein the first rear isolation structure contacts a bottom surface of the gate insulating film surrounding the first inner electrode.

10. 2. The semiconductor device of claim 1, wherein the first and second backside isolation structures each include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

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