Wafer defect inspection system, wafer defect inspection device, and wafer defect inspection method

Abstract

To provide a device and method for preventing increase in device footprint and cost and detecting wafer edge chipping with high reliability.SOLUTION: A wafer defect inspection system includes: a processing part which chamfers an outer periphery of a wafer by contacting a rotating grinding wheel, and an inspection part which inspects an inspection object surface of the wafer. The inspection part includes: imaging means for imaging the inspection object surface of the wafer; and illumination means for emitting light onto the inspection object surface. The imaging means receives light such that the amount of non-specular reflection light, which is light other specular reflection light entering the inspection object surface and returns, is greater than the amount of specular reflection light.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a wafer defect inspection system, a wafer defect inspection device, and a wafer defect inspection method using the same, and more particularly to a wafer defect inspection system, a wafer defect inspection device, and a wafer defect inspection method using the same for inspecting chipping that occurs on an edge face of a semiconductor wafer. [Background technology]

[0002] Wafers of silicon or the like, which are used as materials for semiconductor devices, electronic components, etc., are sliced ​​from ingots using a slicing device such as an inner diameter blade or a wire saw, and then the outer periphery is chamfered to prevent cracks, chips, etc. Chamfering includes rough grinding, which involves grinding with a coarse grinding stone, and fine grinding, which involves grinding with a fine grinding stone.

[0003] Small scratches (hereinafter referred to as chipping) that occur on the periphery of a wafer during rough grinding can cause the wafer to crack or break in later processes. Therefore, chipping must be removed by precision grinding. However, even precision grinding cannot completely remove chipping from the periphery of a wafer, so it is necessary to inspect and evaluate the presence and size of chipping on the periphery of the wafer.

[0004] Chipping at the peripheral edge of the wafer can be detected by, for example, the device described in Patent Document 1. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-085295 Summary of the Invention [Problem to be solved by the invention]

[0006] Patent Document 1 describes an apparatus in which cameras are placed above and below a wafer, and an illumination means emits light from the side of the wafer onto the peripheral edge of the wafer to measure the shape of grinding marks in the notch formed on the peripheral edge of the wafer. The apparatus described in Patent Document 1 can detect chipping that occurs on the upper surface (upper chamfered surface) and lower surface (lower chamfered surface) of the peripheral edge of the wafer, but cannot detect chipping that occurs on the edge surface of the peripheral edge (hereinafter referred to as the edge).

[0007] One known method for detecting chipping on the edge of a wafer involves emitting parallel or coherent light, such as a laser beam, onto the edge of the wafer, capturing the light reflected by the chipping on the edge with a camera, and then analyzing the captured image. While this method can accurately measure the shape and size of chipping on the edge, it has problems such as an increased equipment footprint, higher equipment costs, and the time required for optical position adjustment of each component and image analysis processing.

[0008] The present disclosure has been made in consideration of such problems, and aims to provide a wafer defect inspection device and a wafer defect inspection method that do not increase the device footprint, facilitate position adjustment and image processing, suppress increases in device costs, and can detect chipping on the edge of a wafer with high reliability. [Means for solving the problem]

[0009] The wafer defect inspection system disclosed herein comprises a processing unit that chamfers the outer periphery of a wafer by contacting it with a rotating grinding wheel, and an inspection unit that inspects the inspection target surface of the wafer, wherein the inspection unit comprises an imaging means that images the inspection target surface of the wafer, and an illumination means that emits output light toward the inspection target surface, and the imaging means receives light such that the amount of non-specularly reflected light other than specularly reflected light among the light that is incident on and returns from the inspection target surface is greater than the amount of specularly reflected light. [Effects of the Invention]

[0010] The wafer defect inspection device and wafer defect inspection method disclosed herein do not increase the device footprint, facilitate position adjustment and image processing, suppress increases in device costs, and enable highly reliable detection of chipping on the wafer edge. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view schematically illustrating an embodiment of a wafer defect inspection system. [Figure 2] FIG. 2 is a side view that schematically illustrates an embodiment of a wafer defect inspection system. [Figure 3] FIG. 3 is an enlarged perspective view of the inspection unit shown in FIG. [Figure 4] FIG. 4 is a block diagram showing the system configuration of the inspection unit shown in FIG. [Figure 5] FIG. 5 is a partially enlarged side view showing the positional relationship between the imaging means and the wafer shown in FIG. [Figure 6A] FIG. 6A is a side view of the lighting means shown in FIG. [Figure 6B] FIG. 6B is a plan view of the lighting means shown in FIG. [Figure 7A] FIG. 7A is a diagram illustrating an image that can be obtained in principle by the inspection unit shown in FIG. [Figure 7B] FIG. 7B is a diagram illustrating an image that can be obtained in principle by the inspection unit shown in FIG. [Figure 8] FIG. 8 is a diagram showing the positional relationship between the imaging means and the wafer shown in FIG. 3 as viewed from the side. [Figure 9] FIG. 9 is a diagram showing the positional relationship of the imaging means, wafer, and illumination means shown in FIG. 3 in a plan view. [Figure 10] FIG. 10 is a flowchart illustrating an embodiment of a wafer defect inspection method. [Figure 11] FIG. 11 is a plan view of a modified example of the inspection unit shown in FIG. [Figure 12] FIG. 12 is a plan view of another modified example of the inspection unit shown in FIG. [Figure 13] FIG. 13 is a plan view of yet another modified example of the inspection unit shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of a wafer defect inspection system according to the present disclosure will be described with reference to the drawings. Note that the same reference numerals are used throughout the drawings to designate the same components. The embodiments shown in the drawings are merely examples and do not limit the present disclosure in any way. The embodiments and their variations described below can be combined in any manner, and such combinations are within the scope of the present disclosure.

[0013] 1 is a plan view schematically illustrating an embodiment of a wafer defect inspection system according to the present disclosure. Hereinafter, an example in which the wafer defect inspection system is a chamfering device will be described, but this is not limiting. The chamfering device 1 (wafer defect inspection system) includes a wafer supply / recovery unit 200, a processing unit 100, a transport unit 300, an inspection unit 10, and a controller 63.

[0014] The wafer supply / recovery section 200 removes wafers 2 to be chamfered from a wafer cassette 228 and returns the chamfered and inspected wafers 2 to the wafer cassette 228. In this example, four cassette tables 226 are arranged in parallel in the Y-axis direction, and one supply / recovery robot 220 is provided corresponding to each of the four wafer cassettes 228. The number of wafer cassettes 228 is not limited to four, and any number of wafer cassettes 228 may be provided. Furthermore, multiple supply / recovery robots may be provided, and the number of wafer cassettes 228 corresponding to each supply / recovery robot 220 can also be set arbitrarily.

[0015] A wafer cassette 228 is set on each cassette table 226. Each wafer cassette 228 stores one or more wafers 2 to be chamfered. The supply / recovery robot 220 removes the wafers 2 one by one from the wafer cassettes 228 set on each cassette table 226 and supplies them to the transport unit 300. The supply / recovery robot 220 also receives the wafers 2 that have been chamfered and inspected from the transport unit 300 and returns them to the wafer cassette 228. The supply / recovery robot 220 has a three-axis rotary transport arm 224 with a suction pad (not shown) on its upper surface. The transport arm 224 holds the wafer 2 by vacuum suctioning the backside of the wafer 2 with the suction pad. The transport arm 224 of the supply / recovery robot 220 is mounted on a slide block 222 that can slide along a guide rail 230. The slide block 222 is driven by a driving means (not shown) to move in the Y-axis direction, causing the transfer arm 224 to slide along the four cassette tables 226. The transfer arm 224 can move up and down as the slide block 222 moves in the Z-axis direction using a Z-axis movement shaft (not shown). In this way, the transfer arm 224 of the supply and recovery robot 220 can move and rotate in the horizontal and vertical directions while holding the wafer 2. The supply and recovery robot 220 supplies and recovers the wafer 2 to and from the transfer section 300 by combining these movements of the transfer arm 224.

[0016] The processing unit 100 chamfers the outer peripheral surface of the wafer 2 by bringing the outer peripheral portion of the wafer 2 into contact with a rotating, disk-shaped grinding wheel. The chamfering device 1 of this example has one processing unit 100, but two or more processing units may be arranged side by side in the X-axis direction. The processing unit 100 has a peripheral processing grinding wheel 21 for rough peripheral grinding, a peripheral precision grinding wheel 23 for fine peripheral grinding, and a wafer feed device 30 that moves the wafer 2 relative to these grinding wheels. The detailed configuration of the processing unit 100 will be described later.

[0017] The transport unit 300 has, for example, a fork-type handler 320 that receives the wafer 2 from the transport arm 224 of the supply / recovery robot 220 and transports it to or from the processing unit 100 or the inspection unit 10. The handler 320 can move the wafer 2 in the X-axis direction and the Y-axis direction and rotate it in a horizontal plane using a mechanism not shown. The handler 320 has a suction pad similar to that of the transport arm. The handler 320 can hold the wafer 2 by vacuum-sucking the backside of the wafer 2 using this suction pad.

[0018] The inspection unit 10 is a wafer defect inspection device that inspects the inspection target surface of the wafer 2. The inspection unit 10 has a measurement table 12 that holds and rotates the wafer 2, illumination means (15, 16) that emits light toward the inspection target surface of the wafer 2, and imaging means (17, 18, 19) that images the inspection target surface of the wafer 2. The detailed configuration of the inspection unit 10 will be described later.

[0019] The controller 63 controls the mechanical operations of the wafer supply / recovery unit 200, processing unit 100, transport unit 300, and inspection unit 10 of the chamfering apparatus 1, as well as the timing of wafer transfer between these units, and also controls the execution of a wafer defect inspection method, which will be described later. The controller 63 may be a computer having a processor (CPU), memory (volatile memory, non-volatile memory), an interface, etc. The processor reads a set of instructions for controlling each unit that is pre-recorded in the memory, and controls each unit of the chamfering apparatus 1.

[0020] 2 is a side view schematically illustrating an embodiment of a chamfering apparatus 1 according to the present disclosure. For simplicity of illustration, the wafer supply / recovery unit 200, the transport unit 300, and the controller 63 are omitted. The chamfering apparatus 1 includes an inspection unit 10 and a processing unit 100. The processing unit 100 includes a peripheral grinding device 20 and a wafer feeding device 30.

[0021] The wafer feed device 30 is a moving means for moving the wafer table 11 relative to the grinding wheel of the peripheral grinding device 20, which will be described below. The wafer feed device 30 has an X-axis base 40 mounted on a main body base 31, two X-axis guide rails 39, four X-axis linear guides 41, and an X-axis drive means 42 consisting of a ball screw and a servo motor, and an X-table 38 that is moved in the X direction in Fig. 1 by an X-axis drive means 42 consisting of two Y-axis guide rails 37, four Y-axis linear guides 36, and a ball screw and servo motor (not shown). The X-table 38 incorporates a Y-table 35 that is moved in the Y direction in Fig. 2 by an Y-axis drive means consisting of two Y-axis guide rails 37, four Y-axis linear guides 36, and a ball screw and servo motor (not shown).

[0022] A Z-table 33 is mounted on the upper portion of the Y-table 35. The Z-table 33 is guided by two Z-axis guide rails 34 and four Z-axis linear guides (not shown), and is moved in the Z direction in FIG. 2 by a Z-axis drive means 44 equipped with a ball screw and a stepping motor. A θ-axis motor 43 and a θ-spindle 45 are mounted on the Z-table 33. The θ-spindle 45 is provided with a wafer table 11 that holds and rotates the wafer 2. The wafer table 11 may be connected to a vacuum source (not shown) and hold the wafer 2 by vacuum suction.

[0023] A truing grindstone (hereinafter referred to as a truer) (not shown) for truing the grindstone used for chamfering may be provided, for example, on the underside of the wafer table 11. The wafer table 11 rotates in the θ direction around the rotation axis CW of the wafer table. In this way, the wafer feed device 30 rotates the wafer 2 and the truer in the θ direction in FIG. 2, and also moves the wafer table 11 relative to the grindstone of the outer periphery grinding device 20 described below in the X, Y, and Z directions.

[0024] The outer peripheral grinding device 20 has a grindstone for chamfering the outer periphery of the wafer 2, and a motor and spindle for rotating the grindstone. The grindstone includes an outer peripheral processing grindstone 21 on which multiple outer peripheral rough grinding grooves are formed. The outer peripheral processing grindstone 21 is rotated via an outer peripheral grindstone spindle 22, which is rotated about an axis CH by an outer peripheral grindstone motor (not shown). The grindstone also includes an outer peripheral fine grinding grindstone 23 on which multiple outer peripheral fine grinding grooves are formed. The outer peripheral fine grinding grindstone 23 is a chamfering grindstone that finishes grinding the outer periphery of the wafer 2 and is attached, for example, above the outer peripheral processing grindstone 21. The outer peripheral fine grinding grindstone 23 is rotated via an outer peripheral fine grinding spindle 24, which is rotated by an outer peripheral fine grinding motor 26. A rotary 25 is attached to the outer peripheral fine grinding spindle 24. As the rotary 25 rotates, the outer peripheral fine grinding grindstone 23 moves to a predetermined location. For example, when performing finish chamfering on a wafer, the outer periphery precision grinding wheel 23 moves to the processing position of the wafer 2 on the wafer table 11, and finish chamfering is performed on the wafer 2. When performing truing, the outer periphery precision grinding wheel 23 moves to the position of a truer (not shown) attached to, for example, the underside of the wafer table 11, and a groove for outer periphery precision grinding is formed on the surface of the outer periphery precision grinding wheel 23.

[0025] The inspection unit 10 is a wafer defect inspection device that inspects the inspection target surface of the wafer 2. Here, the inspection target surface refers to, for example, the edge (end face) of the wafer 2. The edge of the wafer 2 refers to, for example, the outer peripheral end face of the wafer 2 after finish chamfering. The inspection target surface does not have to include the notch portion (not shown) of the wafer 2. The inspection target surface may also include the surface or chamfered portion of the wafer 2. The inspection unit 10 includes illumination means (15, 16), imaging means (17, 18, 19), and a measurement table 12.

[0026] Fig. 3 is an enlarged perspective view of the inspection unit 10 shown in Fig. 2. The inspection unit 10 includes an upper and lower surface inspection device unit 50 for detecting chipping that has occurred on the upper and lower surfaces of the outer periphery of the wafer 2, and an edge inspection device unit 60 for detecting chipping that has occurred on the edge of the wafer 2.

[0027] The edge inspection device section 60 includes an illumination means 15, a measuring table 12 that holds and rotates the wafer 2, and an imaging means 17 disposed, for example, diagonally above and to the side of the measuring table 12. The illumination means 15 is disposed, for example, to the side of the measuring table 12. When the wafer 2 is disposed on the measuring table 12 as shown in FIG. 3, the illumination means 15 may be disposed to the side of the wafer 2. Note that the illumination means 15 may be disposed in a position other than the above, as long as it is disposed so as to satisfy the conditions for light received by the imaging means 17 described below. The edge inspection device section 60 may be configured integrally with the processing section 100 described in FIG. 2. In a modified example, the wafer table 11 may also serve as the measuring table 12.

[0028] The top and bottom surface inspection device section 50 includes a second imaging means 18 arranged on one side (the upper side in this example) of the wafer 2, a third imaging means 19 arranged on the other side (the lower side in this example) of the wafer 2, and an illumination means 16 provided on the side of the measurement table 12 (or the wafer 2). Here, the illumination means 15 and the illumination means 16 may be the same. The imaging means 17, the second imaging means 18, and the third imaging means 19 may be the same.

[0029] As described below, the illumination means 15 may be a panel-type LED illumination device in which multiple LEDs are arranged in a two-dimensional grid. The multiple LEDs, which are the light sources of the illumination means 15, irradiate the main surface of the wafer 2 with parallel light. The light emitted from the LEDs is diffused by a light diffusion means (described below), and the diffused light is irradiated onto the edge of the wafer 2. The light emitted from the LEDs may be light that corresponds to the material of the wafer 2. Here, "light that corresponds to the material of the wafer 2" refers to light having a wavelength specific to the material of the wafer 2, which has a high sensitivity to diffuse reflection depending on the material of the wafer 2. For example, when the material of the wafer 2 is silicon, SiC, GaN, GaAs, InP, GaP, etc., the sensitivity of diffused light to diffuse reflection due to chipping of the edge of the wafer 2 is wavelength-dependent. By experimentally determining the wavelength dependence of the sensitivity to diffuse reflection for each material of the wafer 2 and storing the obtained observation values ​​in the memory of the controller 63, the illumination means 15 can irradiate diffused light of a wavelength optimal for the material of the wafer to be inspected.

[0030] The imaging means 17 may be a CCD camera. For example, the CCD camera has a pixel count of approximately 310,000 (640 × 480 pixels). The imaging means 17 is configured to, for example, not receive, or to receive as little as possible, reflected light (e.g., specularly reflected light) from the light incident on and returning (or reflected) from the surface to be inspected. In other words, the imaging means 17 receives light such that the amount of non-specularly reflected light other than specularly reflected light from the light incident on and returning (or reflected) from the surface to be inspected is greater than the amount of specularly reflected light, as described below. Here, non-specularly reflected light refers to light emitted (diffused light) from the illumination means 15 that includes at least one of scattered light and diffusely reflected light from chipping that occurs on the edge of the surface to be inspected of the wafer 2. The imaging means 17 receives light so that the amount of non-specular reflected light, which includes at least one of scattered light and diffuse reflected light, is greater than the amount of specular reflected light, and captures an image of chipping that has occurred on the edge of the surface to be inspected.

[0031] The imaging means 17 is disposed in a position other than perpendicular to the wafer 2. Here, a position other than perpendicular to the wafer 2 refers to a position in which the central axis of the light-receiving surface of the imaging means 17 is not parallel to the normal to the main surface of the wafer 2. In FIG. 3, the imaging means 17 is shown disposed diagonally above the side of the measuring table 12, but this is not limitative and the imaging means 17 may be disposed on the side of the measuring table 12 or diagonally below the side of the measuring table 12. In other words, the imaging means 17 may be disposed at any position within the imaging range determined by the geometric relationship between the direction of the central axis of the light-receiving surface (imaging surface) of the imaging means 17, the direction perpendicular to the edge of the wafer 2 that is the surface to be inspected, the normal direction to the light-emitting surface of the illumination means 15, and the normal direction to the light-emitting surface of the illumination means 16, as will be described later. Here, the imaging range refers to the range in which specular reflection light of the light incident on and returning from the illumination means 15 at chipping that has occurred on the edge, which is the surface to be inspected of the wafer 2, can be received so that the amount of non-specular reflection light, which includes at least one of scattered light and diffuse reflection light, is greater than the amount of specular reflection light.

[0032] When light is irradiated onto the edge of the wafer 2, chipping results in specularly reflected light, scattered light, diffusely reflected light, and other types of light. Because the amount of specularly reflected light is small, detecting chipping of, for example, 100 μm or less requires the use of parallel light, such as laser light. In this disclosure, to detect chipping at the edge of the wafer 2 without using laser light, the geometrical positional relationship of the components described above is utilized to receive a greater amount of non-specularly reflected light, including at least one of scattered light and diffusely reflected light, than the amount of specularly reflected light. Furthermore, in this disclosure, the illumination means 15 emits diffused light toward the edge of the wafer 2 to further increase the amount of non-specularly reflected light, including at least one of scattered light and diffusely reflected light. According to this disclosure, the combined effect of the geometrical positional relationship of the components and the diffused light output enables chipping at the edge of the wafer 2 to be detected using a device with a simple structure and low cost. The detailed principles are described below.

[0033] From the viewpoints of preventing an increase in the footprint of the device and of safety and reliability, the placement of the second imaging means 18, third imaging means 19, and lighting means 16 that constitute the top and bottom surface inspection device section 50, and the imaging means 17 and lighting means 15 that constitute the edge inspection device section 60 must be considered. Specifically, the positions of the imaging means 17 and lighting means 15 must not be such that the outer periphery of the wafer 2 comes into contact with or collides with each means when the wafer 2 is carried onto and off the measurement table 12 by the handler 320 of the transport section 300.

[0034] Fig. 4 is a block diagram showing the system configuration of the inspection unit 10 shown in Fig. 3. The top and bottom surface inspection device unit 50 includes the lighting means 16, a lighting power supply 51 connected to the lighting means for supplying power to the lighting means 16, the second imaging means 18, the third imaging means 19, and an image processing controller 52 connected to the second imaging means 18 and the third imaging means 19 for controlling the operation of the second imaging means 18 and the third imaging means 19 and acquiring image data captured by them. The edge inspection device unit 60 includes the imaging means 17, a camera extension unit 61 connected to the imaging means 17 and the image processing controller 52 for controlling the operation of the imaging means 17 and acquiring image data captured by it, the lighting means 15, and a lighting power supply 62 connected to the lighting means 15 for supplying power to the lighting means 15. The illumination power supply 51, the illumination power supply 62, and the image processing controller 52 are connected to a controller 63 (e.g., a personal computer) that processes image data captured by the imaging means 17, the second imaging means 18, and the third imaging means 19. As described below, the controller 63 determines whether the level and amount of scratches obtained from the images captured by the imaging means 17, the second imaging means 18, and the third imaging means 19 exceed preset thresholds. The controller 63 also controls the power of the illumination power supplies (51, 62) and adjusts the brightness of the captured images. The image processing controller 52, the camera expansion unit 61, and the controller 63 constitute an image processing means 70 that processes images of chipping on the edge of the wafer 2, which is the surface to be inspected, captured by the imaging means (17, 18, 19). The illumination power supply 51, the image processing controller 52, the camera expansion unit 61, the illumination power supply 62, and the controller 63 may be housed in an electrical box 80 (FIG. 4). The controller 63 may be a remote computer, laptop, pad, smartphone, or the like connected via the Internet, wireless LAN, WiFi, or the like.

[0035] FIG. 5 is a partially enlarged side view showing the positional relationship between the imaging means 17 and the wafer 2 of the edge inspection device 60 shown in FIG. 3. In the side view, φ denotes the angle between the central axis 172 of the light-receiving surface 171 of the imaging means 17 and a thickness centerline 173 that is parallel to the main surface of the wafer 2 and passes through the center of the wafer 2 in the thickness direction. The R direction in FIG. 5 indicates the vertical direction of the field of view of the imaging means 17, and the Q direction indicates the horizontal direction of the field of view of the imaging means 17 that is perpendicular to the R direction. The P direction indicates the direction from the center of the main surface of the wafer 2 toward the outer periphery along the thickness centerline 173. The interval 174 indicates the field of view size in the R direction of the imaging means 17, which is tilted by an angle φ with respect to the thickness centerline 173. As shown in FIG. 5, the imaging means 17 is positioned so that the field of view includes the entire edge (end face) of the wafer 2. Here, the field of view refers to the range of the camera field of view of the imaging means 17 in the R direction and the Q direction. That is, the imaging means 17 is disposed so that the camera field of view of the imaging means 17 includes at least the entire edge of the wafer 2 in the R direction. Note that the imaging means 17 does not need to be disposed so that the field of view includes the entire edge (end) of the wafer 2, as long as it can receive light, such as non-specularly reflected light, that is incident on and returned from a chipping on the edge of the wafer 2, if such light is received. The light-receiving surface 171 of the imaging means 17 is oriented in a direction such that the amount of non-specularly reflected light, which includes at least one of scattered light and diffusely reflected light other than specularly reflected light, among the light that is incident on and returned from a chipping on the edge of the wafer 2 (the surface to be inspected), is greater than the amount of specularly reflected light. When the illumination means 15 emits diffused light onto a chipping on the edge of the wafer 2, the diffused light is diffusely reflected by the chipping and becomes scattered light, and / or is reflected at the boundary surface and becomes specularly reflected light, diffusely reflected light, etc. By adjusting the above-mentioned angle φ within a predetermined range, the light receiving surface 171 of the imaging means 17 can receive light such that the amount of non-specular reflected light, including at least one of scattered light and diffuse reflected light, is greater than the amount of specular reflected light, while avoiding specular reflected light.

[0036] FIG. 6A is a side view of the illumination means 15 shown in FIG. 3, and FIG. 6B is a plan view of the illumination means 15 shown in FIG. 3. The illumination means 15 includes a light source unit 151 having a plurality of light sources 153 arranged in a two-dimensional lattice pattern and a light diffusion unit that converts the light emitted by the light sources 153 into diffused light. The illumination means 15 may be a panel-type illumination device having a vertical length L and a horizontal width W. As described above, the light source 153 may be an LED light source capable of emitting light according to the material of the wafer 2. The light according to the material of the wafer 2 refers to light having a wavelength specific to the material of the wafer 2, which has a high sensitivity to diffuse reflection depending on the material of the wafer 2. The LED light source may be a blue LED that emits short-wavelength light with a wavelength of 570 nm or less. The LED light source may also emit light with a wavelength in the visible light range or ultraviolet light range. A blue LED is preferable as the light source 153 because it can stably emit light of a single wavelength. The blue LED may emit light with a wavelength of 450 nm to 495 nm. Using light in this wavelength range can improve measurement accuracy.

[0037] The light diffusion means may be a diffusion plate 152. As shown in FIG. 6A, the diffusion plate 152 converts incident light 154 from a light source 153 into diffused light 155 having a specific luminous intensity distribution angle. The diffusion plate 152 may be a polycarbonate or acrylic sheet containing fine particles therein or having randomly-sized lenses formed on its surface. The diffusion plate 152 preferably has high transmittance for the wavelength of light from the light source 153, which is selected depending on the material of the wafer 2. Note that the diffused light irradiated by the illumination means 15 is not random light in the strict sense.

[0038] The light sources 153 are arranged in a grid pattern, so that the light from the light sources 153 is used without waste, and high-brightness diffused light is obtained. The diffused light is scattered by chipping that occurs on the edge of the wafer 2 and becomes scattered light, and / or is reflected by the chipping to become specularly reflected light, diffusely reflected light, etc. The imaging means 17 can receive light such that the amount of non-specularly reflected light, including at least one of scattered light and diffusely reflected light, is greater than the amount of specularly reflected light, while avoiding specularly reflected light, due to the geometric positional relationship of the components described below.

[0039] 7A and 7B are diagrams illustrating images that can be obtained in principle by the edge inspection device 60 of the inspection unit 10 shown in FIG. 3. FIG. 7A illustrates an image of the edge of the wafer 2 captured by the imaging means 17 when no chipping occurs on the edge of the wafer 2. FIG. 7B illustrates an image of the edge of the wafer 2 captured by the imaging means 17 when chipping occurs on the edge of the wafer 2. In FIGS. 7A and 7B, reference numeral 2A denotes the main surface region of the wafer 2, reference numeral 3A denotes the edge region of the wafer 2, and reference numeral 4A denotes the spatial region below the wafer 2. As described with reference to FIG. 5, the angle φ between the central axis 172 of the light-receiving surface 171 of the imaging means 17 and the thickness center line 173 of the wafer 2 is set to a predetermined angle that avoids specular reflection. Therefore, if no chipping occurs on the edge of the wafer 2, the reflected light of the light emitted by the illumination means 15 does not enter the light-receiving surface 171. 7A, if no chipping occurs on the edge of the wafer 2, the main surface region 2A of the wafer 2, the edge region 3A of the wafer 2, and the spatial region 4A below the wafer 2 all appear dark. In other words, for the imaging means 17, the angle φ formed between the central axis 172 of the light-receiving surface 171 of the imaging means 17 and the thickness center line 173 of the wafer 2 is set so that if no chipping occurs on the edge of the wafer 2, specular reflected light is avoided and the main surface region 2A of the wafer 2, the edge region 3A of the wafer 2, and the spatial region 4A below the wafer 2 all appear dark.

[0040] On the other hand, as shown in FIG. 7B, if chipping occurs on the edge of the wafer 2, the main surface region 2A of the wafer 2 and the spatial region 4A below the wafer 2 appear dark, and only the chipped portion of the edge region 3A of the wafer 2 appears as a bright spot. The diffused light irradiated from the illumination means 15 includes scattered light scattered by the chipping on the edge, and / or specularly reflected light and diffusely reflected light reflected by the chipping. The imaging means 17 is set so that the angle φ between the central axis 172 of the light-receiving surface 171 of the imaging means 17 and the thickness center line 173 of the wafer 2 is a predetermined angle that avoids specularly reflected light. As a result, the light-receiving surface 171 can receive non-specularly reflected light, including at least one of scattered light and diffusely reflected light from the chipping, as a bright spot. In other words, the angle φ between the central axis 172 of the light-receiving surface 171 of the imaging means 17 and the thickness center line 173 of the wafer 2 is set so that, if chipping occurs at the edge of the wafer 2, the main surface region 2A of the wafer 2 and the spatial region 4A below the wafer 2 appear dark, avoiding specular reflection, and only the chipping portion in the edge region 3A of the wafer 2 appears as a bright spot. Note that, although lines dividing these regions are drawn in Figures 7A and 7B for convenience, in reality, each region, including the chipping portion, can be recognized as a difference in contrast (e.g., a difference in brightness). Furthermore, since it is sufficient to detect chipping (bright spots) at the edge of the wafer 2, the lines dividing each region do not necessarily need to be recognized and do not necessarily need to appear in the image.

[0041] 7B, the diffused light emitted by the illumination means 15 is light that can separate the contrast between the chipping portion and the non-chipping portion of the edge of the wafer 2. Furthermore, the diffused light emitted by the illumination means 15 only needs to be capable of detecting the approximate shape and size of the chipping. In other words, the imaging means 17 and the illumination means 15 are arranged to receive light such that the amount of non-specularly reflected light, including at least one of scattered light and diffusely reflected light, is greater than the amount of specularly reflected light, while avoiding specular reflection, so that the amount of light is sufficient to separate the contrast of the chipping portion in the captured image.

[0042] The image of the edge of the wafer 2 captured by the imaging means 17 is processed by the image processing means 70 described above, the approximate shape and size of chipping on the edge of the wafer 2 is detected, and the degree of chipping (i.e., whether or not the damage is within an acceptable range) is determined. In other words, the imaging means 17 can capture light that is easy to process in the image processing means 70 by using the geometric positional relationship of the above-mentioned components and diffused light.

[0043] 8 is a diagram showing the positional relationship between the imaging means 17 and the wafer 2 shown in FIG. 3 in a side view. In this embodiment, the angle formed between the central axis 172 of the light receiving surface 171 of the imaging means 17 and a line parallel to the main surface of the wafer 2 is 0° to 60° in a side view. Here, the line parallel to the main surface of the wafer 2 may be the thickness center line 173 described in FIG. 5. The angle is synonymous with the angle φ described in FIG. 5. In this embodiment, the angle φ is preferably 5° to 40°, more preferably 10° to 30°, and most preferably 15°.

[0044] FIG. 9 is a plan view showing the relative positions of the imaging unit 17, wafer 2, illumination unit 15, and illumination unit 16 of the top and bottom surface inspection device unit 50 shown in FIG. 3 . In this embodiment, the angle ω between the central axis 172 of the light-receiving surface 171 of the imaging unit 17 and the normal 156 of the light-emitting surface of the illumination unit 15 is 15° to 45° in plan view. In this embodiment, the angle ω is preferably 20° to 40°, more preferably 25° to 35°, and most preferably 30°. In this embodiment, the angle δ between the central axis 172 of the light-receiving surface 171 of the imaging unit 17 and the normal 161 of the light-emitting surface of the illumination unit 16 of the top and bottom surface inspection device unit 50 may be 10° to 90° in plan view. The angle δ is preferably 20° to 80°, more preferably 30° to 70°, and most preferably 60°. By arranging the imaging means 17 and the illumination means 15 in the geometrical positional relationship shown in Figures 8 and 9, the imaging means 17 can receive and capture an image of a sufficient amount of non-specular reflected light, including at least one of scattered light and diffuse reflected light, while avoiding specular reflected light due to chipping at the edge of the wafer 2, making it easy to process the image.

[0045] 10 is a flowchart showing an embodiment of a wafer defect inspection method for inspecting the inspection target surface of a wafer. The wafer defect inspection method for inspecting the inspection target surface of a wafer using a wafer defect inspection device having an imaging means and an illumination means according to this embodiment includes emitting light from the illumination means to the inspection target surface and imaging the inspection target surface, wherein the imaging step is characterized by receiving light such that the amount of non-specularly reflected light other than specularly reflected light among the light incident on the inspection target surface and returning from it is greater than the amount of specularly reflected light. A specific flow of the wafer defect inspection method according to this embodiment will be described below.

[0046] First, the wafer 2 is carried into the inspection section 10 by the handler 320 of the transport section 300, placed on the measurement table 12, and held by vacuum suction, after which the measurement table 12 starts to rotate. At this time, the illumination power supply 62 is turned on by the controller 63, and the illumination means 15 is illuminated.

[0047] In step S101, an image of the edge of the rotating wafer 2 is acquired by the imaging means 17. In step S101, the controller 63 issues a command to image the edge of the wafer 2, and the command is transmitted to the imaging means 17 via the image processing controller 52 and the camera expansion unit 61. In response to the command from the controller 63, the imaging means 17 images the edge of the wafer 2, for example, once every five seconds. The imaging timing may be changed according to the rotation speed of the measuring table 12. In other words, the imaging timing may be set so that the entire edge of the wafer 2 is imaged while the measuring table 12 makes one revolution. In this step, images of one revolution of the outer periphery of the wafer 2 may be acquired. The acquired images may be stored in a memory or the like within the controller 63, and may be collectively image-processed by the controller 63 in a subsequent step.

[0048] Next, in steps S102 and S103, an area to be inspected is extracted from the acquired image, and the level and amount of the area are calculated. Here, the level and amount refer to the level and amount of chipping damage that has occurred on the edge. This process is divided into a pre-processing step in step S102 and a detection step in step S103. In the pre-processing step in step S102, chipping areas are identified in the image captured by the imaging means 17, and their contours and contrast are enhanced.

[0049] In the detection process of step S103, edge extraction processing is performed on the pre-processed image. The edge extraction processing makes it possible to clearly detect the edge of the chipped area. At the same time as the edge extraction, the level and amount of damage to the chipped area are calculated.

[0050] Next, in step S104, it is determined whether the level and amount of chipping damage calculated in step S103 exceed a predetermined threshold. Here, the predetermined threshold refers to a value that the user can appropriately determine based on the wafer material, application, price, number of post-processing steps, etc. For example, if the user requires high accuracy in chamfering the wafer edge, the threshold can be set to a relatively small value. By doing so, even if the chipping on the edge of the wafer 2 is extremely small, the wafer 2 will be selected as a candidate for sorting if the level and amount of damage detected as a result of image processing exceed the set small threshold. Conversely, if the user does not require such high accuracy in chamfering the wafer edge, the threshold can be set to a relatively large value. By doing so, even if the chipping on the edge of the wafer 2 is somewhat large, the wafer 2 will not be selected as a candidate for sorting if it does not exceed the set large threshold.

[0051] If the result of the determination is that the calculated chipping damage level and damage amount exceed the threshold (step S104: NO), the wafer 2 is classified as a rejected product (step S105), and the inspection of the wafer 2 ends.

[0052] On the other hand, if the result of the determination is that the threshold value is not exceeded (step S104: YES), the inspection of the wafer 2 is completed. That is, the wafer 2 is determined to have passed the inspection.

[0053] The above steps S101 to S105 may be executed by a computer program that can be read from a memory (not shown) of the controller 63. In this case, information processing by the computer program is specifically realized using hardware resources (a CPU, memory, HDD, various interfaces, etc., not shown, of the controller 63).

[0054] FIG. 11 is a plan view of a modified example of the inspection unit 10 shown in FIG. 3. In the modified example, the same components as those in the embodiment are given the same reference numerals, and their description will be omitted. The inspection unit 10 according to the modified example further includes a mirror 90 that reflects the light emitted by the illumination means 15 toward the inspection target surface of the wafer 2. Here, the mirror 90 may be a flat mirror that can reflect the diffused light emitted by the illumination means 15 toward the edge of the wafer 2. In the example shown in FIG. 11, the mirror 90 is disposed to the side of the imaging means 17, but the position of the mirror 90 is not limited to this and may be any position that does not obstruct the field of view of the imaging means 17. The angle between the normal to the reflective surface of the mirror 90 and the central axis 172 of the light-receiving surface 171 of the imaging means 17, and the angle between the normal to the reflective surface of the mirror 90 and the normal 156 of the light-emitting surface of the illumination means 15 are set so that the diffused light emitted by the illumination means 15 can be reflected by the edge of the wafer 2 and the reflected light can generate non-specular reflected light including at least one of scattered light and diffusely reflected light at chipping. In other words, the mirror 90 is positioned so that the angle ω between the optical path 91 of the reflected light, which is the light incident from the illumination means 15 and reflected by the mirror 90, and the central axis 172 of the light-receiving surface 171 of the imaging means 17, is within the above-mentioned angle range of ω. According to this example, the use of the mirror 90 allows the illumination means 15 to be positioned close to the wafer 2. As a result, the footprint of the inspection unit 10 and the entire chamfering apparatus 1 can be prevented from increasing.

[0055] FIG. 12 is a plan view of another modified example of the inspection unit 10 shown in FIG. 3. In this modified example, the same components as those in the embodiment are designated by the same reference numerals, and their description will be omitted. The inspection unit 10 according to this modified example further includes a mirror 90 that reflects the light emitted by the illumination unit 16 toward the inspection target surface of the wafer 2. Here, the mirror 90 may be a flat mirror that can reflect the diffused light emitted by the illumination unit 16 toward the edge of the wafer 2. The inspection unit 10 according to this example differs in configuration from the modified example shown in FIG. 11 in that it does not include the illumination unit 15. That is, the illumination unit 16 serves as illumination for both the imaging units (18, 19) and the imaging unit 17. In this example, the angle δ formed between the normal 161 of the light-emitting surface of the illumination unit 16 and the central axis 172 of the light-receiving surface 171 of the imaging unit 17 is set to be larger than the angle δ in the modified example shown in FIG. 11. Note that the value of the angle δ in this example is within the above-described angle range of δ. In this example, the mirror 90 reflects the diffused light emitted from the illumination means 16 onto the edge of the wafer 2, and the angle between the normal to the reflective surface of the mirror 90 and the central axis 172 of the light-receiving surface 171 of the imaging means 17, and the angle between the normal to the reflective surface of the mirror 90 and the normal to the light-emitting surface 161 of the illumination means 16 are set so that the mirror 90 reflects the diffused light emitted from the illumination means 16 onto the edge of the wafer 2, and the reflected light generates non-specular reflected light including at least one of scattered light and diffusely reflected light at the chipping. In other words, the mirror 90 is positioned so that the angle ω between the optical path 91 of the reflected light, which is the light incident from the illumination means 16 and reflected by the mirror 90, and the central axis 172 of the light-receiving surface 171 of the imaging means 17, is within the above-mentioned ω angle range. According to this example, the use of the mirror 90 makes it possible to omit the illumination means 15. As a result, it is possible to suppress an increase in the cost of the device and further suppress an increase in the footprint of the inspection unit 10 and the entire chamfering device 1.

[0056] FIG. 13 is a plan view of yet another modification of the inspection unit 10 shown in FIG. 3. In this modification, the same components as those in the embodiment are designated by the same reference numerals, and their description will be omitted. The inspection unit 10 according to this modification further includes a concave mirror 92 that reflects non-specularly reflected light, including at least one of scattered light and diffusely reflected light scattered on the inspection target surface of the wafer 2, toward the light-receiving surface 171 of the imaging means 17. Here, the concave mirror refers to a mirror that reflects and focuses non-specularly reflected light, including at least one of scattered light and diffusely reflected light from the edge of the wafer 2. Examples of concave mirrors include a concave spherical mirror and a parabolic mirror. The concave mirror 92 may be located at the light-receiving surface 171 of the imaging means 17 in the embodiment (referred to as a first viewpoint). In this example, the imaging means 17 may be located at a position (referred to as a second viewpoint) where it can receive reflected light from the concave mirror 92 located at the first viewpoint. In this example, the second viewpoint may be above or below the wafer 2. The concave mirror 92 is used in order to suppress the loss of light intensity when the light receiving surface 171 of the imaging means 17 at the second viewpoint receives non-specularly reflected light, including at least one of scattered light and diffusely reflected light from the chipping reflected at the first viewpoint, to an extent that contrast separation is possible by image processing. According to this example, the imaging means 17 can be disposed above or below the wafer, which increases the degree of freedom in the placement of the imaging means 17 and further suppresses an increase in the footprint of the inspection unit 10 and, in turn, the entire chamfering device 1.

[0057] According to the present disclosure, the wafer defect inspection device provided in the chamfering device comprises an imaging means for imaging the inspection target surface of the wafer and an illumination means for emitting emitted light toward the inspection target surface, and the imaging means is configured to receive light so that the amount of non-specularly reflected light other than specularly reflected light among the light that is incident on the inspection target surface and returned is greater than the amount of specularly reflected light.This does not increase the device footprint, makes position adjustment and image processing easy, suppresses increases in device costs, and enables chipping of the wafer edge to be detected with high reliability.

[0058] The above-described embodiments and modifications of the present disclosure are merely examples of the present disclosure and are not intended to limit the scope of the present disclosure. It will be appreciated by those skilled in the art that various modifications and changes can be made without departing from the spirit and scope of the present disclosure, and that these modifications and changes are also included in the scope of the present disclosure. [Explanation of symbols]

[0059] 1 chamfering device, 2 wafer, 2A main surface area, 3A edge area, 4A lower space area, 10 inspection unit, 11 wafer table, 12 measurement table, 15 lighting means, 16 lighting means, 17 imaging means, 18 second imaging means, 19 third imaging means, 20 outer peripheral grinding device, 21 outer peripheral processing grindstone, 22 outer peripheral grindstone spindle, 23 outer peripheral precision grinding grindstone, 24 outer peripheral precision grinding spindle, 25 rotary, 26 outer peripheral precision grinding motor, 30 wafer feed device, 31 main body base, 33 Z table, 34 Z axis guide rail, 35 Y table, 36 Y axis linear guide, 37 Y axis guide rail, 38 X table, 39 X axis guide rail, 40 X axis base, 41 X axis linear guide, 42 X axis drive means, 43 θ axis motor, 44 Z axis drive means, 50 upper and lower surface inspection device unit, 51 Illumination power supply, 52 image processing controller, 60 edge inspection device section, 61 camera expansion unit, 62 illumination power supply, 63 controller, 70 image processing means, 80 electrical box, 90 mirror, 91 optical path, 92 concave mirror, 100 processing section, 151 light source section, 152 diffusion plate, 153 light source, 154 incident light, 155 diffused light, 156 normal, 161 normal, 171 light receiving surface, 172 central axis, 173 thickness center line, 174 spacing, 200 wafer supply and recovery section, 220 supply and recovery robot, 222 slide block, 224 transport arm, 226 cassette table, 228 wafer cassette, 230 guide rail, 300 transport section, 320 handler

Claims

1. The wafer processing apparatus includes a processing unit that chamfers the outer periphery of the wafer by contacting a rotating grindstone with the outer periphery of the wafer, and an inspection unit that inspects the inspection target surface of the wafer, The inspection unit an imaging means for imaging the inspection target surface of the wafer; an illumination means for emitting an emission light to the inspection target surface; Equipped with A wafer defect inspection system characterized in that the imaging means receives light so that the amount of non-specularly reflected light other than specularly reflected light among the light incident on the inspection target surface and returning is greater than the amount of specularly reflected light.

2. The wafer defect inspection system according to claim 1 , wherein the surface to be inspected is an edge surface of the wafer.

3. the illumination means is disposed to the side of the wafer; 3. The wafer defect inspection system according to claim 2, wherein the imaging means is disposed in a position other than perpendicular to the wafer.

4. 4. The wafer defect inspection system according to claim 3, wherein said imaging means is disposed so as to include the entire edge surface of said wafer within a field of view.

5. The wafer defect inspection system of claim 3 , further comprising a mirror that reflects the emitted light toward the inspection target surface of the wafer.

6. The wafer defect inspection system according to claim 1 , wherein the non-specular reflected light includes at least one of scattered light and diffuse reflected light.

7. an imaging means for imaging the inspection target surface of the wafer; an illumination means for emitting an emission light to the inspection target surface, A wafer defect inspection device characterized in that the imaging means receives light so that the amount of non-specularly reflected light other than specularly reflected light among the light incident on the inspection target surface and returning is greater than the amount of specularly reflected light.

8. A wafer defect inspection method for inspecting an inspection target surface of a wafer using a wafer defect inspection device having an imaging means and an illumination means, comprising: emitting an emission light from the illumination means to the inspection target surface; imaging the inspection target surface; Equipped with A wafer defect inspection method characterized in that, in the imaging, light is received so that the amount of non-specularly reflected light other than specularly reflected light among the light incident on the inspection target surface and returning is greater than the amount of specularly reflected light.

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