Semiconductor device and manufacturing method thereof

Abstract

To provide a miniaturized semiconductor device.SOLUTION: A semiconductor device 100 includes a P-type first channel semiconductor layer 21A provided on a substrate 10, a pair of N-type first source / drain semiconductor layers 22A and 23A sandwiching a first channel semiconductor layer, a first gate electrode 25A sandwiching a first gate insulating film 24A between the pair of first source / drain semiconductor layers and the first channel semiconductor layer, a P-type second channel semiconductor layer 21B provided above the first channel semiconductor layer and away from the first channel semiconductor layer, a pair of N-type second source / drain semiconductor layers 22B and 23B electrically connected to the pair of first source / drain semiconductor layers, respectively, and sandwiching the second channel semiconductor layer therebetween, a first transistor Tr1 having a second gate electrode 25B electrically connected to the first gate electrode with a second gate insulating film interposed therebetween between a pair of second source / drain semiconductor layers and the second channel semiconductor layer.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A known example is a complementary field effect transistor (CFET) that stacks a P-channel transistor and an N-channel transistor, either a FinFET (Field Effect Transistor) or a nanosheet transistor. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Kevin Zhang, Semiconductor Industry: Present & Future, 2024 IEEE International Solid-State Circuits Conference digest of technical papers, pp. 10-15, (2024). Summary of the Invention [Problem to be solved by the invention]

[0004] A CFET consists of a P-channel transistor and an N-channel transistor stacked together, with their gate electrodes electrically connected. Therefore, when using a P-channel or N-channel transistor alone, the unused transistor is not formed or is not electrically operated, which increases the chip size.

[0005] An object of the present disclosure is to provide a semiconductor device that can be miniaturized and a method for manufacturing the same. [Means for solving the problem]

[0006] an embodiment of the present disclosure is a semiconductor device including a first transistor including: a substrate; a first channel semiconductor layer provided on the substrate and having a first conductivity type; a pair of first source / drain semiconductor layers provided on the substrate and sandwiching the first channel semiconductor layer and having a second conductivity type different from the first conductivity type; a first gate electrode sandwiching a first gate insulating film between the pair of first source / drain semiconductor layers and the first channel semiconductor layer; a second channel semiconductor layer provided above the first channel semiconductor layer and spaced apart from the first channel semiconductor layer and having the first conductivity type; a pair of second source / drain semiconductor layers provided on the pair of first source / drain semiconductor layers and electrically connected to the pair of first source / drain semiconductor layers, respectively, sandwiching the second channel semiconductor layer and having the second conductivity type; and a second gate electrode electrically connected to the first gate electrode between the pair of second source / drain semiconductor layers and sandwiching a second gate insulating film between the second channel semiconductor layer and the second channel semiconductor layer.

[0007] An embodiment of the present disclosure relates to a first transistor including: a first channel semiconductor layer provided on a substrate and having a first conductivity type; a pair of first source / drain semiconductor layers provided on the substrate and sandwiching the first channel semiconductor layer and having a second conductivity type different from the first conductivity type; a first gate electrode sandwiching a first gate insulating film between the pair of first source / drain semiconductor layers and the first channel semiconductor layer; a second channel semiconductor layer provided above the first channel semiconductor layer and spaced apart from the first channel semiconductor layer and having the first conductivity type; a pair of second source / drain semiconductor layers provided on the pair of first source / drain semiconductor layers and electrically connected to the pair of first source / drain semiconductor layers, respectively, sandwiching the second channel semiconductor layer and having the second conductivity type; and a second gate electrode sandwiching a second gate insulating film between the pair of second source / drain semiconductor layers and electrically connected to the first gate electrode; a third channel semiconductor layer provided on the substrate and having the second conductivity type; and a pair of second channel semiconductor layers provided on the substrate and sandwiching the third channel semiconductor layer and having the first conductivity type. a third transistor including: a third source / drain semiconductor layer; and a third gate electrode sandwiching a third gate insulating film between the pair of third source / drain semiconductor layers and the third channel semiconductor layer; a fourth channel semiconductor layer having the first conductivity type and provided above the third channel semiconductor layer and spaced apart from the third channel semiconductor layer; a pair of fourth source / drain semiconductor layers having the second conductivity type and provided above the pair of third source / drain semiconductor layers and spaced apart from the pair of third source / drain semiconductor layers and sandwiching the fourth channel semiconductor layer; and a fourth gate electrode electrically connected to the third gate electrode with the fourth channel semiconductor layer sandwiching a fourth gate insulating film between the pair of fourth source / drain semiconductor layers, the method comprising: forming a first semiconductor layer on the substrate; a second semiconductor layer above the first semiconductor layer and spaced apart from the first semiconductor layer; a third semiconductor layer on the substrate; and a fourth semiconductor layer above the third semiconductor layer and spaced apart from the third semiconductor layer;and simultaneously forming the pair of first source-drain semiconductor layers sandwiching the first semiconductor layer, the pair of second source-drain semiconductor layers sandwiching the second semiconductor layer, and the pair of fourth source-drain semiconductor layers sandwiching the fourth semiconductor layer.

[0008] An embodiment of the present disclosure relates to a first transistor including: a first channel semiconductor layer provided on a substrate and having a first conductivity type; a pair of first source / drain semiconductor layers provided on the substrate and sandwiching the first channel semiconductor layer and having a second conductivity type different from the first conductivity type; a first gate electrode sandwiching a first gate insulating film between the pair of first source / drain semiconductor layers and the first channel semiconductor layer; a second channel semiconductor layer provided above the first channel semiconductor layer and spaced apart from the first channel semiconductor layer and having the first conductivity type; a pair of second source / drain semiconductor layers provided on the pair of first source / drain semiconductor layers and electrically connected to the pair of first source / drain semiconductor layers, respectively, sandwiching the second channel semiconductor layer and having the second conductivity type; and a second gate electrode sandwiching a second gate insulating film between the pair of second source / drain semiconductor layers and electrically connected to the first gate electrode; a third channel semiconductor layer provided on the substrate and having the first conductivity type; a fourth channel semiconductor layer having the second conductivity type and provided above the third channel semiconductor layer and at a distance from the third channel semiconductor layer, a pair of fourth source / drain semiconductor layers having the first conductivity type and provided above the pair of third source / drain semiconductor layers and at a distance from the pair of third source / drain semiconductor layers and sandwiching the fourth channel semiconductor layer; and a fourth gate electrode electrically connected to the third gate electrode with the fourth channel semiconductor layer sandwiching a fourth gate insulating film between the pair of fourth source / drain semiconductor layers, the method comprising the steps of: forming a first semiconductor layer on the substrate; a second semiconductor layer above the first semiconductor layer and at a distance from the first semiconductor layer; a third semiconductor layer on the substrate; and a fourth semiconductor layer above the third semiconductor layer and at a distance from the third semiconductor layer;The method for manufacturing a semiconductor device includes: simultaneously forming the pair of second source / drain semiconductor layers sandwiching the second semiconductor layer and the pair of third source / drain semiconductor layers sandwiching the third semiconductor layer; and forming the pair of fourth source / drain semiconductor layers sandwiching the fourth semiconductor layer. [Effects of the Invention]

[0009] The disclosed technology allows for miniaturization. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a perspective view of the second region in the first embodiment. [Figure 3] 3A and 3B are cross-sectional views of the second region in the first embodiment. [Figure 4] 4(A) and 4(B) are cross-sectional views of the first region in the first embodiment. [Figure 5] 5(A) and 5(B) are cross-sectional views of the third region in the first embodiment. [Figure 6] 6A and 6B are cross-sectional views of the third region in the second comparative embodiment. [Figure 7] 7A to 7F are cross-sectional views showing a method 1 for manufacturing a semiconductor device according to the first embodiment. [Figure 8] 8(A) to 8(F) are cross-sectional views showing a manufacturing method 1 for a semiconductor device according to the first embodiment. [Figure 9] 9A to 9F are cross-sectional views showing a manufacturing method 1 for a semiconductor device according to the first embodiment. [Figure 10] 10(A) to 10(F) are cross-sectional views showing a manufacturing method 1 of a semiconductor device according to the first embodiment. [Figure 11] 11(A) to 11(F) are cross-sectional views showing a manufacturing method 1 of a semiconductor device according to the first embodiment. [Figure 12] 12(A) to 12(F) are cross-sectional views showing a manufacturing method 1 of a semiconductor device according to the first embodiment. [Figure 13] 13(A) to 13(F) are cross-sectional views showing a manufacturing method 1 for a semiconductor device according to the first embodiment. [Figure 14] 14(A) to 14(F) are cross-sectional views showing a manufacturing method 1 of the semiconductor device according to the first embodiment. [Figure 15] 15(A) to 15(F) are cross-sectional views showing a manufacturing method 1 of the semiconductor device according to the first embodiment. [Figure 16] 16(A) to 16(F) are cross-sectional views showing a manufacturing method 1 of the semiconductor device according to the first embodiment. [Figure 17] 17(A) to 17(F) are cross-sectional views showing a manufacturing method 1 of the semiconductor device according to the first embodiment. [Figure 18] 18(A) to 18(F) are cross-sectional views showing a manufacturing method 1 of the semiconductor device according to the first embodiment. [Figure 19] 19(A) to 19(F) are cross-sectional views showing a manufacturing method 1 of the semiconductor device according to the first embodiment. [Figure 20] 20(A) to 20(F) are cross-sectional views showing a manufacturing method 1 of the semiconductor device according to the first embodiment. [Figure 21] 21(A) to 21(F) are cross-sectional views showing a manufacturing method 1 of the semiconductor device according to the first embodiment. [Figure 22] 22(A) to 22(F) are cross-sectional views showing a manufacturing method 1 of the semiconductor device according to the first embodiment. [Figure 23] 23(A) to 23(F) are cross-sectional views showing a manufacturing method 1 of the semiconductor device according to the first embodiment. [Figure 24] 24(A) to 24(F) are cross-sectional views showing a second manufacturing method of the semiconductor device according to the first embodiment. [Figure 25]25(A) to 25(F) are cross-sectional views showing a second manufacturing method of the semiconductor device according to the first embodiment. [Figure 26] 26(A) and 26(B) are cross-sectional views of the second region in the first modified example of the first embodiment. [Figure 27] 27(A) and 27(B) are cross-sectional views of a first region in a first modified example of the first embodiment. [Figure 28] 28(A) and 28(B) are cross-sectional views of the third region in the first modified example of the first embodiment. [Figure 29] 29(A) and 29(B) are cross-sectional views of the second region in the second modified example of the first embodiment. [Figure 30] 30(A) and 30(B) are cross-sectional views of the first region in the second modified example of the first embodiment. [Figure 31] 31(A) and 31(B) are cross-sectional views of a third region in a second modified example of the first embodiment. [Figure 32] 32(A) and 32(B) are cross-sectional views of the first region in the third modified example of the first embodiment. [Figure 33] 33(A) and 33(B) are cross-sectional views of a third region in a third modified example of the first embodiment. [Figure 34] 34(A) and 34(B) are cross-sectional views of the first region in the fourth modified example of the first embodiment. [Figure 35] 35(A) and 35(B) are cross-sectional views of the third region in the fourth modified example of the first embodiment. [Figure 36] 36(A) to 36(F) are cross-sectional views of a semiconductor device according to a fifth modification of the first embodiment. [Figure 37] FIG. 37 is a circuit diagram of the semiconductor device according to the second embodiment. [Figure 38] FIG. 38 is a circuit diagram of the semiconductor device according to the second embodiment. [Figure 39] FIG. 39 is a circuit diagram of a semiconductor device according to a first modification of the second embodiment. [Figure 40] FIG. 40 is a circuit diagram of a semiconductor device according to a second modification of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. The following embodiments are examples for embodying the technical ideas of the invention, and the present disclosure is not limited to the described configurations and numerical values. In each drawing, the same components are given the same reference numerals, and duplicate explanations may be omitted as appropriate. The size, positional relationship, etc. of each component shown in each drawing may be exaggerated to facilitate understanding of the invention.

[0012] (First embodiment) FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device 100 of the first embodiment includes a substrate 10, an insulating film 16, a first region 61, a second region 62, and a third region 63. The first region 61 is provided on the substrate 10 and includes a transistor Tr1. The second region 62 is provided on the substrate 10 and includes transistors Tr2 and Tr3. The third region 63 is provided on the substrate 10 and includes a transistor Tr4. The transistors Tr1 and Tr3 are, for example, N-channel transistors. The transistors Tr2 and Tr4 are, for example, P-channel transistors. The insulating film 16 is provided on the substrate 10 and surrounds the first region 61, the second region 62, and the third region 63. The driving force of the transistor Tr1 is approximately twice that of the transistor Tr3, and the driving force of the transistor Tr4 is approximately twice that of the transistor Tr2.

[0013] The conductivity type of the channel semiconductor layers 21A-21E is determined not only by the impurity elements doped into the channel semiconductor layers 21A-21E but also by the combination of the work functions of the channel semiconductor layers 21A-21E and the gate electrodes 25A-25E. Even if the channel semiconductor layers 21A-21E are, for example, intrinsic semiconductors, they can behave as N-type, in which electrons conduct as carriers, or as P-type, in which holes conduct as carriers. In the following description, the term "N-type channel semiconductor layer" is used when electrons conduct as carriers, and the term "P-type channel semiconductor layer" is used when holes conduct as carriers.

[0014] Fig. 2 is a perspective view of the second region in the first embodiment. Figs. 3(A) and 3(B) are cross-sectional views of the second region in the first embodiment. Fig. 2 illustrates channel semiconductor layers 21C and 21D, source / drain semiconductor layers 22C, 22D, 23C, and 23D, and gate electrodes 25C and 25D. Figs. 3(A) and 3(B) correspond to the AA and BB cross-sectional views of Fig. 2, respectively. The thickness direction of the substrate 10 is the Z direction, the arrangement direction of the source / drain semiconductor layers 22C and 23C is the X direction, and the direction perpendicular to the Z direction and the X direction is the Y direction.

[0015] 2 to 3(B), the second region 62 of the semiconductor device 100 has transistors Tr2 and Tr3. An element isolation insulating film 12 is provided in an upper layer portion of the substrate 10. The transistor Tr2 (second transistor) has a channel semiconductor layer 21C (third channel semiconductor layer), a pair of source-drain semiconductor layers 22C and 23C (a pair of third source-drain semiconductor layers), a gate insulating film 24C (third gate insulating film), and a gate electrode 25C (third gate electrode).

[0016] The channel semiconductor layer 21C is provided on the substrate 10 surrounded by the element isolation insulating film 12, and has a third conductivity type (e.g., N type). A pair of source / drain semiconductor layers 22C and 23C is provided on the substrate 10, sandwiches the channel semiconductor layer 21C, and has a fourth conductivity type (e.g., P type) different from the third conductivity type. The gate electrode 25C is located between the source / drain semiconductor layers 22C and 23C, and sandwiches a gate insulating film 24C between the gate electrode 25C and the channel semiconductor layer 21C.

[0017] The transistor Tr3 (third transistor) includes a channel semiconductor layer 21D (fourth channel semiconductor layer), a pair of source / drain semiconductor layers 22D and 23D (a pair of fourth source / drain semiconductor layers), a gate insulating film 24D (fourth gate insulating film), and a gate electrode 25D (fourth gate electrode). The channel semiconductor layer 21D is provided above the channel semiconductor layer 21C and spaced apart from the channel semiconductor layer 21C, and has a fourth conductivity type (e.g., P type). The pair of source / drain semiconductor layers 22D and 23D are provided above the source / drain semiconductor layers 22C and 23C and spaced apart from the source / drain semiconductor layers 22C and 23C, sandwiching the channel semiconductor layer 21D, and has a third conductivity type (e.g., N type). The gate electrode 25D is located between the source / drain semiconductor layers 22D and 23D, and sandwiches the gate insulating film 24D between itself and the channel semiconductor layer 21D. The gate electrodes 25C and 25D are integrally provided and electrically connected. The insulating film 14 electrically separates the channel semiconductor layers 21C and 21D, and also electrically separates the pair of source-drain semiconductor layers 22C and 23C from the pair of source-drain semiconductor layers 22D and 23D. In the transistors Tr2 and Tr3, spacers 26 are provided to sandwich the gate electrodes 25C and 25D in the X direction.

[0018] In the second region 62, a transistor Tr3 having a fourth conductivity type channel is provided on a transistor Tr2 having a third conductivity type channel. The transistors Tr2 and Tr3 have a CFET structure having gate electrodes 25C and 25D at the same potential, and can form, for example, a CMOS inverter.

[0019] 4A and 4B are cross-sectional views of a first region in the first embodiment. As shown in FIGS. 4A and 4B, the first region 61 of the semiconductor device 100 includes a transistor Tr1. The transistor Tr1 (first transistor) includes a channel semiconductor layer 21A (first channel semiconductor layer), a pair of source-drain semiconductor layers 22A and 23A (a pair of first source-drain semiconductor layers), a gate insulating film 24A (first gate insulating film), and a gate electrode 25A (first gate electrode), a channel semiconductor layer 21B (second channel semiconductor layer), a pair of source-drain semiconductor layers 22B and 23B (a pair of second source-drain semiconductor layers), a gate insulating film 24B (second gate insulating film), and a gate electrode 25B (second gate electrode).

[0020] The channel semiconductor layer 21A is provided on the substrate 10 surrounded by the element isolation insulating film 12, and has a first conductivity type (e.g., P type). A pair of source / drain semiconductor layers 22A and 23A is provided on the substrate 10, sandwiches the channel semiconductor layer 21A, and has a second conductivity type (e.g., N type) different from the first conductivity type. The gate electrode 25A is located between the pair of source / drain semiconductor layers 22A and 23A, and sandwiches a gate insulating film 24A between the gate electrode 25A and the channel semiconductor layer 21A.

[0021] The channel semiconductor layer 21B (second channel semiconductor layer) is provided above the channel semiconductor layer 21A at a distance from the channel semiconductor layer 21A and has a first conductivity type (e.g., P type). A pair of source / drain semiconductor layers 22B and 23B is provided on the source / drain semiconductor layers 22A and 23A and is electrically connected to the source / drain semiconductor layers 22A and 23A, respectively, sandwiching the channel semiconductor layer 21B therebetween and having a second conductivity type (e.g., N type). The gate electrode 25B is electrically connected to the gate electrode 25A between the source / drain semiconductor layers 22B and 23B, with the gate insulating film 24B sandwiched between the gate electrode 25B and the channel semiconductor layer 21B. The insulating film 14 is provided between the channel semiconductor layers 21A and 21B.

[0022] In the transistor Tr1, the source-drain semiconductor layers 22A and 22B are electrically connected, the source-drain semiconductor layers 23A and 23B are electrically connected, and the gate electrodes 25A and 25B are electrically connected. This allows the transistor Tr1 to function as a single transistor in which two channel semiconductor layers 21A and 21B are arranged in parallel. The driving power of the transistor Tr1 is approximately twice that of the transistor Tr3.

[0023] 5A and 5B are cross-sectional views of the third region in the first embodiment. As shown in FIGS. 5A and 5B, the third region 63 of the semiconductor device 100 includes a transistor Tr4. The transistor Tr4 (fourth transistor) includes a channel semiconductor layer 21E (fifth channel semiconductor layer), a pair of source-drain semiconductor layers 22E and 23E (a pair of fifth source-drain semiconductor layers), a gate insulating film 24E (fifth gate insulating film), and a gate electrode 25E (fifth gate electrode), a channel semiconductor layer 21F (sixth channel semiconductor layer), a pair of source-drain semiconductor layers 22F and 23F (a pair of sixth source-drain semiconductor layers), a gate insulating film 24F (sixth gate insulating film), and a gate electrode 25F (sixth gate electrode).

[0024] The channel semiconductor layer 21E is provided on the substrate 10 surrounded by the element isolation insulating film 12, and has a second conductivity type (e.g., N type). A pair of source / drain semiconductor layers 22E and 23E is provided on the substrate 10, sandwiches the channel semiconductor layer 21E, and has a first conductivity type (e.g., P type). The gate electrode 25E is located between the pair of source / drain semiconductor layers 22E and 23E, and sandwiches a gate insulating film 24E between the gate electrode 25E and the channel semiconductor layer 21E.

[0025] The channel semiconductor layer 21F (sixth channel semiconductor layer) is provided above the channel semiconductor layer 21E and spaced apart from the channel semiconductor layer 21E, and has a second conductivity type (e.g., N type). A pair of source / drain semiconductor layers 22F and 23F is provided on the source / drain semiconductor layers 22E and 23E, is electrically connected to the source / drain semiconductor layers 22E and 23E, respectively, sandwiches the channel semiconductor layer 21F, and has a second conductivity type (e.g., P type). The gate electrode 25F is electrically connected to the gate electrode 25E between the source / drain semiconductor layers 22F and 23F, with a gate insulating film 24F sandwiched between the gate electrode 25F and the channel semiconductor layer 21F. The insulating film 14 is provided between the channel semiconductor layers 21E and 21F.

[0026] In the transistor Tr4, the source-drain semiconductor layers 22E and 22F are electrically connected, the source-drain semiconductor layers 23E and 23F are electrically connected, and the gate electrodes 25E and 25F are electrically connected. This allows the transistor Tr4 to function as a single transistor in which two channel semiconductor layers 21E and 21F are arranged in parallel. The driving power of the transistor Tr4 is approximately twice that of the transistor Tr2.

[0027] The substrate 10 is a semiconductor substrate such as a silicon (Si) substrate. The channel semiconductor layers 21A-21F and the source / drain semiconductor layers 22A-22F and 23A-23F are, for example, single crystals, such as silicon layers or silicon germanium (SiGe) layers. The P-type source / drain semiconductor layers 22A-22F and 23A-23F and the N-type channel semiconductor layers 21A-21F are preferably silicon germanium layers. This can improve hole mobility in the N-type channel semiconductor layers 21A-21F. The N-type semiconductor layers are doped with, for example, phosphorus (P) or arsenic (As). The P-type semiconductor layers are doped with, for example, boron (B) or aluminum (Al). As described above, the channel semiconductor layers 21A-21E may be intrinsic semiconductors that are not doped with impurity elements, even when they are N-type or P-type. The gate insulating films 24A-24F are, for example, silicon oxide films or high-k films (films with a higher dielectric constant than silicon oxide), such as hafnium oxide films. The gate electrodes 25A-25F are, for example, polycrystalline silicon layers or metal layers. A metal film for adjusting the work function may be provided between the gate electrodes 25A-25F and the gate insulating films 24A-24F. The insulating film 14 is, for example, a silicon nitride film or a silicon oxide film. The insulating film 16 is, for example, a silicon oxide film.

[0028] (First comparative example) In the first comparative example, when a P-channel or N-channel transistor is used alone, only the transistors Tr2 and Tr3 shown in Figures 3A and 3B are used. In this case, the gate electrodes 25C and 25D are electrically connected, which increases the gate parasitic capacitance.

[0029] (Second comparative example) 6A and 6B are cross-sectional views of the third region in the second comparative embodiment. As shown in FIGS. 6A and 6B, the semiconductor device 110 of the second comparative embodiment includes a transistor Tr4 having the same structure as the transistor Tr2 of the first embodiment shown in FIGS. 3A and 3B. The source-drain semiconductor layers 22D and 23D are not provided on the transistor Tr4. The other configurations are the same as those in FIGS. 3A and 3B of the first embodiment. A contact 28 is provided that penetrates the insulating film 16 and connects to the source-drain semiconductor layers 22C and 23C. The contact 28 is formed from the upper surface of the insulating film 16 to the upper surfaces of the source-drain semiconductor layers 22C and 23C. This increases the aspect ratio of the contact 28, making it difficult to form the contact 28. This increases the contact resistance between the contact 28 and the source-drain semiconductor layers 22C and 23C, resulting in degradation of characteristics. Alternatively, the diameter of the contact 28 increases, resulting in a large size.

[0030] When transistors Tr1 and Tr4 are used as stand-alone devices rather than as CFETs, a larger driving force may be required than for transistors Tr2 and Tr3 used in CFETs. In such cases, in the first and second comparative examples, multiple transistors Tr1 or Tr4 are arranged in the XY plane. This increases the chip size and the size of the semiconductor device.

[0031] (Description of the First Embodiment) In the first embodiment, as shown in FIGS. 4A to 5B, transistors Tr1 and Tr4 have channel semiconductor layers 21A and 21B in parallel. Therefore, compared to the first and second comparative embodiments, the driving force can be approximately doubled for the same chip area. This allows the chip area required to form transistors with the same driving force to be approximately halved. This allows for miniaturization. Furthermore, gate electrodes 25A and 25B both face the channel semiconductor layers 21A and 21B, and gate electrodes 25E and 25F both face the channel semiconductor layers 21E and 21F. This prevents the parasitic capacitance from increasing, as in the first embodiment, and improves transistor characteristics. Furthermore, the aspect ratio of the contacts can be reduced.

[0032] (Manufacturing Method 1 of First Embodiment) Figures 7(A) to 23(F) are cross-sectional views showing a manufacturing method 1 of a semiconductor device according to the first embodiment. Figures 7(A) to 23(A) and 7(B) to 23(B) are cross-sectional views of the second region 62. Figures 7(C) to 23(C) and 7(D) to 23(D) are cross-sectional views of the first region 61, and Figures 7(E) to 23(E) and 7(F) to 23(F) are cross-sectional views of the third region 63.

[0033] 7(A) to 7(F), in the second region 62, a semiconductor layer 31C, a barrier layer 39, a dummy layer 38, and a semiconductor layer 31D are stacked in this order on the substrate 10. In the first region 61, a semiconductor layer 31A, a dummy layer 38, and a semiconductor layer 31B are stacked in this order. In the third region 63, a semiconductor layer 31E, a barrier layer 39, a dummy layer 38, a barrier layer 39, and a semiconductor layer 31F are stacked in this order.

[0034] An example will be described in which semiconductor layers 31A, 31B, and 31D are silicon layers, and semiconductor layers 31C, 31E, and 31F are silicon germanium layers. First, a silicon layer is epitaxially grown on substrate 10. Then, the silicon layer in second region 62 and third region 63 is removed. Silicon germanium layers are formed on substrate 10 in second region 62 and third region 63 while protecting the side surfaces of the removed portions. A silicon barrier layer 39 is formed on the silicon layer and silicon germanium layer. As a result, semiconductor layer 31C of a silicon germanium layer is formed in second region 62, semiconductor layer 31A of a silicon layer in first region 61, and semiconductor layer 31E of a silicon germanium layer in third region 63 are formed.

[0035] A dummy layer 38 with a high concentration of germanium is formed on the barrier layer 39. A silicon layer is formed on the dummy layer 38. Then, the silicon layer in the third region 63 is removed. While protecting the side surfaces of the removed portion, a silicon barrier layer 39 and a silicon germanium layer are formed on the substrate 10 in the third region 63. As a result, a semiconductor layer 31D of a silicon layer is formed in the second region 62, a semiconductor layer 31B of a silicon layer is formed in the first region 61, and a semiconductor layer 31F of a silicon germanium layer is formed in the third region 63. The thicknesses of the semiconductor layers 31A to 31F are, for example, 20 nm to 30 nm, the thickness of the dummy layer 38 is, for example, 30 nm, and the thickness of the barrier layer 39 is, for example, several nm. Note that the above silicon layer and silicon germanium layer are merely examples. Each semiconductor layer can be made of any material. The thicknesses of the semiconductor layers 31A to 31F can be, for example, 4 nm to 50 nm, and the thickness of the dummy layer 38 can be, for example, 4 nm to 50 nm.

[0036] 8(A) to 8(F), dummy layer 38 having a high germanium composition is etched to form voids 37. By providing barrier layer 39, etching of semiconductor layers 31C, 31E, and 31F can be suppressed when etching dummy layer 38. Dummy layer 38 may be made of any material as long as it has etching selectivity with semiconductor layers 31A to 31F and can be epitaxially grown.

[0037] 9(A) to 9(F), for example, ALD (Atomic Layer Deposition) is used to form the insulating film 14 in the gap 37. Note that hereinafter, illustration of the barrier layer 39 will be omitted.

[0038] As shown in FIGS. 10A to 10F, a mask layer 40A is formed on the semiconductor layers 31B, 31D, and 31F. The mask layer 40A is an insulating film such as a silicon nitride film. The mask layer 40A is processed into a desired shape using photolithography and etching. Using the mask layer 40A as a mask, the semiconductor layers 31B, 31D, and 31F are processed using, for example, etching. As a result, channel semiconductor layers 21B, 21D, and 21F are formed from the semiconductor layers 31B, 31D, and 31F, respectively. The width of the channel semiconductor layers 21B, 21D, and 21F in the Y direction is, for example, 6 nm. The channel semiconductor layers 21B, 21D, and 21F have a Fin structure. The width of the channel semiconductor layers 21B, 21D, and 21F in the Y direction can be, for example, 4 nm to 15 nm.

[0039] As shown in FIGS. 11(A) to 11(F), an insulating film is formed as a sidewall on the side surfaces of the mask layer 40A and the channel semiconductor layers 21B, 21D, and 21F, thereby forming the mask layer 40 including the mask layer 40A.

[0040] 12(A) to 12(F), the insulating film 14 and the semiconductor layers 31A, 31C, and 31E are processed using, for example, an etching method with the mask layer 40 as a mask. As a result, the channel semiconductor layers 21A, 21C, and 21E are formed from the semiconductor layers 31A, 31C, and 31E, respectively. The channel semiconductor layers 21A, 21C, and 21E have a Fin structure. The channel semiconductor layers 21A, 21C, and 21E may be trimmed to narrow the widths of the channel semiconductor layers 21A, 21C, and 21E in the Y direction to the same as the widths of the channel semiconductor layers 21B, 21D, and 21F in the Y direction. The widths of the channel semiconductor layers 21A, 21C, and 21E in the Y direction may be, for example, 4 nm to 15 nm.

[0041] As shown in Figures 13(A) to 13(F), a dummy gate 41 is formed in a region where a gate electrode is to be formed. As shown in Figures 13(A), 13(C), and 13(E), the dummy gate 41 is provided on both sides of the mask layer 40, the insulating film 14, and the channel semiconductor layers 21A, 21C, and 21E in the Y direction (see Figures 3(A) to 5(B)). As shown in Figures 13(B), 13(D), and 13(F), the dummy gate 41 is provided on the mask layer 40. The dummy gate 41 is made of, for example, polycrystalline silicon.

[0042] 14(A) to 14(F), spacers 26 are formed to sandwich the dummy gate 41 in the X direction. The spacers 26 are insulating films such as silicon nitride films or silicon oxide films.

[0043] As shown in FIGS. 15(A) to 15(F), a mask layer 42 is formed to cover the entire surfaces of the first region 61 and the second region 62. The third region 63 is exposed from the mask layer 42. The mask layer 42 is formed, for example, by using the SOC (Spin On Carbon) method. The mask layer 40 is processed using the mask layer 42 as a mask. As a result, as shown in FIG. 15(F), the mask layer 40 is removed from both sides of the channel semiconductor layer 21F in the X direction. As a result, the side surfaces of the channel semiconductor layers 21C, 21E, and 21F are exposed from the mask layer 40 and the insulating film 14.

[0044] As shown in FIGS. 16(A) to 16(F), after removing the mask layer 42, a mask layer 43 is formed to cover the entire surface of the first region 61. The second region 62 and the third region 63 are exposed from the mask layer 43. The mask layer 43 is formed using, for example, an SOC method. As shown in FIG. 16(B), in the second region 62, both sides of the channel semiconductor layer 21C in the X direction are removed using the mask layer 40 as a mask. As shown in FIG. 16(F), in the third region 63, both sides of the channel semiconductor layers 21E and 21F in the X direction are removed using the mask layer 43 as a mask. At this time, both sides of the insulating film 14 in the X direction are also removed. As a result, both side surfaces of the channel semiconductor layers 21C, 21E, and 21F in the X direction are exposed from the mask layer 40 and the insulating film 14.

[0045] As shown in Figures 17(A) to 17(F), source / drain semiconductor layers 22C, 23C, 22E, 23E, 22F, and 23F are epitaxially grown on the side surfaces of channel semiconductor layers 21C, 21E, and 21F. As shown in Figure 17(B), in the second region 62, the upper surfaces of the source / drain semiconductor layers 22C and 23C are defined by the insulating film 14. As shown in Figures 17(E) and 17(F), since the side surfaces of the insulating film 14 are located at approximately the same level as the side surfaces of the channel semiconductor layers 21E and 21F, by appropriately setting the epitaxial conditions, the source / drain semiconductor layers 22E and 22F come into contact with each other, and the source / drain semiconductor layers 23E and 23F come into contact with each other. Dopant ions may be implanted into the surfaces of the source / drain semiconductor layers 22C, 23C, 22E, 23E, 22F, and 23F. This allows contact layers with low resistivity to be formed on the surfaces of the source / drain semiconductor layers 22C, 23C, 22E, 23E, 22F, and 23F.

[0046] As shown in FIGS. 18A to 18F, after removing the mask layer 43, a mask layer 44 is formed to cover the portion of the second region 62 below the insulating film 14 and to cover the entire surface of the third region. The portion of the second region 62 above the insulating film 14 and the first region 61 are exposed from the mask layer 44. The mask layer 44 is formed using, for example, an SOC method. As shown in FIG. 18B, in the second region 62, the mask layer 40 is removed from both sides of the channel semiconductor layer 21C in the X direction using the mask layer 44 as a mask. As shown in FIG. 18D, in the first region 61, the mask layer 40 is removed from both sides of the channel semiconductor layer 21B in the X direction using the mask layer 44 as a mask. As a result, both side surfaces of the channel semiconductor layers 21A, 21B, and 21D in the X direction are exposed from the mask layer 40 and the insulating film 14.

[0047] As shown in Figures 19(A) to 19(F), layers 22A, 23A, 22B, 23B, 22D, and 23D are epitaxially grown on the side surfaces of channel semiconductor layers 21A, 21B, and 21D. As shown in Figure 19(B), in the second region 62, the lower surfaces of the source / drain semiconductor layers 22D and 23D are defined by an insulating film 14. As shown in Figures 19(C) and 19(D), by appropriately setting the epitaxial growth conditions, the source / drain semiconductor layers 22A and 22B come into contact with each other, and the source / drain semiconductor layers 23A and 23B come into contact with each other. Dopant ions may be implanted into the surfaces of the source / drain semiconductor layers 22A, 23A, 22B, 23B, 22D, and 23D. This allows low-resistivity contact layers to be formed on the surfaces of 22A, 23A, 22B, 23B, 22D, and 23D.

[0048] 20(A) to 20(F), after removing the mask layer 44, an insulating film 16 is formed on the substrate 10 so as to cover the entire structure. The dummy gate 41 is exposed from the upper surface of the insulating film 16.

[0049] 21(A) to 21(F), the dummy gate 41 is selectively removed to form an opening 17 in the insulating film 16. Inside the opening 17, there is a void.

[0050] 22(A) to 22(F), a gate insulating film (not shown) and gate electrodes 25A to 25F are formed in the opening 17. A metal film for adjusting the work function may be formed between the gate insulating film and the gate electrodes 25A to 25F.

[0051] 23(A) to 23(F), contact openings are formed that penetrate at least a portion of the insulating film 16, and contacts 28 are formed in the contact openings. The contacts 28 come into contact with at least one of the source-drain semiconductor layers 22A to 22F and 23A to 23F. Thereafter, an interlayer insulating film and wiring are formed on the insulating film 16, and a semiconductor device is manufactured.

[0052] (Manufacturing method 2 of the first embodiment) 24(A) to 24(F) and 25(A) to 25(F) are cross-sectional views showing a manufacturing method 2 of the semiconductor device according to the first embodiment. In Fig. 24(A) to 24(F), semiconductor layers 31A, 31C, and 31E are the same semiconductor layer 31A, and semiconductor layers 31B, 31D, and 31F are the same semiconductor layer 31B.

[0053] 8(A) to 8(F) to 20(A) to 20(F) are then performed. At this time, in Figures 10(A) to 10(F), a channel semiconductor layer 21B is formed from the semiconductor layer 31B in the first region 61, and a channel semiconductor layer 21D is formed from the semiconductor layer 31B in the second region 62. In Figures 12(A) to 12(F), a channel semiconductor layer 21A is formed from the semiconductor layer 31A in the first region 61.

[0054] 25(A) to 25(F), in the second region 62, a semiconductor layer 31A is provided between the source-drain semiconductor layers 22C and 23C. In the third region 63, a semiconductor layer 31A is provided between the source-drain semiconductor layers 22E and 23E. A semiconductor layer 31B is provided between the source-drain semiconductor layers 22F and 23F. Part or all of the semiconductor layers 31A and 31B are removed, and then the channel semiconductor layers 21C, 21E, and 21F are epitaxially grown. This results in the same structure as in FIGS. 21(A) to 21(F). Thereafter, the steps of FIGS. 22(A) to 22(F) and 23(A) to 23(F) are performed to manufacture the semiconductor device of the first embodiment.

[0055] In Figures 10(A) to 10(F) and Figures 12(A) to 12(F), channel semiconductor layers 21C, 21E and 21F may be formed, and in Figures 25(A) to 25(F), channel semiconductor layers 21A, 21B and 21D may be formed.

[0056] As in manufacturing method 1, the channel semiconductor layers 21A to 21F may be formed before the source / drain semiconductor layers 22A to 22F and 23A to 23F are formed. As in manufacturing method 2, at least a part of the channel semiconductor layers 21A to 21F may be formed after the source / drain semiconductor layers 22A to 22F and 23A to 23F are formed.

[0057] In manufacturing methods 1 and 2 of the first embodiment, as shown in FIGS. 17A to 17F, a pair of source / drain semiconductor layers 22C and 23C (third source / drain semiconductor layers) having P type (first conductivity type) are formed on a substrate 10. As shown in FIGS. 19A to 19F, a pair of source / drain semiconductor layers 22A and 23A (first source / drain semiconductor layers) having N type (second conductivity type), a pair of source / drain semiconductor layers 22B and 23B (second source / drain semiconductor layers) having N type, and a pair of source / drain semiconductor layers 22D and 23D (fourth source / drain semiconductor layers) having N type are simultaneously formed. This allows a transistor Tr1 with a second conductivity type channel to be formed in the first region 61, and a transistor Tr2 with a first conductivity type channel and a transistor Tr3 with a second conductivity type channel to be formed in the second region 62.

[0058] 10(A) to 10(F) and 12(A) to 12(F), channel semiconductor layers 21A to 21D are formed in manufacturing method 1, but semiconductor layer 31A or 31B may be formed instead of channel semiconductor layers 21A to 21D in manufacturing method 2. In this manner, the source-drain semiconductor layers 22A and 23A may sandwich the first semiconductor layer, the source-drain semiconductor layers 22B and 23B may sandwich the second semiconductor layer, the source-drain semiconductor layers 22C and 23C may sandwich the third semiconductor layer, and the source-drain semiconductor layers 22D and 23D may sandwich the fourth semiconductor layer.

[0059] 17(A) to 17(F), a pair of source-drain semiconductor layers 22E and 23E (first source-drain semiconductor layers) having P-type (second conductivity type), a pair of source-drain semiconductor layers 22F and 23F (second source-drain semiconductor layers), and a pair of source-drain semiconductor layers 22C and 23C (third source-drain semiconductor layers) having P-type are simultaneously formed. As shown in FIGS. 19(A) to 19(F), a pair of source-drain semiconductor layers 22D and 23D (fourth source-drain semiconductor layers) having N-type (first conductivity type) are formed. As a result, a transistor Tr4 with a first conductivity type channel can be formed in the third region 63, and a transistor Tr2 with a first conductivity type channel and a transistor Tr2 with a second conductivity type channel can be formed in the second region 62.

[0060] 10(A) to 10(F) and 12(A) to 12(F), channel semiconductor layers 21C to 21F are formed in manufacturing method 1, but semiconductor layer 31A or 31B may be formed instead of channel semiconductor layers 21C to 21F in manufacturing method 2. In this manner, the source-drain semiconductor layers 22E and 23E may sandwich the first semiconductor layer, the source-drain semiconductor layers 22F and 23F may sandwich the second semiconductor layer, the source-drain semiconductor layers 22C and 23C may sandwich the third semiconductor layer, and the source-drain semiconductor layers 22D and 23D may sandwich the fourth semiconductor layer.

[0061] As in manufacturing method 2, after forming the source / drain semiconductor layers 22A to 22E and 22F to 23F, at least one of the semiconductor layers 31A and 31B in the first region 61, the second region 62 and the third region 63 may be removed, and at least one of the corresponding channel semiconductor layers 21A to 21F may be formed in the region from which at least one semiconductor layer has been removed.

[0062] 3A, the height of the upper surface of the channel semiconductor layer 21C from the upper surface of the substrate 10 is defined as HC, and the heights of the lower and upper surfaces of the channel semiconductor layer 21D from the upper surface of the substrate 10 are defined as Hd and HD, respectively. The height of the upper surface of the gate electrode 25D from the upper surface of the substrate 10 is defined as H2. In FIG. 4A, the height of the upper surface of the channel semiconductor layer 21A from the upper surface of the substrate 10 is defined as HA, and the heights of the lower and upper surfaces of the channel semiconductor layer 21B from the upper surface of the substrate 10 are defined as Hb and HB, respectively. The height of the upper surface of the gate electrode 25B from the upper surface of the substrate 10 is defined as H1. In FIG. 5A, the height of the upper surface of the channel semiconductor layer 21E from the upper surface of the substrate 10 is defined as HE, and the heights of the lower and upper surfaces of the channel semiconductor layer 21F from the upper surface of the substrate 10 are defined as Hf and HF, respectively. The height of the upper surface of the gate electrode 25F from the upper surface of the substrate 10 is defined as H3. Heights HA to HF correspond to the heights from the substrate 10 of the channel semiconductor layers 21A to 21F at the farthest points from the substrate 10. Heights Hb, Hd, and Hf correspond to the heights from the substrate 10 of the channel semiconductor layers 21B, 21D, and 21F at the closest points from the substrate 10. Heights H1 and H2 correspond to the heights from the substrate 10 of the gate electrodes 25B, 25D, and 25F at the farthest points from the substrate 10, respectively.

[0063] In manufacturing methods 1 and 2, a fine lithography technique such as EUVL (Extreme Ultraviolet Lithography) is used. EUVL has an extremely shallow depth of focus. In FIGS. 10(A) to 10(F), in order to improve the processing accuracy of the channel semiconductor layers 21B and 21D, the absolute value |HB-HD| of the difference between the heights HB (first height) and HD (second height) is preferably 0.1 times or less, and more preferably 0.05 times or less, of the height HB. |HB-HD| is preferably 10 nm or less, and more preferably 2 nm or less. Furthermore, the difference MAX-MIN between the maximum value MAX (HB, HD, HF) and the minimum value MIN (HB, HD, HF) of the heights HB, HD, and HF is preferably 0.1 times or less, and more preferably 0.05 times or less, of the maximum value MAX. MAX-MIN is preferably 10 nm or less, and more preferably 2 nm or less.

[0064] 13(A) to 13(F), in order to improve the processing accuracy of the dummy gate 41, the difference MAX-MIN between the maximum value MAX (H1, H2, H3) and the minimum value MIN (H1, H2, H3) of the heights H1, H2, and H3 is preferably 0.1 times or less, more preferably 0.05 times or less, and is preferably 10 nm or less, more preferably 2 nm or less.

[0065] If the heights HA, HC, and HE are not uniform, or if the heights Hb, Hd, and Hf are not uniform, the parasitic capacitance of the gate electrode and the aspect ratio of the contact 28 will vary. To suppress these variations, the difference MAX-MIN between the maximum value MAX (HA, HC, HE) and the minimum value MIN (HA, HC, HE) is preferably 0.1 times or less, and more preferably 0.05 times or less, of the maximum value MAX. MAX-MIN is preferably 10 nm or less, and more preferably 2 nm or less. The difference MAX-MIN between the maximum value MAX (Hb, Hd, Hf) and the minimum value MIN (Hb, Hd, Hf) is preferably 0.1 times or less, and more preferably 0.05 times or less, of the maximum value MAX. MAX-MIN is preferably 10 nm or less, and more preferably 2 nm or less.

[0066] (First Modification of the First Embodiment) The first modified example of the first embodiment is an example in which nanosheet transistors are used as transistors Tr1 to Tr4. Figures 26(A) and 26(B) are cross-sectional views of a second region in the first modified example of the first embodiment. Figures 27(A) and 27(B) are cross-sectional views of a first region in the first modified example of the first embodiment. Figures 28(A) and 28(B) are cross-sectional views of a third region in the first modified example of the first embodiment.

[0067] As shown in FIGS. 26A to 28B, in the semiconductor device 101 according to the first modification of the first embodiment, the channel semiconductor layers 21A to 21F each have a nanosheet structure in which a plurality of layers are provided in the Z direction. The gate insulating films 24A to 24F are provided so as to surround the channel semiconductor layers 21A to 21F, respectively. The gate electrodes 25A to 25F are provided so as to sandwich the gate insulating films 24A to 24F and surround the channel semiconductor layers 21A to 21F, respectively. The thickness of the channel semiconductor layers 21A to 21F in the Z direction is, for example, 4 nm to 15 nm, and the spacing between the channel semiconductor layers 21A to 21F in the Z direction is, for example, 4 nm to 15 nm. Although the example in which two channel semiconductor layers 21A to 21F are provided in the Z direction has been described, three or more channel semiconductor layers 21A to 21F may also be provided in the Z direction. The other configurations are the same as those of the first embodiment, and description thereof will be omitted.

[0068] (Second Modification of the First Embodiment) In the second modified example of the first embodiment, a portion of transistor Tr1, a portion of transistor Tr4, and transistor Tr2 are FinFETs, and a portion of transistor Tr1, a portion of transistor Tr4, and transistor Tr3 are nanosheet transistors. Figures 29(A) and 29(B) are cross-sectional views of the second region in the second modified example of the first embodiment. Figures 30(A) and 30(B) are cross-sectional views of the first region in the second modified example of the first embodiment. Figures 31(A) and 31(B) are cross-sectional views of the third region in the second modified example of the first embodiment.

[0069] 29(A) to 31(B), in the semiconductor device 102 according to the second modification of the first embodiment, the channel semiconductor layers 21A, 21C, and 21E have a fin structure, and the channel semiconductor layers 21B, 21D, and 21F each have a nanosheet structure in which a plurality of the channel semiconductor layers 21B, 21D, and 21F are provided in the Z direction. Three or more of each of the channel semiconductor layers 21B, 21D, and 21F may be provided in the Z direction. The other configurations are the same as those of the first embodiment and its first modification, and therefore description thereof will be omitted.

[0070] As in the first embodiment and its first and second modifications, at least one of the channel semiconductor layers 21A to 21F may have a fin structure, or at least one of the channel semiconductor layers 21A to 21F may have a nanosheet structure. It is preferable that the channel semiconductor layers 21A, 21C, and 21E have the same fin structure or the same nanosheet structure, and that the channel semiconductor layers 21B, 21D, and 21F have the same fin structure or the same nanosheet structure. This makes it easier to manufacture the channel semiconductor layers 21A to 21F.

[0071] The electron mobility of silicon is 130 cm along the (110) plane. 2 V -1 s -1 In the (100) plane direction, it is 307 cm 2 V -1 s -1 The hole mobility of silicon is 238 cm in the (110) plane direction. 2 V -1 s -1 In the (100) plane direction, it is 78 cm 2 V -1 s -1 When the substrate 10 is a silicon substrate having a (100) crystal orientation as its main surface, in the Fin structure, the carrier travel direction is the (110) plane direction, and in the nanosheet structure, the carrier travel direction is the (100) plane direction. Therefore, it is preferable that the channel semiconductor layer of a P-type channel transistor has a Fin structure, and that of an N-type channel transistor has a nanosheet structure.

[0072] The CFET in the second region 62 is often required to have high speed. Therefore, one of the channel semiconductor layers 21A and 21C and the channel semiconductor layers 21B and 21D is made to have a Fin structure, and the other is made to have a nanosheet structure. Of the channel semiconductor layers 21C and 21D, the channel semiconductor layer having the Fin structure is N-type. This allows the CFET in the second region 62 to have a high speed. Note that when the magnitude relationship between the electron mobility and the hole mobility is reversed (for example, when a silicon substrate having a (110) plane as the main surface is used), it is preferable that the channel semiconductor layer having the Fin structure is P-type. In a CFET, the transistor Tr2 is often a P-type channel transistor, and the transistor Tr3 is often an N-type channel transistor. Therefore, it is preferable that the channel semiconductor layers 21A, 21C, and 21E have a Fin structure, and the channel semiconductor layers 21B, 21D, and 21F have a nanosheet structure.

[0073] (Third Modification of the First Embodiment) The third modification of the first embodiment is an example in which the gate insulating films of transistors Tr1 and Tr4 are thicker than the gate insulating films of transistors Tr2 and Tr3 in a FinFET. Figures 32(A) and 32(B) are cross-sectional views of the first region in the third modification of the first embodiment. Figures 33(A) and 33(B) are cross-sectional views of the third region in the third modification of the first embodiment. The cross section of the second region 62 is the same as that in Figures 3(A) and 3(B).

[0074] 32(A) to 33(B), in a semiconductor device 103 according to the third modification of the first embodiment, the gate insulating films 24A, 24B, 24E, and 24F are thicker than the gate insulating films 24C and 24D in Figures 3(A) and 3(B). The other configurations are the same as those in the first embodiment, and therefore descriptions thereof will be omitted.

[0075] (Fourth Modification of the First Embodiment) The fourth modification of the first embodiment is an example in which the gate insulating films of transistors Tr1 and Tr4 are thicker than the gate insulating films of transistors Tr2 and Tr3 in a nanosheet transistor. Figures 34(A) and 34(B) are cross-sectional views of the first region in the fourth modification of the first embodiment. Figures 35(A) and 35(B) are cross-sectional views of the third region in the fourth modification of the first embodiment. The cross section of the second region 62 is the same as that in Figures 26(A) and 26(B).

[0076] 34(A) to 35(B), in the semiconductor device 104 according to the fourth modification of the first embodiment, the gate insulating films 24A, 24B, 24E, and 24F are thicker than the gate insulating films 24C and 24D in Figures 26(A) and 26(B). The other configurations are the same as those in the first modification of the first embodiment, and therefore description thereof will be omitted.

[0077] Because transistors Tr1 and Tr4 are used in, for example, an input / output circuit, the voltage applied to gate electrodes 25A, 25B, 25E, and 25F may be higher than the voltage applied to gate electrodes 25C and 25D of transistors Tr2 and Tr3. As in the third and fourth modifications of the first embodiment, the thicknesses of gate insulating films 24A, 24B, 24E, and 24F are all greater than the thicknesses of gate insulating films 24C and 24D. This allows the breakdown voltage of transistors Tr1 and Tr4 to be higher than that of transistors Tr2 and Tr3. Meanwhile, the thin gate insulating films 24C and 24D enable high-speed operation of transistors Tr2 and Tr3. The thicknesses of gate insulating films 24A, 24B, 24E, and 24F are preferably at least 1.2 times, and more preferably at least 1.5 times, the thickness of gate insulating films 24C and 24D. As in the second modification of the first embodiment, when FinFETs and nanosheet transistors are mixed, the gate insulating films 24A, 24B, 24E, and 24F may be made thicker than the gate insulating films 24C and 24D.

[0078] As in the fourth modification of the first embodiment, in a nanosheet transistor, the spacing between the channel semiconductor layers 21A (21B, 21E, and 21F) in the Z direction is small. Therefore, if the gate insulating film 24A (24B, 24E, and 24F) is made thicker, the thickness of the gate electrode 25A (25B, 25E, and 25F) between the channel semiconductor layers 21A (21B, 21E, and 21F) becomes smaller. Therefore, when the gate insulating films 24A, 24B, 24E, and 24F are made thicker than the gate insulating films 24C and 24D, it is preferable that the transistors Tr1 to Tr4 are FinFETs, as in the third modification of the first embodiment.

[0079] (Fifth Modification of the First Embodiment) 36(A) to 36(F) are cross-sectional views of a semiconductor device according to a fifth modified example of the first embodiment. As shown in FIGS. 36(A) to 36(F), in a semiconductor device 105 according to the fifth modified example of the first embodiment, an insulating film 11 is provided between the channel semiconductor layers 21A, 21C, and 21E and the substrate 10. The insulating film 11 is, for example, a silicon oxide film. The other configurations are the same as in the first embodiment, and description thereof will be omitted. The insulating film 11 may also be provided in the first to fourth modified examples of the first embodiment.

[0080] When the insulating film 11 is provided as in the fifth modification of the first embodiment, leakage current between the substrate 10 and the transistors Tr1, Tr2, and Tr4 can be suppressed. When the channel semiconductor layers 21A, 21C, and 21D of the transistors Tr1, Tr2, and Tr4 are in contact with the substrate 10 without providing the insulating film 11 as in the first embodiment, the characteristics of the transistors Tr1, Tr2, and Tr4 can be controlled by controlling the potential of the substrate 10. When the insulating film 11 is not provided, it is preferable to suppress leakage current using a technique such as a channel stop.

[0081] (Second embodiment) The second embodiment and its modifications are examples in which the transistors Tr1 to Tr4 of the first embodiment and its modifications are used in a semiconductor device having a circuit. The second embodiment is an example in which the transistors Tr1 to Tr3 are used in an SRAM (Static Random Access Memory) cell. FIG. 37 is a circuit diagram of a semiconductor device according to the second embodiment. As shown in FIG. 37, a semiconductor device 106 according to the second embodiment includes a bistable circuit 50 and pass gate transistors T1 and T2. The bistable circuit 50 includes inverter circuits 51 and 52. The inverter circuit 51 includes an NFETN1 and a PFETP1. The source of NFETN1 is electrically connected to a ground line 66, and the source of PFETP1 is electrically connected to a power supply line 65. The drains of NFETN1 and PFETP1 are electrically connected to form an output node of the inverter circuit 51. The gates of NFETN1 and PFETP1 are electrically connected to form an input node of the inverter circuit 51.

[0082] The inverter circuit 52 includes an NFETN2 and a PFETP2. The source of NFETN2 is electrically connected to a ground line 66, and the source of PFETP2 is electrically connected to a power supply line 65. The drains of NFETN2 and PFETP2 are electrically connected and form an output node of the inverter circuit 52. The gates of NFETN2 and PFETP2 are electrically connected and form an input node of the inverter circuit 52. A ground voltage GND is supplied to the ground line 66, and a power supply voltage VDD is supplied to the power supply line 65.

[0083] The output node of inverter circuit 51 and the input node of inverter circuit 52 are electrically connected to form storage node Q1, while the input node of inverter circuit 51 and the output node of inverter circuit 52 are electrically connected to form storage node Q2.

[0084] One of the source and drain of the pass-gate transistor T1 is electrically connected to the storage node Q1, and the other of the source and drain is electrically connected to the bit line BL. The gate of the pass-gate transistor T1 is electrically connected to the word line WL. One of the source and drain of the pass-gate transistor T2 is electrically connected to the storage node Q2, and the other of the source and drain is electrically connected to the bit line BL'. The gate of the pass-gate transistor T2 is electrically connected to the word line WL.

[0085] When writing data to the bistable circuit 50, the bit lines BL and BL' are set to a write potential. The word line WL is set to a high level, and the pass gate transistors T1 and T2 are turned on. This causes the data on the bit lines BL and BL' to be written to the storage nodes Q1 and Q2, respectively. When reading data from the bistable circuit 50, the bit lines BL and BL' are set to a floating state, the word line WL is set to a high level, and the pass gate transistors T1 and T2 are turned on. This causes the data on the storage nodes Q1 and Q2 to be read onto the bit lines BL and BL'.

[0086] The NFETs N1 and N2 correspond to the transistor Tr3 in the first embodiment and its modifications, the PFETs P1 and P2 correspond to the transistor Tr2 in the first embodiment and its modifications, and the pass-gate transistors T1 and T2 correspond to the transistor Tr1 in the first embodiment and its modifications. Thus, the bistable circuit 50 includes a pair of inverter circuits 51 and 52 having transistors Tr2 and Tr3. The pass-gate transistors T1 and T2 are the transistor Tr1 connected to the storage nodes Q1 and Q2. This allows the driving power of the pass-gate transistors T1 and T2 to be approximately twice the driving power of the NFETs N1, N2, and PFET P1. Therefore, when writing data to the storage nodes Q1 and Q2, the data can be written to the storage nodes Q1 and Q2 more reliably.

[0087] FIG. 38 is a circuit diagram of a semiconductor device according to a second embodiment. When data is read from storage nodes Q1 and Q2, if the driving force of pass-gate transistors T1 and T2 is large, the charges of storage nodes Q1 and Q2 may not be enough to charge or discharge bit lines BL and BL', resulting in inversion of the data at storage nodes Q1 and Q2. Therefore, as shown in FIG. 38, when reading data, the voltage of power supply line 65 is set to VDD+ΔV, which is higher than VDD, or the voltage of ground line 66 is set to GND-ΔV, which is lower than GND. This allows for assistance in reading data (i.e., read assist). When retaining data and when writing data, the voltages of power supply line 65 and ground line 66 are VDD and GND, respectively, as shown in FIG. 37.

[0088] Using CFETs in the SRAM cells can reduce the chip size by approximately 0.8 times. Furthermore, using transistor Tr1 as the pass gate transistors T1 and T2 can reduce the chip size without changing the pass gate transistors T1 and T2.

[0089] (First modified example of the second embodiment) The first modified example of the second embodiment is an example of a transfer gate. FIG. 39 is a circuit diagram of a semiconductor device according to the first modified example of the second embodiment. As shown in FIG. 39, a semiconductor device 107 according to the first modified example of the second embodiment includes transistors T3 and T4. One of the source and drain of the transistor T3 is electrically connected to an input node IN, and the other of the source and drain is electrically connected to an output node OUT. A clock signal C' is input to the gate of the transistor T3. One of the source and drain of the transistor T4 is electrically connected to the input node IN, and the other of the source and drain is electrically connected to the output node OUT. A clock signal C' is input to the gate of the transistor T4. The clock signals C' and C' are inverted signals of C. As a result, when the clock signal C is at a high level, the input node IN and the output node OUT are electrically connected, and when the clock signal C is at a low level, the input node IN and the output node OUT are electrically disconnected.

[0090] Transistor T3 is transistor Tr4 in the first embodiment and its modifications, and transistor T4 is transistor Tr1 in the first embodiment and its modifications. A large driving force is required for the transfer gate. Therefore, transistors Tr1 and Tr4 are used in the transfer gate. This improves the driving force of the transfer gate. When using transfer gates with the same driving force, the chip size can be reduced.

[0091] (Second Modification of the Second Embodiment) The second modification of the second embodiment is an example of a tri-state inverter. Fig. 40 is a circuit diagram of a semiconductor device according to the second modification of the second embodiment. As shown in Fig. 40, a semiconductor device 108 according to the second modification of the second embodiment includes inverter circuits 53 and 54 and transistors T5 and T6.

[0092] The inverter circuit 53 includes an NFETN3 and a PFETP3. An input node IN is electrically connected to the gates of the NFETN3 and the PFETP3, and an output node OUT is electrically connected to the drains of the NFETN3 and the PFETP3. The source of the transistor T5 is electrically connected to the power supply line 65, and the drain is electrically connected to the source of the PFETP3. The source of the transistor T6 is electrically connected to the ground line 66, and the drain is electrically connected to the source of the NFETN3.

[0093] The inverter circuit 54 includes an NFET N4 and a PFET P4. An enable signal OE is input to the gate of the transistor T5, and a signal obtained by inverting the enable signal OE by the inverter circuit 54 is input to the gate of the transistor T6. When the enable signal OE is at a low level, the transistors T5 and T6 are turned on, and the inverter circuit 53 operates. When the enable signal OE is at a high level, the transistors T5 and T6 are turned off, the inverter circuit 53 does not operate, and the output node OUT becomes an input impedance.

[0094] Transistor T5 corresponds to transistor Tr4 in the first embodiment and its modifications, and transistor T6 corresponds to transistor Tr1 in the first embodiment and its modifications. NFETs N3 and N4 correspond to transistor Tr3 in the first embodiment and its modifications, and PFETs P3 and P4 correspond to transistor Tr2 in the first embodiment and its modifications. Thus, the inverter circuit 53 includes PFET P3 (transistor Tr2) and NFET N3 (transistor Tr3). Transistor T6 (transistor Tr1) is connected between NFET N3 and a ground line 66 (first power supply line), and transistor T5 (transistor Tr4) is connected between PFET P3 and a power supply line 65 (second power supply line). This improves the driving power of transistors T5 and T6. Furthermore, the chip size can be reduced.

[0095] Transistors Tr1 and Tr4 can also be applied to circuits other than those of the second embodiment and its modifications. In a CFET, the NFET and PFET share the same gate electrode. Therefore, transistors Tr1 and Tr4 can be used when the gate electrodes of the NFET and PFET are electrically isolated. Furthermore, input / output circuits or analog circuits may use high voltages (e.g., 2.5 V or higher). Therefore, as in the third and fourth modifications of the first embodiment, the gate insulating films of transistors Tr1 and Tr4 can be made thicker than the gate insulating films of transistors Tr2 and Tr3. Furthermore, since the driving power of transistors Tr1 and Tr4 is approximately twice that of transistors Tr2 and Tr3, using transistors Tr1 and Tr4 as transistors with large driving power can reduce the chip size.

[0096] Although the present disclosure has been described above based on the embodiments, the present invention is not limited to the requirements set forth in the above embodiments. These requirements can be changed without departing from the spirit of the present disclosure, and can be appropriately determined depending on the application form. [Explanation of symbols]

[0097] 10 Substrate 11, 14, 16 Insulating film 12 Element isolation insulating film 21A, 21B, 21C, 21D, 21E, 21F Channel semiconductor layer 22A, 22B, 22C, 22D, 22E, 22F, 23A, 23B, 23C, 23D, 23E, 23F Source / drain semiconductor layer 24A, 24B, 24C, 24D, 24E, 24F Gate insulating film 25A, 25B, 25C, 25D, 25E, 25F Gate electrodes 31A, 31B, 31C, 31D, 31E, 31F Semiconductor layers 50 bistable circuit 51, 52, 53, 54 Inverter circuit 61 1st area 62 Second area 63 Third area 65 Power line 66 Ground Line

Claims

1. A substrate; a first channel semiconductor layer provided on the substrate and having a first conductivity type; a pair of first source / drain semiconductor layers provided on the substrate, sandwiching the first channel semiconductor layer and having a second conductivity type different from the first conductivity type; a first gate electrode sandwiching a first gate insulating film between the pair of first source / drain semiconductor layers and the first channel semiconductor layer; a second channel semiconductor layer having the first conductivity type and provided above and apart from the first channel semiconductor layer; a pair of second source / drain semiconductor layers provided on the pair of first source / drain semiconductor layers, electrically connected to the pair of first source / drain semiconductor layers, sandwiching the second channel semiconductor layer, and having the second conductivity type; a second gate electrode electrically connected to the first gate electrode, sandwiching a second gate insulating film between the pair of second source / drain semiconductor layers and the second channel semiconductor layer; a first transistor having A semiconductor device comprising:

2. a third channel semiconductor layer provided on the substrate and having a third conductivity type which is either the first conductivity type or the second conductivity type; a pair of third source / drain semiconductor layers provided on the substrate, sandwiching the third channel semiconductor layer and having a fourth conductivity type different from the third conductivity type; a third gate electrode sandwiching a third gate insulating film between the pair of third source / drain semiconductor layers and the third channel semiconductor layer; a second transistor having a fourth channel semiconductor layer having the fourth conductivity type, the fourth channel semiconductor layer being provided above and spaced apart from the third channel semiconductor layer; a pair of fourth source / drain semiconductor layers having the third conductivity type, the fourth source / drain semiconductor layers being provided above and spaced apart from the pair of third source / drain semiconductor layers, with the fourth channel semiconductor layer sandwiched therebetween; a fourth gate electrode electrically connected to the third gate electrode, with a fourth gate insulating film sandwiched between the pair of fourth source / drain semiconductor layers and the fourth channel semiconductor layer; a third transistor having The semiconductor device according to claim 1 , comprising:

3. a fifth channel semiconductor layer provided on the substrate and having the second conductivity type; a pair of fifth source / drain semiconductor layers having the first conductivity type, the fifth source / drain semiconductor layers sandwiching the fifth channel semiconductor layer on the substrate; a fifth gate electrode sandwiching a fifth gate insulating film between the fifth channel semiconductor layer and the fifth source / drain semiconductor layer; a sixth channel semiconductor layer having the second conductivity type and provided above and apart from the fifth channel semiconductor layer; a pair of sixth source / drain semiconductor layers that are provided on the pair of fifth source / drain semiconductor layers, are electrically connected to the pair of fifth source / drain semiconductor layers, sandwich the sixth channel semiconductor layer, and have the first conductivity type; a sixth gate electrode electrically connected to the fifth gate electrode, sandwiching a sixth gate insulating film between the pair of sixth source / drain semiconductor layers and the sixth channel semiconductor layer; The semiconductor device according to claim 2 , further comprising a fourth transistor having:

4. 4. The semiconductor device according to claim 2, wherein an absolute value of a difference between a first height from the substrate at a portion of the second channel semiconductor layer farthest from the substrate and a second height from the substrate at a portion of the fourth channel semiconductor layer farthest from the substrate is 0.1 times or less of the first height.

5. 4. The semiconductor device according to claim 2, wherein the thickness of the third gate insulating film and the thickness of the fourth gate insulating film are both greater than the thickness of the first gate insulating film and the thickness of the second gate insulating film.

6. The semiconductor device according to claim 1 , wherein the first channel semiconductor layer of the first transistor is in contact with the substrate.

7. 4. The semiconductor device according to claim 2, wherein one of the first channel semiconductor layer and the third channel semiconductor layer and the second channel semiconductor layer and the fourth channel semiconductor layer has a Fin structure, and the other of the first channel semiconductor layer and the third channel semiconductor layer and the second channel semiconductor layer and the fourth channel semiconductor layer has a nanosheet structure.

8. 4. The semiconductor device according to claim 2, further comprising an SRAM cell having: a bistable circuit including a pair of inverter circuits having the second transistor and the third transistor; and a pass gate transistor which is the first transistor connected to a storage node of the bistable circuit.

9. The semiconductor device according to claim 3 , further comprising a transfer gate having said first transistor and said fourth transistor.

10. 4. The semiconductor device according to claim 3, further comprising a tri-state inverter comprising an inverter circuit having the second transistor and the third transistor, the first transistor being connected between the third transistor and a first power supply line, the fourth transistor being connected between the second transistor and a second power supply line, and the third conductivity type being the second conductivity type.

11. a first channel semiconductor layer provided on a substrate and having a first conductivity type; a pair of first source / drain semiconductor layers provided on the substrate, sandwiching the first channel semiconductor layer and having a second conductivity type different from the first conductivity type; a first gate electrode sandwiching a first gate insulating film between the pair of first source / drain semiconductor layers and the first channel semiconductor layer; a second channel semiconductor layer having the first conductivity type and provided above and apart from the first channel semiconductor layer; a pair of second source / drain semiconductor layers provided on the pair of first source / drain semiconductor layers, electrically connected to the pair of first source / drain semiconductor layers, sandwiching the second channel semiconductor layer, and having the second conductivity type; a second gate electrode electrically connected to the first gate electrode, sandwiching a second gate insulating film between the pair of second source / drain semiconductor layers and the second channel semiconductor layer; a first transistor having a third channel semiconductor layer provided on the substrate and having the second conductivity type; a pair of third source / drain semiconductor layers of the first conductivity type provided on the substrate and sandwiching the third channel semiconductor layer; a third gate electrode sandwiching a third gate insulating film between the pair of third source / drain semiconductor layers and the third channel semiconductor layer; a second transistor having a fourth channel semiconductor layer having the first conductivity type and provided above and apart from the third channel semiconductor layer; a pair of fourth source / drain semiconductor layers having the second conductivity type, the fourth channel semiconductor layer being sandwiched between the pair of third source / drain semiconductor layers and spaced apart from the pair of third source / drain semiconductor layers; a fourth gate electrode electrically connected to the third gate electrode, with a fourth gate insulating film sandwiched between the pair of fourth source / drain semiconductor layers and the fourth channel semiconductor layer; a third transistor having A method for manufacturing a semiconductor device, comprising: forming a first semiconductor layer on the substrate, a second semiconductor layer above the first semiconductor layer and spaced apart from the first semiconductor layer, a third semiconductor layer on the substrate, and a fourth semiconductor layer above the third semiconductor layer and spaced apart from the third semiconductor layer; forming the pair of third source / drain semiconductor layers sandwiching the third semiconductor layer; simultaneously forming the pair of first source / drain semiconductor layers sandwiching the first semiconductor layer, the pair of second source / drain semiconductor layers sandwiching the second semiconductor layer, and the pair of fourth source / drain semiconductor layers sandwiching the fourth semiconductor layer; A method for manufacturing a semiconductor device, comprising:

12. a first channel semiconductor layer provided on a substrate and having a first conductivity type; a pair of first source / drain semiconductor layers provided on the substrate, sandwiching the first channel semiconductor layer and having a second conductivity type different from the first conductivity type; a first gate electrode sandwiching a first gate insulating film between the pair of first source / drain semiconductor layers and the first channel semiconductor layer; a second channel semiconductor layer having the first conductivity type and provided above and apart from the first channel semiconductor layer; a pair of second source / drain semiconductor layers provided on the pair of first source / drain semiconductor layers, electrically connected to the pair of first source / drain semiconductor layers, sandwiching the second channel semiconductor layer, and having the second conductivity type; a second gate electrode electrically connected to the first gate electrode, sandwiching a second gate insulating film between the pair of second source / drain semiconductor layers and the second channel semiconductor layer; a first transistor having a third channel semiconductor layer provided on the substrate and having the first conductivity type; a pair of third source / drain semiconductor layers of the second conductivity type provided on the substrate and sandwiching the third channel semiconductor layer; a third gate electrode sandwiching a third gate insulating film between the pair of third source / drain semiconductor layers and the third channel semiconductor layer; a second transistor having a fourth channel semiconductor layer having the second conductivity type and provided above and apart from the third channel semiconductor layer; a pair of fourth source / drain semiconductor layers having the first conductivity type, the fourth channel semiconductor layer being sandwiched between the pair of third source / drain semiconductor layers and spaced apart from the pair of third source / drain semiconductor layers; a fourth gate electrode electrically connected to the third gate electrode, with a fourth gate insulating film sandwiched between the pair of fourth source / drain semiconductor layers and the fourth channel semiconductor layer; a third transistor having A method for manufacturing a semiconductor device, comprising: forming a first semiconductor layer on the substrate, a second semiconductor layer above the first semiconductor layer and spaced apart from the first semiconductor layer, a third semiconductor layer on the substrate, and a fourth semiconductor layer above the third semiconductor layer and spaced apart from the third semiconductor layer; a step of simultaneously forming the pair of first source / drain semiconductor layers sandwiching the first semiconductor layer, the pair of second source / drain semiconductor layers sandwiching the second semiconductor layer, and the pair of third source / drain semiconductor layers sandwiching the third semiconductor layer; forming the pair of fourth source / drain semiconductor layers sandwiching the fourth semiconductor layer; A method for manufacturing a semiconductor device, comprising:

13. the first semiconductor layer is the first channel semiconductor layer, the second semiconductor layer is the second channel semiconductor layer, the third semiconductor layer is the third channel semiconductor layer, the fourth semiconductor layer is the fourth channel semiconductor layer; The method for manufacturing a semiconductor device according to claim 11 or 12.

14. 13. The method for manufacturing a semiconductor device according to claim 11, further comprising the steps of: after forming the pair of first source-drain semiconductor layers, the pair of second source-drain semiconductor layers, the pair of third source-drain semiconductor layers, and the pair of fourth source-drain semiconductor layers, removing at least one semiconductor layer from the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer; and forming at least one channel semiconductor layer from the corresponding first channel semiconductor layer, the second channel semiconductor layer, the third channel semiconductor layer, and the fourth channel semiconductor layer in a region from which the at least one semiconductor layer has been removed.

Images